LiteX: support for VexRiscV interrupt controller
[linux/fpc-iii.git] / crypto / aegis.h
blob6920ebe7767953c53261960f5e203aa8422c9359
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * AEGIS common definitions
5 * Copyright (c) 2018 Ondrej Mosnacek <omosnacek@gmail.com>
6 * Copyright (c) 2018 Red Hat, Inc. All rights reserved.
7 */
9 #ifndef _CRYPTO_AEGIS_H
10 #define _CRYPTO_AEGIS_H
12 #include <crypto/aes.h>
13 #include <linux/bitops.h>
14 #include <linux/types.h>
16 #define AEGIS_BLOCK_SIZE 16
18 union aegis_block {
19 __le64 words64[AEGIS_BLOCK_SIZE / sizeof(__le64)];
20 __le32 words32[AEGIS_BLOCK_SIZE / sizeof(__le32)];
21 u8 bytes[AEGIS_BLOCK_SIZE];
24 #define AEGIS_BLOCK_ALIGN (__alignof__(union aegis_block))
25 #define AEGIS_ALIGNED(p) IS_ALIGNED((uintptr_t)p, AEGIS_BLOCK_ALIGN)
27 static __always_inline void crypto_aegis_block_xor(union aegis_block *dst,
28 const union aegis_block *src)
30 dst->words64[0] ^= src->words64[0];
31 dst->words64[1] ^= src->words64[1];
34 static __always_inline void crypto_aegis_block_and(union aegis_block *dst,
35 const union aegis_block *src)
37 dst->words64[0] &= src->words64[0];
38 dst->words64[1] &= src->words64[1];
41 static __always_inline void crypto_aegis_aesenc(union aegis_block *dst,
42 const union aegis_block *src,
43 const union aegis_block *key)
45 const u8 *s = src->bytes;
46 const u32 *t = crypto_ft_tab[0];
47 u32 d0, d1, d2, d3;
49 d0 = t[s[ 0]] ^ rol32(t[s[ 5]], 8) ^ rol32(t[s[10]], 16) ^ rol32(t[s[15]], 24);
50 d1 = t[s[ 4]] ^ rol32(t[s[ 9]], 8) ^ rol32(t[s[14]], 16) ^ rol32(t[s[ 3]], 24);
51 d2 = t[s[ 8]] ^ rol32(t[s[13]], 8) ^ rol32(t[s[ 2]], 16) ^ rol32(t[s[ 7]], 24);
52 d3 = t[s[12]] ^ rol32(t[s[ 1]], 8) ^ rol32(t[s[ 6]], 16) ^ rol32(t[s[11]], 24);
54 dst->words32[0] = cpu_to_le32(d0) ^ key->words32[0];
55 dst->words32[1] = cpu_to_le32(d1) ^ key->words32[1];
56 dst->words32[2] = cpu_to_le32(d2) ^ key->words32[2];
57 dst->words32[3] = cpu_to_le32(d3) ^ key->words32[3];
60 #endif /* _CRYPTO_AEGIS_H */