drivers/clk/ux500/u8500_of_clk.c

   1 /*
   2  * Clock definitions for u8500 platform.
   3  *
   4  * Copyright (C) 2012 ST-Ericsson SA
   5  * Author: Ulf Hansson <ulf.hansson@linaro.org>
   6  *
   7  * License terms: GNU General Public License (GPL) version 2
   8  */
   9
  10 #include <linux/of.h>
  11 #include <linux/of_address.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/mfd/dbx500-prcmu.h>
  14 #include <linux/platform_data/clk-ux500.h>
  15 #include "clk.h"
  16
  17 #define PRCC_NUM_PERIPH_CLUSTERS 6
  18 #define PRCC_PERIPHS_PER_CLUSTER 32
  19
  20 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
  21 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  22 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  23
  24 #define PRCC_SHOW(clk, base, bit) \
  25         clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
  26 #define PRCC_PCLK_STORE(clk, base, bit) \
  27         prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  28 #define PRCC_KCLK_STORE(clk, base, bit)        \
  29         prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  30
  31 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec,
  32                                      void *data)
  33 {
  34         struct clk **clk_data = data;
  35         unsigned int base, bit;
  36
  37         if (clkspec->args_count != 2)
  38                 return  ERR_PTR(-EINVAL);
  39
  40         base = clkspec->args[0];
  41         bit = clkspec->args[1];
  42
  43         if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) {
  44                 pr_err("%s: invalid PRCC base %d\n", __func__, base);
  45                 return ERR_PTR(-EINVAL);
  46         }
  47
  48         return PRCC_SHOW(clk_data, base, bit);
  49 }
  50
  51 static const struct of_device_id u8500_clk_of_match[] = {
  52         { .compatible = "stericsson,u8500-clks", },
  53         { },
  54 };
  55
  56 /* CLKRST4 is missing making it hard to index things */
  57 enum clkrst_index {
  58         CLKRST1_INDEX = 0,
  59         CLKRST2_INDEX,
  60         CLKRST3_INDEX,
  61         CLKRST5_INDEX,
  62         CLKRST6_INDEX,
  63         CLKRST_MAX,
  64 };
  65
  66 void u8500_clk_init(void)
  67 {
  68         struct prcmu_fw_version *fw_version;
  69         struct device_node *np = NULL;
  70         struct device_node *child = NULL;
  71         const char *sgaclk_parent = NULL;
  72         struct clk *clk, *rtc_clk, *twd_clk;
  73         u32 bases[CLKRST_MAX];
  74         int i;
  75
  76         if (of_have_populated_dt())
  77                 np = of_find_matching_node(NULL, u8500_clk_of_match);
  78         if (!np) {
  79                 pr_err("Either DT or U8500 Clock node not found\n");
  80                 return;
  81         }
  82         for (i = 0; i < ARRAY_SIZE(bases); i++) {
  83                 struct resource r;
  84
  85                 if (of_address_to_resource(np, i, &r))
  86                         /* Not much choice but to continue */
  87                         pr_err("failed to get CLKRST %d base address\n",
  88                                i + 1);
  89                 bases[i] = r.start;
  90         }
  91
  92         /* Clock sources */
  93         clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
  94                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  95         prcmu_clk[PRCMU_PLLSOC0] = clk;
  96
  97         clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
  98                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  99         prcmu_clk[PRCMU_PLLSOC1] = clk;
 100
 101         clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
 102                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
 103         prcmu_clk[PRCMU_PLLDDR] = clk;
 104
 105         /* FIXME: Add sys, ulp and int clocks here. */
 106
 107         rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
 108                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED,
 109                                 32768);
 110
 111         /* PRCMU clocks */
 112         fw_version = prcmu_get_fw_version();
 113         if (fw_version != NULL) {
 114                 switch (fw_version->project) {
 115                 case PRCMU_FW_PROJECT_U8500_C2:
 116                 case PRCMU_FW_PROJECT_U8520:
 117                 case PRCMU_FW_PROJECT_U8420:
 118                         sgaclk_parent = "soc0_pll";
 119                         break;
 120                 default:
 121                         break;
 122                 }
 123         }
 124
 125         if (sgaclk_parent)
 126                 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
 127                                         PRCMU_SGACLK, 0);
 128         else
 129                 clk = clk_reg_prcmu_gate("sgclk", NULL,
 130                                         PRCMU_SGACLK, CLK_IS_ROOT);
 131         prcmu_clk[PRCMU_SGACLK] = clk;
 132
 133         clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
 134         prcmu_clk[PRCMU_UARTCLK] = clk;
 135
 136         clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
 137         prcmu_clk[PRCMU_MSP02CLK] = clk;
 138
 139         clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
 140         prcmu_clk[PRCMU_MSP1CLK] = clk;
 141
 142         clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
 143         prcmu_clk[PRCMU_I2CCLK] = clk;
 144
 145         clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
 146         prcmu_clk[PRCMU_SLIMCLK] = clk;
 147
 148         clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
 149         prcmu_clk[PRCMU_PER1CLK] = clk;
 150
 151         clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
 152         prcmu_clk[PRCMU_PER2CLK] = clk;
 153
 154         clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
 155         prcmu_clk[PRCMU_PER3CLK] = clk;
 156
 157         clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
 158         prcmu_clk[PRCMU_PER5CLK] = clk;
 159
 160         clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
 161         prcmu_clk[PRCMU_PER6CLK] = clk;
 162
 163         clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
 164         prcmu_clk[PRCMU_PER7CLK] = clk;
 165
 166         clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
 167                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 168         prcmu_clk[PRCMU_LCDCLK] = clk;
 169
 170         clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
 171         prcmu_clk[PRCMU_BMLCLK] = clk;
 172
 173         clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
 174                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 175         prcmu_clk[PRCMU_HSITXCLK] = clk;
 176
 177         clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
 178                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 179         prcmu_clk[PRCMU_HSIRXCLK] = clk;
 180
 181         clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
 182                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 183         prcmu_clk[PRCMU_HDMICLK] = clk;
 184
 185         clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
 186         prcmu_clk[PRCMU_APEATCLK] = clk;
 187
 188         clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
 189                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 190         prcmu_clk[PRCMU_APETRACECLK] = clk;
 191
 192         clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
 193         prcmu_clk[PRCMU_MCDECLK] = clk;
 194
 195         clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
 196                                 CLK_IS_ROOT);
 197         prcmu_clk[PRCMU_IPI2CCLK] = clk;
 198
 199         clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
 200                                 CLK_IS_ROOT);
 201         prcmu_clk[PRCMU_DSIALTCLK] = clk;
 202
 203         clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
 204         prcmu_clk[PRCMU_DMACLK] = clk;
 205
 206         clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
 207         prcmu_clk[PRCMU_B2R2CLK] = clk;
 208
 209         clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
 210                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 211         prcmu_clk[PRCMU_TVCLK] = clk;
 212
 213         clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
 214         prcmu_clk[PRCMU_SSPCLK] = clk;
 215
 216         clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
 217         prcmu_clk[PRCMU_RNGCLK] = clk;
 218
 219         clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
 220         prcmu_clk[PRCMU_UICCCLK] = clk;
 221
 222         clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
 223         prcmu_clk[PRCMU_TIMCLK] = clk;
 224
 225         clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
 226                                         100000000,
 227                                         CLK_IS_ROOT|CLK_SET_RATE_GATE);
 228         prcmu_clk[PRCMU_SDMMCCLK] = clk;
 229
 230         clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
 231                                 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
 232         prcmu_clk[PRCMU_PLLDSI] = clk;
 233
 234         clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
 235                                 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
 236         prcmu_clk[PRCMU_DSI0CLK] = clk;
 237
 238         clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
 239                                 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
 240         prcmu_clk[PRCMU_DSI1CLK] = clk;
 241
 242         clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
 243                                 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
 244         prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
 245
 246         clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
 247                                 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
 248         prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
 249
 250         clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
 251                                 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
 252         prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
 253
 254         clk = clk_reg_prcmu_scalable_rate("armss", NULL,
 255                                 PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
 256         prcmu_clk[PRCMU_ARMSS] = clk;
 257
 258         twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
 259                                 CLK_IGNORE_UNUSED, 1, 2);
 260
 261         /*
 262          * FIXME: Add special handled PRCMU clocks here:
 263          * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
 264          * 2. ab9540_clkout1yuv, see clkout0yuv
 265          */
 266
 267         /* PRCC P-clocks */
 268         clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
 269                                 BIT(0), 0);
 270         PRCC_PCLK_STORE(clk, 1, 0);
 271
 272         clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
 273                                 BIT(1), 0);
 274         PRCC_PCLK_STORE(clk, 1, 1);
 275
 276         clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
 277                                 BIT(2), 0);
 278         PRCC_PCLK_STORE(clk, 1, 2);
 279
 280         clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
 281                                 BIT(3), 0);
 282         PRCC_PCLK_STORE(clk, 1, 3);
 283
 284         clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
 285                                 BIT(4), 0);
 286         PRCC_PCLK_STORE(clk, 1, 4);
 287
 288         clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
 289                                 BIT(5), 0);
 290         PRCC_PCLK_STORE(clk, 1, 5);
 291
 292         clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
 293                                 BIT(6), 0);
 294         PRCC_PCLK_STORE(clk, 1, 6);
 295
 296         clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
 297                                 BIT(7), 0);
 298         PRCC_PCLK_STORE(clk, 1, 7);
 299
 300         clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
 301                                 BIT(8), 0);
 302         PRCC_PCLK_STORE(clk, 1, 8);
 303
 304         clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
 305                                 BIT(9), 0);
 306         PRCC_PCLK_STORE(clk, 1, 9);
 307
 308         clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
 309                                 BIT(10), 0);
 310         PRCC_PCLK_STORE(clk, 1, 10);
 311
 312         clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
 313                                 BIT(11), 0);
 314         PRCC_PCLK_STORE(clk, 1, 11);
 315
 316         clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
 317                                 BIT(0), 0);
 318         PRCC_PCLK_STORE(clk, 2, 0);
 319
 320         clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
 321                                 BIT(1), 0);
 322         PRCC_PCLK_STORE(clk, 2, 1);
 323
 324         clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
 325                                 BIT(2), 0);
 326         PRCC_PCLK_STORE(clk, 2, 2);
 327
 328         clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
 329                                 BIT(3), 0);
 330         PRCC_PCLK_STORE(clk, 2, 3);
 331
 332         clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
 333                                 BIT(4), 0);
 334         PRCC_PCLK_STORE(clk, 2, 4);
 335
 336         clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
 337                                 BIT(5), 0);
 338         PRCC_PCLK_STORE(clk, 2, 5);
 339
 340         clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
 341                                 BIT(6), 0);
 342         PRCC_PCLK_STORE(clk, 2, 6);
 343
 344         clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
 345                                 BIT(7), 0);
 346         PRCC_PCLK_STORE(clk, 2, 7);
 347
 348         clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
 349                                 BIT(8), 0);
 350         PRCC_PCLK_STORE(clk, 2, 8);
 351
 352         clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
 353                                 BIT(9), 0);
 354         PRCC_PCLK_STORE(clk, 2, 9);
 355
 356         clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
 357                                 BIT(10), 0);
 358         PRCC_PCLK_STORE(clk, 2, 10);
 359
 360         clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
 361                                 BIT(11), 0);
 362         PRCC_PCLK_STORE(clk, 2, 11);
 363
 364         clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
 365                                 BIT(12), 0);
 366         PRCC_PCLK_STORE(clk, 2, 12);
 367
 368         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
 369                                 BIT(0), 0);
 370         PRCC_PCLK_STORE(clk, 3, 0);
 371
 372         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
 373                                 BIT(1), 0);
 374         PRCC_PCLK_STORE(clk, 3, 1);
 375
 376         clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
 377                                 BIT(2), 0);
 378         PRCC_PCLK_STORE(clk, 3, 2);
 379
 380         clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
 381                                 BIT(3), 0);
 382         PRCC_PCLK_STORE(clk, 3, 3);
 383
 384         clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
 385                                 BIT(4), 0);
 386         PRCC_PCLK_STORE(clk, 3, 4);
 387
 388         clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
 389                                 BIT(5), 0);
 390         PRCC_PCLK_STORE(clk, 3, 5);
 391
 392         clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
 393                                 BIT(6), 0);
 394         PRCC_PCLK_STORE(clk, 3, 6);
 395
 396         clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
 397                                 BIT(7), 0);
 398         PRCC_PCLK_STORE(clk, 3, 7);
 399
 400         clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
 401                                 BIT(8), 0);
 402         PRCC_PCLK_STORE(clk, 3, 8);
 403
 404         clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
 405                                 BIT(0), 0);
 406         PRCC_PCLK_STORE(clk, 5, 0);
 407
 408         clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
 409                                 BIT(1), 0);
 410         PRCC_PCLK_STORE(clk, 5, 1);
 411
 412         clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
 413                                 BIT(0), 0);
 414         PRCC_PCLK_STORE(clk, 6, 0);
 415
 416         clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
 417                                 BIT(1), 0);
 418         PRCC_PCLK_STORE(clk, 6, 1);
 419
 420         clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
 421                                 BIT(2), 0);
 422         PRCC_PCLK_STORE(clk, 6, 2);
 423
 424         clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
 425                                 BIT(3), 0);
 426         PRCC_PCLK_STORE(clk, 6, 3);
 427
 428         clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
 429                                 BIT(4), 0);
 430         PRCC_PCLK_STORE(clk, 6, 4);
 431
 432         clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
 433                                 BIT(5), 0);
 434         PRCC_PCLK_STORE(clk, 6, 5);
 435
 436         clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
 437                                 BIT(6), 0);
 438         PRCC_PCLK_STORE(clk, 6, 6);
 439
 440         clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
 441                                 BIT(7), 0);
 442         PRCC_PCLK_STORE(clk, 6, 7);
 443
 444         /* PRCC K-clocks
 445          *
 446          * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
 447          * by enabling just the K-clock, even if it is not a valid parent to
 448          * the K-clock. Until drivers get fixed we might need some kind of
 449          * "parent muxed join".
 450          */
 451
 452         /* Periph1 */
 453         clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
 454                         bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
 455         PRCC_KCLK_STORE(clk, 1, 0);
 456
 457         clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
 458                         bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
 459         PRCC_KCLK_STORE(clk, 1, 1);
 460
 461         clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
 462                         bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
 463         PRCC_KCLK_STORE(clk, 1, 2);
 464
 465         clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 466                         bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
 467         PRCC_KCLK_STORE(clk, 1, 3);
 468
 469         clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
 470                         bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
 471         PRCC_KCLK_STORE(clk, 1, 4);
 472
 473         clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
 474                         bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
 475         PRCC_KCLK_STORE(clk, 1, 5);
 476
 477         clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
 478                         bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
 479         PRCC_KCLK_STORE(clk, 1, 6);
 480
 481         clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
 482                         bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
 483         PRCC_KCLK_STORE(clk, 1, 8);
 484
 485         clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 486                         bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
 487         PRCC_KCLK_STORE(clk, 1, 9);
 488
 489         clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 490                         bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
 491         PRCC_KCLK_STORE(clk, 1, 10);
 492
 493         /* Periph2 */
 494         clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
 495                         bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
 496         PRCC_KCLK_STORE(clk, 2, 0);
 497
 498         clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
 499                         bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
 500         PRCC_KCLK_STORE(clk, 2, 2);
 501
 502         clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
 503                         bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
 504         PRCC_KCLK_STORE(clk, 2, 3);
 505
 506         clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
 507                         bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
 508         PRCC_KCLK_STORE(clk, 2, 4);
 509
 510         clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
 511                         bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
 512         PRCC_KCLK_STORE(clk, 2, 5);
 513
 514         /* Note that rate is received from parent. */
 515         clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
 516                         bases[CLKRST2_INDEX], BIT(6),
 517                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 518         PRCC_KCLK_STORE(clk, 2, 6);
 519
 520         clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
 521                         bases[CLKRST2_INDEX], BIT(7),
 522                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 523         PRCC_KCLK_STORE(clk, 2, 7);
 524
 525         /* Periph3 */
 526         clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
 527                         bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
 528         PRCC_KCLK_STORE(clk, 3, 1);
 529
 530         clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 531                         bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
 532         PRCC_KCLK_STORE(clk, 3, 2);
 533
 534         clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 535                         bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
 536         PRCC_KCLK_STORE(clk, 3, 3);
 537
 538         clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
 539                         bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
 540         PRCC_KCLK_STORE(clk, 3, 4);
 541
 542         clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
 543                         bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
 544         PRCC_KCLK_STORE(clk, 3, 5);
 545
 546         clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
 547                         bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
 548         PRCC_KCLK_STORE(clk, 3, 6);
 549
 550         clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
 551                         bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
 552         PRCC_KCLK_STORE(clk, 3, 7);
 553
 554         /* Periph6 */
 555         clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
 556                         bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
 557         PRCC_KCLK_STORE(clk, 6, 0);
 558
 559         for_each_child_of_node(np, child) {
 560                 static struct clk_onecell_data clk_data;
 561
 562                 if (!of_node_cmp(child->name, "prcmu-clock")) {
 563                         clk_data.clks = prcmu_clk;
 564                         clk_data.clk_num = ARRAY_SIZE(prcmu_clk);
 565                         of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data);
 566                 }
 567                 if (!of_node_cmp(child->name, "prcc-periph-clock"))
 568                         of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);
 569
 570                 if (!of_node_cmp(child->name, "prcc-kernel-clock"))
 571                         of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);
 572
 573                 if (!of_node_cmp(child->name, "rtc32k-clock"))
 574                         of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk);
 575
 576                 if (!of_node_cmp(child->name, "smp-twd-clock"))
 577                         of_clk_add_provider(child, of_clk_src_simple_get, twd_clk);
 578         }
 579 }