drivers/i2c/busses/i2c-designware-core.h

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  * ----------------------------------------------------------------------------
  26  *
  27  */
  28
  29
  30 #define DW_IC_CON_MASTER                0x1
  31 #define DW_IC_CON_SPEED_STD             0x2
  32 #define DW_IC_CON_SPEED_FAST            0x4
  33 #define DW_IC_CON_10BITADDR_MASTER      0x10
  34 #define DW_IC_CON_RESTART_EN            0x20
  35 #define DW_IC_CON_SLAVE_DISABLE         0x40
  36
  37
  38 /**
  39  * struct dw_i2c_dev - private i2c-designware data
  40  * @dev: driver model device node
  41  * @base: IO registers pointer
  42  * @cmd_complete: tx completion indicator
  43  * @lock: protect this struct and IO registers
  44  * @clk: input reference clock
  45  * @cmd_err: run time hadware error code
  46  * @msgs: points to an array of messages currently being transfered
  47  * @msgs_num: the number of elements in msgs
  48  * @msg_write_idx: the element index of the current tx message in the msgs
  49  *      array
  50  * @tx_buf_len: the length of the current tx buffer
  51  * @tx_buf: the current tx buffer
  52  * @msg_read_idx: the element index of the current rx message in the msgs
  53  *      array
  54  * @rx_buf_len: the length of the current rx buffer
  55  * @rx_buf: the current rx buffer
  56  * @msg_err: error status of the current transfer
  57  * @status: i2c master status, one of STATUS_*
  58  * @abort_source: copy of the TX_ABRT_SOURCE register
  59  * @irq: interrupt number for the i2c master
  60  * @adapter: i2c subsystem adapter node
  61  * @tx_fifo_depth: depth of the hardware tx fifo
  62  * @rx_fifo_depth: depth of the hardware rx fifo
  63  */
  64 struct dw_i2c_dev {
  65         struct device           *dev;
  66         void __iomem            *base;
  67         struct completion       cmd_complete;
  68         struct mutex            lock;
  69         struct clk              *clk;
  70         u32                     (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
  71         struct dw_pci_controller *controller;
  72         int                     cmd_err;
  73         struct i2c_msg          *msgs;
  74         int                     msgs_num;
  75         int                     msg_write_idx;
  76         u32                     tx_buf_len;
  77         u8                      *tx_buf;
  78         int                     msg_read_idx;
  79         u32                     rx_buf_len;
  80         u8                      *rx_buf;
  81         int                     msg_err;
  82         unsigned int            status;
  83         u32                     abort_source;
  84         int                     irq;
  85         u32                     accessor_flags;
  86         struct i2c_adapter      adapter;
  87         u32                     functionality;
  88         u32                     master_cfg;
  89         unsigned int            tx_fifo_depth;
  90         unsigned int            rx_fifo_depth;
  91 };
  92
  93 #define ACCESS_SWAP             0x00000001
  94 #define ACCESS_16BIT            0x00000002
  95
  96 extern u32 dw_readl(struct dw_i2c_dev *dev, int offset);
  97 extern void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);
  98 extern int i2c_dw_init(struct dw_i2c_dev *dev);
  99 extern int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 100                 int num);
 101 extern u32 i2c_dw_func(struct i2c_adapter *adap);
 102 extern irqreturn_t i2c_dw_isr(int this_irq, void *dev_id);
 103 extern void i2c_dw_enable(struct dw_i2c_dev *dev);
 104 extern u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev);
 105 extern void i2c_dw_disable(struct dw_i2c_dev *dev);
 106 extern void i2c_dw_clear_int(struct dw_i2c_dev *dev);
 107 extern void i2c_dw_disable_int(struct dw_i2c_dev *dev);
 108 extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);