?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mm/zsmalloc: allocate exactly size of struct zs_pool
[linux/fpc-iii.git] / drivers / scsi / mvsas / mv_init.c
blobf15df3de6790eeea406dd5593f3e87e74c83957f
1 /*
2 * Marvell 88SE64xx/88SE94xx pci init
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
7 *
8 * This file is licensed under GPLv2.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
13 * License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24 */
25
26
27 #include "mv_sas.h"
28
29 int interrupt_coalescing = 0x80;
30
31 static struct scsi_transport_template *mvs_stt;
32 static const struct mvs_chip_info mvs_chips[] = {
33 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
34 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
35 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
36 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
37 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
38 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
39 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
40 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
41 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
42 };
43
44 struct device_attribute *mvst_host_attrs[];
45
46 #define SOC_SAS_NUM 2
47
48 static struct scsi_host_template mvs_sht = {
49 .module = THIS_MODULE,
50 .name = DRV_NAME,
51 .queuecommand = sas_queuecommand,
52 .target_alloc = sas_target_alloc,
53 .slave_configure = sas_slave_configure,
54 .scan_finished = mvs_scan_finished,
55 .scan_start = mvs_scan_start,
56 .change_queue_depth = sas_change_queue_depth,
57 .change_queue_type = sas_change_queue_type,
58 .bios_param = sas_bios_param,
59 .can_queue = 1,
60 .cmd_per_lun = 1,
61 .this_id = -1,
62 .sg_tablesize = SG_ALL,
63 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
64 .use_clustering = ENABLE_CLUSTERING,
65 .eh_device_reset_handler = sas_eh_device_reset_handler,
66 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
67 .target_destroy = sas_target_destroy,
68 .ioctl = sas_ioctl,
69 .shost_attrs = mvst_host_attrs,
70 .use_blk_tags = 1,
71 .track_queue_depth = 1,
72 };
73
74 static struct sas_domain_function_template mvs_transport_ops = {
75 .lldd_dev_found = mvs_dev_found,
76 .lldd_dev_gone = mvs_dev_gone,
77 .lldd_execute_task = mvs_queue_command,
78 .lldd_control_phy = mvs_phy_control,
79
80 .lldd_abort_task = mvs_abort_task,
81 .lldd_abort_task_set = mvs_abort_task_set,
82 .lldd_clear_aca = mvs_clear_aca,
83 .lldd_clear_task_set = mvs_clear_task_set,
84 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
85 .lldd_lu_reset = mvs_lu_reset,
86 .lldd_query_task = mvs_query_task,
87 .lldd_port_formed = mvs_port_formed,
88 .lldd_port_deformed = mvs_port_deformed,
89
90 };
91
92 static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
93 {
94 struct mvs_phy *phy = &mvi->phy[phy_id];
95 struct asd_sas_phy *sas_phy = &phy->sas_phy;
96
97 phy->mvi = mvi;
98 phy->port = NULL;
99 init_timer(&phy->timer);
100 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
101 sas_phy->class = SAS;
102 sas_phy->iproto = SAS_PROTOCOL_ALL;
103 sas_phy->tproto = 0;
104 sas_phy->type = PHY_TYPE_PHYSICAL;
105 sas_phy->role = PHY_ROLE_INITIATOR;
106 sas_phy->oob_mode = OOB_NOT_CONNECTED;
107 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
108
109 sas_phy->id = phy_id;
110 sas_phy->sas_addr = &mvi->sas_addr[0];
111 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
112 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
113 sas_phy->lldd_phy = phy;
114 }
115
116 static void mvs_free(struct mvs_info *mvi)
117 {
118 struct mvs_wq *mwq;
119 int slot_nr;
120
121 if (!mvi)
122 return;
123
124 if (mvi->flags & MVF_FLAG_SOC)
125 slot_nr = MVS_SOC_SLOTS;
126 else
127 slot_nr = MVS_CHIP_SLOT_SZ;
128
129 if (mvi->dma_pool)
130 pci_pool_destroy(mvi->dma_pool);
131
132 if (mvi->tx)
133 dma_free_coherent(mvi->dev,
134 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
135 mvi->tx, mvi->tx_dma);
136 if (mvi->rx_fis)
137 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
138 mvi->rx_fis, mvi->rx_fis_dma);
139 if (mvi->rx)
140 dma_free_coherent(mvi->dev,
141 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
142 mvi->rx, mvi->rx_dma);
143 if (mvi->slot)
144 dma_free_coherent(mvi->dev,
145 sizeof(*mvi->slot) * slot_nr,
146 mvi->slot, mvi->slot_dma);
147
148 if (mvi->bulk_buffer)
149 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
150 mvi->bulk_buffer, mvi->bulk_buffer_dma);
151 if (mvi->bulk_buffer1)
152 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
153 mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
154
155 MVS_CHIP_DISP->chip_iounmap(mvi);
156 if (mvi->shost)
157 scsi_host_put(mvi->shost);
158 list_for_each_entry(mwq, &mvi->wq_list, entry)
159 cancel_delayed_work(&mwq->work_q);
160 kfree(mvi->tags);
161 kfree(mvi);
162 }
163
164 #ifdef CONFIG_SCSI_MVSAS_TASKLET
165 static void mvs_tasklet(unsigned long opaque)
166 {
167 u32 stat;
168 u16 core_nr, i = 0;
169
170 struct mvs_info *mvi;
171 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
172
173 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
174 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
175
176 if (unlikely(!mvi))
177 BUG_ON(1);
178
179 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
180 if (!stat)
181 goto out;
182
183 for (i = 0; i < core_nr; i++) {
184 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
185 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
186 }
187 out:
188 MVS_CHIP_DISP->interrupt_enable(mvi);
189
190 }
191 #endif
192
193 static irqreturn_t mvs_interrupt(int irq, void *opaque)
194 {
195 u32 core_nr;
196 u32 stat;
197 struct mvs_info *mvi;
198 struct sas_ha_struct *sha = opaque;
199 #ifndef CONFIG_SCSI_MVSAS_TASKLET
200 u32 i;
201 #endif
202
203 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
204 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
205
206 if (unlikely(!mvi))
207 return IRQ_NONE;
208 #ifdef CONFIG_SCSI_MVSAS_TASKLET
209 MVS_CHIP_DISP->interrupt_disable(mvi);
210 #endif
211
212 stat = MVS_CHIP_DISP->isr_status(mvi, irq);
213 if (!stat) {
214 #ifdef CONFIG_SCSI_MVSAS_TASKLET
215 MVS_CHIP_DISP->interrupt_enable(mvi);
216 #endif
217 return IRQ_NONE;
218 }
219
220 #ifdef CONFIG_SCSI_MVSAS_TASKLET
221 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
222 #else
223 for (i = 0; i < core_nr; i++) {
224 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
225 MVS_CHIP_DISP->isr(mvi, irq, stat);
226 }
227 #endif
228 return IRQ_HANDLED;
229 }
230
231 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
232 {
233 int i = 0, slot_nr;
234 char pool_name[32];
235
236 if (mvi->flags & MVF_FLAG_SOC)
237 slot_nr = MVS_SOC_SLOTS;
238 else
239 slot_nr = MVS_CHIP_SLOT_SZ;
240
241 spin_lock_init(&mvi->lock);
242 for (i = 0; i < mvi->chip->n_phy; i++) {
243 mvs_phy_init(mvi, i);
244 mvi->port[i].wide_port_phymap = 0;
245 mvi->port[i].port_attached = 0;
246 INIT_LIST_HEAD(&mvi->port[i].list);
247 }
248 for (i = 0; i < MVS_MAX_DEVICES; i++) {
249 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
250 mvi->devices[i].dev_type = SAS_PHY_UNUSED;
251 mvi->devices[i].device_id = i;
252 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
253 init_timer(&mvi->devices[i].timer);
254 }
255
256 /*
257 * alloc and init our DMA areas
258 */
259 mvi->tx = dma_alloc_coherent(mvi->dev,
260 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
261 &mvi->tx_dma, GFP_KERNEL);
262 if (!mvi->tx)
263 goto err_out;
264 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
265 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
266 &mvi->rx_fis_dma, GFP_KERNEL);
267 if (!mvi->rx_fis)
268 goto err_out;
269 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
270
271 mvi->rx = dma_alloc_coherent(mvi->dev,
272 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
273 &mvi->rx_dma, GFP_KERNEL);
274 if (!mvi->rx)
275 goto err_out;
276 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
277 mvi->rx[0] = cpu_to_le32(0xfff);
278 mvi->rx_cons = 0xfff;
279
280 mvi->slot = dma_alloc_coherent(mvi->dev,
281 sizeof(*mvi->slot) * slot_nr,
282 &mvi->slot_dma, GFP_KERNEL);
283 if (!mvi->slot)
284 goto err_out;
285 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
286
287 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
288 TRASH_BUCKET_SIZE,
289 &mvi->bulk_buffer_dma, GFP_KERNEL);
290 if (!mvi->bulk_buffer)
291 goto err_out;
292
293 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
294 TRASH_BUCKET_SIZE,
295 &mvi->bulk_buffer_dma1, GFP_KERNEL);
296 if (!mvi->bulk_buffer1)
297 goto err_out;
298
299 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
300 mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0);
301 if (!mvi->dma_pool) {
302 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
303 goto err_out;
304 }
305 mvi->tags_num = slot_nr;
306
307 /* Initialize tags */
308 mvs_tag_init(mvi);
309 return 0;
310 err_out:
311 return 1;
312 }
313
314
315 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
316 {
317 unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
318 struct pci_dev *pdev = mvi->pdev;
319 if (bar_ex != -1) {
320 /*
321 * ioremap main and peripheral registers
322 */
323 res_start = pci_resource_start(pdev, bar_ex);
324 res_len = pci_resource_len(pdev, bar_ex);
325 if (!res_start || !res_len)
326 goto err_out;
327
328 res_flag_ex = pci_resource_flags(pdev, bar_ex);
329 if (res_flag_ex & IORESOURCE_MEM) {
330 if (res_flag_ex & IORESOURCE_CACHEABLE)
331 mvi->regs_ex = ioremap(res_start, res_len);
332 else
333 mvi->regs_ex = ioremap_nocache(res_start,
334 res_len);
335 } else
336 mvi->regs_ex = (void *)res_start;
337 if (!mvi->regs_ex)
338 goto err_out;
339 }
340
341 res_start = pci_resource_start(pdev, bar);
342 res_len = pci_resource_len(pdev, bar);
343 if (!res_start || !res_len)
344 goto err_out;
345
346 res_flag = pci_resource_flags(pdev, bar);
347 if (res_flag & IORESOURCE_CACHEABLE)
348 mvi->regs = ioremap(res_start, res_len);
349 else
350 mvi->regs = ioremap_nocache(res_start, res_len);
351
352 if (!mvi->regs) {
353 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
354 iounmap(mvi->regs_ex);
355 mvi->regs_ex = NULL;
356 goto err_out;
357 }
358
359 return 0;
360 err_out:
361 return -1;
362 }
363
364 void mvs_iounmap(void __iomem *regs)
365 {
366 iounmap(regs);
367 }
368
369 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
370 const struct pci_device_id *ent,
371 struct Scsi_Host *shost, unsigned int id)
372 {
373 struct mvs_info *mvi = NULL;
374 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
375
376 mvi = kzalloc(sizeof(*mvi) +
377 (1L << mvs_chips[ent->driver_data].slot_width) *
378 sizeof(struct mvs_slot_info), GFP_KERNEL);
379 if (!mvi)
380 return NULL;
381
382 mvi->pdev = pdev;
383 mvi->dev = &pdev->dev;
384 mvi->chip_id = ent->driver_data;
385 mvi->chip = &mvs_chips[mvi->chip_id];
386 INIT_LIST_HEAD(&mvi->wq_list);
387
388 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
389 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
390
391 mvi->id = id;
392 mvi->sas = sha;
393 mvi->shost = shost;
394
395 mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
396 if (!mvi->tags)
397 goto err_out;
398
399 if (MVS_CHIP_DISP->chip_ioremap(mvi))
400 goto err_out;
401 if (!mvs_alloc(mvi, shost))
402 return mvi;
403 err_out:
404 mvs_free(mvi);
405 return NULL;
406 }
407
408 static int pci_go_64(struct pci_dev *pdev)
409 {
410 int rc;
411
412 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
413 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
414 if (rc) {
415 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
416 if (rc) {
417 dev_printk(KERN_ERR, &pdev->dev,
418 "64-bit DMA enable failed\n");
419 return rc;
420 }
421 }
422 } else {
423 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
424 if (rc) {
425 dev_printk(KERN_ERR, &pdev->dev,
426 "32-bit DMA enable failed\n");
427 return rc;
428 }
429 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
430 if (rc) {
431 dev_printk(KERN_ERR, &pdev->dev,
432 "32-bit consistent DMA enable failed\n");
433 return rc;
434 }
435 }
436
437 return rc;
438 }
439
440 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
441 const struct mvs_chip_info *chip_info)
442 {
443 int phy_nr, port_nr; unsigned short core_nr;
444 struct asd_sas_phy **arr_phy;
445 struct asd_sas_port **arr_port;
446 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
447
448 core_nr = chip_info->n_host;
449 phy_nr = core_nr * chip_info->n_phy;
450 port_nr = phy_nr;
451
452 memset(sha, 0x00, sizeof(struct sas_ha_struct));
453 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
454 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
455 if (!arr_phy || !arr_port)
456 goto exit_free;
457
458 sha->sas_phy = arr_phy;
459 sha->sas_port = arr_port;
460 sha->core.shost = shost;
461
462 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
463 if (!sha->lldd_ha)
464 goto exit_free;
465
466 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
467
468 shost->transportt = mvs_stt;
469 shost->max_id = MVS_MAX_DEVICES;
470 shost->max_lun = ~0;
471 shost->max_channel = 1;
472 shost->max_cmd_len = 16;
473
474 return 0;
475 exit_free:
476 kfree(arr_phy);
477 kfree(arr_port);
478 return -1;
479
480 }
481
482 static void mvs_post_sas_ha_init(struct Scsi_Host *shost,
483 const struct mvs_chip_info *chip_info)
484 {
485 int can_queue, i = 0, j = 0;
486 struct mvs_info *mvi = NULL;
487 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
488 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
489
490 for (j = 0; j < nr_core; j++) {
491 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
492 for (i = 0; i < chip_info->n_phy; i++) {
493 sha->sas_phy[j * chip_info->n_phy + i] =
494 &mvi->phy[i].sas_phy;
495 sha->sas_port[j * chip_info->n_phy + i] =
496 &mvi->port[i].sas_port;
497 }
498 }
499
500 sha->sas_ha_name = DRV_NAME;
501 sha->dev = mvi->dev;
502 sha->lldd_module = THIS_MODULE;
503 sha->sas_addr = &mvi->sas_addr[0];
504
505 sha->num_phys = nr_core * chip_info->n_phy;
506
507 if (mvi->flags & MVF_FLAG_SOC)
508 can_queue = MVS_SOC_CAN_QUEUE;
509 else
510 can_queue = MVS_CHIP_SLOT_SZ;
511
512 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
513 shost->can_queue = can_queue;
514 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
515 sha->core.shost = mvi->shost;
516 }
517
518 static void mvs_init_sas_add(struct mvs_info *mvi)
519 {
520 u8 i;
521 for (i = 0; i < mvi->chip->n_phy; i++) {
522 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
523 mvi->phy[i].dev_sas_addr =
524 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
525 }
526
527 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
528 }
529
530 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
531 {
532 unsigned int rc, nhost = 0;
533 struct mvs_info *mvi;
534 struct mvs_prv_info *mpi;
535 irq_handler_t irq_handler = mvs_interrupt;
536 struct Scsi_Host *shost = NULL;
537 const struct mvs_chip_info *chip;
538
539 dev_printk(KERN_INFO, &pdev->dev,
540 "mvsas: driver version %s\n", DRV_VERSION);
541 rc = pci_enable_device(pdev);
542 if (rc)
543 goto err_out_enable;
544
545 pci_set_master(pdev);
546
547 rc = pci_request_regions(pdev, DRV_NAME);
548 if (rc)
549 goto err_out_disable;
550
551 rc = pci_go_64(pdev);
552 if (rc)
553 goto err_out_regions;
554
555 shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
556 if (!shost) {
557 rc = -ENOMEM;
558 goto err_out_regions;
559 }
560
561 chip = &mvs_chips[ent->driver_data];
562 SHOST_TO_SAS_HA(shost) =
563 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
564 if (!SHOST_TO_SAS_HA(shost)) {
565 kfree(shost);
566 rc = -ENOMEM;
567 goto err_out_regions;
568 }
569
570 rc = mvs_prep_sas_ha_init(shost, chip);
571 if (rc) {
572 kfree(shost);
573 rc = -ENOMEM;
574 goto err_out_regions;
575 }
576
577 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
578
579 do {
580 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
581 if (!mvi) {
582 rc = -ENOMEM;
583 goto err_out_regions;
584 }
585
586 memset(&mvi->hba_info_param, 0xFF,
587 sizeof(struct hba_info_page));
588
589 mvs_init_sas_add(mvi);
590
591 mvi->instance = nhost;
592 rc = MVS_CHIP_DISP->chip_init(mvi);
593 if (rc) {
594 mvs_free(mvi);
595 goto err_out_regions;
596 }
597 nhost++;
598 } while (nhost < chip->n_host);
599 mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
600 #ifdef CONFIG_SCSI_MVSAS_TASKLET
601 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
602 (unsigned long)SHOST_TO_SAS_HA(shost));
603 #endif
604
605 mvs_post_sas_ha_init(shost, chip);
606
607 rc = scsi_add_host(shost, &pdev->dev);
608 if (rc)
609 goto err_out_shost;
610
611 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
612 if (rc)
613 goto err_out_shost;
614 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
615 DRV_NAME, SHOST_TO_SAS_HA(shost));
616 if (rc)
617 goto err_not_sas;
618
619 MVS_CHIP_DISP->interrupt_enable(mvi);
620
621 scsi_scan_host(mvi->shost);
622
623 return 0;
624
625 err_not_sas:
626 sas_unregister_ha(SHOST_TO_SAS_HA(shost));
627 err_out_shost:
628 scsi_remove_host(mvi->shost);
629 err_out_regions:
630 pci_release_regions(pdev);
631 err_out_disable:
632 pci_disable_device(pdev);
633 err_out_enable:
634 return rc;
635 }
636
637 static void mvs_pci_remove(struct pci_dev *pdev)
638 {
639 unsigned short core_nr, i = 0;
640 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
641 struct mvs_info *mvi = NULL;
642
643 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
644 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
645
646 #ifdef CONFIG_SCSI_MVSAS_TASKLET
647 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
648 #endif
649
650 sas_unregister_ha(sha);
651 sas_remove_host(mvi->shost);
652 scsi_remove_host(mvi->shost);
653
654 MVS_CHIP_DISP->interrupt_disable(mvi);
655 free_irq(mvi->pdev->irq, sha);
656 for (i = 0; i < core_nr; i++) {
657 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
658 mvs_free(mvi);
659 }
660 kfree(sha->sas_phy);
661 kfree(sha->sas_port);
662 kfree(sha);
663 pci_release_regions(pdev);
664 pci_disable_device(pdev);
665 return;
666 }
667
668 static struct pci_device_id mvs_pci_table[] = {
669 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
670 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
671 {
672 .vendor = PCI_VENDOR_ID_MARVELL,
673 .device = 0x6440,
674 .subvendor = PCI_ANY_ID,
675 .subdevice = 0x6480,
676 .class = 0,
677 .class_mask = 0,
678 .driver_data = chip_6485,
679 },
680 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
681 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
682 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
683 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
684 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
685 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
686 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
687 { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
688 { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
689 { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
690 { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
691 { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
692 { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
693 { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
694 {
695 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
696 .device = 0x9480,
697 .subvendor = PCI_ANY_ID,
698 .subdevice = 0x9480,
699 .class = 0,
700 .class_mask = 0,
701 .driver_data = chip_9480,
702 },
703 {
704 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
705 .device = 0x9445,
706 .subvendor = PCI_ANY_ID,
707 .subdevice = 0x9480,
708 .class = 0,
709 .class_mask = 0,
710 .driver_data = chip_9445,
711 },
712 {
713 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
714 .device = 0x9485,
715 .subvendor = PCI_ANY_ID,
716 .subdevice = 0x9480,
717 .class = 0,
718 .class_mask = 0,
719 .driver_data = chip_9485,
720 },
721 {
722 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
723 .device = 0x9485,
724 .subvendor = PCI_ANY_ID,
725 .subdevice = 0x9485,
726 .class = 0,
727 .class_mask = 0,
728 .driver_data = chip_9485,
729 },
730 { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */
731 { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
732 { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
733 { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
734 { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
735 { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
736 { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
737 { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
738 { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
739 { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
740
741 { } /* terminate list */
742 };
743
744 static struct pci_driver mvs_pci_driver = {
745 .name = DRV_NAME,
746 .id_table = mvs_pci_table,
747 .probe = mvs_pci_init,
748 .remove = mvs_pci_remove,
749 };
750
751 static ssize_t
752 mvs_show_driver_version(struct device *cdev,
753 struct device_attribute *attr, char *buffer)
754 {
755 return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
756 }
757
758 static DEVICE_ATTR(driver_version,
759 S_IRUGO,
760 mvs_show_driver_version,
761 NULL);
762
763 static ssize_t
764 mvs_store_interrupt_coalescing(struct device *cdev,
765 struct device_attribute *attr,
766 const char *buffer, size_t size)
767 {
768 int val = 0;
769 struct mvs_info *mvi = NULL;
770 struct Scsi_Host *shost = class_to_shost(cdev);
771 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
772 u8 i, core_nr;
773 if (buffer == NULL)
774 return size;
775
776 if (sscanf(buffer, "%d", &val) != 1)
777 return -EINVAL;
778
779 if (val >= 0x10000) {
780 mv_dprintk("interrupt coalescing timer %d us is"
781 "too long\n", val);
782 return strlen(buffer);
783 }
784
785 interrupt_coalescing = val;
786
787 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
788 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
789
790 if (unlikely(!mvi))
791 return -EINVAL;
792
793 for (i = 0; i < core_nr; i++) {
794 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
795 if (MVS_CHIP_DISP->tune_interrupt)
796 MVS_CHIP_DISP->tune_interrupt(mvi,
797 interrupt_coalescing);
798 }
799 mv_dprintk("set interrupt coalescing time to %d us\n",
800 interrupt_coalescing);
801 return strlen(buffer);
802 }
803
804 static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
805 struct device_attribute *attr, char *buffer)
806 {
807 return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
808 }
809
810 static DEVICE_ATTR(interrupt_coalescing,
811 S_IRUGO|S_IWUSR,
812 mvs_show_interrupt_coalescing,
813 mvs_store_interrupt_coalescing);
814
815 /* task handler */
816 struct task_struct *mvs_th;
817 static int __init mvs_init(void)
818 {
819 int rc;
820 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
821 if (!mvs_stt)
822 return -ENOMEM;
823
824 rc = pci_register_driver(&mvs_pci_driver);
825 if (rc)
826 goto err_out;
827
828 return 0;
829
830 err_out:
831 sas_release_transport(mvs_stt);
832 return rc;
833 }
834
835 static void __exit mvs_exit(void)
836 {
837 pci_unregister_driver(&mvs_pci_driver);
838 sas_release_transport(mvs_stt);
839 }
840
841 struct device_attribute *mvst_host_attrs[] = {
842 &dev_attr_driver_version,
843 &dev_attr_interrupt_coalescing,
844 NULL,
845 };
846
847 module_init(mvs_init);
848 module_exit(mvs_exit);
849
850 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
851 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
852 MODULE_VERSION(DRV_VERSION);
853 MODULE_LICENSE("GPL");
854 #ifdef CONFIG_PCI
855 MODULE_DEVICE_TABLE(pci, mvs_pci_table);
856 #endif
Linux with added FPC-III support