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hugetlb: introduce generic version of hugetlb_free_pgd_range
[linux/fpc-iii.git] / arch / x86 / events / intel / core.c
blob0fb8659b20d8d76fd974406873df8416359ab157
1 /*
2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/stddef.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/export.h>
15 #include <linux/nmi.h>
16
17 #include <asm/cpufeature.h>
18 #include <asm/hardirq.h>
19 #include <asm/intel-family.h>
20 #include <asm/apic.h>
21
22 #include "../perf_event.h"
23
24 /*
25 * Intel PerfMon, used on Core and later.
26 */
27 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
28 {
29 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
30 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
31 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
32 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
33 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
34 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
35 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
36 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
37 };
38
39 static struct event_constraint intel_core_event_constraints[] __read_mostly =
40 {
41 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
42 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
43 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
44 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
45 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
46 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
47 EVENT_CONSTRAINT_END
48 };
49
50 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
51 {
52 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
53 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
54 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
55 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
56 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
57 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
58 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
59 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
60 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
61 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
62 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
63 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
64 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
65 EVENT_CONSTRAINT_END
66 };
67
68 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
69 {
70 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
71 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
72 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
73 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
74 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
75 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
76 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
77 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
78 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
79 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
80 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
81 EVENT_CONSTRAINT_END
82 };
83
84 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
85 {
86 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
87 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
88 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
89 EVENT_EXTRA_END
90 };
91
92 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
93 {
94 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
95 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
96 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
97 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
98 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
99 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
100 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
101 EVENT_CONSTRAINT_END
102 };
103
104 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
105 {
106 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
107 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
108 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
109 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
110 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
112 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
113 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
114 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
115 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
118
119 /*
120 * When HT is off these events can only run on the bottom 4 counters
121 * When HT is on, they are impacted by the HT bug and require EXCL access
122 */
123 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
124 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
125 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
126 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
127
128 EVENT_CONSTRAINT_END
129 };
130
131 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
132 {
133 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
134 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
135 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
136 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
138 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
139 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
141 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
142 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
144 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
146
147 /*
148 * When HT is off these events can only run on the bottom 4 counters
149 * When HT is on, they are impacted by the HT bug and require EXCL access
150 */
151 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
152 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
153 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
154 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
155
156 EVENT_CONSTRAINT_END
157 };
158
159 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
160 {
161 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
162 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
163 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
164 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
165 EVENT_EXTRA_END
166 };
167
168 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
169 {
170 EVENT_CONSTRAINT_END
171 };
172
173 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
174 {
175 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
176 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
177 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
178 EVENT_CONSTRAINT_END
179 };
180
181 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
182 {
183 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
184 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
185 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
186 EVENT_CONSTRAINT_END
187 };
188
189 static struct event_constraint intel_skl_event_constraints[] = {
190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
193 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
194
195 /*
196 * when HT is off, these can only run on the bottom 4 counters
197 */
198 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
199 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
200 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
201 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
203
204 EVENT_CONSTRAINT_END
205 };
206
207 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
208 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
209 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
210 EVENT_EXTRA_END
211 };
212
213 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
214 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
215 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
216 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
217 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
218 EVENT_EXTRA_END
219 };
220
221 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
222 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
223 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
224 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
225 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
226 EVENT_EXTRA_END
227 };
228
229 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
230 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
231 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
232 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
233 /*
234 * Note the low 8 bits eventsel code is not a continuous field, containing
235 * some #GPing bits. These are masked out.
236 */
237 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
238 EVENT_EXTRA_END
239 };
240
241 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
242 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
243 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
244
245 static struct attribute *nhm_mem_events_attrs[] = {
246 EVENT_PTR(mem_ld_nhm),
247 NULL,
248 };
249
250 /*
251 * topdown events for Intel Core CPUs.
252 *
253 * The events are all in slots, which is a free slot in a 4 wide
254 * pipeline. Some events are already reported in slots, for cycle
255 * events we multiply by the pipeline width (4).
256 *
257 * With Hyper Threading on, topdown metrics are either summed or averaged
258 * between the threads of a core: (count_t0 + count_t1).
259 *
260 * For the average case the metric is always scaled to pipeline width,
261 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
262 */
263
264 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
265 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
266 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
267 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
268 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
269 "event=0xe,umask=0x1"); /* uops_issued.any */
270 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
271 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
272 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
273 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
274 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
275 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
276 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
277 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
278 "4", "2");
279
280 static struct attribute *snb_events_attrs[] = {
281 EVENT_PTR(td_slots_issued),
282 EVENT_PTR(td_slots_retired),
283 EVENT_PTR(td_fetch_bubbles),
284 EVENT_PTR(td_total_slots),
285 EVENT_PTR(td_total_slots_scale),
286 EVENT_PTR(td_recovery_bubbles),
287 EVENT_PTR(td_recovery_bubbles_scale),
288 NULL,
289 };
290
291 static struct attribute *snb_mem_events_attrs[] = {
292 EVENT_PTR(mem_ld_snb),
293 EVENT_PTR(mem_st_snb),
294 NULL,
295 };
296
297 static struct event_constraint intel_hsw_event_constraints[] = {
298 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
299 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
300 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
301 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
302 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
303 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
304 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
305 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
306 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
307 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
308 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
309 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
310
311 /*
312 * When HT is off these events can only run on the bottom 4 counters
313 * When HT is on, they are impacted by the HT bug and require EXCL access
314 */
315 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
316 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
317 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
318 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
319
320 EVENT_CONSTRAINT_END
321 };
322
323 static struct event_constraint intel_bdw_event_constraints[] = {
324 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
325 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
326 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
327 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
328 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
329 /*
330 * when HT is off, these can only run on the bottom 4 counters
331 */
332 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
333 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
334 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
335 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
336 EVENT_CONSTRAINT_END
337 };
338
339 static u64 intel_pmu_event_map(int hw_event)
340 {
341 return intel_perfmon_event_map[hw_event];
342 }
343
344 /*
345 * Notes on the events:
346 * - data reads do not include code reads (comparable to earlier tables)
347 * - data counts include speculative execution (except L1 write, dtlb, bpu)
348 * - remote node access includes remote memory, remote cache, remote mmio.
349 * - prefetches are not included in the counts.
350 * - icache miss does not include decoded icache
351 */
352
353 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
354 #define SKL_DEMAND_RFO BIT_ULL(1)
355 #define SKL_ANY_RESPONSE BIT_ULL(16)
356 #define SKL_SUPPLIER_NONE BIT_ULL(17)
357 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
358 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
359 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
360 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
361 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
362 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
363 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
364 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
365 #define SKL_SPL_HIT BIT_ULL(30)
366 #define SKL_SNOOP_NONE BIT_ULL(31)
367 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
368 #define SKL_SNOOP_MISS BIT_ULL(33)
369 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
370 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
371 #define SKL_SNOOP_HITM BIT_ULL(36)
372 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
373 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
374 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
375 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
376 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
377 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
378 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
379 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
380 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
381 SKL_SNOOP_HITM|SKL_SPL_HIT)
382 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
383 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
384 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
385 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
386 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
387
388 static __initconst const u64 skl_hw_cache_event_ids
389 [PERF_COUNT_HW_CACHE_MAX]
390 [PERF_COUNT_HW_CACHE_OP_MAX]
391 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
392 {
393 [ C(L1D ) ] = {
394 [ C(OP_READ) ] = {
395 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
396 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
397 },
398 [ C(OP_WRITE) ] = {
399 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
400 [ C(RESULT_MISS) ] = 0x0,
401 },
402 [ C(OP_PREFETCH) ] = {
403 [ C(RESULT_ACCESS) ] = 0x0,
404 [ C(RESULT_MISS) ] = 0x0,
405 },
406 },
407 [ C(L1I ) ] = {
408 [ C(OP_READ) ] = {
409 [ C(RESULT_ACCESS) ] = 0x0,
410 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
411 },
412 [ C(OP_WRITE) ] = {
413 [ C(RESULT_ACCESS) ] = -1,
414 [ C(RESULT_MISS) ] = -1,
415 },
416 [ C(OP_PREFETCH) ] = {
417 [ C(RESULT_ACCESS) ] = 0x0,
418 [ C(RESULT_MISS) ] = 0x0,
419 },
420 },
421 [ C(LL ) ] = {
422 [ C(OP_READ) ] = {
423 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
424 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
425 },
426 [ C(OP_WRITE) ] = {
427 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
428 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
429 },
430 [ C(OP_PREFETCH) ] = {
431 [ C(RESULT_ACCESS) ] = 0x0,
432 [ C(RESULT_MISS) ] = 0x0,
433 },
434 },
435 [ C(DTLB) ] = {
436 [ C(OP_READ) ] = {
437 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
438 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
439 },
440 [ C(OP_WRITE) ] = {
441 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
442 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
443 },
444 [ C(OP_PREFETCH) ] = {
445 [ C(RESULT_ACCESS) ] = 0x0,
446 [ C(RESULT_MISS) ] = 0x0,
447 },
448 },
449 [ C(ITLB) ] = {
450 [ C(OP_READ) ] = {
451 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
452 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
453 },
454 [ C(OP_WRITE) ] = {
455 [ C(RESULT_ACCESS) ] = -1,
456 [ C(RESULT_MISS) ] = -1,
457 },
458 [ C(OP_PREFETCH) ] = {
459 [ C(RESULT_ACCESS) ] = -1,
460 [ C(RESULT_MISS) ] = -1,
461 },
462 },
463 [ C(BPU ) ] = {
464 [ C(OP_READ) ] = {
465 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
466 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
467 },
468 [ C(OP_WRITE) ] = {
469 [ C(RESULT_ACCESS) ] = -1,
470 [ C(RESULT_MISS) ] = -1,
471 },
472 [ C(OP_PREFETCH) ] = {
473 [ C(RESULT_ACCESS) ] = -1,
474 [ C(RESULT_MISS) ] = -1,
475 },
476 },
477 [ C(NODE) ] = {
478 [ C(OP_READ) ] = {
479 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
480 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
481 },
482 [ C(OP_WRITE) ] = {
483 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
484 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
485 },
486 [ C(OP_PREFETCH) ] = {
487 [ C(RESULT_ACCESS) ] = 0x0,
488 [ C(RESULT_MISS) ] = 0x0,
489 },
490 },
491 };
492
493 static __initconst const u64 skl_hw_cache_extra_regs
494 [PERF_COUNT_HW_CACHE_MAX]
495 [PERF_COUNT_HW_CACHE_OP_MAX]
496 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
497 {
498 [ C(LL ) ] = {
499 [ C(OP_READ) ] = {
500 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
501 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
502 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
503 SKL_L3_MISS|SKL_ANY_SNOOP|
504 SKL_SUPPLIER_NONE,
505 },
506 [ C(OP_WRITE) ] = {
507 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
508 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
509 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
510 SKL_L3_MISS|SKL_ANY_SNOOP|
511 SKL_SUPPLIER_NONE,
512 },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = 0x0,
515 [ C(RESULT_MISS) ] = 0x0,
516 },
517 },
518 [ C(NODE) ] = {
519 [ C(OP_READ) ] = {
520 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
521 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
522 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
523 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
524 },
525 [ C(OP_WRITE) ] = {
526 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
527 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
528 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
529 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
530 },
531 [ C(OP_PREFETCH) ] = {
532 [ C(RESULT_ACCESS) ] = 0x0,
533 [ C(RESULT_MISS) ] = 0x0,
534 },
535 },
536 };
537
538 #define SNB_DMND_DATA_RD (1ULL << 0)
539 #define SNB_DMND_RFO (1ULL << 1)
540 #define SNB_DMND_IFETCH (1ULL << 2)
541 #define SNB_DMND_WB (1ULL << 3)
542 #define SNB_PF_DATA_RD (1ULL << 4)
543 #define SNB_PF_RFO (1ULL << 5)
544 #define SNB_PF_IFETCH (1ULL << 6)
545 #define SNB_LLC_DATA_RD (1ULL << 7)
546 #define SNB_LLC_RFO (1ULL << 8)
547 #define SNB_LLC_IFETCH (1ULL << 9)
548 #define SNB_BUS_LOCKS (1ULL << 10)
549 #define SNB_STRM_ST (1ULL << 11)
550 #define SNB_OTHER (1ULL << 15)
551 #define SNB_RESP_ANY (1ULL << 16)
552 #define SNB_NO_SUPP (1ULL << 17)
553 #define SNB_LLC_HITM (1ULL << 18)
554 #define SNB_LLC_HITE (1ULL << 19)
555 #define SNB_LLC_HITS (1ULL << 20)
556 #define SNB_LLC_HITF (1ULL << 21)
557 #define SNB_LOCAL (1ULL << 22)
558 #define SNB_REMOTE (0xffULL << 23)
559 #define SNB_SNP_NONE (1ULL << 31)
560 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
561 #define SNB_SNP_MISS (1ULL << 33)
562 #define SNB_NO_FWD (1ULL << 34)
563 #define SNB_SNP_FWD (1ULL << 35)
564 #define SNB_HITM (1ULL << 36)
565 #define SNB_NON_DRAM (1ULL << 37)
566
567 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
568 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
569 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
570
571 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
572 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
573 SNB_HITM)
574
575 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
576 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
577
578 #define SNB_L3_ACCESS SNB_RESP_ANY
579 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
580
581 static __initconst const u64 snb_hw_cache_extra_regs
582 [PERF_COUNT_HW_CACHE_MAX]
583 [PERF_COUNT_HW_CACHE_OP_MAX]
584 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
585 {
586 [ C(LL ) ] = {
587 [ C(OP_READ) ] = {
588 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
589 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
590 },
591 [ C(OP_WRITE) ] = {
592 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
593 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
594 },
595 [ C(OP_PREFETCH) ] = {
596 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
597 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
598 },
599 },
600 [ C(NODE) ] = {
601 [ C(OP_READ) ] = {
602 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
603 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
604 },
605 [ C(OP_WRITE) ] = {
606 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
607 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
608 },
609 [ C(OP_PREFETCH) ] = {
610 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
611 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
612 },
613 },
614 };
615
616 static __initconst const u64 snb_hw_cache_event_ids
617 [PERF_COUNT_HW_CACHE_MAX]
618 [PERF_COUNT_HW_CACHE_OP_MAX]
619 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
620 {
621 [ C(L1D) ] = {
622 [ C(OP_READ) ] = {
623 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
624 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
625 },
626 [ C(OP_WRITE) ] = {
627 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
628 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
629 },
630 [ C(OP_PREFETCH) ] = {
631 [ C(RESULT_ACCESS) ] = 0x0,
632 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
633 },
634 },
635 [ C(L1I ) ] = {
636 [ C(OP_READ) ] = {
637 [ C(RESULT_ACCESS) ] = 0x0,
638 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
639 },
640 [ C(OP_WRITE) ] = {
641 [ C(RESULT_ACCESS) ] = -1,
642 [ C(RESULT_MISS) ] = -1,
643 },
644 [ C(OP_PREFETCH) ] = {
645 [ C(RESULT_ACCESS) ] = 0x0,
646 [ C(RESULT_MISS) ] = 0x0,
647 },
648 },
649 [ C(LL ) ] = {
650 [ C(OP_READ) ] = {
651 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
652 [ C(RESULT_ACCESS) ] = 0x01b7,
653 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
654 [ C(RESULT_MISS) ] = 0x01b7,
655 },
656 [ C(OP_WRITE) ] = {
657 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
658 [ C(RESULT_ACCESS) ] = 0x01b7,
659 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
660 [ C(RESULT_MISS) ] = 0x01b7,
661 },
662 [ C(OP_PREFETCH) ] = {
663 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
664 [ C(RESULT_ACCESS) ] = 0x01b7,
665 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
666 [ C(RESULT_MISS) ] = 0x01b7,
667 },
668 },
669 [ C(DTLB) ] = {
670 [ C(OP_READ) ] = {
671 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
672 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
673 },
674 [ C(OP_WRITE) ] = {
675 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
676 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
677 },
678 [ C(OP_PREFETCH) ] = {
679 [ C(RESULT_ACCESS) ] = 0x0,
680 [ C(RESULT_MISS) ] = 0x0,
681 },
682 },
683 [ C(ITLB) ] = {
684 [ C(OP_READ) ] = {
685 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
686 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
687 },
688 [ C(OP_WRITE) ] = {
689 [ C(RESULT_ACCESS) ] = -1,
690 [ C(RESULT_MISS) ] = -1,
691 },
692 [ C(OP_PREFETCH) ] = {
693 [ C(RESULT_ACCESS) ] = -1,
694 [ C(RESULT_MISS) ] = -1,
695 },
696 },
697 [ C(BPU ) ] = {
698 [ C(OP_READ) ] = {
699 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
700 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
701 },
702 [ C(OP_WRITE) ] = {
703 [ C(RESULT_ACCESS) ] = -1,
704 [ C(RESULT_MISS) ] = -1,
705 },
706 [ C(OP_PREFETCH) ] = {
707 [ C(RESULT_ACCESS) ] = -1,
708 [ C(RESULT_MISS) ] = -1,
709 },
710 },
711 [ C(NODE) ] = {
712 [ C(OP_READ) ] = {
713 [ C(RESULT_ACCESS) ] = 0x01b7,
714 [ C(RESULT_MISS) ] = 0x01b7,
715 },
716 [ C(OP_WRITE) ] = {
717 [ C(RESULT_ACCESS) ] = 0x01b7,
718 [ C(RESULT_MISS) ] = 0x01b7,
719 },
720 [ C(OP_PREFETCH) ] = {
721 [ C(RESULT_ACCESS) ] = 0x01b7,
722 [ C(RESULT_MISS) ] = 0x01b7,
723 },
724 },
725
726 };
727
728 /*
729 * Notes on the events:
730 * - data reads do not include code reads (comparable to earlier tables)
731 * - data counts include speculative execution (except L1 write, dtlb, bpu)
732 * - remote node access includes remote memory, remote cache, remote mmio.
733 * - prefetches are not included in the counts because they are not
734 * reliably counted.
735 */
736
737 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
738 #define HSW_DEMAND_RFO BIT_ULL(1)
739 #define HSW_ANY_RESPONSE BIT_ULL(16)
740 #define HSW_SUPPLIER_NONE BIT_ULL(17)
741 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
742 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
743 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
744 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
745 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
746 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
747 HSW_L3_MISS_REMOTE_HOP2P)
748 #define HSW_SNOOP_NONE BIT_ULL(31)
749 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
750 #define HSW_SNOOP_MISS BIT_ULL(33)
751 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
752 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
753 #define HSW_SNOOP_HITM BIT_ULL(36)
754 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
755 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
756 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
757 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
758 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
759 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
760 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
761 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
762 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
763 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
764 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
765
766 #define BDW_L3_MISS_LOCAL BIT(26)
767 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
768 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
769 HSW_L3_MISS_REMOTE_HOP2P)
770
771
772 static __initconst const u64 hsw_hw_cache_event_ids
773 [PERF_COUNT_HW_CACHE_MAX]
774 [PERF_COUNT_HW_CACHE_OP_MAX]
775 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
776 {
777 [ C(L1D ) ] = {
778 [ C(OP_READ) ] = {
779 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
780 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
781 },
782 [ C(OP_WRITE) ] = {
783 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
784 [ C(RESULT_MISS) ] = 0x0,
785 },
786 [ C(OP_PREFETCH) ] = {
787 [ C(RESULT_ACCESS) ] = 0x0,
788 [ C(RESULT_MISS) ] = 0x0,
789 },
790 },
791 [ C(L1I ) ] = {
792 [ C(OP_READ) ] = {
793 [ C(RESULT_ACCESS) ] = 0x0,
794 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
795 },
796 [ C(OP_WRITE) ] = {
797 [ C(RESULT_ACCESS) ] = -1,
798 [ C(RESULT_MISS) ] = -1,
799 },
800 [ C(OP_PREFETCH) ] = {
801 [ C(RESULT_ACCESS) ] = 0x0,
802 [ C(RESULT_MISS) ] = 0x0,
803 },
804 },
805 [ C(LL ) ] = {
806 [ C(OP_READ) ] = {
807 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
808 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
809 },
810 [ C(OP_WRITE) ] = {
811 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
812 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
813 },
814 [ C(OP_PREFETCH) ] = {
815 [ C(RESULT_ACCESS) ] = 0x0,
816 [ C(RESULT_MISS) ] = 0x0,
817 },
818 },
819 [ C(DTLB) ] = {
820 [ C(OP_READ) ] = {
821 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
822 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
823 },
824 [ C(OP_WRITE) ] = {
825 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
826 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
827 },
828 [ C(OP_PREFETCH) ] = {
829 [ C(RESULT_ACCESS) ] = 0x0,
830 [ C(RESULT_MISS) ] = 0x0,
831 },
832 },
833 [ C(ITLB) ] = {
834 [ C(OP_READ) ] = {
835 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
836 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
837 },
838 [ C(OP_WRITE) ] = {
839 [ C(RESULT_ACCESS) ] = -1,
840 [ C(RESULT_MISS) ] = -1,
841 },
842 [ C(OP_PREFETCH) ] = {
843 [ C(RESULT_ACCESS) ] = -1,
844 [ C(RESULT_MISS) ] = -1,
845 },
846 },
847 [ C(BPU ) ] = {
848 [ C(OP_READ) ] = {
849 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
850 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
851 },
852 [ C(OP_WRITE) ] = {
853 [ C(RESULT_ACCESS) ] = -1,
854 [ C(RESULT_MISS) ] = -1,
855 },
856 [ C(OP_PREFETCH) ] = {
857 [ C(RESULT_ACCESS) ] = -1,
858 [ C(RESULT_MISS) ] = -1,
859 },
860 },
861 [ C(NODE) ] = {
862 [ C(OP_READ) ] = {
863 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
864 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
865 },
866 [ C(OP_WRITE) ] = {
867 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
868 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
869 },
870 [ C(OP_PREFETCH) ] = {
871 [ C(RESULT_ACCESS) ] = 0x0,
872 [ C(RESULT_MISS) ] = 0x0,
873 },
874 },
875 };
876
877 static __initconst const u64 hsw_hw_cache_extra_regs
878 [PERF_COUNT_HW_CACHE_MAX]
879 [PERF_COUNT_HW_CACHE_OP_MAX]
880 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
881 {
882 [ C(LL ) ] = {
883 [ C(OP_READ) ] = {
884 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
885 HSW_LLC_ACCESS,
886 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
887 HSW_L3_MISS|HSW_ANY_SNOOP,
888 },
889 [ C(OP_WRITE) ] = {
890 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
891 HSW_LLC_ACCESS,
892 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
893 HSW_L3_MISS|HSW_ANY_SNOOP,
894 },
895 [ C(OP_PREFETCH) ] = {
896 [ C(RESULT_ACCESS) ] = 0x0,
897 [ C(RESULT_MISS) ] = 0x0,
898 },
899 },
900 [ C(NODE) ] = {
901 [ C(OP_READ) ] = {
902 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
903 HSW_L3_MISS_LOCAL_DRAM|
904 HSW_SNOOP_DRAM,
905 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
906 HSW_L3_MISS_REMOTE|
907 HSW_SNOOP_DRAM,
908 },
909 [ C(OP_WRITE) ] = {
910 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
911 HSW_L3_MISS_LOCAL_DRAM|
912 HSW_SNOOP_DRAM,
913 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
914 HSW_L3_MISS_REMOTE|
915 HSW_SNOOP_DRAM,
916 },
917 [ C(OP_PREFETCH) ] = {
918 [ C(RESULT_ACCESS) ] = 0x0,
919 [ C(RESULT_MISS) ] = 0x0,
920 },
921 },
922 };
923
924 static __initconst const u64 westmere_hw_cache_event_ids
925 [PERF_COUNT_HW_CACHE_MAX]
926 [PERF_COUNT_HW_CACHE_OP_MAX]
927 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
928 {
929 [ C(L1D) ] = {
930 [ C(OP_READ) ] = {
931 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
932 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
933 },
934 [ C(OP_WRITE) ] = {
935 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
936 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
937 },
938 [ C(OP_PREFETCH) ] = {
939 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
940 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
941 },
942 },
943 [ C(L1I ) ] = {
944 [ C(OP_READ) ] = {
945 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
946 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
947 },
948 [ C(OP_WRITE) ] = {
949 [ C(RESULT_ACCESS) ] = -1,
950 [ C(RESULT_MISS) ] = -1,
951 },
952 [ C(OP_PREFETCH) ] = {
953 [ C(RESULT_ACCESS) ] = 0x0,
954 [ C(RESULT_MISS) ] = 0x0,
955 },
956 },
957 [ C(LL ) ] = {
958 [ C(OP_READ) ] = {
959 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
960 [ C(RESULT_ACCESS) ] = 0x01b7,
961 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
962 [ C(RESULT_MISS) ] = 0x01b7,
963 },
964 /*
965 * Use RFO, not WRITEBACK, because a write miss would typically occur
966 * on RFO.
967 */
968 [ C(OP_WRITE) ] = {
969 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
970 [ C(RESULT_ACCESS) ] = 0x01b7,
971 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
972 [ C(RESULT_MISS) ] = 0x01b7,
973 },
974 [ C(OP_PREFETCH) ] = {
975 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
976 [ C(RESULT_ACCESS) ] = 0x01b7,
977 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
978 [ C(RESULT_MISS) ] = 0x01b7,
979 },
980 },
981 [ C(DTLB) ] = {
982 [ C(OP_READ) ] = {
983 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
984 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
985 },
986 [ C(OP_WRITE) ] = {
987 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
988 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
989 },
990 [ C(OP_PREFETCH) ] = {
991 [ C(RESULT_ACCESS) ] = 0x0,
992 [ C(RESULT_MISS) ] = 0x0,
993 },
994 },
995 [ C(ITLB) ] = {
996 [ C(OP_READ) ] = {
997 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
998 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
999 },
1000 [ C(OP_WRITE) ] = {
1001 [ C(RESULT_ACCESS) ] = -1,
1002 [ C(RESULT_MISS) ] = -1,
1003 },
1004 [ C(OP_PREFETCH) ] = {
1005 [ C(RESULT_ACCESS) ] = -1,
1006 [ C(RESULT_MISS) ] = -1,
1007 },
1008 },
1009 [ C(BPU ) ] = {
1010 [ C(OP_READ) ] = {
1011 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1012 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1013 },
1014 [ C(OP_WRITE) ] = {
1015 [ C(RESULT_ACCESS) ] = -1,
1016 [ C(RESULT_MISS) ] = -1,
1017 },
1018 [ C(OP_PREFETCH) ] = {
1019 [ C(RESULT_ACCESS) ] = -1,
1020 [ C(RESULT_MISS) ] = -1,
1021 },
1022 },
1023 [ C(NODE) ] = {
1024 [ C(OP_READ) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x01b7,
1026 [ C(RESULT_MISS) ] = 0x01b7,
1027 },
1028 [ C(OP_WRITE) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x01b7,
1030 [ C(RESULT_MISS) ] = 0x01b7,
1031 },
1032 [ C(OP_PREFETCH) ] = {
1033 [ C(RESULT_ACCESS) ] = 0x01b7,
1034 [ C(RESULT_MISS) ] = 0x01b7,
1035 },
1036 },
1037 };
1038
1039 /*
1040 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1041 * See IA32 SDM Vol 3B 30.6.1.3
1042 */
1043
1044 #define NHM_DMND_DATA_RD (1 << 0)
1045 #define NHM_DMND_RFO (1 << 1)
1046 #define NHM_DMND_IFETCH (1 << 2)
1047 #define NHM_DMND_WB (1 << 3)
1048 #define NHM_PF_DATA_RD (1 << 4)
1049 #define NHM_PF_DATA_RFO (1 << 5)
1050 #define NHM_PF_IFETCH (1 << 6)
1051 #define NHM_OFFCORE_OTHER (1 << 7)
1052 #define NHM_UNCORE_HIT (1 << 8)
1053 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1054 #define NHM_OTHER_CORE_HITM (1 << 10)
1055 /* reserved */
1056 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1057 #define NHM_REMOTE_DRAM (1 << 13)
1058 #define NHM_LOCAL_DRAM (1 << 14)
1059 #define NHM_NON_DRAM (1 << 15)
1060
1061 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1062 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1063
1064 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1065 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1066 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1067
1068 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1069 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1070 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1071
1072 static __initconst const u64 nehalem_hw_cache_extra_regs
1073 [PERF_COUNT_HW_CACHE_MAX]
1074 [PERF_COUNT_HW_CACHE_OP_MAX]
1075 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1076 {
1077 [ C(LL ) ] = {
1078 [ C(OP_READ) ] = {
1079 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1080 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1081 },
1082 [ C(OP_WRITE) ] = {
1083 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1084 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1085 },
1086 [ C(OP_PREFETCH) ] = {
1087 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1088 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1089 },
1090 },
1091 [ C(NODE) ] = {
1092 [ C(OP_READ) ] = {
1093 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1094 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1095 },
1096 [ C(OP_WRITE) ] = {
1097 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1098 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1099 },
1100 [ C(OP_PREFETCH) ] = {
1101 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1102 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1103 },
1104 },
1105 };
1106
1107 static __initconst const u64 nehalem_hw_cache_event_ids
1108 [PERF_COUNT_HW_CACHE_MAX]
1109 [PERF_COUNT_HW_CACHE_OP_MAX]
1110 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1111 {
1112 [ C(L1D) ] = {
1113 [ C(OP_READ) ] = {
1114 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1115 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1116 },
1117 [ C(OP_WRITE) ] = {
1118 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1119 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1120 },
1121 [ C(OP_PREFETCH) ] = {
1122 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1123 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1124 },
1125 },
1126 [ C(L1I ) ] = {
1127 [ C(OP_READ) ] = {
1128 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1129 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1130 },
1131 [ C(OP_WRITE) ] = {
1132 [ C(RESULT_ACCESS) ] = -1,
1133 [ C(RESULT_MISS) ] = -1,
1134 },
1135 [ C(OP_PREFETCH) ] = {
1136 [ C(RESULT_ACCESS) ] = 0x0,
1137 [ C(RESULT_MISS) ] = 0x0,
1138 },
1139 },
1140 [ C(LL ) ] = {
1141 [ C(OP_READ) ] = {
1142 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1143 [ C(RESULT_ACCESS) ] = 0x01b7,
1144 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1145 [ C(RESULT_MISS) ] = 0x01b7,
1146 },
1147 /*
1148 * Use RFO, not WRITEBACK, because a write miss would typically occur
1149 * on RFO.
1150 */
1151 [ C(OP_WRITE) ] = {
1152 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1153 [ C(RESULT_ACCESS) ] = 0x01b7,
1154 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1155 [ C(RESULT_MISS) ] = 0x01b7,
1156 },
1157 [ C(OP_PREFETCH) ] = {
1158 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1159 [ C(RESULT_ACCESS) ] = 0x01b7,
1160 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1161 [ C(RESULT_MISS) ] = 0x01b7,
1162 },
1163 },
1164 [ C(DTLB) ] = {
1165 [ C(OP_READ) ] = {
1166 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1167 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1168 },
1169 [ C(OP_WRITE) ] = {
1170 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1171 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1172 },
1173 [ C(OP_PREFETCH) ] = {
1174 [ C(RESULT_ACCESS) ] = 0x0,
1175 [ C(RESULT_MISS) ] = 0x0,
1176 },
1177 },
1178 [ C(ITLB) ] = {
1179 [ C(OP_READ) ] = {
1180 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1181 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1182 },
1183 [ C(OP_WRITE) ] = {
1184 [ C(RESULT_ACCESS) ] = -1,
1185 [ C(RESULT_MISS) ] = -1,
1186 },
1187 [ C(OP_PREFETCH) ] = {
1188 [ C(RESULT_ACCESS) ] = -1,
1189 [ C(RESULT_MISS) ] = -1,
1190 },
1191 },
1192 [ C(BPU ) ] = {
1193 [ C(OP_READ) ] = {
1194 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1195 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1196 },
1197 [ C(OP_WRITE) ] = {
1198 [ C(RESULT_ACCESS) ] = -1,
1199 [ C(RESULT_MISS) ] = -1,
1200 },
1201 [ C(OP_PREFETCH) ] = {
1202 [ C(RESULT_ACCESS) ] = -1,
1203 [ C(RESULT_MISS) ] = -1,
1204 },
1205 },
1206 [ C(NODE) ] = {
1207 [ C(OP_READ) ] = {
1208 [ C(RESULT_ACCESS) ] = 0x01b7,
1209 [ C(RESULT_MISS) ] = 0x01b7,
1210 },
1211 [ C(OP_WRITE) ] = {
1212 [ C(RESULT_ACCESS) ] = 0x01b7,
1213 [ C(RESULT_MISS) ] = 0x01b7,
1214 },
1215 [ C(OP_PREFETCH) ] = {
1216 [ C(RESULT_ACCESS) ] = 0x01b7,
1217 [ C(RESULT_MISS) ] = 0x01b7,
1218 },
1219 },
1220 };
1221
1222 static __initconst const u64 core2_hw_cache_event_ids
1223 [PERF_COUNT_HW_CACHE_MAX]
1224 [PERF_COUNT_HW_CACHE_OP_MAX]
1225 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1226 {
1227 [ C(L1D) ] = {
1228 [ C(OP_READ) ] = {
1229 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1230 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1231 },
1232 [ C(OP_WRITE) ] = {
1233 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1234 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1235 },
1236 [ C(OP_PREFETCH) ] = {
1237 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1238 [ C(RESULT_MISS) ] = 0,
1239 },
1240 },
1241 [ C(L1I ) ] = {
1242 [ C(OP_READ) ] = {
1243 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1244 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1245 },
1246 [ C(OP_WRITE) ] = {
1247 [ C(RESULT_ACCESS) ] = -1,
1248 [ C(RESULT_MISS) ] = -1,
1249 },
1250 [ C(OP_PREFETCH) ] = {
1251 [ C(RESULT_ACCESS) ] = 0,
1252 [ C(RESULT_MISS) ] = 0,
1253 },
1254 },
1255 [ C(LL ) ] = {
1256 [ C(OP_READ) ] = {
1257 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1258 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1259 },
1260 [ C(OP_WRITE) ] = {
1261 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1262 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1263 },
1264 [ C(OP_PREFETCH) ] = {
1265 [ C(RESULT_ACCESS) ] = 0,
1266 [ C(RESULT_MISS) ] = 0,
1267 },
1268 },
1269 [ C(DTLB) ] = {
1270 [ C(OP_READ) ] = {
1271 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1272 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1273 },
1274 [ C(OP_WRITE) ] = {
1275 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1276 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1277 },
1278 [ C(OP_PREFETCH) ] = {
1279 [ C(RESULT_ACCESS) ] = 0,
1280 [ C(RESULT_MISS) ] = 0,
1281 },
1282 },
1283 [ C(ITLB) ] = {
1284 [ C(OP_READ) ] = {
1285 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1286 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1287 },
1288 [ C(OP_WRITE) ] = {
1289 [ C(RESULT_ACCESS) ] = -1,
1290 [ C(RESULT_MISS) ] = -1,
1291 },
1292 [ C(OP_PREFETCH) ] = {
1293 [ C(RESULT_ACCESS) ] = -1,
1294 [ C(RESULT_MISS) ] = -1,
1295 },
1296 },
1297 [ C(BPU ) ] = {
1298 [ C(OP_READ) ] = {
1299 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1300 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1301 },
1302 [ C(OP_WRITE) ] = {
1303 [ C(RESULT_ACCESS) ] = -1,
1304 [ C(RESULT_MISS) ] = -1,
1305 },
1306 [ C(OP_PREFETCH) ] = {
1307 [ C(RESULT_ACCESS) ] = -1,
1308 [ C(RESULT_MISS) ] = -1,
1309 },
1310 },
1311 };
1312
1313 static __initconst const u64 atom_hw_cache_event_ids
1314 [PERF_COUNT_HW_CACHE_MAX]
1315 [PERF_COUNT_HW_CACHE_OP_MAX]
1316 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1317 {
1318 [ C(L1D) ] = {
1319 [ C(OP_READ) ] = {
1320 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1321 [ C(RESULT_MISS) ] = 0,
1322 },
1323 [ C(OP_WRITE) ] = {
1324 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1325 [ C(RESULT_MISS) ] = 0,
1326 },
1327 [ C(OP_PREFETCH) ] = {
1328 [ C(RESULT_ACCESS) ] = 0x0,
1329 [ C(RESULT_MISS) ] = 0,
1330 },
1331 },
1332 [ C(L1I ) ] = {
1333 [ C(OP_READ) ] = {
1334 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1335 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1336 },
1337 [ C(OP_WRITE) ] = {
1338 [ C(RESULT_ACCESS) ] = -1,
1339 [ C(RESULT_MISS) ] = -1,
1340 },
1341 [ C(OP_PREFETCH) ] = {
1342 [ C(RESULT_ACCESS) ] = 0,
1343 [ C(RESULT_MISS) ] = 0,
1344 },
1345 },
1346 [ C(LL ) ] = {
1347 [ C(OP_READ) ] = {
1348 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1349 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1350 },
1351 [ C(OP_WRITE) ] = {
1352 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1353 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1354 },
1355 [ C(OP_PREFETCH) ] = {
1356 [ C(RESULT_ACCESS) ] = 0,
1357 [ C(RESULT_MISS) ] = 0,
1358 },
1359 },
1360 [ C(DTLB) ] = {
1361 [ C(OP_READ) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1363 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1364 },
1365 [ C(OP_WRITE) ] = {
1366 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1367 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1368 },
1369 [ C(OP_PREFETCH) ] = {
1370 [ C(RESULT_ACCESS) ] = 0,
1371 [ C(RESULT_MISS) ] = 0,
1372 },
1373 },
1374 [ C(ITLB) ] = {
1375 [ C(OP_READ) ] = {
1376 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1377 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1378 },
1379 [ C(OP_WRITE) ] = {
1380 [ C(RESULT_ACCESS) ] = -1,
1381 [ C(RESULT_MISS) ] = -1,
1382 },
1383 [ C(OP_PREFETCH) ] = {
1384 [ C(RESULT_ACCESS) ] = -1,
1385 [ C(RESULT_MISS) ] = -1,
1386 },
1387 },
1388 [ C(BPU ) ] = {
1389 [ C(OP_READ) ] = {
1390 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1391 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1392 },
1393 [ C(OP_WRITE) ] = {
1394 [ C(RESULT_ACCESS) ] = -1,
1395 [ C(RESULT_MISS) ] = -1,
1396 },
1397 [ C(OP_PREFETCH) ] = {
1398 [ C(RESULT_ACCESS) ] = -1,
1399 [ C(RESULT_MISS) ] = -1,
1400 },
1401 },
1402 };
1403
1404 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1405 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1406 /* no_alloc_cycles.not_delivered */
1407 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1408 "event=0xca,umask=0x50");
1409 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1410 /* uops_retired.all */
1411 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1412 "event=0xc2,umask=0x10");
1413 /* uops_retired.all */
1414 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1415 "event=0xc2,umask=0x10");
1416
1417 static struct attribute *slm_events_attrs[] = {
1418 EVENT_PTR(td_total_slots_slm),
1419 EVENT_PTR(td_total_slots_scale_slm),
1420 EVENT_PTR(td_fetch_bubbles_slm),
1421 EVENT_PTR(td_fetch_bubbles_scale_slm),
1422 EVENT_PTR(td_slots_issued_slm),
1423 EVENT_PTR(td_slots_retired_slm),
1424 NULL
1425 };
1426
1427 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1428 {
1429 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1430 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1431 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1432 EVENT_EXTRA_END
1433 };
1434
1435 #define SLM_DMND_READ SNB_DMND_DATA_RD
1436 #define SLM_DMND_WRITE SNB_DMND_RFO
1437 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1438
1439 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1440 #define SLM_LLC_ACCESS SNB_RESP_ANY
1441 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1442
1443 static __initconst const u64 slm_hw_cache_extra_regs
1444 [PERF_COUNT_HW_CACHE_MAX]
1445 [PERF_COUNT_HW_CACHE_OP_MAX]
1446 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1447 {
1448 [ C(LL ) ] = {
1449 [ C(OP_READ) ] = {
1450 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1451 [ C(RESULT_MISS) ] = 0,
1452 },
1453 [ C(OP_WRITE) ] = {
1454 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1455 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1456 },
1457 [ C(OP_PREFETCH) ] = {
1458 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1459 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1460 },
1461 },
1462 };
1463
1464 static __initconst const u64 slm_hw_cache_event_ids
1465 [PERF_COUNT_HW_CACHE_MAX]
1466 [PERF_COUNT_HW_CACHE_OP_MAX]
1467 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1468 {
1469 [ C(L1D) ] = {
1470 [ C(OP_READ) ] = {
1471 [ C(RESULT_ACCESS) ] = 0,
1472 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1473 },
1474 [ C(OP_WRITE) ] = {
1475 [ C(RESULT_ACCESS) ] = 0,
1476 [ C(RESULT_MISS) ] = 0,
1477 },
1478 [ C(OP_PREFETCH) ] = {
1479 [ C(RESULT_ACCESS) ] = 0,
1480 [ C(RESULT_MISS) ] = 0,
1481 },
1482 },
1483 [ C(L1I ) ] = {
1484 [ C(OP_READ) ] = {
1485 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1486 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1487 },
1488 [ C(OP_WRITE) ] = {
1489 [ C(RESULT_ACCESS) ] = -1,
1490 [ C(RESULT_MISS) ] = -1,
1491 },
1492 [ C(OP_PREFETCH) ] = {
1493 [ C(RESULT_ACCESS) ] = 0,
1494 [ C(RESULT_MISS) ] = 0,
1495 },
1496 },
1497 [ C(LL ) ] = {
1498 [ C(OP_READ) ] = {
1499 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1500 [ C(RESULT_ACCESS) ] = 0x01b7,
1501 [ C(RESULT_MISS) ] = 0,
1502 },
1503 [ C(OP_WRITE) ] = {
1504 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1505 [ C(RESULT_ACCESS) ] = 0x01b7,
1506 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1507 [ C(RESULT_MISS) ] = 0x01b7,
1508 },
1509 [ C(OP_PREFETCH) ] = {
1510 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1511 [ C(RESULT_ACCESS) ] = 0x01b7,
1512 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1513 [ C(RESULT_MISS) ] = 0x01b7,
1514 },
1515 },
1516 [ C(DTLB) ] = {
1517 [ C(OP_READ) ] = {
1518 [ C(RESULT_ACCESS) ] = 0,
1519 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1520 },
1521 [ C(OP_WRITE) ] = {
1522 [ C(RESULT_ACCESS) ] = 0,
1523 [ C(RESULT_MISS) ] = 0,
1524 },
1525 [ C(OP_PREFETCH) ] = {
1526 [ C(RESULT_ACCESS) ] = 0,
1527 [ C(RESULT_MISS) ] = 0,
1528 },
1529 },
1530 [ C(ITLB) ] = {
1531 [ C(OP_READ) ] = {
1532 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1533 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1534 },
1535 [ C(OP_WRITE) ] = {
1536 [ C(RESULT_ACCESS) ] = -1,
1537 [ C(RESULT_MISS) ] = -1,
1538 },
1539 [ C(OP_PREFETCH) ] = {
1540 [ C(RESULT_ACCESS) ] = -1,
1541 [ C(RESULT_MISS) ] = -1,
1542 },
1543 },
1544 [ C(BPU ) ] = {
1545 [ C(OP_READ) ] = {
1546 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1547 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1548 },
1549 [ C(OP_WRITE) ] = {
1550 [ C(RESULT_ACCESS) ] = -1,
1551 [ C(RESULT_MISS) ] = -1,
1552 },
1553 [ C(OP_PREFETCH) ] = {
1554 [ C(RESULT_ACCESS) ] = -1,
1555 [ C(RESULT_MISS) ] = -1,
1556 },
1557 },
1558 };
1559
1560 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1561 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1562 /* UOPS_NOT_DELIVERED.ANY */
1563 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1564 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1565 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1566 /* UOPS_RETIRED.ANY */
1567 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1568 /* UOPS_ISSUED.ANY */
1569 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1570
1571 static struct attribute *glm_events_attrs[] = {
1572 EVENT_PTR(td_total_slots_glm),
1573 EVENT_PTR(td_total_slots_scale_glm),
1574 EVENT_PTR(td_fetch_bubbles_glm),
1575 EVENT_PTR(td_recovery_bubbles_glm),
1576 EVENT_PTR(td_slots_issued_glm),
1577 EVENT_PTR(td_slots_retired_glm),
1578 NULL
1579 };
1580
1581 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1582 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1583 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1584 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1585 EVENT_EXTRA_END
1586 };
1587
1588 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1589 #define GLM_DEMAND_RFO BIT_ULL(1)
1590 #define GLM_ANY_RESPONSE BIT_ULL(16)
1591 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1592 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1593 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1594 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1595 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1596 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1597 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1598
1599 static __initconst const u64 glm_hw_cache_event_ids
1600 [PERF_COUNT_HW_CACHE_MAX]
1601 [PERF_COUNT_HW_CACHE_OP_MAX]
1602 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1603 [C(L1D)] = {
1604 [C(OP_READ)] = {
1605 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1606 [C(RESULT_MISS)] = 0x0,
1607 },
1608 [C(OP_WRITE)] = {
1609 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1610 [C(RESULT_MISS)] = 0x0,
1611 },
1612 [C(OP_PREFETCH)] = {
1613 [C(RESULT_ACCESS)] = 0x0,
1614 [C(RESULT_MISS)] = 0x0,
1615 },
1616 },
1617 [C(L1I)] = {
1618 [C(OP_READ)] = {
1619 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1620 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1621 },
1622 [C(OP_WRITE)] = {
1623 [C(RESULT_ACCESS)] = -1,
1624 [C(RESULT_MISS)] = -1,
1625 },
1626 [C(OP_PREFETCH)] = {
1627 [C(RESULT_ACCESS)] = 0x0,
1628 [C(RESULT_MISS)] = 0x0,
1629 },
1630 },
1631 [C(LL)] = {
1632 [C(OP_READ)] = {
1633 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1634 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1635 },
1636 [C(OP_WRITE)] = {
1637 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1638 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1639 },
1640 [C(OP_PREFETCH)] = {
1641 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1642 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1643 },
1644 },
1645 [C(DTLB)] = {
1646 [C(OP_READ)] = {
1647 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1648 [C(RESULT_MISS)] = 0x0,
1649 },
1650 [C(OP_WRITE)] = {
1651 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1652 [C(RESULT_MISS)] = 0x0,
1653 },
1654 [C(OP_PREFETCH)] = {
1655 [C(RESULT_ACCESS)] = 0x0,
1656 [C(RESULT_MISS)] = 0x0,
1657 },
1658 },
1659 [C(ITLB)] = {
1660 [C(OP_READ)] = {
1661 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1662 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1663 },
1664 [C(OP_WRITE)] = {
1665 [C(RESULT_ACCESS)] = -1,
1666 [C(RESULT_MISS)] = -1,
1667 },
1668 [C(OP_PREFETCH)] = {
1669 [C(RESULT_ACCESS)] = -1,
1670 [C(RESULT_MISS)] = -1,
1671 },
1672 },
1673 [C(BPU)] = {
1674 [C(OP_READ)] = {
1675 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1676 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1677 },
1678 [C(OP_WRITE)] = {
1679 [C(RESULT_ACCESS)] = -1,
1680 [C(RESULT_MISS)] = -1,
1681 },
1682 [C(OP_PREFETCH)] = {
1683 [C(RESULT_ACCESS)] = -1,
1684 [C(RESULT_MISS)] = -1,
1685 },
1686 },
1687 };
1688
1689 static __initconst const u64 glm_hw_cache_extra_regs
1690 [PERF_COUNT_HW_CACHE_MAX]
1691 [PERF_COUNT_HW_CACHE_OP_MAX]
1692 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1693 [C(LL)] = {
1694 [C(OP_READ)] = {
1695 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1696 GLM_LLC_ACCESS,
1697 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1698 GLM_LLC_MISS,
1699 },
1700 [C(OP_WRITE)] = {
1701 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1702 GLM_LLC_ACCESS,
1703 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1704 GLM_LLC_MISS,
1705 },
1706 [C(OP_PREFETCH)] = {
1707 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1708 GLM_LLC_ACCESS,
1709 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1710 GLM_LLC_MISS,
1711 },
1712 },
1713 };
1714
1715 static __initconst const u64 glp_hw_cache_event_ids
1716 [PERF_COUNT_HW_CACHE_MAX]
1717 [PERF_COUNT_HW_CACHE_OP_MAX]
1718 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1719 [C(L1D)] = {
1720 [C(OP_READ)] = {
1721 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1722 [C(RESULT_MISS)] = 0x0,
1723 },
1724 [C(OP_WRITE)] = {
1725 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1726 [C(RESULT_MISS)] = 0x0,
1727 },
1728 [C(OP_PREFETCH)] = {
1729 [C(RESULT_ACCESS)] = 0x0,
1730 [C(RESULT_MISS)] = 0x0,
1731 },
1732 },
1733 [C(L1I)] = {
1734 [C(OP_READ)] = {
1735 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1736 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1737 },
1738 [C(OP_WRITE)] = {
1739 [C(RESULT_ACCESS)] = -1,
1740 [C(RESULT_MISS)] = -1,
1741 },
1742 [C(OP_PREFETCH)] = {
1743 [C(RESULT_ACCESS)] = 0x0,
1744 [C(RESULT_MISS)] = 0x0,
1745 },
1746 },
1747 [C(LL)] = {
1748 [C(OP_READ)] = {
1749 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1750 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1751 },
1752 [C(OP_WRITE)] = {
1753 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1754 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1755 },
1756 [C(OP_PREFETCH)] = {
1757 [C(RESULT_ACCESS)] = 0x0,
1758 [C(RESULT_MISS)] = 0x0,
1759 },
1760 },
1761 [C(DTLB)] = {
1762 [C(OP_READ)] = {
1763 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1764 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1765 },
1766 [C(OP_WRITE)] = {
1767 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1768 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1769 },
1770 [C(OP_PREFETCH)] = {
1771 [C(RESULT_ACCESS)] = 0x0,
1772 [C(RESULT_MISS)] = 0x0,
1773 },
1774 },
1775 [C(ITLB)] = {
1776 [C(OP_READ)] = {
1777 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1778 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1779 },
1780 [C(OP_WRITE)] = {
1781 [C(RESULT_ACCESS)] = -1,
1782 [C(RESULT_MISS)] = -1,
1783 },
1784 [C(OP_PREFETCH)] = {
1785 [C(RESULT_ACCESS)] = -1,
1786 [C(RESULT_MISS)] = -1,
1787 },
1788 },
1789 [C(BPU)] = {
1790 [C(OP_READ)] = {
1791 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1792 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1793 },
1794 [C(OP_WRITE)] = {
1795 [C(RESULT_ACCESS)] = -1,
1796 [C(RESULT_MISS)] = -1,
1797 },
1798 [C(OP_PREFETCH)] = {
1799 [C(RESULT_ACCESS)] = -1,
1800 [C(RESULT_MISS)] = -1,
1801 },
1802 },
1803 };
1804
1805 static __initconst const u64 glp_hw_cache_extra_regs
1806 [PERF_COUNT_HW_CACHE_MAX]
1807 [PERF_COUNT_HW_CACHE_OP_MAX]
1808 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1809 [C(LL)] = {
1810 [C(OP_READ)] = {
1811 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1812 GLM_LLC_ACCESS,
1813 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1814 GLM_LLC_MISS,
1815 },
1816 [C(OP_WRITE)] = {
1817 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1818 GLM_LLC_ACCESS,
1819 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1820 GLM_LLC_MISS,
1821 },
1822 [C(OP_PREFETCH)] = {
1823 [C(RESULT_ACCESS)] = 0x0,
1824 [C(RESULT_MISS)] = 0x0,
1825 },
1826 },
1827 };
1828
1829 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1830 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1831 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
1832 #define KNL_MCDRAM_FAR BIT_ULL(22)
1833 #define KNL_DDR_LOCAL BIT_ULL(23)
1834 #define KNL_DDR_FAR BIT_ULL(24)
1835 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1836 KNL_DDR_LOCAL | KNL_DDR_FAR)
1837 #define KNL_L2_READ SLM_DMND_READ
1838 #define KNL_L2_WRITE SLM_DMND_WRITE
1839 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1840 #define KNL_L2_ACCESS SLM_LLC_ACCESS
1841 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1842 KNL_DRAM_ANY | SNB_SNP_ANY | \
1843 SNB_NON_DRAM)
1844
1845 static __initconst const u64 knl_hw_cache_extra_regs
1846 [PERF_COUNT_HW_CACHE_MAX]
1847 [PERF_COUNT_HW_CACHE_OP_MAX]
1848 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1849 [C(LL)] = {
1850 [C(OP_READ)] = {
1851 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1852 [C(RESULT_MISS)] = 0,
1853 },
1854 [C(OP_WRITE)] = {
1855 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1856 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1857 },
1858 [C(OP_PREFETCH)] = {
1859 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1860 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1861 },
1862 },
1863 };
1864
1865 /*
1866 * Used from PMIs where the LBRs are already disabled.
1867 *
1868 * This function could be called consecutively. It is required to remain in
1869 * disabled state if called consecutively.
1870 *
1871 * During consecutive calls, the same disable value will be written to related
1872 * registers, so the PMU state remains unchanged.
1873 *
1874 * intel_bts events don't coexist with intel PMU's BTS events because of
1875 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
1876 * disabled around intel PMU's event batching etc, only inside the PMI handler.
1877 */
1878 static void __intel_pmu_disable_all(void)
1879 {
1880 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1881
1882 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1883
1884 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1885 intel_pmu_disable_bts();
1886
1887 intel_pmu_pebs_disable_all();
1888 }
1889
1890 static void intel_pmu_disable_all(void)
1891 {
1892 __intel_pmu_disable_all();
1893 intel_pmu_lbr_disable_all();
1894 }
1895
1896 static void __intel_pmu_enable_all(int added, bool pmi)
1897 {
1898 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1899
1900 intel_pmu_pebs_enable_all();
1901 intel_pmu_lbr_enable_all(pmi);
1902 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1903 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1904
1905 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1906 struct perf_event *event =
1907 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1908
1909 if (WARN_ON_ONCE(!event))
1910 return;
1911
1912 intel_pmu_enable_bts(event->hw.config);
1913 }
1914 }
1915
1916 static void intel_pmu_enable_all(int added)
1917 {
1918 __intel_pmu_enable_all(added, false);
1919 }
1920
1921 /*
1922 * Workaround for:
1923 * Intel Errata AAK100 (model 26)
1924 * Intel Errata AAP53 (model 30)
1925 * Intel Errata BD53 (model 44)
1926 *
1927 * The official story:
1928 * These chips need to be 'reset' when adding counters by programming the
1929 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1930 * in sequence on the same PMC or on different PMCs.
1931 *
1932 * In practise it appears some of these events do in fact count, and
1933 * we need to programm all 4 events.
1934 */
1935 static void intel_pmu_nhm_workaround(void)
1936 {
1937 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1938 static const unsigned long nhm_magic[4] = {
1939 0x4300B5,
1940 0x4300D2,
1941 0x4300B1,
1942 0x4300B1
1943 };
1944 struct perf_event *event;
1945 int i;
1946
1947 /*
1948 * The Errata requires below steps:
1949 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1950 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1951 * the corresponding PMCx;
1952 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1953 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1954 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1955 */
1956
1957 /*
1958 * The real steps we choose are a little different from above.
1959 * A) To reduce MSR operations, we don't run step 1) as they
1960 * are already cleared before this function is called;
1961 * B) Call x86_perf_event_update to save PMCx before configuring
1962 * PERFEVTSELx with magic number;
1963 * C) With step 5), we do clear only when the PERFEVTSELx is
1964 * not used currently.
1965 * D) Call x86_perf_event_set_period to restore PMCx;
1966 */
1967
1968 /* We always operate 4 pairs of PERF Counters */
1969 for (i = 0; i < 4; i++) {
1970 event = cpuc->events[i];
1971 if (event)
1972 x86_perf_event_update(event);
1973 }
1974
1975 for (i = 0; i < 4; i++) {
1976 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1977 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1978 }
1979
1980 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1981 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1982
1983 for (i = 0; i < 4; i++) {
1984 event = cpuc->events[i];
1985
1986 if (event) {
1987 x86_perf_event_set_period(event);
1988 __x86_pmu_enable_event(&event->hw,
1989 ARCH_PERFMON_EVENTSEL_ENABLE);
1990 } else
1991 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1992 }
1993 }
1994
1995 static void intel_pmu_nhm_enable_all(int added)
1996 {
1997 if (added)
1998 intel_pmu_nhm_workaround();
1999 intel_pmu_enable_all(added);
2000 }
2001
2002 static void enable_counter_freeze(void)
2003 {
2004 update_debugctlmsr(get_debugctlmsr() |
2005 DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2006 }
2007
2008 static void disable_counter_freeze(void)
2009 {
2010 update_debugctlmsr(get_debugctlmsr() &
2011 ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2012 }
2013
2014 static inline u64 intel_pmu_get_status(void)
2015 {
2016 u64 status;
2017
2018 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2019
2020 return status;
2021 }
2022
2023 static inline void intel_pmu_ack_status(u64 ack)
2024 {
2025 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2026 }
2027
2028 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
2029 {
2030 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
2031 u64 ctrl_val, mask;
2032
2033 mask = 0xfULL << (idx * 4);
2034
2035 rdmsrl(hwc->config_base, ctrl_val);
2036 ctrl_val &= ~mask;
2037 wrmsrl(hwc->config_base, ctrl_val);
2038 }
2039
2040 static inline bool event_is_checkpointed(struct perf_event *event)
2041 {
2042 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2043 }
2044
2045 static void intel_pmu_disable_event(struct perf_event *event)
2046 {
2047 struct hw_perf_event *hwc = &event->hw;
2048 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2049
2050 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
2051 intel_pmu_disable_bts();
2052 intel_pmu_drain_bts_buffer();
2053 return;
2054 }
2055
2056 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
2057 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2058 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
2059
2060 if (unlikely(event->attr.precise_ip))
2061 intel_pmu_pebs_disable(event);
2062
2063 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
2064 intel_pmu_disable_fixed(hwc);
2065 return;
2066 }
2067
2068 x86_pmu_disable_event(event);
2069 }
2070
2071 static void intel_pmu_del_event(struct perf_event *event)
2072 {
2073 if (needs_branch_stack(event))
2074 intel_pmu_lbr_del(event);
2075 if (event->attr.precise_ip)
2076 intel_pmu_pebs_del(event);
2077 }
2078
2079 static void intel_pmu_read_event(struct perf_event *event)
2080 {
2081 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2082 intel_pmu_auto_reload_read(event);
2083 else
2084 x86_perf_event_update(event);
2085 }
2086
2087 static void intel_pmu_enable_fixed(struct perf_event *event)
2088 {
2089 struct hw_perf_event *hwc = &event->hw;
2090 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
2091 u64 ctrl_val, mask, bits = 0;
2092
2093 /*
2094 * Enable IRQ generation (0x8), if not PEBS,
2095 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2096 * if requested:
2097 */
2098 if (!event->attr.precise_ip)
2099 bits |= 0x8;
2100 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2101 bits |= 0x2;
2102 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2103 bits |= 0x1;
2104
2105 /*
2106 * ANY bit is supported in v3 and up
2107 */
2108 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2109 bits |= 0x4;
2110
2111 bits <<= (idx * 4);
2112 mask = 0xfULL << (idx * 4);
2113
2114 rdmsrl(hwc->config_base, ctrl_val);
2115 ctrl_val &= ~mask;
2116 ctrl_val |= bits;
2117 wrmsrl(hwc->config_base, ctrl_val);
2118 }
2119
2120 static void intel_pmu_enable_event(struct perf_event *event)
2121 {
2122 struct hw_perf_event *hwc = &event->hw;
2123 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2124
2125 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
2126 if (!__this_cpu_read(cpu_hw_events.enabled))
2127 return;
2128
2129 intel_pmu_enable_bts(hwc->config);
2130 return;
2131 }
2132
2133 if (event->attr.exclude_host)
2134 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
2135 if (event->attr.exclude_guest)
2136 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
2137
2138 if (unlikely(event_is_checkpointed(event)))
2139 cpuc->intel_cp_status |= (1ull << hwc->idx);
2140
2141 if (unlikely(event->attr.precise_ip))
2142 intel_pmu_pebs_enable(event);
2143
2144 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
2145 intel_pmu_enable_fixed(event);
2146 return;
2147 }
2148
2149 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2150 }
2151
2152 static void intel_pmu_add_event(struct perf_event *event)
2153 {
2154 if (event->attr.precise_ip)
2155 intel_pmu_pebs_add(event);
2156 if (needs_branch_stack(event))
2157 intel_pmu_lbr_add(event);
2158 }
2159
2160 /*
2161 * Save and restart an expired event. Called by NMI contexts,
2162 * so it has to be careful about preempting normal event ops:
2163 */
2164 int intel_pmu_save_and_restart(struct perf_event *event)
2165 {
2166 x86_perf_event_update(event);
2167 /*
2168 * For a checkpointed counter always reset back to 0. This
2169 * avoids a situation where the counter overflows, aborts the
2170 * transaction and is then set back to shortly before the
2171 * overflow, and overflows and aborts again.
2172 */
2173 if (unlikely(event_is_checkpointed(event))) {
2174 /* No race with NMIs because the counter should not be armed */
2175 wrmsrl(event->hw.event_base, 0);
2176 local64_set(&event->hw.prev_count, 0);
2177 }
2178 return x86_perf_event_set_period(event);
2179 }
2180
2181 static void intel_pmu_reset(void)
2182 {
2183 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2184 unsigned long flags;
2185 int idx;
2186
2187 if (!x86_pmu.num_counters)
2188 return;
2189
2190 local_irq_save(flags);
2191
2192 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2193
2194 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2195 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2196 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2197 }
2198 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
2199 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2200
2201 if (ds)
2202 ds->bts_index = ds->bts_buffer_base;
2203
2204 /* Ack all overflows and disable fixed counters */
2205 if (x86_pmu.version >= 2) {
2206 intel_pmu_ack_status(intel_pmu_get_status());
2207 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2208 }
2209
2210 /* Reset LBRs and LBR freezing */
2211 if (x86_pmu.lbr_nr) {
2212 update_debugctlmsr(get_debugctlmsr() &
2213 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2214 }
2215
2216 local_irq_restore(flags);
2217 }
2218
2219 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2220 {
2221 struct perf_sample_data data;
2222 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2223 int bit;
2224 int handled = 0;
2225
2226 inc_irq_stat(apic_perf_irqs);
2227
2228 /*
2229 * Ignore a range of extra bits in status that do not indicate
2230 * overflow by themselves.
2231 */
2232 status &= ~(GLOBAL_STATUS_COND_CHG |
2233 GLOBAL_STATUS_ASIF |
2234 GLOBAL_STATUS_LBRS_FROZEN);
2235 if (!status)
2236 return 0;
2237 /*
2238 * In case multiple PEBS events are sampled at the same time,
2239 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2240 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2241 * having their bits set in the status register. This is a sign
2242 * that there was at least one PEBS record pending at the time
2243 * of the PMU interrupt. PEBS counters must only be processed
2244 * via the drain_pebs() calls and not via the regular sample
2245 * processing loop coming after that the function, otherwise
2246 * phony regular samples may be generated in the sampling buffer
2247 * not marked with the EXACT tag. Another possibility is to have
2248 * one PEBS event and at least one non-PEBS event whic hoverflows
2249 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2250 * not be set, yet the overflow status bit for the PEBS counter will
2251 * be on Skylake.
2252 *
2253 * To avoid this problem, we systematically ignore the PEBS-enabled
2254 * counters from the GLOBAL_STATUS mask and we always process PEBS
2255 * events via drain_pebs().
2256 */
2257 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2258 status &= ~cpuc->pebs_enabled;
2259 else
2260 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2261
2262 /*
2263 * PEBS overflow sets bit 62 in the global status register
2264 */
2265 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
2266 handled++;
2267 x86_pmu.drain_pebs(regs);
2268 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2269 }
2270
2271 /*
2272 * Intel PT
2273 */
2274 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
2275 handled++;
2276 intel_pt_interrupt();
2277 }
2278
2279 /*
2280 * Checkpointed counters can lead to 'spurious' PMIs because the
2281 * rollback caused by the PMI will have cleared the overflow status
2282 * bit. Therefore always force probe these counters.
2283 */
2284 status |= cpuc->intel_cp_status;
2285
2286 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2287 struct perf_event *event = cpuc->events[bit];
2288
2289 handled++;
2290
2291 if (!test_bit(bit, cpuc->active_mask))
2292 continue;
2293
2294 if (!intel_pmu_save_and_restart(event))
2295 continue;
2296
2297 perf_sample_data_init(&data, 0, event->hw.last_period);
2298
2299 if (has_branch_stack(event))
2300 data.br_stack = &cpuc->lbr_stack;
2301
2302 if (perf_event_overflow(event, &data, regs))
2303 x86_pmu_stop(event, 0);
2304 }
2305
2306 return handled;
2307 }
2308
2309 static bool disable_counter_freezing;
2310 static int __init intel_perf_counter_freezing_setup(char *s)
2311 {
2312 disable_counter_freezing = true;
2313 pr_info("Intel PMU Counter freezing feature disabled\n");
2314 return 1;
2315 }
2316 __setup("disable_counter_freezing", intel_perf_counter_freezing_setup);
2317
2318 /*
2319 * Simplified handler for Arch Perfmon v4:
2320 * - We rely on counter freezing/unfreezing to enable/disable the PMU.
2321 * This is done automatically on PMU ack.
2322 * - Ack the PMU only after the APIC.
2323 */
2324
2325 static int intel_pmu_handle_irq_v4(struct pt_regs *regs)
2326 {
2327 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2328 int handled = 0;
2329 bool bts = false;
2330 u64 status;
2331 int pmu_enabled = cpuc->enabled;
2332 int loops = 0;
2333
2334 /* PMU has been disabled because of counter freezing */
2335 cpuc->enabled = 0;
2336 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2337 bts = true;
2338 intel_bts_disable_local();
2339 handled = intel_pmu_drain_bts_buffer();
2340 handled += intel_bts_interrupt();
2341 }
2342 status = intel_pmu_get_status();
2343 if (!status)
2344 goto done;
2345 again:
2346 intel_pmu_lbr_read();
2347 if (++loops > 100) {
2348 static bool warned;
2349
2350 if (!warned) {
2351 WARN(1, "perfevents: irq loop stuck!\n");
2352 perf_event_print_debug();
2353 warned = true;
2354 }
2355 intel_pmu_reset();
2356 goto done;
2357 }
2358
2359
2360 handled += handle_pmi_common(regs, status);
2361 done:
2362 /* Ack the PMI in the APIC */
2363 apic_write(APIC_LVTPC, APIC_DM_NMI);
2364
2365 /*
2366 * The counters start counting immediately while ack the status.
2367 * Make it as close as possible to IRET. This avoids bogus
2368 * freezing on Skylake CPUs.
2369 */
2370 if (status) {
2371 intel_pmu_ack_status(status);
2372 } else {
2373 /*
2374 * CPU may issues two PMIs very close to each other.
2375 * When the PMI handler services the first one, the
2376 * GLOBAL_STATUS is already updated to reflect both.
2377 * When it IRETs, the second PMI is immediately
2378 * handled and it sees clear status. At the meantime,
2379 * there may be a third PMI, because the freezing bit
2380 * isn't set since the ack in first PMI handlers.
2381 * Double check if there is more work to be done.
2382 */
2383 status = intel_pmu_get_status();
2384 if (status)
2385 goto again;
2386 }
2387
2388 if (bts)
2389 intel_bts_enable_local();
2390 cpuc->enabled = pmu_enabled;
2391 return handled;
2392 }
2393
2394 /*
2395 * This handler is triggered by the local APIC, so the APIC IRQ handling
2396 * rules apply:
2397 */
2398 static int intel_pmu_handle_irq(struct pt_regs *regs)
2399 {
2400 struct cpu_hw_events *cpuc;
2401 int loops;
2402 u64 status;
2403 int handled;
2404 int pmu_enabled;
2405
2406 cpuc = this_cpu_ptr(&cpu_hw_events);
2407
2408 /*
2409 * Save the PMU state.
2410 * It needs to be restored when leaving the handler.
2411 */
2412 pmu_enabled = cpuc->enabled;
2413 /*
2414 * No known reason to not always do late ACK,
2415 * but just in case do it opt-in.
2416 */
2417 if (!x86_pmu.late_ack)
2418 apic_write(APIC_LVTPC, APIC_DM_NMI);
2419 intel_bts_disable_local();
2420 cpuc->enabled = 0;
2421 __intel_pmu_disable_all();
2422 handled = intel_pmu_drain_bts_buffer();
2423 handled += intel_bts_interrupt();
2424 status = intel_pmu_get_status();
2425 if (!status)
2426 goto done;
2427
2428 loops = 0;
2429 again:
2430 intel_pmu_lbr_read();
2431 intel_pmu_ack_status(status);
2432 if (++loops > 100) {
2433 static bool warned;
2434
2435 if (!warned) {
2436 WARN(1, "perfevents: irq loop stuck!\n");
2437 perf_event_print_debug();
2438 warned = true;
2439 }
2440 intel_pmu_reset();
2441 goto done;
2442 }
2443
2444 handled += handle_pmi_common(regs, status);
2445
2446 /*
2447 * Repeat if there is more work to be done:
2448 */
2449 status = intel_pmu_get_status();
2450 if (status)
2451 goto again;
2452
2453 done:
2454 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2455 cpuc->enabled = pmu_enabled;
2456 if (pmu_enabled)
2457 __intel_pmu_enable_all(0, true);
2458 intel_bts_enable_local();
2459
2460 /*
2461 * Only unmask the NMI after the overflow counters
2462 * have been reset. This avoids spurious NMIs on
2463 * Haswell CPUs.
2464 */
2465 if (x86_pmu.late_ack)
2466 apic_write(APIC_LVTPC, APIC_DM_NMI);
2467 return handled;
2468 }
2469
2470 static struct event_constraint *
2471 intel_bts_constraints(struct perf_event *event)
2472 {
2473 struct hw_perf_event *hwc = &event->hw;
2474 unsigned int hw_event, bts_event;
2475
2476 if (event->attr.freq)
2477 return NULL;
2478
2479 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
2480 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
2481
2482 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
2483 return &bts_constraint;
2484
2485 return NULL;
2486 }
2487
2488 static int intel_alt_er(int idx, u64 config)
2489 {
2490 int alt_idx = idx;
2491
2492 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
2493 return idx;
2494
2495 if (idx == EXTRA_REG_RSP_0)
2496 alt_idx = EXTRA_REG_RSP_1;
2497
2498 if (idx == EXTRA_REG_RSP_1)
2499 alt_idx = EXTRA_REG_RSP_0;
2500
2501 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2502 return idx;
2503
2504 return alt_idx;
2505 }
2506
2507 static void intel_fixup_er(struct perf_event *event, int idx)
2508 {
2509 event->hw.extra_reg.idx = idx;
2510
2511 if (idx == EXTRA_REG_RSP_0) {
2512 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2513 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
2514 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
2515 } else if (idx == EXTRA_REG_RSP_1) {
2516 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2517 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
2518 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
2519 }
2520 }
2521
2522 /*
2523 * manage allocation of shared extra msr for certain events
2524 *
2525 * sharing can be:
2526 * per-cpu: to be shared between the various events on a single PMU
2527 * per-core: per-cpu + shared by HT threads
2528 */
2529 static struct event_constraint *
2530 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
2531 struct perf_event *event,
2532 struct hw_perf_event_extra *reg)
2533 {
2534 struct event_constraint *c = &emptyconstraint;
2535 struct er_account *era;
2536 unsigned long flags;
2537 int idx = reg->idx;
2538
2539 /*
2540 * reg->alloc can be set due to existing state, so for fake cpuc we
2541 * need to ignore this, otherwise we might fail to allocate proper fake
2542 * state for this extra reg constraint. Also see the comment below.
2543 */
2544 if (reg->alloc && !cpuc->is_fake)
2545 return NULL; /* call x86_get_event_constraint() */
2546
2547 again:
2548 era = &cpuc->shared_regs->regs[idx];
2549 /*
2550 * we use spin_lock_irqsave() to avoid lockdep issues when
2551 * passing a fake cpuc
2552 */
2553 raw_spin_lock_irqsave(&era->lock, flags);
2554
2555 if (!atomic_read(&era->ref) || era->config == reg->config) {
2556
2557 /*
2558 * If its a fake cpuc -- as per validate_{group,event}() we
2559 * shouldn't touch event state and we can avoid doing so
2560 * since both will only call get_event_constraints() once
2561 * on each event, this avoids the need for reg->alloc.
2562 *
2563 * Not doing the ER fixup will only result in era->reg being
2564 * wrong, but since we won't actually try and program hardware
2565 * this isn't a problem either.
2566 */
2567 if (!cpuc->is_fake) {
2568 if (idx != reg->idx)
2569 intel_fixup_er(event, idx);
2570
2571 /*
2572 * x86_schedule_events() can call get_event_constraints()
2573 * multiple times on events in the case of incremental
2574 * scheduling(). reg->alloc ensures we only do the ER
2575 * allocation once.
2576 */
2577 reg->alloc = 1;
2578 }
2579
2580 /* lock in msr value */
2581 era->config = reg->config;
2582 era->reg = reg->reg;
2583
2584 /* one more user */
2585 atomic_inc(&era->ref);
2586
2587 /*
2588 * need to call x86_get_event_constraint()
2589 * to check if associated event has constraints
2590 */
2591 c = NULL;
2592 } else {
2593 idx = intel_alt_er(idx, reg->config);
2594 if (idx != reg->idx) {
2595 raw_spin_unlock_irqrestore(&era->lock, flags);
2596 goto again;
2597 }
2598 }
2599 raw_spin_unlock_irqrestore(&era->lock, flags);
2600
2601 return c;
2602 }
2603
2604 static void
2605 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2606 struct hw_perf_event_extra *reg)
2607 {
2608 struct er_account *era;
2609
2610 /*
2611 * Only put constraint if extra reg was actually allocated. Also takes
2612 * care of event which do not use an extra shared reg.
2613 *
2614 * Also, if this is a fake cpuc we shouldn't touch any event state
2615 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2616 * either since it'll be thrown out.
2617 */
2618 if (!reg->alloc || cpuc->is_fake)
2619 return;
2620
2621 era = &cpuc->shared_regs->regs[reg->idx];
2622
2623 /* one fewer user */
2624 atomic_dec(&era->ref);
2625
2626 /* allocate again next time */
2627 reg->alloc = 0;
2628 }
2629
2630 static struct event_constraint *
2631 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2632 struct perf_event *event)
2633 {
2634 struct event_constraint *c = NULL, *d;
2635 struct hw_perf_event_extra *xreg, *breg;
2636
2637 xreg = &event->hw.extra_reg;
2638 if (xreg->idx != EXTRA_REG_NONE) {
2639 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2640 if (c == &emptyconstraint)
2641 return c;
2642 }
2643 breg = &event->hw.branch_reg;
2644 if (breg->idx != EXTRA_REG_NONE) {
2645 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2646 if (d == &emptyconstraint) {
2647 __intel_shared_reg_put_constraints(cpuc, xreg);
2648 c = d;
2649 }
2650 }
2651 return c;
2652 }
2653
2654 struct event_constraint *
2655 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2656 struct perf_event *event)
2657 {
2658 struct event_constraint *c;
2659
2660 if (x86_pmu.event_constraints) {
2661 for_each_event_constraint(c, x86_pmu.event_constraints) {
2662 if ((event->hw.config & c->cmask) == c->code) {
2663 event->hw.flags |= c->flags;
2664 return c;
2665 }
2666 }
2667 }
2668
2669 return &unconstrained;
2670 }
2671
2672 static struct event_constraint *
2673 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2674 struct perf_event *event)
2675 {
2676 struct event_constraint *c;
2677
2678 c = intel_bts_constraints(event);
2679 if (c)
2680 return c;
2681
2682 c = intel_shared_regs_constraints(cpuc, event);
2683 if (c)
2684 return c;
2685
2686 c = intel_pebs_constraints(event);
2687 if (c)
2688 return c;
2689
2690 return x86_get_event_constraints(cpuc, idx, event);
2691 }
2692
2693 static void
2694 intel_start_scheduling(struct cpu_hw_events *cpuc)
2695 {
2696 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2697 struct intel_excl_states *xl;
2698 int tid = cpuc->excl_thread_id;
2699
2700 /*
2701 * nothing needed if in group validation mode
2702 */
2703 if (cpuc->is_fake || !is_ht_workaround_enabled())
2704 return;
2705
2706 /*
2707 * no exclusion needed
2708 */
2709 if (WARN_ON_ONCE(!excl_cntrs))
2710 return;
2711
2712 xl = &excl_cntrs->states[tid];
2713
2714 xl->sched_started = true;
2715 /*
2716 * lock shared state until we are done scheduling
2717 * in stop_event_scheduling()
2718 * makes scheduling appear as a transaction
2719 */
2720 raw_spin_lock(&excl_cntrs->lock);
2721 }
2722
2723 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2724 {
2725 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2726 struct event_constraint *c = cpuc->event_constraint[idx];
2727 struct intel_excl_states *xl;
2728 int tid = cpuc->excl_thread_id;
2729
2730 if (cpuc->is_fake || !is_ht_workaround_enabled())
2731 return;
2732
2733 if (WARN_ON_ONCE(!excl_cntrs))
2734 return;
2735
2736 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2737 return;
2738
2739 xl = &excl_cntrs->states[tid];
2740
2741 lockdep_assert_held(&excl_cntrs->lock);
2742
2743 if (c->flags & PERF_X86_EVENT_EXCL)
2744 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
2745 else
2746 xl->state[cntr] = INTEL_EXCL_SHARED;
2747 }
2748
2749 static void
2750 intel_stop_scheduling(struct cpu_hw_events *cpuc)
2751 {
2752 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2753 struct intel_excl_states *xl;
2754 int tid = cpuc->excl_thread_id;
2755
2756 /*
2757 * nothing needed if in group validation mode
2758 */
2759 if (cpuc->is_fake || !is_ht_workaround_enabled())
2760 return;
2761 /*
2762 * no exclusion needed
2763 */
2764 if (WARN_ON_ONCE(!excl_cntrs))
2765 return;
2766
2767 xl = &excl_cntrs->states[tid];
2768
2769 xl->sched_started = false;
2770 /*
2771 * release shared state lock (acquired in intel_start_scheduling())
2772 */
2773 raw_spin_unlock(&excl_cntrs->lock);
2774 }
2775
2776 static struct event_constraint *
2777 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2778 int idx, struct event_constraint *c)
2779 {
2780 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2781 struct intel_excl_states *xlo;
2782 int tid = cpuc->excl_thread_id;
2783 int is_excl, i;
2784
2785 /*
2786 * validating a group does not require
2787 * enforcing cross-thread exclusion
2788 */
2789 if (cpuc->is_fake || !is_ht_workaround_enabled())
2790 return c;
2791
2792 /*
2793 * no exclusion needed
2794 */
2795 if (WARN_ON_ONCE(!excl_cntrs))
2796 return c;
2797
2798 /*
2799 * because we modify the constraint, we need
2800 * to make a copy. Static constraints come
2801 * from static const tables.
2802 *
2803 * only needed when constraint has not yet
2804 * been cloned (marked dynamic)
2805 */
2806 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2807 struct event_constraint *cx;
2808
2809 /*
2810 * grab pre-allocated constraint entry
2811 */
2812 cx = &cpuc->constraint_list[idx];
2813
2814 /*
2815 * initialize dynamic constraint
2816 * with static constraint
2817 */
2818 *cx = *c;
2819
2820 /*
2821 * mark constraint as dynamic, so we
2822 * can free it later on
2823 */
2824 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2825 c = cx;
2826 }
2827
2828 /*
2829 * From here on, the constraint is dynamic.
2830 * Either it was just allocated above, or it
2831 * was allocated during a earlier invocation
2832 * of this function
2833 */
2834
2835 /*
2836 * state of sibling HT
2837 */
2838 xlo = &excl_cntrs->states[tid ^ 1];
2839
2840 /*
2841 * event requires exclusive counter access
2842 * across HT threads
2843 */
2844 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2845 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2846 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2847 if (!cpuc->n_excl++)
2848 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2849 }
2850
2851 /*
2852 * Modify static constraint with current dynamic
2853 * state of thread
2854 *
2855 * EXCLUSIVE: sibling counter measuring exclusive event
2856 * SHARED : sibling counter measuring non-exclusive event
2857 * UNUSED : sibling counter unused
2858 */
2859 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
2860 /*
2861 * exclusive event in sibling counter
2862 * our corresponding counter cannot be used
2863 * regardless of our event
2864 */
2865 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
2866 __clear_bit(i, c->idxmsk);
2867 /*
2868 * if measuring an exclusive event, sibling
2869 * measuring non-exclusive, then counter cannot
2870 * be used
2871 */
2872 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
2873 __clear_bit(i, c->idxmsk);
2874 }
2875
2876 /*
2877 * recompute actual bit weight for scheduling algorithm
2878 */
2879 c->weight = hweight64(c->idxmsk64);
2880
2881 /*
2882 * if we return an empty mask, then switch
2883 * back to static empty constraint to avoid
2884 * the cost of freeing later on
2885 */
2886 if (c->weight == 0)
2887 c = &emptyconstraint;
2888
2889 return c;
2890 }
2891
2892 static struct event_constraint *
2893 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2894 struct perf_event *event)
2895 {
2896 struct event_constraint *c1 = NULL;
2897 struct event_constraint *c2;
2898
2899 if (idx >= 0) /* fake does < 0 */
2900 c1 = cpuc->event_constraint[idx];
2901
2902 /*
2903 * first time only
2904 * - static constraint: no change across incremental scheduling calls
2905 * - dynamic constraint: handled by intel_get_excl_constraints()
2906 */
2907 c2 = __intel_get_event_constraints(cpuc, idx, event);
2908 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2909 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2910 c1->weight = c2->weight;
2911 c2 = c1;
2912 }
2913
2914 if (cpuc->excl_cntrs)
2915 return intel_get_excl_constraints(cpuc, event, idx, c2);
2916
2917 return c2;
2918 }
2919
2920 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2921 struct perf_event *event)
2922 {
2923 struct hw_perf_event *hwc = &event->hw;
2924 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2925 int tid = cpuc->excl_thread_id;
2926 struct intel_excl_states *xl;
2927
2928 /*
2929 * nothing needed if in group validation mode
2930 */
2931 if (cpuc->is_fake)
2932 return;
2933
2934 if (WARN_ON_ONCE(!excl_cntrs))
2935 return;
2936
2937 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2938 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2939 if (!--cpuc->n_excl)
2940 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2941 }
2942
2943 /*
2944 * If event was actually assigned, then mark the counter state as
2945 * unused now.
2946 */
2947 if (hwc->idx >= 0) {
2948 xl = &excl_cntrs->states[tid];
2949
2950 /*
2951 * put_constraint may be called from x86_schedule_events()
2952 * which already has the lock held so here make locking
2953 * conditional.
2954 */
2955 if (!xl->sched_started)
2956 raw_spin_lock(&excl_cntrs->lock);
2957
2958 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
2959
2960 if (!xl->sched_started)
2961 raw_spin_unlock(&excl_cntrs->lock);
2962 }
2963 }
2964
2965 static void
2966 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
2967 struct perf_event *event)
2968 {
2969 struct hw_perf_event_extra *reg;
2970
2971 reg = &event->hw.extra_reg;
2972 if (reg->idx != EXTRA_REG_NONE)
2973 __intel_shared_reg_put_constraints(cpuc, reg);
2974
2975 reg = &event->hw.branch_reg;
2976 if (reg->idx != EXTRA_REG_NONE)
2977 __intel_shared_reg_put_constraints(cpuc, reg);
2978 }
2979
2980 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2981 struct perf_event *event)
2982 {
2983 intel_put_shared_regs_event_constraints(cpuc, event);
2984
2985 /*
2986 * is PMU has exclusive counter restrictions, then
2987 * all events are subject to and must call the
2988 * put_excl_constraints() routine
2989 */
2990 if (cpuc->excl_cntrs)
2991 intel_put_excl_constraints(cpuc, event);
2992 }
2993
2994 static void intel_pebs_aliases_core2(struct perf_event *event)
2995 {
2996 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2997 /*
2998 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2999 * (0x003c) so that we can use it with PEBS.
3000 *
3001 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3002 * PEBS capable. However we can use INST_RETIRED.ANY_P
3003 * (0x00c0), which is a PEBS capable event, to get the same
3004 * count.
3005 *
3006 * INST_RETIRED.ANY_P counts the number of cycles that retires
3007 * CNTMASK instructions. By setting CNTMASK to a value (16)
3008 * larger than the maximum number of instructions that can be
3009 * retired per cycle (4) and then inverting the condition, we
3010 * count all cycles that retire 16 or less instructions, which
3011 * is every cycle.
3012 *
3013 * Thereby we gain a PEBS capable cycle counter.
3014 */
3015 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3016
3017 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3018 event->hw.config = alt_config;
3019 }
3020 }
3021
3022 static void intel_pebs_aliases_snb(struct perf_event *event)
3023 {
3024 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3025 /*
3026 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3027 * (0x003c) so that we can use it with PEBS.
3028 *
3029 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3030 * PEBS capable. However we can use UOPS_RETIRED.ALL
3031 * (0x01c2), which is a PEBS capable event, to get the same
3032 * count.
3033 *
3034 * UOPS_RETIRED.ALL counts the number of cycles that retires
3035 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3036 * larger than the maximum number of micro-ops that can be
3037 * retired per cycle (4) and then inverting the condition, we
3038 * count all cycles that retire 16 or less micro-ops, which
3039 * is every cycle.
3040 *
3041 * Thereby we gain a PEBS capable cycle counter.
3042 */
3043 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3044
3045 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3046 event->hw.config = alt_config;
3047 }
3048 }
3049
3050 static void intel_pebs_aliases_precdist(struct perf_event *event)
3051 {
3052 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3053 /*
3054 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3055 * (0x003c) so that we can use it with PEBS.
3056 *
3057 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3058 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3059 * (0x01c0), which is a PEBS capable event, to get the same
3060 * count.
3061 *
3062 * The PREC_DIST event has special support to minimize sample
3063 * shadowing effects. One drawback is that it can be
3064 * only programmed on counter 1, but that seems like an
3065 * acceptable trade off.
3066 */
3067 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3068
3069 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3070 event->hw.config = alt_config;
3071 }
3072 }
3073
3074 static void intel_pebs_aliases_ivb(struct perf_event *event)
3075 {
3076 if (event->attr.precise_ip < 3)
3077 return intel_pebs_aliases_snb(event);
3078 return intel_pebs_aliases_precdist(event);
3079 }
3080
3081 static void intel_pebs_aliases_skl(struct perf_event *event)
3082 {
3083 if (event->attr.precise_ip < 3)
3084 return intel_pebs_aliases_core2(event);
3085 return intel_pebs_aliases_precdist(event);
3086 }
3087
3088 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3089 {
3090 unsigned long flags = x86_pmu.large_pebs_flags;
3091
3092 if (event->attr.use_clockid)
3093 flags &= ~PERF_SAMPLE_TIME;
3094 if (!event->attr.exclude_kernel)
3095 flags &= ~PERF_SAMPLE_REGS_USER;
3096 if (event->attr.sample_regs_user & ~PEBS_REGS)
3097 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3098 return flags;
3099 }
3100
3101 static int intel_pmu_hw_config(struct perf_event *event)
3102 {
3103 int ret = x86_pmu_hw_config(event);
3104
3105 if (ret)
3106 return ret;
3107
3108 if (event->attr.precise_ip) {
3109 if (!event->attr.freq) {
3110 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3111 if (!(event->attr.sample_type &
3112 ~intel_pmu_large_pebs_flags(event)))
3113 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3114 }
3115 if (x86_pmu.pebs_aliases)
3116 x86_pmu.pebs_aliases(event);
3117
3118 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3119 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
3120 }
3121
3122 if (needs_branch_stack(event)) {
3123 ret = intel_pmu_setup_lbr_filter(event);
3124 if (ret)
3125 return ret;
3126
3127 /*
3128 * BTS is set up earlier in this path, so don't account twice
3129 */
3130 if (!intel_pmu_has_bts(event)) {
3131 /* disallow lbr if conflicting events are present */
3132 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3133 return -EBUSY;
3134
3135 event->destroy = hw_perf_lbr_event_destroy;
3136 }
3137 }
3138
3139 if (event->attr.type != PERF_TYPE_RAW)
3140 return 0;
3141
3142 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3143 return 0;
3144
3145 if (x86_pmu.version < 3)
3146 return -EINVAL;
3147
3148 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
3149 return -EACCES;
3150
3151 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3152
3153 return 0;
3154 }
3155
3156 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
3157 {
3158 if (x86_pmu.guest_get_msrs)
3159 return x86_pmu.guest_get_msrs(nr);
3160 *nr = 0;
3161 return NULL;
3162 }
3163 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
3164
3165 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3166 {
3167 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3168 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3169
3170 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3171 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3172 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3173 /*
3174 * If PMU counter has PEBS enabled it is not enough to disable counter
3175 * on a guest entry since PEBS memory write can overshoot guest entry
3176 * and corrupt guest memory. Disabling PEBS solves the problem.
3177 */
3178 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3179 arr[1].host = cpuc->pebs_enabled;
3180 arr[1].guest = 0;
3181
3182 *nr = 2;
3183 return arr;
3184 }
3185
3186 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3187 {
3188 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3189 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3190 int idx;
3191
3192 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3193 struct perf_event *event = cpuc->events[idx];
3194
3195 arr[idx].msr = x86_pmu_config_addr(idx);
3196 arr[idx].host = arr[idx].guest = 0;
3197
3198 if (!test_bit(idx, cpuc->active_mask))
3199 continue;
3200
3201 arr[idx].host = arr[idx].guest =
3202 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3203
3204 if (event->attr.exclude_host)
3205 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3206 else if (event->attr.exclude_guest)
3207 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3208 }
3209
3210 *nr = x86_pmu.num_counters;
3211 return arr;
3212 }
3213
3214 static void core_pmu_enable_event(struct perf_event *event)
3215 {
3216 if (!event->attr.exclude_host)
3217 x86_pmu_enable_event(event);
3218 }
3219
3220 static void core_pmu_enable_all(int added)
3221 {
3222 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3223 int idx;
3224
3225 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3226 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3227
3228 if (!test_bit(idx, cpuc->active_mask) ||
3229 cpuc->events[idx]->attr.exclude_host)
3230 continue;
3231
3232 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3233 }
3234 }
3235
3236 static int hsw_hw_config(struct perf_event *event)
3237 {
3238 int ret = intel_pmu_hw_config(event);
3239
3240 if (ret)
3241 return ret;
3242 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3243 return 0;
3244 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3245
3246 /*
3247 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3248 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3249 * this combination.
3250 */
3251 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3252 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3253 event->attr.precise_ip > 0))
3254 return -EOPNOTSUPP;
3255
3256 if (event_is_checkpointed(event)) {
3257 /*
3258 * Sampling of checkpointed events can cause situations where
3259 * the CPU constantly aborts because of a overflow, which is
3260 * then checkpointed back and ignored. Forbid checkpointing
3261 * for sampling.
3262 *
3263 * But still allow a long sampling period, so that perf stat
3264 * from KVM works.
3265 */
3266 if (event->attr.sample_period > 0 &&
3267 event->attr.sample_period < 0x7fffffff)
3268 return -EOPNOTSUPP;
3269 }
3270 return 0;
3271 }
3272
3273 static struct event_constraint counter0_constraint =
3274 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3275
3276 static struct event_constraint counter2_constraint =
3277 EVENT_CONSTRAINT(0, 0x4, 0);
3278
3279 static struct event_constraint *
3280 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3281 struct perf_event *event)
3282 {
3283 struct event_constraint *c;
3284
3285 c = intel_get_event_constraints(cpuc, idx, event);
3286
3287 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3288 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3289 if (c->idxmsk64 & (1U << 2))
3290 return &counter2_constraint;
3291 return &emptyconstraint;
3292 }
3293
3294 return c;
3295 }
3296
3297 static struct event_constraint *
3298 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3299 struct perf_event *event)
3300 {
3301 struct event_constraint *c;
3302
3303 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
3304 if (event->attr.precise_ip == 3)
3305 return &counter0_constraint;
3306
3307 c = intel_get_event_constraints(cpuc, idx, event);
3308
3309 return c;
3310 }
3311
3312 /*
3313 * Broadwell:
3314 *
3315 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
3316 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
3317 * the two to enforce a minimum period of 128 (the smallest value that has bits
3318 * 0-5 cleared and >= 100).
3319 *
3320 * Because of how the code in x86_perf_event_set_period() works, the truncation
3321 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
3322 * to make up for the 'lost' events due to carrying the 'error' in period_left.
3323 *
3324 * Therefore the effective (average) period matches the requested period,
3325 * despite coarser hardware granularity.
3326 */
3327 static u64 bdw_limit_period(struct perf_event *event, u64 left)
3328 {
3329 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
3330 X86_CONFIG(.event=0xc0, .umask=0x01)) {
3331 if (left < 128)
3332 left = 128;
3333 left &= ~0x3fULL;
3334 }
3335 return left;
3336 }
3337
3338 PMU_FORMAT_ATTR(event, "config:0-7" );
3339 PMU_FORMAT_ATTR(umask, "config:8-15" );
3340 PMU_FORMAT_ATTR(edge, "config:18" );
3341 PMU_FORMAT_ATTR(pc, "config:19" );
3342 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
3343 PMU_FORMAT_ATTR(inv, "config:23" );
3344 PMU_FORMAT_ATTR(cmask, "config:24-31" );
3345 PMU_FORMAT_ATTR(in_tx, "config:32");
3346 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
3347
3348 static struct attribute *intel_arch_formats_attr[] = {
3349 &format_attr_event.attr,
3350 &format_attr_umask.attr,
3351 &format_attr_edge.attr,
3352 &format_attr_pc.attr,
3353 &format_attr_inv.attr,
3354 &format_attr_cmask.attr,
3355 NULL,
3356 };
3357
3358 ssize_t intel_event_sysfs_show(char *page, u64 config)
3359 {
3360 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
3361
3362 return x86_event_sysfs_show(page, config, event);
3363 }
3364
3365 struct intel_shared_regs *allocate_shared_regs(int cpu)
3366 {
3367 struct intel_shared_regs *regs;
3368 int i;
3369
3370 regs = kzalloc_node(sizeof(struct intel_shared_regs),
3371 GFP_KERNEL, cpu_to_node(cpu));
3372 if (regs) {
3373 /*
3374 * initialize the locks to keep lockdep happy
3375 */
3376 for (i = 0; i < EXTRA_REG_MAX; i++)
3377 raw_spin_lock_init(&regs->regs[i].lock);
3378
3379 regs->core_id = -1;
3380 }
3381 return regs;
3382 }
3383
3384 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
3385 {
3386 struct intel_excl_cntrs *c;
3387
3388 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
3389 GFP_KERNEL, cpu_to_node(cpu));
3390 if (c) {
3391 raw_spin_lock_init(&c->lock);
3392 c->core_id = -1;
3393 }
3394 return c;
3395 }
3396
3397 static int intel_pmu_cpu_prepare(int cpu)
3398 {
3399 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3400
3401 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
3402 cpuc->shared_regs = allocate_shared_regs(cpu);
3403 if (!cpuc->shared_regs)
3404 goto err;
3405 }
3406
3407 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3408 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
3409
3410 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
3411 if (!cpuc->constraint_list)
3412 goto err_shared_regs;
3413
3414 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
3415 if (!cpuc->excl_cntrs)
3416 goto err_constraint_list;
3417
3418 cpuc->excl_thread_id = 0;
3419 }
3420
3421 return 0;
3422
3423 err_constraint_list:
3424 kfree(cpuc->constraint_list);
3425 cpuc->constraint_list = NULL;
3426
3427 err_shared_regs:
3428 kfree(cpuc->shared_regs);
3429 cpuc->shared_regs = NULL;
3430
3431 err:
3432 return -ENOMEM;
3433 }
3434
3435 static void flip_smm_bit(void *data)
3436 {
3437 unsigned long set = *(unsigned long *)data;
3438
3439 if (set > 0) {
3440 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
3441 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3442 } else {
3443 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
3444 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3445 }
3446 }
3447
3448 static void intel_pmu_cpu_starting(int cpu)
3449 {
3450 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3451 int core_id = topology_core_id(cpu);
3452 int i;
3453
3454 init_debug_store_on_cpu(cpu);
3455 /*
3456 * Deal with CPUs that don't clear their LBRs on power-up.
3457 */
3458 intel_pmu_lbr_reset();
3459
3460 cpuc->lbr_sel = NULL;
3461
3462 if (x86_pmu.version > 1)
3463 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
3464
3465 if (x86_pmu.counter_freezing)
3466 enable_counter_freeze();
3467
3468 if (!cpuc->shared_regs)
3469 return;
3470
3471 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
3472 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3473 struct intel_shared_regs *pc;
3474
3475 pc = per_cpu(cpu_hw_events, i).shared_regs;
3476 if (pc && pc->core_id == core_id) {
3477 cpuc->kfree_on_online[0] = cpuc->shared_regs;
3478 cpuc->shared_regs = pc;
3479 break;
3480 }
3481 }
3482 cpuc->shared_regs->core_id = core_id;
3483 cpuc->shared_regs->refcnt++;
3484 }
3485
3486 if (x86_pmu.lbr_sel_map)
3487 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
3488
3489 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3490 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3491 struct cpu_hw_events *sibling;
3492 struct intel_excl_cntrs *c;
3493
3494 sibling = &per_cpu(cpu_hw_events, i);
3495 c = sibling->excl_cntrs;
3496 if (c && c->core_id == core_id) {
3497 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
3498 cpuc->excl_cntrs = c;
3499 if (!sibling->excl_thread_id)
3500 cpuc->excl_thread_id = 1;
3501 break;
3502 }
3503 }
3504 cpuc->excl_cntrs->core_id = core_id;
3505 cpuc->excl_cntrs->refcnt++;
3506 }
3507 }
3508
3509 static void free_excl_cntrs(int cpu)
3510 {
3511 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3512 struct intel_excl_cntrs *c;
3513
3514 c = cpuc->excl_cntrs;
3515 if (c) {
3516 if (c->core_id == -1 || --c->refcnt == 0)
3517 kfree(c);
3518 cpuc->excl_cntrs = NULL;
3519 kfree(cpuc->constraint_list);
3520 cpuc->constraint_list = NULL;
3521 }
3522 }
3523
3524 static void intel_pmu_cpu_dying(int cpu)
3525 {
3526 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3527 struct intel_shared_regs *pc;
3528
3529 pc = cpuc->shared_regs;
3530 if (pc) {
3531 if (pc->core_id == -1 || --pc->refcnt == 0)
3532 kfree(pc);
3533 cpuc->shared_regs = NULL;
3534 }
3535
3536 free_excl_cntrs(cpu);
3537
3538 fini_debug_store_on_cpu(cpu);
3539
3540 if (x86_pmu.counter_freezing)
3541 disable_counter_freeze();
3542 }
3543
3544 static void intel_pmu_sched_task(struct perf_event_context *ctx,
3545 bool sched_in)
3546 {
3547 intel_pmu_pebs_sched_task(ctx, sched_in);
3548 intel_pmu_lbr_sched_task(ctx, sched_in);
3549 }
3550
3551 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
3552
3553 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
3554
3555 PMU_FORMAT_ATTR(frontend, "config1:0-23");
3556
3557 static struct attribute *intel_arch3_formats_attr[] = {
3558 &format_attr_event.attr,
3559 &format_attr_umask.attr,
3560 &format_attr_edge.attr,
3561 &format_attr_pc.attr,
3562 &format_attr_any.attr,
3563 &format_attr_inv.attr,
3564 &format_attr_cmask.attr,
3565 NULL,
3566 };
3567
3568 static struct attribute *hsw_format_attr[] = {
3569 &format_attr_in_tx.attr,
3570 &format_attr_in_tx_cp.attr,
3571 &format_attr_offcore_rsp.attr,
3572 &format_attr_ldlat.attr,
3573 NULL
3574 };
3575
3576 static struct attribute *nhm_format_attr[] = {
3577 &format_attr_offcore_rsp.attr,
3578 &format_attr_ldlat.attr,
3579 NULL
3580 };
3581
3582 static struct attribute *slm_format_attr[] = {
3583 &format_attr_offcore_rsp.attr,
3584 NULL
3585 };
3586
3587 static struct attribute *skl_format_attr[] = {
3588 &format_attr_frontend.attr,
3589 NULL,
3590 };
3591
3592 static __initconst const struct x86_pmu core_pmu = {
3593 .name = "core",
3594 .handle_irq = x86_pmu_handle_irq,
3595 .disable_all = x86_pmu_disable_all,
3596 .enable_all = core_pmu_enable_all,
3597 .enable = core_pmu_enable_event,
3598 .disable = x86_pmu_disable_event,
3599 .hw_config = x86_pmu_hw_config,
3600 .schedule_events = x86_schedule_events,
3601 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3602 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3603 .event_map = intel_pmu_event_map,
3604 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3605 .apic = 1,
3606 .large_pebs_flags = LARGE_PEBS_FLAGS,
3607
3608 /*
3609 * Intel PMCs cannot be accessed sanely above 32-bit width,
3610 * so we install an artificial 1<<31 period regardless of
3611 * the generic event period:
3612 */
3613 .max_period = (1ULL<<31) - 1,
3614 .get_event_constraints = intel_get_event_constraints,
3615 .put_event_constraints = intel_put_event_constraints,
3616 .event_constraints = intel_core_event_constraints,
3617 .guest_get_msrs = core_guest_get_msrs,
3618 .format_attrs = intel_arch_formats_attr,
3619 .events_sysfs_show = intel_event_sysfs_show,
3620
3621 /*
3622 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3623 * together with PMU version 1 and thus be using core_pmu with
3624 * shared_regs. We need following callbacks here to allocate
3625 * it properly.
3626 */
3627 .cpu_prepare = intel_pmu_cpu_prepare,
3628 .cpu_starting = intel_pmu_cpu_starting,
3629 .cpu_dying = intel_pmu_cpu_dying,
3630 };
3631
3632 static struct attribute *intel_pmu_attrs[];
3633
3634 static __initconst const struct x86_pmu intel_pmu = {
3635 .name = "Intel",
3636 .handle_irq = intel_pmu_handle_irq,
3637 .disable_all = intel_pmu_disable_all,
3638 .enable_all = intel_pmu_enable_all,
3639 .enable = intel_pmu_enable_event,
3640 .disable = intel_pmu_disable_event,
3641 .add = intel_pmu_add_event,
3642 .del = intel_pmu_del_event,
3643 .read = intel_pmu_read_event,
3644 .hw_config = intel_pmu_hw_config,
3645 .schedule_events = x86_schedule_events,
3646 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3647 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3648 .event_map = intel_pmu_event_map,
3649 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3650 .apic = 1,
3651 .large_pebs_flags = LARGE_PEBS_FLAGS,
3652 /*
3653 * Intel PMCs cannot be accessed sanely above 32 bit width,
3654 * so we install an artificial 1<<31 period regardless of
3655 * the generic event period:
3656 */
3657 .max_period = (1ULL << 31) - 1,
3658 .get_event_constraints = intel_get_event_constraints,
3659 .put_event_constraints = intel_put_event_constraints,
3660 .pebs_aliases = intel_pebs_aliases_core2,
3661
3662 .format_attrs = intel_arch3_formats_attr,
3663 .events_sysfs_show = intel_event_sysfs_show,
3664
3665 .attrs = intel_pmu_attrs,
3666
3667 .cpu_prepare = intel_pmu_cpu_prepare,
3668 .cpu_starting = intel_pmu_cpu_starting,
3669 .cpu_dying = intel_pmu_cpu_dying,
3670 .guest_get_msrs = intel_guest_get_msrs,
3671 .sched_task = intel_pmu_sched_task,
3672 };
3673
3674 static __init void intel_clovertown_quirk(void)
3675 {
3676 /*
3677 * PEBS is unreliable due to:
3678 *
3679 * AJ67 - PEBS may experience CPL leaks
3680 * AJ68 - PEBS PMI may be delayed by one event
3681 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3682 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3683 *
3684 * AJ67 could be worked around by restricting the OS/USR flags.
3685 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3686 *
3687 * AJ106 could possibly be worked around by not allowing LBR
3688 * usage from PEBS, including the fixup.
3689 * AJ68 could possibly be worked around by always programming
3690 * a pebs_event_reset[0] value and coping with the lost events.
3691 *
3692 * But taken together it might just make sense to not enable PEBS on
3693 * these chips.
3694 */
3695 pr_warn("PEBS disabled due to CPU errata\n");
3696 x86_pmu.pebs = 0;
3697 x86_pmu.pebs_constraints = NULL;
3698 }
3699
3700 static int intel_snb_pebs_broken(int cpu)
3701 {
3702 u32 rev = UINT_MAX; /* default to broken for unknown models */
3703
3704 switch (cpu_data(cpu).x86_model) {
3705 case INTEL_FAM6_SANDYBRIDGE:
3706 rev = 0x28;
3707 break;
3708
3709 case INTEL_FAM6_SANDYBRIDGE_X:
3710 switch (cpu_data(cpu).x86_stepping) {
3711 case 6: rev = 0x618; break;
3712 case 7: rev = 0x70c; break;
3713 }
3714 }
3715
3716 return (cpu_data(cpu).microcode < rev);
3717 }
3718
3719 static void intel_snb_check_microcode(void)
3720 {
3721 int pebs_broken = 0;
3722 int cpu;
3723
3724 for_each_online_cpu(cpu) {
3725 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3726 break;
3727 }
3728
3729 if (pebs_broken == x86_pmu.pebs_broken)
3730 return;
3731
3732 /*
3733 * Serialized by the microcode lock..
3734 */
3735 if (x86_pmu.pebs_broken) {
3736 pr_info("PEBS enabled due to microcode update\n");
3737 x86_pmu.pebs_broken = 0;
3738 } else {
3739 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3740 x86_pmu.pebs_broken = 1;
3741 }
3742 }
3743
3744 static bool is_lbr_from(unsigned long msr)
3745 {
3746 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
3747
3748 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
3749 }
3750
3751 /*
3752 * Under certain circumstances, access certain MSR may cause #GP.
3753 * The function tests if the input MSR can be safely accessed.
3754 */
3755 static bool check_msr(unsigned long msr, u64 mask)
3756 {
3757 u64 val_old, val_new, val_tmp;
3758
3759 /*
3760 * Read the current value, change it and read it back to see if it
3761 * matches, this is needed to detect certain hardware emulators
3762 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3763 */
3764 if (rdmsrl_safe(msr, &val_old))
3765 return false;
3766
3767 /*
3768 * Only change the bits which can be updated by wrmsrl.
3769 */
3770 val_tmp = val_old ^ mask;
3771
3772 if (is_lbr_from(msr))
3773 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
3774
3775 if (wrmsrl_safe(msr, val_tmp) ||
3776 rdmsrl_safe(msr, &val_new))
3777 return false;
3778
3779 /*
3780 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
3781 * should equal rdmsrl()'s even with the quirk.
3782 */
3783 if (val_new != val_tmp)
3784 return false;
3785
3786 if (is_lbr_from(msr))
3787 val_old = lbr_from_signext_quirk_wr(val_old);
3788
3789 /* Here it's sure that the MSR can be safely accessed.
3790 * Restore the old value and return.
3791 */
3792 wrmsrl(msr, val_old);
3793
3794 return true;
3795 }
3796
3797 static __init void intel_sandybridge_quirk(void)
3798 {
3799 x86_pmu.check_microcode = intel_snb_check_microcode;
3800 cpus_read_lock();
3801 intel_snb_check_microcode();
3802 cpus_read_unlock();
3803 }
3804
3805 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3806 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3807 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3808 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3809 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3810 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3811 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3812 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
3813 };
3814
3815 static __init void intel_arch_events_quirk(void)
3816 {
3817 int bit;
3818
3819 /* disable event that reported as not presend by cpuid */
3820 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3821 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
3822 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3823 intel_arch_events_map[bit].name);
3824 }
3825 }
3826
3827 static __init void intel_nehalem_quirk(void)
3828 {
3829 union cpuid10_ebx ebx;
3830
3831 ebx.full = x86_pmu.events_maskl;
3832 if (ebx.split.no_branch_misses_retired) {
3833 /*
3834 * Erratum AAJ80 detected, we work it around by using
3835 * the BR_MISP_EXEC.ANY event. This will over-count
3836 * branch-misses, but it's still much better than the
3837 * architectural event which is often completely bogus:
3838 */
3839 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3840 ebx.split.no_branch_misses_retired = 0;
3841 x86_pmu.events_maskl = ebx.full;
3842 pr_info("CPU erratum AAJ80 worked around\n");
3843 }
3844 }
3845
3846 static bool intel_glp_counter_freezing_broken(int cpu)
3847 {
3848 u32 rev = UINT_MAX; /* default to broken for unknown stepping */
3849
3850 switch (cpu_data(cpu).x86_stepping) {
3851 case 1:
3852 rev = 0x28;
3853 break;
3854 case 8:
3855 rev = 0x6;
3856 break;
3857 }
3858
3859 return (cpu_data(cpu).microcode < rev);
3860 }
3861
3862 static __init void intel_glp_counter_freezing_quirk(void)
3863 {
3864 /* Check if it's already disabled */
3865 if (disable_counter_freezing)
3866 return;
3867
3868 /*
3869 * If the system starts with the wrong ucode, leave the
3870 * counter-freezing feature permanently disabled.
3871 */
3872 if (intel_glp_counter_freezing_broken(raw_smp_processor_id())) {
3873 pr_info("PMU counter freezing disabled due to CPU errata,"
3874 "please upgrade microcode\n");
3875 x86_pmu.counter_freezing = false;
3876 x86_pmu.handle_irq = intel_pmu_handle_irq;
3877 }
3878 }
3879
3880 /*
3881 * enable software workaround for errata:
3882 * SNB: BJ122
3883 * IVB: BV98
3884 * HSW: HSD29
3885 *
3886 * Only needed when HT is enabled. However detecting
3887 * if HT is enabled is difficult (model specific). So instead,
3888 * we enable the workaround in the early boot, and verify if
3889 * it is needed in a later initcall phase once we have valid
3890 * topology information to check if HT is actually enabled
3891 */
3892 static __init void intel_ht_bug(void)
3893 {
3894 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
3895
3896 x86_pmu.start_scheduling = intel_start_scheduling;
3897 x86_pmu.commit_scheduling = intel_commit_scheduling;
3898 x86_pmu.stop_scheduling = intel_stop_scheduling;
3899 }
3900
3901 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
3902 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
3903
3904 /* Haswell special events */
3905 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
3906 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
3907 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
3908 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
3909 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
3910 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
3911 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
3912 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
3913 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
3914 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
3915 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3916 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
3917
3918 static struct attribute *hsw_events_attrs[] = {
3919 EVENT_PTR(td_slots_issued),
3920 EVENT_PTR(td_slots_retired),
3921 EVENT_PTR(td_fetch_bubbles),
3922 EVENT_PTR(td_total_slots),
3923 EVENT_PTR(td_total_slots_scale),
3924 EVENT_PTR(td_recovery_bubbles),
3925 EVENT_PTR(td_recovery_bubbles_scale),
3926 NULL
3927 };
3928
3929 static struct attribute *hsw_mem_events_attrs[] = {
3930 EVENT_PTR(mem_ld_hsw),
3931 EVENT_PTR(mem_st_hsw),
3932 NULL,
3933 };
3934
3935 static struct attribute *hsw_tsx_events_attrs[] = {
3936 EVENT_PTR(tx_start),
3937 EVENT_PTR(tx_commit),
3938 EVENT_PTR(tx_abort),
3939 EVENT_PTR(tx_capacity),
3940 EVENT_PTR(tx_conflict),
3941 EVENT_PTR(el_start),
3942 EVENT_PTR(el_commit),
3943 EVENT_PTR(el_abort),
3944 EVENT_PTR(el_capacity),
3945 EVENT_PTR(el_conflict),
3946 EVENT_PTR(cycles_t),
3947 EVENT_PTR(cycles_ct),
3948 NULL
3949 };
3950
3951 static ssize_t freeze_on_smi_show(struct device *cdev,
3952 struct device_attribute *attr,
3953 char *buf)
3954 {
3955 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
3956 }
3957
3958 static DEFINE_MUTEX(freeze_on_smi_mutex);
3959
3960 static ssize_t freeze_on_smi_store(struct device *cdev,
3961 struct device_attribute *attr,
3962 const char *buf, size_t count)
3963 {
3964 unsigned long val;
3965 ssize_t ret;
3966
3967 ret = kstrtoul(buf, 0, &val);
3968 if (ret)
3969 return ret;
3970
3971 if (val > 1)
3972 return -EINVAL;
3973
3974 mutex_lock(&freeze_on_smi_mutex);
3975
3976 if (x86_pmu.attr_freeze_on_smi == val)
3977 goto done;
3978
3979 x86_pmu.attr_freeze_on_smi = val;
3980
3981 get_online_cpus();
3982 on_each_cpu(flip_smm_bit, &val, 1);
3983 put_online_cpus();
3984 done:
3985 mutex_unlock(&freeze_on_smi_mutex);
3986
3987 return count;
3988 }
3989
3990 static DEVICE_ATTR_RW(freeze_on_smi);
3991
3992 static ssize_t branches_show(struct device *cdev,
3993 struct device_attribute *attr,
3994 char *buf)
3995 {
3996 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
3997 }
3998
3999 static DEVICE_ATTR_RO(branches);
4000
4001 static struct attribute *lbr_attrs[] = {
4002 &dev_attr_branches.attr,
4003 NULL
4004 };
4005
4006 static char pmu_name_str[30];
4007
4008 static ssize_t pmu_name_show(struct device *cdev,
4009 struct device_attribute *attr,
4010 char *buf)
4011 {
4012 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
4013 }
4014
4015 static DEVICE_ATTR_RO(pmu_name);
4016
4017 static struct attribute *intel_pmu_caps_attrs[] = {
4018 &dev_attr_pmu_name.attr,
4019 NULL
4020 };
4021
4022 static struct attribute *intel_pmu_attrs[] = {
4023 &dev_attr_freeze_on_smi.attr,
4024 NULL,
4025 };
4026
4027 static __init struct attribute **
4028 get_events_attrs(struct attribute **base,
4029 struct attribute **mem,
4030 struct attribute **tsx)
4031 {
4032 struct attribute **attrs = base;
4033 struct attribute **old;
4034
4035 if (mem && x86_pmu.pebs)
4036 attrs = merge_attr(attrs, mem);
4037
4038 if (tsx && boot_cpu_has(X86_FEATURE_RTM)) {
4039 old = attrs;
4040 attrs = merge_attr(attrs, tsx);
4041 if (old != base)
4042 kfree(old);
4043 }
4044
4045 return attrs;
4046 }
4047
4048 __init int intel_pmu_init(void)
4049 {
4050 struct attribute **extra_attr = NULL;
4051 struct attribute **mem_attr = NULL;
4052 struct attribute **tsx_attr = NULL;
4053 struct attribute **to_free = NULL;
4054 union cpuid10_edx edx;
4055 union cpuid10_eax eax;
4056 union cpuid10_ebx ebx;
4057 struct event_constraint *c;
4058 unsigned int unused;
4059 struct extra_reg *er;
4060 int version, i;
4061 char *name;
4062
4063 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
4064 switch (boot_cpu_data.x86) {
4065 case 0x6:
4066 return p6_pmu_init();
4067 case 0xb:
4068 return knc_pmu_init();
4069 case 0xf:
4070 return p4_pmu_init();
4071 }
4072 return -ENODEV;
4073 }
4074
4075 /*
4076 * Check whether the Architectural PerfMon supports
4077 * Branch Misses Retired hw_event or not.
4078 */
4079 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
4080 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
4081 return -ENODEV;
4082
4083 version = eax.split.version_id;
4084 if (version < 2)
4085 x86_pmu = core_pmu;
4086 else
4087 x86_pmu = intel_pmu;
4088
4089 x86_pmu.version = version;
4090 x86_pmu.num_counters = eax.split.num_counters;
4091 x86_pmu.cntval_bits = eax.split.bit_width;
4092 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
4093
4094 x86_pmu.events_maskl = ebx.full;
4095 x86_pmu.events_mask_len = eax.split.mask_length;
4096
4097 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
4098
4099 /*
4100 * Quirk: v2 perfmon does not report fixed-purpose events, so
4101 * assume at least 3 events, when not running in a hypervisor:
4102 */
4103 if (version > 1) {
4104 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
4105
4106 x86_pmu.num_counters_fixed =
4107 max((int)edx.split.num_counters_fixed, assume);
4108 }
4109
4110 if (version >= 4)
4111 x86_pmu.counter_freezing = !disable_counter_freezing;
4112
4113 if (boot_cpu_has(X86_FEATURE_PDCM)) {
4114 u64 capabilities;
4115
4116 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
4117 x86_pmu.intel_cap.capabilities = capabilities;
4118 }
4119
4120 intel_ds_init();
4121
4122 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
4123
4124 /*
4125 * Install the hw-cache-events table:
4126 */
4127 switch (boot_cpu_data.x86_model) {
4128 case INTEL_FAM6_CORE_YONAH:
4129 pr_cont("Core events, ");
4130 name = "core";
4131 break;
4132
4133 case INTEL_FAM6_CORE2_MEROM:
4134 x86_add_quirk(intel_clovertown_quirk);
4135 case INTEL_FAM6_CORE2_MEROM_L:
4136 case INTEL_FAM6_CORE2_PENRYN:
4137 case INTEL_FAM6_CORE2_DUNNINGTON:
4138 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
4139 sizeof(hw_cache_event_ids));
4140
4141 intel_pmu_lbr_init_core();
4142
4143 x86_pmu.event_constraints = intel_core2_event_constraints;
4144 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
4145 pr_cont("Core2 events, ");
4146 name = "core2";
4147 break;
4148
4149 case INTEL_FAM6_NEHALEM:
4150 case INTEL_FAM6_NEHALEM_EP:
4151 case INTEL_FAM6_NEHALEM_EX:
4152 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
4153 sizeof(hw_cache_event_ids));
4154 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
4155 sizeof(hw_cache_extra_regs));
4156
4157 intel_pmu_lbr_init_nhm();
4158
4159 x86_pmu.event_constraints = intel_nehalem_event_constraints;
4160 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
4161 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
4162 x86_pmu.extra_regs = intel_nehalem_extra_regs;
4163
4164 mem_attr = nhm_mem_events_attrs;
4165
4166 /* UOPS_ISSUED.STALLED_CYCLES */
4167 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4168 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4169 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
4170 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4171 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
4172
4173 intel_pmu_pebs_data_source_nhm();
4174 x86_add_quirk(intel_nehalem_quirk);
4175 x86_pmu.pebs_no_tlb = 1;
4176 extra_attr = nhm_format_attr;
4177
4178 pr_cont("Nehalem events, ");
4179 name = "nehalem";
4180 break;
4181
4182 case INTEL_FAM6_ATOM_BONNELL:
4183 case INTEL_FAM6_ATOM_BONNELL_MID:
4184 case INTEL_FAM6_ATOM_SALTWELL:
4185 case INTEL_FAM6_ATOM_SALTWELL_MID:
4186 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
4187 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
4188 sizeof(hw_cache_event_ids));
4189
4190 intel_pmu_lbr_init_atom();
4191
4192 x86_pmu.event_constraints = intel_gen_event_constraints;
4193 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
4194 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
4195 pr_cont("Atom events, ");
4196 name = "bonnell";
4197 break;
4198
4199 case INTEL_FAM6_ATOM_SILVERMONT:
4200 case INTEL_FAM6_ATOM_SILVERMONT_X:
4201 case INTEL_FAM6_ATOM_SILVERMONT_MID:
4202 case INTEL_FAM6_ATOM_AIRMONT:
4203 case INTEL_FAM6_ATOM_AIRMONT_MID:
4204 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
4205 sizeof(hw_cache_event_ids));
4206 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
4207 sizeof(hw_cache_extra_regs));
4208
4209 intel_pmu_lbr_init_slm();
4210
4211 x86_pmu.event_constraints = intel_slm_event_constraints;
4212 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
4213 x86_pmu.extra_regs = intel_slm_extra_regs;
4214 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4215 x86_pmu.cpu_events = slm_events_attrs;
4216 extra_attr = slm_format_attr;
4217 pr_cont("Silvermont events, ");
4218 name = "silvermont";
4219 break;
4220
4221 case INTEL_FAM6_ATOM_GOLDMONT:
4222 case INTEL_FAM6_ATOM_GOLDMONT_X:
4223 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
4224 sizeof(hw_cache_event_ids));
4225 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
4226 sizeof(hw_cache_extra_regs));
4227
4228 intel_pmu_lbr_init_skl();
4229
4230 x86_pmu.event_constraints = intel_slm_event_constraints;
4231 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
4232 x86_pmu.extra_regs = intel_glm_extra_regs;
4233 /*
4234 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4235 * for precise cycles.
4236 * :pp is identical to :ppp
4237 */
4238 x86_pmu.pebs_aliases = NULL;
4239 x86_pmu.pebs_prec_dist = true;
4240 x86_pmu.lbr_pt_coexist = true;
4241 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4242 x86_pmu.cpu_events = glm_events_attrs;
4243 extra_attr = slm_format_attr;
4244 pr_cont("Goldmont events, ");
4245 name = "goldmont";
4246 break;
4247
4248 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4249 x86_add_quirk(intel_glp_counter_freezing_quirk);
4250 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
4251 sizeof(hw_cache_event_ids));
4252 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
4253 sizeof(hw_cache_extra_regs));
4254
4255 intel_pmu_lbr_init_skl();
4256
4257 x86_pmu.event_constraints = intel_slm_event_constraints;
4258 x86_pmu.extra_regs = intel_glm_extra_regs;
4259 /*
4260 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4261 * for precise cycles.
4262 */
4263 x86_pmu.pebs_aliases = NULL;
4264 x86_pmu.pebs_prec_dist = true;
4265 x86_pmu.lbr_pt_coexist = true;
4266 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4267 x86_pmu.flags |= PMU_FL_PEBS_ALL;
4268 x86_pmu.get_event_constraints = glp_get_event_constraints;
4269 x86_pmu.cpu_events = glm_events_attrs;
4270 /* Goldmont Plus has 4-wide pipeline */
4271 event_attr_td_total_slots_scale_glm.event_str = "4";
4272 extra_attr = slm_format_attr;
4273 pr_cont("Goldmont plus events, ");
4274 name = "goldmont_plus";
4275 break;
4276
4277 case INTEL_FAM6_WESTMERE:
4278 case INTEL_FAM6_WESTMERE_EP:
4279 case INTEL_FAM6_WESTMERE_EX:
4280 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
4281 sizeof(hw_cache_event_ids));
4282 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
4283 sizeof(hw_cache_extra_regs));
4284
4285 intel_pmu_lbr_init_nhm();
4286
4287 x86_pmu.event_constraints = intel_westmere_event_constraints;
4288 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
4289 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
4290 x86_pmu.extra_regs = intel_westmere_extra_regs;
4291 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4292
4293 mem_attr = nhm_mem_events_attrs;
4294
4295 /* UOPS_ISSUED.STALLED_CYCLES */
4296 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4297 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4298 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
4299 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4300 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
4301
4302 intel_pmu_pebs_data_source_nhm();
4303 extra_attr = nhm_format_attr;
4304 pr_cont("Westmere events, ");
4305 name = "westmere";
4306 break;
4307
4308 case INTEL_FAM6_SANDYBRIDGE:
4309 case INTEL_FAM6_SANDYBRIDGE_X:
4310 x86_add_quirk(intel_sandybridge_quirk);
4311 x86_add_quirk(intel_ht_bug);
4312 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4313 sizeof(hw_cache_event_ids));
4314 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4315 sizeof(hw_cache_extra_regs));
4316
4317 intel_pmu_lbr_init_snb();
4318
4319 x86_pmu.event_constraints = intel_snb_event_constraints;
4320 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
4321 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
4322 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
4323 x86_pmu.extra_regs = intel_snbep_extra_regs;
4324 else
4325 x86_pmu.extra_regs = intel_snb_extra_regs;
4326
4327
4328 /* all extra regs are per-cpu when HT is on */
4329 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4330 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4331
4332 x86_pmu.cpu_events = snb_events_attrs;
4333 mem_attr = snb_mem_events_attrs;
4334
4335 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
4336 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4337 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4338 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
4339 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4340 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
4341
4342 extra_attr = nhm_format_attr;
4343
4344 pr_cont("SandyBridge events, ");
4345 name = "sandybridge";
4346 break;
4347
4348 case INTEL_FAM6_IVYBRIDGE:
4349 case INTEL_FAM6_IVYBRIDGE_X:
4350 x86_add_quirk(intel_ht_bug);
4351 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4352 sizeof(hw_cache_event_ids));
4353 /* dTLB-load-misses on IVB is different than SNB */
4354 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
4355
4356 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4357 sizeof(hw_cache_extra_regs));
4358
4359 intel_pmu_lbr_init_snb();
4360
4361 x86_pmu.event_constraints = intel_ivb_event_constraints;
4362 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
4363 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4364 x86_pmu.pebs_prec_dist = true;
4365 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
4366 x86_pmu.extra_regs = intel_snbep_extra_regs;
4367 else
4368 x86_pmu.extra_regs = intel_snb_extra_regs;
4369 /* all extra regs are per-cpu when HT is on */
4370 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4371 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4372
4373 x86_pmu.cpu_events = snb_events_attrs;
4374 mem_attr = snb_mem_events_attrs;
4375
4376 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
4377 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4378 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4379
4380 extra_attr = nhm_format_attr;
4381
4382 pr_cont("IvyBridge events, ");
4383 name = "ivybridge";
4384 break;
4385
4386
4387 case INTEL_FAM6_HASWELL_CORE:
4388 case INTEL_FAM6_HASWELL_X:
4389 case INTEL_FAM6_HASWELL_ULT:
4390 case INTEL_FAM6_HASWELL_GT3E:
4391 x86_add_quirk(intel_ht_bug);
4392 x86_pmu.late_ack = true;
4393 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4394 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4395
4396 intel_pmu_lbr_init_hsw();
4397
4398 x86_pmu.event_constraints = intel_hsw_event_constraints;
4399 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
4400 x86_pmu.extra_regs = intel_snbep_extra_regs;
4401 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4402 x86_pmu.pebs_prec_dist = true;
4403 /* all extra regs are per-cpu when HT is on */
4404 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4405 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4406
4407 x86_pmu.hw_config = hsw_hw_config;
4408 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4409 x86_pmu.cpu_events = hsw_events_attrs;
4410 x86_pmu.lbr_double_abort = true;
4411 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4412 hsw_format_attr : nhm_format_attr;
4413 mem_attr = hsw_mem_events_attrs;
4414 tsx_attr = hsw_tsx_events_attrs;
4415 pr_cont("Haswell events, ");
4416 name = "haswell";
4417 break;
4418
4419 case INTEL_FAM6_BROADWELL_CORE:
4420 case INTEL_FAM6_BROADWELL_XEON_D:
4421 case INTEL_FAM6_BROADWELL_GT3E:
4422 case INTEL_FAM6_BROADWELL_X:
4423 x86_pmu.late_ack = true;
4424 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4425 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4426
4427 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
4428 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
4429 BDW_L3_MISS|HSW_SNOOP_DRAM;
4430 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
4431 HSW_SNOOP_DRAM;
4432 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
4433 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4434 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
4435 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4436
4437 intel_pmu_lbr_init_hsw();
4438
4439 x86_pmu.event_constraints = intel_bdw_event_constraints;
4440 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
4441 x86_pmu.extra_regs = intel_snbep_extra_regs;
4442 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4443 x86_pmu.pebs_prec_dist = true;
4444 /* all extra regs are per-cpu when HT is on */
4445 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4446 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4447
4448 x86_pmu.hw_config = hsw_hw_config;
4449 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4450 x86_pmu.cpu_events = hsw_events_attrs;
4451 x86_pmu.limit_period = bdw_limit_period;
4452 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4453 hsw_format_attr : nhm_format_attr;
4454 mem_attr = hsw_mem_events_attrs;
4455 tsx_attr = hsw_tsx_events_attrs;
4456 pr_cont("Broadwell events, ");
4457 name = "broadwell";
4458 break;
4459
4460 case INTEL_FAM6_XEON_PHI_KNL:
4461 case INTEL_FAM6_XEON_PHI_KNM:
4462 memcpy(hw_cache_event_ids,
4463 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4464 memcpy(hw_cache_extra_regs,
4465 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4466 intel_pmu_lbr_init_knl();
4467
4468 x86_pmu.event_constraints = intel_slm_event_constraints;
4469 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
4470 x86_pmu.extra_regs = intel_knl_extra_regs;
4471
4472 /* all extra regs are per-cpu when HT is on */
4473 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4474 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4475 extra_attr = slm_format_attr;
4476 pr_cont("Knights Landing/Mill events, ");
4477 name = "knights-landing";
4478 break;
4479
4480 case INTEL_FAM6_SKYLAKE_MOBILE:
4481 case INTEL_FAM6_SKYLAKE_DESKTOP:
4482 case INTEL_FAM6_SKYLAKE_X:
4483 case INTEL_FAM6_KABYLAKE_MOBILE:
4484 case INTEL_FAM6_KABYLAKE_DESKTOP:
4485 x86_pmu.late_ack = true;
4486 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4487 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4488 intel_pmu_lbr_init_skl();
4489
4490 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
4491 event_attr_td_recovery_bubbles.event_str_noht =
4492 "event=0xd,umask=0x1,cmask=1";
4493 event_attr_td_recovery_bubbles.event_str_ht =
4494 "event=0xd,umask=0x1,cmask=1,any=1";
4495
4496 x86_pmu.event_constraints = intel_skl_event_constraints;
4497 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
4498 x86_pmu.extra_regs = intel_skl_extra_regs;
4499 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
4500 x86_pmu.pebs_prec_dist = true;
4501 /* all extra regs are per-cpu when HT is on */
4502 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4503 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4504
4505 x86_pmu.hw_config = hsw_hw_config;
4506 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4507 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4508 hsw_format_attr : nhm_format_attr;
4509 extra_attr = merge_attr(extra_attr, skl_format_attr);
4510 to_free = extra_attr;
4511 x86_pmu.cpu_events = hsw_events_attrs;
4512 mem_attr = hsw_mem_events_attrs;
4513 tsx_attr = hsw_tsx_events_attrs;
4514 intel_pmu_pebs_data_source_skl(
4515 boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X);
4516 pr_cont("Skylake events, ");
4517 name = "skylake";
4518 break;
4519
4520 default:
4521 switch (x86_pmu.version) {
4522 case 1:
4523 x86_pmu.event_constraints = intel_v1_event_constraints;
4524 pr_cont("generic architected perfmon v1, ");
4525 name = "generic_arch_v1";
4526 break;
4527 default:
4528 /*
4529 * default constraints for v2 and up
4530 */
4531 x86_pmu.event_constraints = intel_gen_event_constraints;
4532 pr_cont("generic architected perfmon, ");
4533 name = "generic_arch_v2+";
4534 break;
4535 }
4536 }
4537
4538 snprintf(pmu_name_str, sizeof pmu_name_str, "%s", name);
4539
4540 if (version >= 2 && extra_attr) {
4541 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
4542 extra_attr);
4543 WARN_ON(!x86_pmu.format_attrs);
4544 }
4545
4546 x86_pmu.cpu_events = get_events_attrs(x86_pmu.cpu_events,
4547 mem_attr, tsx_attr);
4548
4549 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
4550 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
4551 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
4552 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
4553 }
4554 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1;
4555
4556 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
4557 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
4558 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
4559 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
4560 }
4561
4562 x86_pmu.intel_ctrl |=
4563 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
4564
4565 if (x86_pmu.event_constraints) {
4566 /*
4567 * event on fixed counter2 (REF_CYCLES) only works on this
4568 * counter, so do not extend mask to generic counters
4569 */
4570 for_each_event_constraint(c, x86_pmu.event_constraints) {
4571 if (c->cmask == FIXED_EVENT_FLAGS
4572 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
4573 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
4574 }
4575 c->idxmsk64 &=
4576 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
4577 c->weight = hweight64(c->idxmsk64);
4578 }
4579 }
4580
4581 /*
4582 * Access LBR MSR may cause #GP under certain circumstances.
4583 * E.g. KVM doesn't support LBR MSR
4584 * Check all LBT MSR here.
4585 * Disable LBR access if any LBR MSRs can not be accessed.
4586 */
4587 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
4588 x86_pmu.lbr_nr = 0;
4589 for (i = 0; i < x86_pmu.lbr_nr; i++) {
4590 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
4591 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
4592 x86_pmu.lbr_nr = 0;
4593 }
4594
4595 x86_pmu.caps_attrs = intel_pmu_caps_attrs;
4596
4597 if (x86_pmu.lbr_nr) {
4598 x86_pmu.caps_attrs = merge_attr(x86_pmu.caps_attrs, lbr_attrs);
4599 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
4600 }
4601
4602 /*
4603 * Access extra MSR may cause #GP under certain circumstances.
4604 * E.g. KVM doesn't support offcore event
4605 * Check all extra_regs here.
4606 */
4607 if (x86_pmu.extra_regs) {
4608 for (er = x86_pmu.extra_regs; er->msr; er++) {
4609 er->extra_msr_access = check_msr(er->msr, 0x11UL);
4610 /* Disable LBR select mapping */
4611 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
4612 x86_pmu.lbr_sel_map = NULL;
4613 }
4614 }
4615
4616 /* Support full width counters using alternative MSR range */
4617 if (x86_pmu.intel_cap.full_width_write) {
4618 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
4619 x86_pmu.perfctr = MSR_IA32_PMC0;
4620 pr_cont("full-width counters, ");
4621 }
4622
4623 /*
4624 * For arch perfmon 4 use counter freezing to avoid
4625 * several MSR accesses in the PMI.
4626 */
4627 if (x86_pmu.counter_freezing)
4628 x86_pmu.handle_irq = intel_pmu_handle_irq_v4;
4629
4630 kfree(to_free);
4631 return 0;
4632 }
4633
4634 /*
4635 * HT bug: phase 2 init
4636 * Called once we have valid topology information to check
4637 * whether or not HT is enabled
4638 * If HT is off, then we disable the workaround
4639 */
4640 static __init int fixup_ht_bug(void)
4641 {
4642 int c;
4643 /*
4644 * problem not present on this CPU model, nothing to do
4645 */
4646 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
4647 return 0;
4648
4649 if (topology_max_smt_threads() > 1) {
4650 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
4651 return 0;
4652 }
4653
4654 cpus_read_lock();
4655
4656 hardlockup_detector_perf_stop();
4657
4658 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
4659
4660 x86_pmu.start_scheduling = NULL;
4661 x86_pmu.commit_scheduling = NULL;
4662 x86_pmu.stop_scheduling = NULL;
4663
4664 hardlockup_detector_perf_restart();
4665
4666 for_each_online_cpu(c)
4667 free_excl_cntrs(c);
4668
4669 cpus_read_unlock();
4670 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
4671 return 0;
4672 }
4673 subsys_initcall(fixup_ht_bug)
Linux with added FPC-III support