2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/clk-provider.h>
26 #define PLL_BASE_BYPASS BIT(31)
27 #define PLL_BASE_ENABLE BIT(30)
28 #define PLL_BASE_REF_ENABLE BIT(29)
29 #define PLL_BASE_OVERRIDE BIT(28)
31 #define PLL_BASE_DIVP_SHIFT 20
32 #define PLL_BASE_DIVP_WIDTH 3
33 #define PLL_BASE_DIVN_SHIFT 8
34 #define PLL_BASE_DIVN_WIDTH 10
35 #define PLL_BASE_DIVM_SHIFT 0
36 #define PLL_BASE_DIVM_WIDTH 5
37 #define PLLU_POST_DIVP_MASK 0x1
39 #define PLL_MISC_DCCON_SHIFT 20
40 #define PLL_MISC_CPCON_SHIFT 8
41 #define PLL_MISC_CPCON_WIDTH 4
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43 #define PLL_MISC_LFCON_SHIFT 4
44 #define PLL_MISC_LFCON_WIDTH 4
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46 #define PLL_MISC_VCOCON_SHIFT 0
47 #define PLL_MISC_VCOCON_WIDTH 4
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
50 #define OUT_OF_TABLE_CPCON 8
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
56 #define PLL_POST_LOCK_DELAY 50
58 #define PLLDU_LFCON_SET_DIVN 600
60 #define PLLE_BASE_DIVCML_SHIFT 24
61 #define PLLE_BASE_DIVCML_MASK 0xf
62 #define PLLE_BASE_DIVP_SHIFT 16
63 #define PLLE_BASE_DIVP_WIDTH 6
64 #define PLLE_BASE_DIVN_SHIFT 8
65 #define PLLE_BASE_DIVN_WIDTH 8
66 #define PLLE_BASE_DIVM_SHIFT 0
67 #define PLLE_BASE_DIVM_WIDTH 8
68 #define PLLE_BASE_ENABLE BIT(31)
70 #define PLLE_MISC_SETUP_BASE_SHIFT 16
71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
72 #define PLLE_MISC_LOCK_ENABLE BIT(9)
73 #define PLLE_MISC_READY BIT(15)
74 #define PLLE_MISC_SETUP_EX_SHIFT 2
75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
77 PLLE_MISC_SETUP_EX_MASK)
78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
80 #define PLLE_SS_CTRL 0x68
81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
83 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
84 #define PLLE_SS_CNTL_CENTER BIT(14)
85 #define PLLE_SS_CNTL_INVERT BIT(15)
86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
88 #define PLLE_SS_MAX_MASK 0x1ff
89 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
90 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
91 #define PLLE_SS_INC_MASK (0xff << 16)
92 #define PLLE_SS_INC_VAL (0x1 << 16)
93 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
94 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
95 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
96 #define PLLE_SS_COEFFICIENTS_MASK \
97 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
98 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
99 (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
100 PLLE_SS_INCINTRV_VAL_TEGRA114)
101 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
102 (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
103 PLLE_SS_INCINTRV_VAL_TEGRA210)
105 #define PLLE_AUX_PLLP_SEL BIT(2)
106 #define PLLE_AUX_USE_LOCKDET BIT(3)
107 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
108 #define PLLE_AUX_SS_SWCTL BIT(6)
109 #define PLLE_AUX_SEQ_ENABLE BIT(24)
110 #define PLLE_AUX_SEQ_START_STATE BIT(25)
111 #define PLLE_AUX_PLLRE_SEL BIT(28)
112 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
114 #define XUSBIO_PLL_CFG0 0x51c
115 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
116 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
117 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
118 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
119 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
121 #define SATA_PLL_CFG0 0x490
122 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
123 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
124 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
125 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
127 #define PLLE_MISC_PLLE_PTS BIT(8)
128 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
129 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
130 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
131 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
132 #define PLLE_MISC_VREG_CTRL_SHIFT 2
133 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
135 #define PLLCX_MISC_STROBE BIT(31)
136 #define PLLCX_MISC_RESET BIT(30)
137 #define PLLCX_MISC_SDM_DIV_SHIFT 28
138 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
139 #define PLLCX_MISC_FILT_DIV_SHIFT 26
140 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
141 #define PLLCX_MISC_ALPHA_SHIFT 18
142 #define PLLCX_MISC_DIV_LOW_RANGE \
143 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
144 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
145 #define PLLCX_MISC_DIV_HIGH_RANGE \
146 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
147 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
148 #define PLLCX_MISC_COEF_LOW_RANGE \
149 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
150 #define PLLCX_MISC_KA_SHIFT 2
151 #define PLLCX_MISC_KB_SHIFT 9
152 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
153 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
154 PLLCX_MISC_DIV_LOW_RANGE | \
156 #define PLLCX_MISC1_DEFAULT 0x000d2308
157 #define PLLCX_MISC2_DEFAULT 0x30211200
158 #define PLLCX_MISC3_DEFAULT 0x200
160 #define PMC_SATA_PWRGT 0x1ac
161 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
162 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
164 #define PLLSS_MISC_KCP 0
165 #define PLLSS_MISC_KVCO 0
166 #define PLLSS_MISC_SETUP 0
167 #define PLLSS_EN_SDM 0
168 #define PLLSS_EN_SSC 0
169 #define PLLSS_EN_DITHER2 0
170 #define PLLSS_EN_DITHER 1
171 #define PLLSS_SDM_RESET 0
172 #define PLLSS_CLAMP 0
173 #define PLLSS_SDM_SSC_MAX 0
174 #define PLLSS_SDM_SSC_MIN 0
175 #define PLLSS_SDM_SSC_STEP 0
176 #define PLLSS_SDM_DIN 0
177 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
178 (PLLSS_MISC_KVCO << 24) | \
180 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
181 (PLLSS_EN_SSC << 30) | \
182 (PLLSS_EN_DITHER2 << 29) | \
183 (PLLSS_EN_DITHER << 28) | \
184 (PLLSS_SDM_RESET) << 27 | \
186 #define PLLSS_CTRL1_DEFAULT \
187 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
188 #define PLLSS_CTRL2_DEFAULT \
189 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
190 #define PLLSS_LOCK_OVERRIDE BIT(24)
191 #define PLLSS_REF_SRC_SEL_SHIFT 25
192 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
194 #define UTMIP_PLL_CFG1 0x484
195 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
196 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
197 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
198 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
199 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
200 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
201 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
203 #define UTMIP_PLL_CFG2 0x488
204 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
205 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
206 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
207 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
208 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
209 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
210 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
211 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
212 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
213 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
214 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
216 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
217 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
218 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
219 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
220 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
221 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
222 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
223 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
224 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
226 #define PLLU_HW_PWRDN_CFG0 0x530
227 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
228 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
229 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
230 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
231 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
232 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
234 #define XUSB_PLL_CFG0 0x534
235 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
236 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
238 #define PLLU_BASE_CLKENABLE_USB BIT(21)
239 #define PLLU_BASE_OVERRIDE BIT(24)
241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
242 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
243 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
244 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
245 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
246 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
248 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
249 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
250 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
251 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
252 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
253 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
255 #define mask(w) ((1 << (w)) - 1)
256 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
257 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
258 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
259 mask(p->params->div_nmp->divp_width))
260 #define sdm_din_mask(p) p->params->sdm_din_mask
261 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
263 #define divm_shift(p) (p)->params->div_nmp->divm_shift
264 #define divn_shift(p) (p)->params->div_nmp->divn_shift
265 #define divp_shift(p) (p)->params->div_nmp->divp_shift
267 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
268 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
269 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
271 #define divm_max(p) (divm_mask(p))
272 #define divn_max(p) (divn_mask(p))
273 #define divp_max(p) (1 << (divp_mask(p)))
275 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
276 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
278 static struct div_nmp default_nmp
= {
279 .divn_shift
= PLL_BASE_DIVN_SHIFT
,
280 .divn_width
= PLL_BASE_DIVN_WIDTH
,
281 .divm_shift
= PLL_BASE_DIVM_SHIFT
,
282 .divm_width
= PLL_BASE_DIVM_WIDTH
,
283 .divp_shift
= PLL_BASE_DIVP_SHIFT
,
284 .divp_width
= PLL_BASE_DIVP_WIDTH
,
287 static void clk_pll_enable_lock(struct tegra_clk_pll
*pll
)
291 if (!(pll
->params
->flags
& TEGRA_PLL_USE_LOCK
))
294 if (!(pll
->params
->flags
& TEGRA_PLL_HAS_LOCK_ENABLE
))
297 val
= pll_readl_misc(pll
);
298 val
|= BIT(pll
->params
->lock_enable_bit_idx
);
299 pll_writel_misc(val
, pll
);
302 static int clk_pll_wait_for_lock(struct tegra_clk_pll
*pll
)
306 void __iomem
*lock_addr
;
308 if (!(pll
->params
->flags
& TEGRA_PLL_USE_LOCK
)) {
309 udelay(pll
->params
->lock_delay
);
313 lock_addr
= pll
->clk_base
;
314 if (pll
->params
->flags
& TEGRA_PLL_LOCK_MISC
)
315 lock_addr
+= pll
->params
->misc_reg
;
317 lock_addr
+= pll
->params
->base_reg
;
319 lock_mask
= pll
->params
->lock_mask
;
321 for (i
= 0; i
< pll
->params
->lock_delay
; i
++) {
322 val
= readl_relaxed(lock_addr
);
323 if ((val
& lock_mask
) == lock_mask
) {
324 udelay(PLL_POST_LOCK_DELAY
);
327 udelay(2); /* timeout = 2 * lock time */
330 pr_err("%s: Timed out waiting for pll %s lock\n", __func__
,
331 clk_hw_get_name(&pll
->hw
));
336 int tegra_pll_wait_for_lock(struct tegra_clk_pll
*pll
)
338 return clk_pll_wait_for_lock(pll
);
341 static int clk_pll_is_enabled(struct clk_hw
*hw
)
343 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
346 if (pll
->params
->flags
& TEGRA_PLLM
) {
347 val
= readl_relaxed(pll
->pmc
+ PMC_PLLP_WB0_OVERRIDE
);
348 if (val
& PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE
)
349 return val
& PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE
? 1 : 0;
352 val
= pll_readl_base(pll
);
354 return val
& PLL_BASE_ENABLE
? 1 : 0;
357 static void _clk_pll_enable(struct clk_hw
*hw
)
359 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
362 if (pll
->params
->iddq_reg
) {
363 val
= pll_readl(pll
->params
->iddq_reg
, pll
);
364 val
&= ~BIT(pll
->params
->iddq_bit_idx
);
365 pll_writel(val
, pll
->params
->iddq_reg
, pll
);
369 if (pll
->params
->reset_reg
) {
370 val
= pll_readl(pll
->params
->reset_reg
, pll
);
371 val
&= ~BIT(pll
->params
->reset_bit_idx
);
372 pll_writel(val
, pll
->params
->reset_reg
, pll
);
375 clk_pll_enable_lock(pll
);
377 val
= pll_readl_base(pll
);
378 if (pll
->params
->flags
& TEGRA_PLL_BYPASS
)
379 val
&= ~PLL_BASE_BYPASS
;
380 val
|= PLL_BASE_ENABLE
;
381 pll_writel_base(val
, pll
);
383 if (pll
->params
->flags
& TEGRA_PLLM
) {
384 val
= readl_relaxed(pll
->pmc
+ PMC_PLLP_WB0_OVERRIDE
);
385 val
|= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE
;
386 writel_relaxed(val
, pll
->pmc
+ PMC_PLLP_WB0_OVERRIDE
);
390 static void _clk_pll_disable(struct clk_hw
*hw
)
392 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
395 val
= pll_readl_base(pll
);
396 if (pll
->params
->flags
& TEGRA_PLL_BYPASS
)
397 val
&= ~PLL_BASE_BYPASS
;
398 val
&= ~PLL_BASE_ENABLE
;
399 pll_writel_base(val
, pll
);
401 if (pll
->params
->flags
& TEGRA_PLLM
) {
402 val
= readl_relaxed(pll
->pmc
+ PMC_PLLP_WB0_OVERRIDE
);
403 val
&= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE
;
404 writel_relaxed(val
, pll
->pmc
+ PMC_PLLP_WB0_OVERRIDE
);
407 if (pll
->params
->reset_reg
) {
408 val
= pll_readl(pll
->params
->reset_reg
, pll
);
409 val
|= BIT(pll
->params
->reset_bit_idx
);
410 pll_writel(val
, pll
->params
->reset_reg
, pll
);
413 if (pll
->params
->iddq_reg
) {
414 val
= pll_readl(pll
->params
->iddq_reg
, pll
);
415 val
|= BIT(pll
->params
->iddq_bit_idx
);
416 pll_writel(val
, pll
->params
->iddq_reg
, pll
);
421 static void pll_clk_start_ss(struct tegra_clk_pll
*pll
)
423 if (pll
->params
->defaults_set
&& pll
->params
->ssc_ctrl_reg
) {
424 u32 val
= pll_readl(pll
->params
->ssc_ctrl_reg
, pll
);
426 val
|= pll
->params
->ssc_ctrl_en_mask
;
427 pll_writel(val
, pll
->params
->ssc_ctrl_reg
, pll
);
431 static void pll_clk_stop_ss(struct tegra_clk_pll
*pll
)
433 if (pll
->params
->defaults_set
&& pll
->params
->ssc_ctrl_reg
) {
434 u32 val
= pll_readl(pll
->params
->ssc_ctrl_reg
, pll
);
436 val
&= ~pll
->params
->ssc_ctrl_en_mask
;
437 pll_writel(val
, pll
->params
->ssc_ctrl_reg
, pll
);
441 static int clk_pll_enable(struct clk_hw
*hw
)
443 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
444 unsigned long flags
= 0;
448 spin_lock_irqsave(pll
->lock
, flags
);
452 ret
= clk_pll_wait_for_lock(pll
);
454 pll_clk_start_ss(pll
);
457 spin_unlock_irqrestore(pll
->lock
, flags
);
462 static void clk_pll_disable(struct clk_hw
*hw
)
464 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
465 unsigned long flags
= 0;
468 spin_lock_irqsave(pll
->lock
, flags
);
470 pll_clk_stop_ss(pll
);
472 _clk_pll_disable(hw
);
475 spin_unlock_irqrestore(pll
->lock
, flags
);
478 static int _p_div_to_hw(struct clk_hw
*hw
, u8 p_div
)
480 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
481 const struct pdiv_map
*p_tohw
= pll
->params
->pdiv_tohw
;
484 while (p_tohw
->pdiv
) {
485 if (p_div
<= p_tohw
->pdiv
)
486 return p_tohw
->hw_val
;
494 int tegra_pll_p_div_to_hw(struct tegra_clk_pll
*pll
, u8 p_div
)
496 return _p_div_to_hw(&pll
->hw
, p_div
);
499 static int _hw_to_p_div(struct clk_hw
*hw
, u8 p_div_hw
)
501 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
502 const struct pdiv_map
*p_tohw
= pll
->params
->pdiv_tohw
;
505 while (p_tohw
->pdiv
) {
506 if (p_div_hw
== p_tohw
->hw_val
)
513 return 1 << p_div_hw
;
516 static int _get_table_rate(struct clk_hw
*hw
,
517 struct tegra_clk_pll_freq_table
*cfg
,
518 unsigned long rate
, unsigned long parent_rate
)
520 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
521 struct tegra_clk_pll_freq_table
*sel
;
524 for (sel
= pll
->params
->freq_table
; sel
->input_rate
!= 0; sel
++)
525 if (sel
->input_rate
== parent_rate
&&
526 sel
->output_rate
== rate
)
529 if (sel
->input_rate
== 0)
532 if (pll
->params
->pdiv_tohw
) {
533 p
= _p_div_to_hw(hw
, sel
->p
);
540 cfg
->input_rate
= sel
->input_rate
;
541 cfg
->output_rate
= sel
->output_rate
;
545 cfg
->cpcon
= sel
->cpcon
;
546 cfg
->sdm_data
= sel
->sdm_data
;
551 static int _calc_rate(struct clk_hw
*hw
, struct tegra_clk_pll_freq_table
*cfg
,
552 unsigned long rate
, unsigned long parent_rate
)
554 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
559 switch (parent_rate
) {
562 cfreq
= (rate
<= 1000000 * 1000) ? 1000000 : 2000000;
565 cfreq
= (rate
<= 1000000 * 1000) ? 1000000 : 2600000;
569 cfreq
= (rate
<= 1200000 * 1000) ? 1200000 : 2400000;
574 * PLL_P_OUT1 rate is not listed in PLLA table
576 cfreq
= parent_rate
/ (parent_rate
/ 1000000);
579 pr_err("%s Unexpected reference rate %lu\n",
580 __func__
, parent_rate
);
584 /* Raise VCO to guarantee 0.5% accuracy */
585 for (cfg
->output_rate
= rate
; cfg
->output_rate
< 200 * cfreq
;
586 cfg
->output_rate
<<= 1)
589 cfg
->m
= parent_rate
/ cfreq
;
590 cfg
->n
= cfg
->output_rate
/ cfreq
;
591 cfg
->cpcon
= OUT_OF_TABLE_CPCON
;
593 if (cfg
->m
> divm_max(pll
) || cfg
->n
> divn_max(pll
) ||
594 (1 << p_div
) > divp_max(pll
)
595 || cfg
->output_rate
> pll
->params
->vco_max
) {
599 cfg
->output_rate
>>= p_div
;
601 if (pll
->params
->pdiv_tohw
) {
602 ret
= _p_div_to_hw(hw
, 1 << p_div
);
614 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
615 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
616 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
617 * to indicate that SDM is disabled.
619 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
621 static void clk_pll_set_sdm_data(struct clk_hw
*hw
,
622 struct tegra_clk_pll_freq_table
*cfg
)
624 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
628 if (!pll
->params
->sdm_din_reg
)
632 val
= pll_readl_sdm_din(pll
) & (~sdm_din_mask(pll
));
633 val
|= sdin_data_to_din(cfg
->sdm_data
) & sdm_din_mask(pll
);
634 pll_writel_sdm_din(val
, pll
);
637 val
= pll_readl_sdm_ctrl(pll
);
638 enabled
= (val
& sdm_en_mask(pll
));
640 if (cfg
->sdm_data
== 0 && enabled
)
641 val
&= ~pll
->params
->sdm_ctrl_en_mask
;
643 if (cfg
->sdm_data
!= 0 && !enabled
)
644 val
|= pll
->params
->sdm_ctrl_en_mask
;
646 pll_writel_sdm_ctrl(val
, pll
);
649 static void _update_pll_mnp(struct tegra_clk_pll
*pll
,
650 struct tegra_clk_pll_freq_table
*cfg
)
653 struct tegra_clk_pll_params
*params
= pll
->params
;
654 struct div_nmp
*div_nmp
= params
->div_nmp
;
656 if ((params
->flags
& (TEGRA_PLLM
| TEGRA_PLLMB
)) &&
657 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE
, pll
) &
658 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE
)) {
659 val
= pll_override_readl(params
->pmc_divp_reg
, pll
);
660 val
&= ~(divp_mask(pll
) << div_nmp
->override_divp_shift
);
661 val
|= cfg
->p
<< div_nmp
->override_divp_shift
;
662 pll_override_writel(val
, params
->pmc_divp_reg
, pll
);
664 val
= pll_override_readl(params
->pmc_divnm_reg
, pll
);
665 val
&= ~(divm_mask(pll
) << div_nmp
->override_divm_shift
) |
666 ~(divn_mask(pll
) << div_nmp
->override_divn_shift
);
667 val
|= (cfg
->m
<< div_nmp
->override_divm_shift
) |
668 (cfg
->n
<< div_nmp
->override_divn_shift
);
669 pll_override_writel(val
, params
->pmc_divnm_reg
, pll
);
671 val
= pll_readl_base(pll
);
673 val
&= ~(divm_mask_shifted(pll
) | divn_mask_shifted(pll
) |
674 divp_mask_shifted(pll
));
676 val
|= (cfg
->m
<< divm_shift(pll
)) |
677 (cfg
->n
<< divn_shift(pll
)) |
678 (cfg
->p
<< divp_shift(pll
));
680 pll_writel_base(val
, pll
);
682 clk_pll_set_sdm_data(&pll
->hw
, cfg
);
686 static void _get_pll_mnp(struct tegra_clk_pll
*pll
,
687 struct tegra_clk_pll_freq_table
*cfg
)
690 struct tegra_clk_pll_params
*params
= pll
->params
;
691 struct div_nmp
*div_nmp
= params
->div_nmp
;
693 *cfg
= (struct tegra_clk_pll_freq_table
) { };
695 if ((params
->flags
& (TEGRA_PLLM
| TEGRA_PLLMB
)) &&
696 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE
, pll
) &
697 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE
)) {
698 val
= pll_override_readl(params
->pmc_divp_reg
, pll
);
699 cfg
->p
= (val
>> div_nmp
->override_divp_shift
) & divp_mask(pll
);
701 val
= pll_override_readl(params
->pmc_divnm_reg
, pll
);
702 cfg
->m
= (val
>> div_nmp
->override_divm_shift
) & divm_mask(pll
);
703 cfg
->n
= (val
>> div_nmp
->override_divn_shift
) & divn_mask(pll
);
705 val
= pll_readl_base(pll
);
707 cfg
->m
= (val
>> div_nmp
->divm_shift
) & divm_mask(pll
);
708 cfg
->n
= (val
>> div_nmp
->divn_shift
) & divn_mask(pll
);
709 cfg
->p
= (val
>> div_nmp
->divp_shift
) & divp_mask(pll
);
711 if (pll
->params
->sdm_din_reg
) {
712 if (sdm_en_mask(pll
) & pll_readl_sdm_ctrl(pll
)) {
713 val
= pll_readl_sdm_din(pll
);
714 val
&= sdm_din_mask(pll
);
715 cfg
->sdm_data
= sdin_din_to_data(val
);
721 static void _update_pll_cpcon(struct tegra_clk_pll
*pll
,
722 struct tegra_clk_pll_freq_table
*cfg
,
727 val
= pll_readl_misc(pll
);
729 val
&= ~(PLL_MISC_CPCON_MASK
<< PLL_MISC_CPCON_SHIFT
);
730 val
|= cfg
->cpcon
<< PLL_MISC_CPCON_SHIFT
;
732 if (pll
->params
->flags
& TEGRA_PLL_SET_LFCON
) {
733 val
&= ~(PLL_MISC_LFCON_MASK
<< PLL_MISC_LFCON_SHIFT
);
734 if (cfg
->n
>= PLLDU_LFCON_SET_DIVN
)
735 val
|= 1 << PLL_MISC_LFCON_SHIFT
;
736 } else if (pll
->params
->flags
& TEGRA_PLL_SET_DCCON
) {
737 val
&= ~(1 << PLL_MISC_DCCON_SHIFT
);
738 if (rate
>= (pll
->params
->vco_max
>> 1))
739 val
|= 1 << PLL_MISC_DCCON_SHIFT
;
742 pll_writel_misc(val
, pll
);
745 static int _program_pll(struct clk_hw
*hw
, struct tegra_clk_pll_freq_table
*cfg
,
748 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
749 struct tegra_clk_pll_freq_table old_cfg
;
752 state
= clk_pll_is_enabled(hw
);
754 _get_pll_mnp(pll
, &old_cfg
);
756 if (state
&& pll
->params
->defaults_set
&& pll
->params
->dyn_ramp
&&
757 (cfg
->m
== old_cfg
.m
) && (cfg
->p
== old_cfg
.p
)) {
758 ret
= pll
->params
->dyn_ramp(pll
, cfg
);
764 pll_clk_stop_ss(pll
);
765 _clk_pll_disable(hw
);
768 if (!pll
->params
->defaults_set
&& pll
->params
->set_defaults
)
769 pll
->params
->set_defaults(pll
);
771 _update_pll_mnp(pll
, cfg
);
773 if (pll
->params
->flags
& TEGRA_PLL_HAS_CPCON
)
774 _update_pll_cpcon(pll
, cfg
, rate
);
778 ret
= clk_pll_wait_for_lock(pll
);
779 pll_clk_start_ss(pll
);
785 static int clk_pll_set_rate(struct clk_hw
*hw
, unsigned long rate
,
786 unsigned long parent_rate
)
788 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
789 struct tegra_clk_pll_freq_table cfg
, old_cfg
;
790 unsigned long flags
= 0;
793 if (pll
->params
->flags
& TEGRA_PLL_FIXED
) {
794 if (rate
!= pll
->params
->fixed_rate
) {
795 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
796 __func__
, clk_hw_get_name(hw
),
797 pll
->params
->fixed_rate
, rate
);
803 if (_get_table_rate(hw
, &cfg
, rate
, parent_rate
) &&
804 pll
->params
->calc_rate(hw
, &cfg
, rate
, parent_rate
)) {
805 pr_err("%s: Failed to set %s rate %lu\n", __func__
,
806 clk_hw_get_name(hw
), rate
);
811 spin_lock_irqsave(pll
->lock
, flags
);
813 _get_pll_mnp(pll
, &old_cfg
);
814 if (pll
->params
->flags
& TEGRA_PLL_VCO_OUT
)
817 if (old_cfg
.m
!= cfg
.m
|| old_cfg
.n
!= cfg
.n
|| old_cfg
.p
!= cfg
.p
||
818 old_cfg
.sdm_data
!= cfg
.sdm_data
)
819 ret
= _program_pll(hw
, &cfg
, rate
);
822 spin_unlock_irqrestore(pll
->lock
, flags
);
827 static long clk_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
828 unsigned long *prate
)
830 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
831 struct tegra_clk_pll_freq_table cfg
;
833 if (pll
->params
->flags
& TEGRA_PLL_FIXED
) {
834 /* PLLM/MB are used for memory; we do not change rate */
835 if (pll
->params
->flags
& (TEGRA_PLLM
| TEGRA_PLLMB
))
836 return clk_hw_get_rate(hw
);
837 return pll
->params
->fixed_rate
;
840 if (_get_table_rate(hw
, &cfg
, rate
, *prate
) &&
841 pll
->params
->calc_rate(hw
, &cfg
, rate
, *prate
))
844 return cfg
.output_rate
;
847 static unsigned long clk_pll_recalc_rate(struct clk_hw
*hw
,
848 unsigned long parent_rate
)
850 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
851 struct tegra_clk_pll_freq_table cfg
;
853 u64 rate
= parent_rate
;
856 val
= pll_readl_base(pll
);
858 if ((pll
->params
->flags
& TEGRA_PLL_BYPASS
) && (val
& PLL_BASE_BYPASS
))
861 if ((pll
->params
->flags
& TEGRA_PLL_FIXED
) &&
862 !(pll
->params
->flags
& (TEGRA_PLLM
| TEGRA_PLLMB
)) &&
863 !(val
& PLL_BASE_OVERRIDE
)) {
864 struct tegra_clk_pll_freq_table sel
;
865 if (_get_table_rate(hw
, &sel
, pll
->params
->fixed_rate
,
867 pr_err("Clock %s has unknown fixed frequency\n",
868 clk_hw_get_name(hw
));
871 return pll
->params
->fixed_rate
;
874 _get_pll_mnp(pll
, &cfg
);
876 if (pll
->params
->flags
& TEGRA_PLL_VCO_OUT
) {
879 pdiv
= _hw_to_p_div(hw
, cfg
.p
);
881 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
882 clk_hw_get_name(hw
), cfg
.p
);
887 if (pll
->params
->set_gain
)
888 pll
->params
->set_gain(&cfg
);
898 static int clk_plle_training(struct tegra_clk_pll
*pll
)
901 unsigned long timeout
;
907 * PLLE is already disabled, and setup cleared;
908 * create falling edge on PLLE IDDQ input.
910 val
= readl(pll
->pmc
+ PMC_SATA_PWRGT
);
911 val
|= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE
;
912 writel(val
, pll
->pmc
+ PMC_SATA_PWRGT
);
914 val
= readl(pll
->pmc
+ PMC_SATA_PWRGT
);
915 val
|= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL
;
916 writel(val
, pll
->pmc
+ PMC_SATA_PWRGT
);
918 val
= readl(pll
->pmc
+ PMC_SATA_PWRGT
);
919 val
&= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE
;
920 writel(val
, pll
->pmc
+ PMC_SATA_PWRGT
);
922 val
= pll_readl_misc(pll
);
924 timeout
= jiffies
+ msecs_to_jiffies(100);
926 val
= pll_readl_misc(pll
);
927 if (val
& PLLE_MISC_READY
)
929 if (time_after(jiffies
, timeout
)) {
930 pr_err("%s: timeout waiting for PLLE\n", __func__
);
939 static int clk_plle_enable(struct clk_hw
*hw
)
941 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
942 unsigned long input_rate
= clk_hw_get_rate(clk_hw_get_parent(hw
));
943 struct tegra_clk_pll_freq_table sel
;
947 if (_get_table_rate(hw
, &sel
, pll
->params
->fixed_rate
, input_rate
))
952 val
= pll_readl_misc(pll
);
953 val
&= ~(PLLE_MISC_LOCK_ENABLE
| PLLE_MISC_SETUP_MASK
);
954 pll_writel_misc(val
, pll
);
956 val
= pll_readl_misc(pll
);
957 if (!(val
& PLLE_MISC_READY
)) {
958 err
= clk_plle_training(pll
);
963 if (pll
->params
->flags
& TEGRA_PLLE_CONFIGURE
) {
964 /* configure dividers */
965 val
= pll_readl_base(pll
);
966 val
&= ~(divp_mask_shifted(pll
) | divn_mask_shifted(pll
) |
967 divm_mask_shifted(pll
));
968 val
&= ~(PLLE_BASE_DIVCML_MASK
<< PLLE_BASE_DIVCML_SHIFT
);
969 val
|= sel
.m
<< divm_shift(pll
);
970 val
|= sel
.n
<< divn_shift(pll
);
971 val
|= sel
.p
<< divp_shift(pll
);
972 val
|= sel
.cpcon
<< PLLE_BASE_DIVCML_SHIFT
;
973 pll_writel_base(val
, pll
);
976 val
= pll_readl_misc(pll
);
977 val
|= PLLE_MISC_SETUP_VALUE
;
978 val
|= PLLE_MISC_LOCK_ENABLE
;
979 pll_writel_misc(val
, pll
);
981 val
= readl(pll
->clk_base
+ PLLE_SS_CTRL
);
982 val
&= ~PLLE_SS_COEFFICIENTS_MASK
;
983 val
|= PLLE_SS_DISABLE
;
984 writel(val
, pll
->clk_base
+ PLLE_SS_CTRL
);
986 val
= pll_readl_base(pll
);
987 val
|= (PLL_BASE_BYPASS
| PLL_BASE_ENABLE
);
988 pll_writel_base(val
, pll
);
990 clk_pll_wait_for_lock(pll
);
995 static unsigned long clk_plle_recalc_rate(struct clk_hw
*hw
,
996 unsigned long parent_rate
)
998 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
999 u32 val
= pll_readl_base(pll
);
1000 u32 divn
= 0, divm
= 0, divp
= 0;
1001 u64 rate
= parent_rate
;
1003 divp
= (val
>> pll
->params
->div_nmp
->divp_shift
) & (divp_mask(pll
));
1004 divn
= (val
>> pll
->params
->div_nmp
->divn_shift
) & (divn_mask(pll
));
1005 divm
= (val
>> pll
->params
->div_nmp
->divm_shift
) & (divm_mask(pll
));
1013 const struct clk_ops tegra_clk_pll_ops
= {
1014 .is_enabled
= clk_pll_is_enabled
,
1015 .enable
= clk_pll_enable
,
1016 .disable
= clk_pll_disable
,
1017 .recalc_rate
= clk_pll_recalc_rate
,
1018 .round_rate
= clk_pll_round_rate
,
1019 .set_rate
= clk_pll_set_rate
,
1022 const struct clk_ops tegra_clk_plle_ops
= {
1023 .recalc_rate
= clk_plle_recalc_rate
,
1024 .is_enabled
= clk_pll_is_enabled
,
1025 .disable
= clk_pll_disable
,
1026 .enable
= clk_plle_enable
,
1030 * Structure defining the fields for USB UTMI clocks Parameters.
1032 struct utmi_clk_param
{
1033 /* Oscillator Frequency in Hz */
1035 /* UTMIP PLL Enable Delay Count */
1036 u8 enable_delay_count
;
1037 /* UTMIP PLL Stable count */
1039 /* UTMIP PLL Active delay count */
1040 u8 active_delay_count
;
1041 /* UTMIP PLL Xtal frequency count */
1045 static const struct utmi_clk_param utmi_parameters
[] = {
1047 .osc_frequency
= 13000000, .enable_delay_count
= 0x02,
1048 .stable_count
= 0x33, .active_delay_count
= 0x05,
1049 .xtal_freq_count
= 0x7f
1051 .osc_frequency
= 19200000, .enable_delay_count
= 0x03,
1052 .stable_count
= 0x4b, .active_delay_count
= 0x06,
1053 .xtal_freq_count
= 0xbb
1055 .osc_frequency
= 12000000, .enable_delay_count
= 0x02,
1056 .stable_count
= 0x2f, .active_delay_count
= 0x04,
1057 .xtal_freq_count
= 0x76
1059 .osc_frequency
= 26000000, .enable_delay_count
= 0x04,
1060 .stable_count
= 0x66, .active_delay_count
= 0x09,
1061 .xtal_freq_count
= 0xfe
1063 .osc_frequency
= 16800000, .enable_delay_count
= 0x03,
1064 .stable_count
= 0x41, .active_delay_count
= 0x0a,
1065 .xtal_freq_count
= 0xa4
1067 .osc_frequency
= 38400000, .enable_delay_count
= 0x0,
1068 .stable_count
= 0x0, .active_delay_count
= 0x6,
1069 .xtal_freq_count
= 0x80
1073 static int clk_pllu_enable(struct clk_hw
*hw
)
1075 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1076 struct clk_hw
*pll_ref
= clk_hw_get_parent(hw
);
1077 struct clk_hw
*osc
= clk_hw_get_parent(pll_ref
);
1078 const struct utmi_clk_param
*params
= NULL
;
1079 unsigned long flags
= 0, input_rate
;
1085 pr_err("%s: failed to get OSC clock\n", __func__
);
1089 input_rate
= clk_hw_get_rate(osc
);
1092 spin_lock_irqsave(pll
->lock
, flags
);
1094 _clk_pll_enable(hw
);
1096 ret
= clk_pll_wait_for_lock(pll
);
1100 for (i
= 0; i
< ARRAY_SIZE(utmi_parameters
); i
++) {
1101 if (input_rate
== utmi_parameters
[i
].osc_frequency
) {
1102 params
= &utmi_parameters
[i
];
1108 pr_err("%s: unexpected input rate %lu Hz\n", __func__
,
1114 value
= pll_readl_base(pll
);
1115 value
&= ~PLLU_BASE_OVERRIDE
;
1116 pll_writel_base(value
, pll
);
1118 value
= readl_relaxed(pll
->clk_base
+ UTMIP_PLL_CFG2
);
1119 /* Program UTMIP PLL stable and active counts */
1120 value
&= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1121 value
|= UTMIP_PLL_CFG2_STABLE_COUNT(params
->stable_count
);
1122 value
&= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1123 value
|= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params
->active_delay_count
);
1124 /* Remove power downs from UTMIP PLL control bits */
1125 value
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN
;
1126 value
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN
;
1127 value
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN
;
1128 writel_relaxed(value
, pll
->clk_base
+ UTMIP_PLL_CFG2
);
1130 value
= readl_relaxed(pll
->clk_base
+ UTMIP_PLL_CFG1
);
1131 /* Program UTMIP PLL delay and oscillator frequency counts */
1132 value
&= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1133 value
|= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params
->enable_delay_count
);
1134 value
&= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1135 value
|= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params
->xtal_freq_count
);
1136 /* Remove power downs from UTMIP PLL control bits */
1137 value
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN
;
1138 value
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN
;
1139 value
&= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN
;
1140 writel_relaxed(value
, pll
->clk_base
+ UTMIP_PLL_CFG1
);
1144 spin_unlock_irqrestore(pll
->lock
, flags
);
1149 static const struct clk_ops tegra_clk_pllu_ops
= {
1150 .is_enabled
= clk_pll_is_enabled
,
1151 .enable
= clk_pllu_enable
,
1152 .disable
= clk_pll_disable
,
1153 .recalc_rate
= clk_pll_recalc_rate
,
1156 static int _pll_fixed_mdiv(struct tegra_clk_pll_params
*pll_params
,
1157 unsigned long parent_rate
)
1159 u16 mdiv
= parent_rate
/ pll_params
->cf_min
;
1161 if (pll_params
->flags
& TEGRA_MDIV_NEW
)
1162 return (!pll_params
->mdiv_default
? mdiv
:
1163 min(mdiv
, pll_params
->mdiv_default
));
1165 if (pll_params
->mdiv_default
)
1166 return pll_params
->mdiv_default
;
1168 if (parent_rate
> pll_params
->cf_max
)
1174 static int _calc_dynamic_ramp_rate(struct clk_hw
*hw
,
1175 struct tegra_clk_pll_freq_table
*cfg
,
1176 unsigned long rate
, unsigned long parent_rate
)
1178 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1185 p
= DIV_ROUND_UP(pll
->params
->vco_min
, rate
);
1186 cfg
->m
= _pll_fixed_mdiv(pll
->params
, parent_rate
);
1187 cfg
->output_rate
= rate
* p
;
1188 cfg
->n
= cfg
->output_rate
* cfg
->m
/ parent_rate
;
1189 cfg
->input_rate
= parent_rate
;
1191 p_div
= _p_div_to_hw(hw
, p
);
1197 if (cfg
->n
> divn_max(pll
) || cfg
->output_rate
> pll
->params
->vco_max
)
1203 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1204 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1205 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1206 defined(CONFIG_ARCH_TEGRA_210_SOC)
1208 u16
tegra_pll_get_fixed_mdiv(struct clk_hw
*hw
, unsigned long input_rate
)
1210 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1212 return (u16
)_pll_fixed_mdiv(pll
->params
, input_rate
);
1215 static unsigned long _clip_vco_min(unsigned long vco_min
,
1216 unsigned long parent_rate
)
1218 return DIV_ROUND_UP(vco_min
, parent_rate
) * parent_rate
;
1221 static int _setup_dynamic_ramp(struct tegra_clk_pll_params
*pll_params
,
1222 void __iomem
*clk_base
,
1223 unsigned long parent_rate
)
1228 switch (parent_rate
) {
1244 pr_err("%s: Unexpected reference rate %lu\n",
1245 __func__
, parent_rate
);
1250 val
= step_a
<< pll_params
->stepa_shift
;
1251 val
|= step_b
<< pll_params
->stepb_shift
;
1252 writel_relaxed(val
, clk_base
+ pll_params
->dyn_ramp_reg
);
1257 static int _pll_ramp_calc_pll(struct clk_hw
*hw
,
1258 struct tegra_clk_pll_freq_table
*cfg
,
1259 unsigned long rate
, unsigned long parent_rate
)
1261 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1264 err
= _get_table_rate(hw
, cfg
, rate
, parent_rate
);
1266 err
= _calc_dynamic_ramp_rate(hw
, cfg
, rate
, parent_rate
);
1268 if (cfg
->m
!= _pll_fixed_mdiv(pll
->params
, parent_rate
)) {
1275 if (cfg
->p
> pll
->params
->max_p
)
1282 static int clk_pllxc_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1283 unsigned long parent_rate
)
1285 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1286 struct tegra_clk_pll_freq_table cfg
, old_cfg
;
1287 unsigned long flags
= 0;
1290 ret
= _pll_ramp_calc_pll(hw
, &cfg
, rate
, parent_rate
);
1295 spin_lock_irqsave(pll
->lock
, flags
);
1297 _get_pll_mnp(pll
, &old_cfg
);
1298 if (pll
->params
->flags
& TEGRA_PLL_VCO_OUT
)
1301 if (old_cfg
.m
!= cfg
.m
|| old_cfg
.n
!= cfg
.n
|| old_cfg
.p
!= cfg
.p
)
1302 ret
= _program_pll(hw
, &cfg
, rate
);
1305 spin_unlock_irqrestore(pll
->lock
, flags
);
1310 static long clk_pll_ramp_round_rate(struct clk_hw
*hw
, unsigned long rate
,
1311 unsigned long *prate
)
1313 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1314 struct tegra_clk_pll_freq_table cfg
;
1316 u64 output_rate
= *prate
;
1318 ret
= _pll_ramp_calc_pll(hw
, &cfg
, rate
, *prate
);
1322 p_div
= _hw_to_p_div(hw
, cfg
.p
);
1326 if (pll
->params
->set_gain
)
1327 pll
->params
->set_gain(&cfg
);
1329 output_rate
*= cfg
.n
;
1330 do_div(output_rate
, cfg
.m
* p_div
);
1335 static void _pllcx_strobe(struct tegra_clk_pll
*pll
)
1339 val
= pll_readl_misc(pll
);
1340 val
|= PLLCX_MISC_STROBE
;
1341 pll_writel_misc(val
, pll
);
1344 val
&= ~PLLCX_MISC_STROBE
;
1345 pll_writel_misc(val
, pll
);
1348 static int clk_pllc_enable(struct clk_hw
*hw
)
1350 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1353 unsigned long flags
= 0;
1356 spin_lock_irqsave(pll
->lock
, flags
);
1358 _clk_pll_enable(hw
);
1361 val
= pll_readl_misc(pll
);
1362 val
&= ~PLLCX_MISC_RESET
;
1363 pll_writel_misc(val
, pll
);
1368 ret
= clk_pll_wait_for_lock(pll
);
1371 spin_unlock_irqrestore(pll
->lock
, flags
);
1376 static void _clk_pllc_disable(struct clk_hw
*hw
)
1378 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1381 _clk_pll_disable(hw
);
1383 val
= pll_readl_misc(pll
);
1384 val
|= PLLCX_MISC_RESET
;
1385 pll_writel_misc(val
, pll
);
1389 static void clk_pllc_disable(struct clk_hw
*hw
)
1391 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1392 unsigned long flags
= 0;
1395 spin_lock_irqsave(pll
->lock
, flags
);
1397 _clk_pllc_disable(hw
);
1400 spin_unlock_irqrestore(pll
->lock
, flags
);
1403 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll
*pll
,
1404 unsigned long input_rate
, u32 n
)
1406 u32 val
, n_threshold
;
1408 switch (input_rate
) {
1423 pr_err("%s: Unexpected reference rate %lu\n",
1424 __func__
, input_rate
);
1428 val
= pll_readl_misc(pll
);
1429 val
&= ~(PLLCX_MISC_SDM_DIV_MASK
| PLLCX_MISC_FILT_DIV_MASK
);
1430 val
|= n
<= n_threshold
?
1431 PLLCX_MISC_DIV_LOW_RANGE
: PLLCX_MISC_DIV_HIGH_RANGE
;
1432 pll_writel_misc(val
, pll
);
1437 static int clk_pllc_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1438 unsigned long parent_rate
)
1440 struct tegra_clk_pll_freq_table cfg
, old_cfg
;
1441 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1442 unsigned long flags
= 0;
1446 spin_lock_irqsave(pll
->lock
, flags
);
1448 ret
= _pll_ramp_calc_pll(hw
, &cfg
, rate
, parent_rate
);
1452 _get_pll_mnp(pll
, &old_cfg
);
1454 if (cfg
.m
!= old_cfg
.m
) {
1459 if (old_cfg
.n
== cfg
.n
&& old_cfg
.p
== cfg
.p
)
1462 state
= clk_pll_is_enabled(hw
);
1464 _clk_pllc_disable(hw
);
1466 ret
= _pllcx_update_dynamic_coef(pll
, parent_rate
, cfg
.n
);
1470 _update_pll_mnp(pll
, &cfg
);
1473 ret
= clk_pllc_enable(hw
);
1477 spin_unlock_irqrestore(pll
->lock
, flags
);
1482 static long _pllre_calc_rate(struct tegra_clk_pll
*pll
,
1483 struct tegra_clk_pll_freq_table
*cfg
,
1484 unsigned long rate
, unsigned long parent_rate
)
1487 u64 output_rate
= parent_rate
;
1489 m
= _pll_fixed_mdiv(pll
->params
, parent_rate
);
1490 n
= rate
* m
/ parent_rate
;
1493 do_div(output_rate
, m
);
1503 static int clk_pllre_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1504 unsigned long parent_rate
)
1506 struct tegra_clk_pll_freq_table cfg
, old_cfg
;
1507 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1508 unsigned long flags
= 0;
1512 spin_lock_irqsave(pll
->lock
, flags
);
1514 _pllre_calc_rate(pll
, &cfg
, rate
, parent_rate
);
1515 _get_pll_mnp(pll
, &old_cfg
);
1518 if (cfg
.m
!= old_cfg
.m
|| cfg
.n
!= old_cfg
.n
) {
1519 state
= clk_pll_is_enabled(hw
);
1521 _clk_pll_disable(hw
);
1523 _update_pll_mnp(pll
, &cfg
);
1526 _clk_pll_enable(hw
);
1527 ret
= clk_pll_wait_for_lock(pll
);
1532 spin_unlock_irqrestore(pll
->lock
, flags
);
1537 static unsigned long clk_pllre_recalc_rate(struct clk_hw
*hw
,
1538 unsigned long parent_rate
)
1540 struct tegra_clk_pll_freq_table cfg
;
1541 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1542 u64 rate
= parent_rate
;
1544 _get_pll_mnp(pll
, &cfg
);
1547 do_div(rate
, cfg
.m
);
1552 static long clk_pllre_round_rate(struct clk_hw
*hw
, unsigned long rate
,
1553 unsigned long *prate
)
1555 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1557 return _pllre_calc_rate(pll
, NULL
, rate
, *prate
);
1560 static int clk_plle_tegra114_enable(struct clk_hw
*hw
)
1562 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1563 struct tegra_clk_pll_freq_table sel
;
1566 unsigned long flags
= 0;
1567 unsigned long input_rate
= clk_hw_get_rate(clk_hw_get_parent(hw
));
1569 if (_get_table_rate(hw
, &sel
, pll
->params
->fixed_rate
, input_rate
))
1573 spin_lock_irqsave(pll
->lock
, flags
);
1575 val
= pll_readl_base(pll
);
1576 val
&= ~BIT(29); /* Disable lock override */
1577 pll_writel_base(val
, pll
);
1579 val
= pll_readl(pll
->params
->aux_reg
, pll
);
1580 val
|= PLLE_AUX_ENABLE_SWCTL
;
1581 val
&= ~PLLE_AUX_SEQ_ENABLE
;
1582 pll_writel(val
, pll
->params
->aux_reg
, pll
);
1585 val
= pll_readl_misc(pll
);
1586 val
|= PLLE_MISC_LOCK_ENABLE
;
1587 val
|= PLLE_MISC_IDDQ_SW_CTRL
;
1588 val
&= ~PLLE_MISC_IDDQ_SW_VALUE
;
1589 val
|= PLLE_MISC_PLLE_PTS
;
1590 val
&= ~(PLLE_MISC_VREG_BG_CTRL_MASK
| PLLE_MISC_VREG_CTRL_MASK
);
1591 pll_writel_misc(val
, pll
);
1594 val
= pll_readl(PLLE_SS_CTRL
, pll
);
1595 val
|= PLLE_SS_DISABLE
;
1596 pll_writel(val
, PLLE_SS_CTRL
, pll
);
1598 val
= pll_readl_base(pll
);
1599 val
&= ~(divp_mask_shifted(pll
) | divn_mask_shifted(pll
) |
1600 divm_mask_shifted(pll
));
1601 val
&= ~(PLLE_BASE_DIVCML_MASK
<< PLLE_BASE_DIVCML_SHIFT
);
1602 val
|= sel
.m
<< divm_shift(pll
);
1603 val
|= sel
.n
<< divn_shift(pll
);
1604 val
|= sel
.cpcon
<< PLLE_BASE_DIVCML_SHIFT
;
1605 pll_writel_base(val
, pll
);
1608 _clk_pll_enable(hw
);
1609 ret
= clk_pll_wait_for_lock(pll
);
1614 val
= pll_readl(PLLE_SS_CTRL
, pll
);
1615 val
&= ~(PLLE_SS_CNTL_CENTER
| PLLE_SS_CNTL_INVERT
);
1616 val
&= ~PLLE_SS_COEFFICIENTS_MASK
;
1617 val
|= PLLE_SS_COEFFICIENTS_VAL_TEGRA114
;
1618 pll_writel(val
, PLLE_SS_CTRL
, pll
);
1619 val
&= ~(PLLE_SS_CNTL_SSC_BYP
| PLLE_SS_CNTL_BYPASS_SS
);
1620 pll_writel(val
, PLLE_SS_CTRL
, pll
);
1622 val
&= ~PLLE_SS_CNTL_INTERP_RESET
;
1623 pll_writel(val
, PLLE_SS_CTRL
, pll
);
1626 /* Enable hw control of xusb brick pll */
1627 val
= pll_readl_misc(pll
);
1628 val
&= ~PLLE_MISC_IDDQ_SW_CTRL
;
1629 pll_writel_misc(val
, pll
);
1631 val
= pll_readl(pll
->params
->aux_reg
, pll
);
1632 val
|= (PLLE_AUX_USE_LOCKDET
| PLLE_AUX_SEQ_START_STATE
);
1633 val
&= ~(PLLE_AUX_ENABLE_SWCTL
| PLLE_AUX_SS_SWCTL
);
1634 pll_writel(val
, pll
->params
->aux_reg
, pll
);
1636 val
|= PLLE_AUX_SEQ_ENABLE
;
1637 pll_writel(val
, pll
->params
->aux_reg
, pll
);
1639 val
= pll_readl(XUSBIO_PLL_CFG0
, pll
);
1640 val
|= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET
|
1641 XUSBIO_PLL_CFG0_SEQ_START_STATE
);
1642 val
&= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL
|
1643 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL
);
1644 pll_writel(val
, XUSBIO_PLL_CFG0
, pll
);
1646 val
|= XUSBIO_PLL_CFG0_SEQ_ENABLE
;
1647 pll_writel(val
, XUSBIO_PLL_CFG0
, pll
);
1649 /* Enable hw control of SATA pll */
1650 val
= pll_readl(SATA_PLL_CFG0
, pll
);
1651 val
&= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL
;
1652 val
|= SATA_PLL_CFG0_PADPLL_USE_LOCKDET
;
1653 val
|= SATA_PLL_CFG0_SEQ_START_STATE
;
1654 pll_writel(val
, SATA_PLL_CFG0
, pll
);
1658 val
= pll_readl(SATA_PLL_CFG0
, pll
);
1659 val
|= SATA_PLL_CFG0_SEQ_ENABLE
;
1660 pll_writel(val
, SATA_PLL_CFG0
, pll
);
1664 spin_unlock_irqrestore(pll
->lock
, flags
);
1669 static void clk_plle_tegra114_disable(struct clk_hw
*hw
)
1671 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1672 unsigned long flags
= 0;
1676 spin_lock_irqsave(pll
->lock
, flags
);
1678 _clk_pll_disable(hw
);
1680 val
= pll_readl_misc(pll
);
1681 val
|= PLLE_MISC_IDDQ_SW_CTRL
| PLLE_MISC_IDDQ_SW_VALUE
;
1682 pll_writel_misc(val
, pll
);
1686 spin_unlock_irqrestore(pll
->lock
, flags
);
1689 static int clk_pllu_tegra114_enable(struct clk_hw
*hw
)
1691 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
1692 const struct utmi_clk_param
*params
= NULL
;
1693 struct clk
*osc
= __clk_lookup("osc");
1694 unsigned long flags
= 0, input_rate
;
1700 pr_err("%s: failed to get OSC clock\n", __func__
);
1704 input_rate
= clk_hw_get_rate(__clk_get_hw(osc
));
1707 spin_lock_irqsave(pll
->lock
, flags
);
1709 _clk_pll_enable(hw
);
1711 ret
= clk_pll_wait_for_lock(pll
);
1715 for (i
= 0; i
< ARRAY_SIZE(utmi_parameters
); i
++) {
1716 if (input_rate
== utmi_parameters
[i
].osc_frequency
) {
1717 params
= &utmi_parameters
[i
];
1723 pr_err("%s: unexpected input rate %lu Hz\n", __func__
,
1729 value
= pll_readl_base(pll
);
1730 value
&= ~PLLU_BASE_OVERRIDE
;
1731 pll_writel_base(value
, pll
);
1733 value
= readl_relaxed(pll
->clk_base
+ UTMIP_PLL_CFG2
);
1734 /* Program UTMIP PLL stable and active counts */
1735 value
&= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1736 value
|= UTMIP_PLL_CFG2_STABLE_COUNT(params
->stable_count
);
1737 value
&= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1738 value
|= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params
->active_delay_count
);
1739 /* Remove power downs from UTMIP PLL control bits */
1740 value
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN
;
1741 value
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN
;
1742 value
&= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN
;
1743 writel_relaxed(value
, pll
->clk_base
+ UTMIP_PLL_CFG2
);
1745 value
= readl_relaxed(pll
->clk_base
+ UTMIP_PLL_CFG1
);
1746 /* Program UTMIP PLL delay and oscillator frequency counts */
1747 value
&= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1748 value
|= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params
->enable_delay_count
);
1749 value
&= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1750 value
|= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params
->xtal_freq_count
);
1751 /* Remove power downs from UTMIP PLL control bits */
1752 value
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN
;
1753 value
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN
;
1754 value
&= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP
;
1755 value
&= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN
;
1756 writel_relaxed(value
, pll
->clk_base
+ UTMIP_PLL_CFG1
);
1758 /* Setup HW control of UTMIPLL */
1759 value
= readl_relaxed(pll
->clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
1760 value
|= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET
;
1761 value
&= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL
;
1762 value
|= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE
;
1763 writel_relaxed(value
, pll
->clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
1765 value
= readl_relaxed(pll
->clk_base
+ UTMIP_PLL_CFG1
);
1766 value
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP
;
1767 value
&= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN
;
1768 writel_relaxed(value
, pll
->clk_base
+ UTMIP_PLL_CFG1
);
1773 * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1776 value
= readl_relaxed(pll
->clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
1777 value
|= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL
;
1778 value
&= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE
;
1779 writel_relaxed(value
, pll
->clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
1783 /* Enable HW control of UTMIPLL */
1784 value
= readl_relaxed(pll
->clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
1785 value
|= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE
;
1786 writel_relaxed(value
, pll
->clk_base
+ UTMIPLL_HW_PWRDN_CFG0
);
1790 spin_unlock_irqrestore(pll
->lock
, flags
);
1796 static struct tegra_clk_pll
*_tegra_init_pll(void __iomem
*clk_base
,
1797 void __iomem
*pmc
, struct tegra_clk_pll_params
*pll_params
,
1800 struct tegra_clk_pll
*pll
;
1802 pll
= kzalloc(sizeof(*pll
), GFP_KERNEL
);
1804 return ERR_PTR(-ENOMEM
);
1806 pll
->clk_base
= clk_base
;
1809 pll
->params
= pll_params
;
1812 if (!pll_params
->div_nmp
)
1813 pll_params
->div_nmp
= &default_nmp
;
1818 static struct clk
*_tegra_clk_register_pll(struct tegra_clk_pll
*pll
,
1819 const char *name
, const char *parent_name
, unsigned long flags
,
1820 const struct clk_ops
*ops
)
1822 struct clk_init_data init
;
1827 init
.parent_names
= (parent_name
? &parent_name
: NULL
);
1828 init
.num_parents
= (parent_name
? 1 : 0);
1830 /* Default to _calc_rate if unspecified */
1831 if (!pll
->params
->calc_rate
) {
1832 if (pll
->params
->flags
& TEGRA_PLLM
)
1833 pll
->params
->calc_rate
= _calc_dynamic_ramp_rate
;
1835 pll
->params
->calc_rate
= _calc_rate
;
1838 if (pll
->params
->set_defaults
)
1839 pll
->params
->set_defaults(pll
);
1841 /* Data in .init is copied by clk_register(), so stack variable OK */
1842 pll
->hw
.init
= &init
;
1844 return clk_register(NULL
, &pll
->hw
);
1847 struct clk
*tegra_clk_register_pll(const char *name
, const char *parent_name
,
1848 void __iomem
*clk_base
, void __iomem
*pmc
,
1849 unsigned long flags
, struct tegra_clk_pll_params
*pll_params
,
1852 struct tegra_clk_pll
*pll
;
1855 pll_params
->flags
|= TEGRA_PLL_BYPASS
;
1857 pll
= _tegra_init_pll(clk_base
, pmc
, pll_params
, lock
);
1859 return ERR_CAST(pll
);
1861 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
1862 &tegra_clk_pll_ops
);
1869 static struct div_nmp pll_e_nmp
= {
1870 .divn_shift
= PLLE_BASE_DIVN_SHIFT
,
1871 .divn_width
= PLLE_BASE_DIVN_WIDTH
,
1872 .divm_shift
= PLLE_BASE_DIVM_SHIFT
,
1873 .divm_width
= PLLE_BASE_DIVM_WIDTH
,
1874 .divp_shift
= PLLE_BASE_DIVP_SHIFT
,
1875 .divp_width
= PLLE_BASE_DIVP_WIDTH
,
1878 struct clk
*tegra_clk_register_plle(const char *name
, const char *parent_name
,
1879 void __iomem
*clk_base
, void __iomem
*pmc
,
1880 unsigned long flags
, struct tegra_clk_pll_params
*pll_params
,
1883 struct tegra_clk_pll
*pll
;
1886 pll_params
->flags
|= TEGRA_PLL_BYPASS
;
1888 if (!pll_params
->div_nmp
)
1889 pll_params
->div_nmp
= &pll_e_nmp
;
1891 pll
= _tegra_init_pll(clk_base
, pmc
, pll_params
, lock
);
1893 return ERR_CAST(pll
);
1895 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
1896 &tegra_clk_plle_ops
);
1903 struct clk
*tegra_clk_register_pllu(const char *name
, const char *parent_name
,
1904 void __iomem
*clk_base
, unsigned long flags
,
1905 struct tegra_clk_pll_params
*pll_params
, spinlock_t
*lock
)
1907 struct tegra_clk_pll
*pll
;
1910 pll_params
->flags
|= TEGRA_PLLU
;
1912 pll
= _tegra_init_pll(clk_base
, NULL
, pll_params
, lock
);
1914 return ERR_CAST(pll
);
1916 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
1917 &tegra_clk_pllu_ops
);
1924 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1925 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1926 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1927 defined(CONFIG_ARCH_TEGRA_210_SOC)
1928 static const struct clk_ops tegra_clk_pllxc_ops
= {
1929 .is_enabled
= clk_pll_is_enabled
,
1930 .enable
= clk_pll_enable
,
1931 .disable
= clk_pll_disable
,
1932 .recalc_rate
= clk_pll_recalc_rate
,
1933 .round_rate
= clk_pll_ramp_round_rate
,
1934 .set_rate
= clk_pllxc_set_rate
,
1937 static const struct clk_ops tegra_clk_pllc_ops
= {
1938 .is_enabled
= clk_pll_is_enabled
,
1939 .enable
= clk_pllc_enable
,
1940 .disable
= clk_pllc_disable
,
1941 .recalc_rate
= clk_pll_recalc_rate
,
1942 .round_rate
= clk_pll_ramp_round_rate
,
1943 .set_rate
= clk_pllc_set_rate
,
1946 static const struct clk_ops tegra_clk_pllre_ops
= {
1947 .is_enabled
= clk_pll_is_enabled
,
1948 .enable
= clk_pll_enable
,
1949 .disable
= clk_pll_disable
,
1950 .recalc_rate
= clk_pllre_recalc_rate
,
1951 .round_rate
= clk_pllre_round_rate
,
1952 .set_rate
= clk_pllre_set_rate
,
1955 static const struct clk_ops tegra_clk_plle_tegra114_ops
= {
1956 .is_enabled
= clk_pll_is_enabled
,
1957 .enable
= clk_plle_tegra114_enable
,
1958 .disable
= clk_plle_tegra114_disable
,
1959 .recalc_rate
= clk_pll_recalc_rate
,
1962 static const struct clk_ops tegra_clk_pllu_tegra114_ops
= {
1963 .is_enabled
= clk_pll_is_enabled
,
1964 .enable
= clk_pllu_tegra114_enable
,
1965 .disable
= clk_pll_disable
,
1966 .recalc_rate
= clk_pll_recalc_rate
,
1969 struct clk
*tegra_clk_register_pllxc(const char *name
, const char *parent_name
,
1970 void __iomem
*clk_base
, void __iomem
*pmc
,
1971 unsigned long flags
,
1972 struct tegra_clk_pll_params
*pll_params
,
1975 struct tegra_clk_pll
*pll
;
1976 struct clk
*clk
, *parent
;
1977 unsigned long parent_rate
;
1980 parent
= __clk_lookup(parent_name
);
1982 WARN(1, "parent clk %s of %s must be registered first\n",
1984 return ERR_PTR(-EINVAL
);
1987 if (!pll_params
->pdiv_tohw
)
1988 return ERR_PTR(-EINVAL
);
1990 parent_rate
= clk_get_rate(parent
);
1992 pll_params
->vco_min
= _clip_vco_min(pll_params
->vco_min
, parent_rate
);
1994 if (pll_params
->adjust_vco
)
1995 pll_params
->vco_min
= pll_params
->adjust_vco(pll_params
,
1999 * If the pll has a set_defaults callback, it will take care of
2000 * configuring dynamic ramping and setting IDDQ in that path.
2002 if (!pll_params
->set_defaults
) {
2005 err
= _setup_dynamic_ramp(pll_params
, clk_base
, parent_rate
);
2007 return ERR_PTR(err
);
2009 val
= readl_relaxed(clk_base
+ pll_params
->base_reg
);
2010 val_iddq
= readl_relaxed(clk_base
+ pll_params
->iddq_reg
);
2012 if (val
& PLL_BASE_ENABLE
)
2013 WARN_ON(val_iddq
& BIT(pll_params
->iddq_bit_idx
));
2015 val_iddq
|= BIT(pll_params
->iddq_bit_idx
);
2016 writel_relaxed(val_iddq
,
2017 clk_base
+ pll_params
->iddq_reg
);
2021 pll
= _tegra_init_pll(clk_base
, pmc
, pll_params
, lock
);
2023 return ERR_CAST(pll
);
2025 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2026 &tegra_clk_pllxc_ops
);
2033 struct clk
*tegra_clk_register_pllre(const char *name
, const char *parent_name
,
2034 void __iomem
*clk_base
, void __iomem
*pmc
,
2035 unsigned long flags
,
2036 struct tegra_clk_pll_params
*pll_params
,
2037 spinlock_t
*lock
, unsigned long parent_rate
)
2040 struct tegra_clk_pll
*pll
;
2043 pll_params
->vco_min
= _clip_vco_min(pll_params
->vco_min
, parent_rate
);
2045 if (pll_params
->adjust_vco
)
2046 pll_params
->vco_min
= pll_params
->adjust_vco(pll_params
,
2049 pll
= _tegra_init_pll(clk_base
, pmc
, pll_params
, lock
);
2051 return ERR_CAST(pll
);
2053 /* program minimum rate by default */
2055 val
= pll_readl_base(pll
);
2056 if (val
& PLL_BASE_ENABLE
)
2057 WARN_ON(readl_relaxed(clk_base
+ pll_params
->iddq_reg
) &
2058 BIT(pll_params
->iddq_bit_idx
));
2062 m
= _pll_fixed_mdiv(pll_params
, parent_rate
);
2063 val
= m
<< divm_shift(pll
);
2064 val
|= (pll_params
->vco_min
/ parent_rate
) << divn_shift(pll
);
2065 pll_writel_base(val
, pll
);
2068 /* disable lock override */
2070 val
= pll_readl_misc(pll
);
2072 pll_writel_misc(val
, pll
);
2074 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2075 &tegra_clk_pllre_ops
);
2082 struct clk
*tegra_clk_register_pllm(const char *name
, const char *parent_name
,
2083 void __iomem
*clk_base
, void __iomem
*pmc
,
2084 unsigned long flags
,
2085 struct tegra_clk_pll_params
*pll_params
,
2088 struct tegra_clk_pll
*pll
;
2089 struct clk
*clk
, *parent
;
2090 unsigned long parent_rate
;
2092 if (!pll_params
->pdiv_tohw
)
2093 return ERR_PTR(-EINVAL
);
2095 parent
= __clk_lookup(parent_name
);
2097 WARN(1, "parent clk %s of %s must be registered first\n",
2099 return ERR_PTR(-EINVAL
);
2102 parent_rate
= clk_get_rate(parent
);
2104 pll_params
->vco_min
= _clip_vco_min(pll_params
->vco_min
, parent_rate
);
2106 if (pll_params
->adjust_vco
)
2107 pll_params
->vco_min
= pll_params
->adjust_vco(pll_params
,
2110 pll_params
->flags
|= TEGRA_PLL_BYPASS
;
2111 pll_params
->flags
|= TEGRA_PLLM
;
2112 pll
= _tegra_init_pll(clk_base
, pmc
, pll_params
, lock
);
2114 return ERR_CAST(pll
);
2116 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2117 &tegra_clk_pll_ops
);
2124 struct clk
*tegra_clk_register_pllc(const char *name
, const char *parent_name
,
2125 void __iomem
*clk_base
, void __iomem
*pmc
,
2126 unsigned long flags
,
2127 struct tegra_clk_pll_params
*pll_params
,
2130 struct clk
*parent
, *clk
;
2131 const struct pdiv_map
*p_tohw
= pll_params
->pdiv_tohw
;
2132 struct tegra_clk_pll
*pll
;
2133 struct tegra_clk_pll_freq_table cfg
;
2134 unsigned long parent_rate
;
2137 return ERR_PTR(-EINVAL
);
2139 parent
= __clk_lookup(parent_name
);
2141 WARN(1, "parent clk %s of %s must be registered first\n",
2143 return ERR_PTR(-EINVAL
);
2146 parent_rate
= clk_get_rate(parent
);
2148 pll_params
->vco_min
= _clip_vco_min(pll_params
->vco_min
, parent_rate
);
2150 pll_params
->flags
|= TEGRA_PLL_BYPASS
;
2151 pll
= _tegra_init_pll(clk_base
, pmc
, pll_params
, lock
);
2153 return ERR_CAST(pll
);
2156 * Most of PLLC register fields are shadowed, and can not be read
2157 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2158 * Initialize PLL to default state: disabled, reset; shadow registers
2159 * loaded with default parameters; dividers are preset for half of
2160 * minimum VCO rate (the latter assured that shadowed divider settings
2161 * are within supported range).
2164 cfg
.m
= _pll_fixed_mdiv(pll_params
, parent_rate
);
2165 cfg
.n
= cfg
.m
* pll_params
->vco_min
/ parent_rate
;
2167 while (p_tohw
->pdiv
) {
2168 if (p_tohw
->pdiv
== 2) {
2169 cfg
.p
= p_tohw
->hw_val
;
2175 if (!p_tohw
->pdiv
) {
2177 return ERR_PTR(-EINVAL
);
2180 pll_writel_base(0, pll
);
2181 _update_pll_mnp(pll
, &cfg
);
2183 pll_writel_misc(PLLCX_MISC_DEFAULT
, pll
);
2184 pll_writel(PLLCX_MISC1_DEFAULT
, pll_params
->ext_misc_reg
[0], pll
);
2185 pll_writel(PLLCX_MISC2_DEFAULT
, pll_params
->ext_misc_reg
[1], pll
);
2186 pll_writel(PLLCX_MISC3_DEFAULT
, pll_params
->ext_misc_reg
[2], pll
);
2188 _pllcx_update_dynamic_coef(pll
, parent_rate
, cfg
.n
);
2190 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2191 &tegra_clk_pllc_ops
);
2198 struct clk
*tegra_clk_register_plle_tegra114(const char *name
,
2199 const char *parent_name
,
2200 void __iomem
*clk_base
, unsigned long flags
,
2201 struct tegra_clk_pll_params
*pll_params
,
2204 struct tegra_clk_pll
*pll
;
2208 pll
= _tegra_init_pll(clk_base
, NULL
, pll_params
, lock
);
2210 return ERR_CAST(pll
);
2212 /* ensure parent is set to pll_re_vco */
2214 val
= pll_readl_base(pll
);
2215 val_aux
= pll_readl(pll_params
->aux_reg
, pll
);
2217 if (val
& PLL_BASE_ENABLE
) {
2218 if ((val_aux
& PLLE_AUX_PLLRE_SEL
) ||
2219 (val_aux
& PLLE_AUX_PLLP_SEL
))
2220 WARN(1, "pll_e enabled with unsupported parent %s\n",
2221 (val_aux
& PLLE_AUX_PLLP_SEL
) ? "pllp_out0" :
2224 val_aux
&= ~(PLLE_AUX_PLLRE_SEL
| PLLE_AUX_PLLP_SEL
);
2225 pll_writel(val_aux
, pll_params
->aux_reg
, pll
);
2228 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2229 &tegra_clk_plle_tegra114_ops
);
2237 tegra_clk_register_pllu_tegra114(const char *name
, const char *parent_name
,
2238 void __iomem
*clk_base
, unsigned long flags
,
2239 struct tegra_clk_pll_params
*pll_params
,
2242 struct tegra_clk_pll
*pll
;
2245 pll_params
->flags
|= TEGRA_PLLU
;
2247 pll
= _tegra_init_pll(clk_base
, NULL
, pll_params
, lock
);
2249 return ERR_CAST(pll
);
2251 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2252 &tegra_clk_pllu_tegra114_ops
);
2260 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
2261 static const struct clk_ops tegra_clk_pllss_ops
= {
2262 .is_enabled
= clk_pll_is_enabled
,
2263 .enable
= clk_pll_enable
,
2264 .disable
= clk_pll_disable
,
2265 .recalc_rate
= clk_pll_recalc_rate
,
2266 .round_rate
= clk_pll_ramp_round_rate
,
2267 .set_rate
= clk_pllxc_set_rate
,
2270 struct clk
*tegra_clk_register_pllss(const char *name
, const char *parent_name
,
2271 void __iomem
*clk_base
, unsigned long flags
,
2272 struct tegra_clk_pll_params
*pll_params
,
2275 struct tegra_clk_pll
*pll
;
2276 struct clk
*clk
, *parent
;
2277 struct tegra_clk_pll_freq_table cfg
;
2278 unsigned long parent_rate
;
2282 if (!pll_params
->div_nmp
)
2283 return ERR_PTR(-EINVAL
);
2285 parent
= __clk_lookup(parent_name
);
2287 WARN(1, "parent clk %s of %s must be registered first\n",
2289 return ERR_PTR(-EINVAL
);
2292 pll
= _tegra_init_pll(clk_base
, NULL
, pll_params
, lock
);
2294 return ERR_CAST(pll
);
2296 val
= pll_readl_base(pll
);
2297 val
&= ~PLLSS_REF_SRC_SEL_MASK
;
2298 pll_writel_base(val
, pll
);
2300 parent_rate
= clk_get_rate(parent
);
2302 pll_params
->vco_min
= _clip_vco_min(pll_params
->vco_min
, parent_rate
);
2304 /* initialize PLL to minimum rate */
2306 cfg
.m
= _pll_fixed_mdiv(pll_params
, parent_rate
);
2307 cfg
.n
= cfg
.m
* pll_params
->vco_min
/ parent_rate
;
2309 for (i
= 0; pll_params
->pdiv_tohw
[i
].pdiv
; i
++)
2313 return ERR_PTR(-EINVAL
);
2316 cfg
.p
= pll_params
->pdiv_tohw
[i
-1].hw_val
;
2318 _update_pll_mnp(pll
, &cfg
);
2320 pll_writel_misc(PLLSS_MISC_DEFAULT
, pll
);
2321 pll_writel(PLLSS_CFG_DEFAULT
, pll_params
->ext_misc_reg
[0], pll
);
2322 pll_writel(PLLSS_CTRL1_DEFAULT
, pll_params
->ext_misc_reg
[1], pll
);
2323 pll_writel(PLLSS_CTRL1_DEFAULT
, pll_params
->ext_misc_reg
[2], pll
);
2325 val
= pll_readl_base(pll
);
2326 val_iddq
= readl_relaxed(clk_base
+ pll_params
->iddq_reg
);
2327 if (val
& PLL_BASE_ENABLE
) {
2328 if (val_iddq
& BIT(pll_params
->iddq_bit_idx
)) {
2329 WARN(1, "%s is on but IDDQ set\n", name
);
2331 return ERR_PTR(-EINVAL
);
2334 val_iddq
|= BIT(pll_params
->iddq_bit_idx
);
2335 writel_relaxed(val_iddq
, clk_base
+ pll_params
->iddq_reg
);
2338 val
&= ~PLLSS_LOCK_OVERRIDE
;
2339 pll_writel_base(val
, pll
);
2341 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2342 &tegra_clk_pllss_ops
);
2351 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2352 struct clk
*tegra_clk_register_pllre_tegra210(const char *name
,
2353 const char *parent_name
, void __iomem
*clk_base
,
2354 void __iomem
*pmc
, unsigned long flags
,
2355 struct tegra_clk_pll_params
*pll_params
,
2356 spinlock_t
*lock
, unsigned long parent_rate
)
2358 struct tegra_clk_pll
*pll
;
2361 pll_params
->vco_min
= _clip_vco_min(pll_params
->vco_min
, parent_rate
);
2363 if (pll_params
->adjust_vco
)
2364 pll_params
->vco_min
= pll_params
->adjust_vco(pll_params
,
2367 pll
= _tegra_init_pll(clk_base
, pmc
, pll_params
, lock
);
2369 return ERR_CAST(pll
);
2371 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2372 &tegra_clk_pll_ops
);
2379 static int clk_plle_tegra210_enable(struct clk_hw
*hw
)
2381 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
2382 struct tegra_clk_pll_freq_table sel
;
2385 unsigned long flags
= 0;
2386 unsigned long input_rate
= clk_hw_get_rate(clk_hw_get_parent(hw
));
2388 if (_get_table_rate(hw
, &sel
, pll
->params
->fixed_rate
, input_rate
))
2392 spin_lock_irqsave(pll
->lock
, flags
);
2394 val
= pll_readl(pll
->params
->aux_reg
, pll
);
2395 if (val
& PLLE_AUX_SEQ_ENABLE
)
2398 val
= pll_readl_base(pll
);
2399 val
&= ~BIT(30); /* Disable lock override */
2400 pll_writel_base(val
, pll
);
2402 val
= pll_readl_misc(pll
);
2403 val
|= PLLE_MISC_LOCK_ENABLE
;
2404 val
|= PLLE_MISC_IDDQ_SW_CTRL
;
2405 val
&= ~PLLE_MISC_IDDQ_SW_VALUE
;
2406 val
|= PLLE_MISC_PLLE_PTS
;
2407 val
&= ~(PLLE_MISC_VREG_BG_CTRL_MASK
| PLLE_MISC_VREG_CTRL_MASK
);
2408 pll_writel_misc(val
, pll
);
2411 val
= pll_readl(PLLE_SS_CTRL
, pll
);
2412 val
|= PLLE_SS_DISABLE
;
2413 pll_writel(val
, PLLE_SS_CTRL
, pll
);
2415 val
= pll_readl_base(pll
);
2416 val
&= ~(divp_mask_shifted(pll
) | divn_mask_shifted(pll
) |
2417 divm_mask_shifted(pll
));
2418 val
&= ~(PLLE_BASE_DIVCML_MASK
<< PLLE_BASE_DIVCML_SHIFT
);
2419 val
|= sel
.m
<< divm_shift(pll
);
2420 val
|= sel
.n
<< divn_shift(pll
);
2421 val
|= sel
.cpcon
<< PLLE_BASE_DIVCML_SHIFT
;
2422 pll_writel_base(val
, pll
);
2425 val
= pll_readl_base(pll
);
2426 val
|= PLLE_BASE_ENABLE
;
2427 pll_writel_base(val
, pll
);
2429 ret
= clk_pll_wait_for_lock(pll
);
2434 val
= pll_readl(PLLE_SS_CTRL
, pll
);
2435 val
&= ~(PLLE_SS_CNTL_CENTER
| PLLE_SS_CNTL_INVERT
);
2436 val
&= ~PLLE_SS_COEFFICIENTS_MASK
;
2437 val
|= PLLE_SS_COEFFICIENTS_VAL_TEGRA210
;
2438 pll_writel(val
, PLLE_SS_CTRL
, pll
);
2439 val
&= ~(PLLE_SS_CNTL_SSC_BYP
| PLLE_SS_CNTL_BYPASS_SS
);
2440 pll_writel(val
, PLLE_SS_CTRL
, pll
);
2442 val
&= ~PLLE_SS_CNTL_INTERP_RESET
;
2443 pll_writel(val
, PLLE_SS_CTRL
, pll
);
2446 val
= pll_readl_misc(pll
);
2447 val
&= ~PLLE_MISC_IDDQ_SW_CTRL
;
2448 pll_writel_misc(val
, pll
);
2450 val
= pll_readl(pll
->params
->aux_reg
, pll
);
2451 val
|= (PLLE_AUX_USE_LOCKDET
| PLLE_AUX_SS_SEQ_INCLUDE
);
2452 val
&= ~(PLLE_AUX_ENABLE_SWCTL
| PLLE_AUX_SS_SWCTL
);
2453 pll_writel(val
, pll
->params
->aux_reg
, pll
);
2455 val
|= PLLE_AUX_SEQ_ENABLE
;
2456 pll_writel(val
, pll
->params
->aux_reg
, pll
);
2460 spin_unlock_irqrestore(pll
->lock
, flags
);
2465 static void clk_plle_tegra210_disable(struct clk_hw
*hw
)
2467 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
2468 unsigned long flags
= 0;
2472 spin_lock_irqsave(pll
->lock
, flags
);
2474 /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2475 val
= pll_readl(pll
->params
->aux_reg
, pll
);
2476 if (val
& PLLE_AUX_SEQ_ENABLE
)
2479 val
= pll_readl_base(pll
);
2480 val
&= ~PLLE_BASE_ENABLE
;
2481 pll_writel_base(val
, pll
);
2483 val
= pll_readl(pll
->params
->aux_reg
, pll
);
2484 val
|= PLLE_AUX_ENABLE_SWCTL
| PLLE_AUX_SS_SWCTL
;
2485 pll_writel(val
, pll
->params
->aux_reg
, pll
);
2487 val
= pll_readl_misc(pll
);
2488 val
|= PLLE_MISC_IDDQ_SW_CTRL
| PLLE_MISC_IDDQ_SW_VALUE
;
2489 pll_writel_misc(val
, pll
);
2494 spin_unlock_irqrestore(pll
->lock
, flags
);
2497 static int clk_plle_tegra210_is_enabled(struct clk_hw
*hw
)
2499 struct tegra_clk_pll
*pll
= to_clk_pll(hw
);
2502 val
= pll_readl_base(pll
);
2504 return val
& PLLE_BASE_ENABLE
? 1 : 0;
2507 static const struct clk_ops tegra_clk_plle_tegra210_ops
= {
2508 .is_enabled
= clk_plle_tegra210_is_enabled
,
2509 .enable
= clk_plle_tegra210_enable
,
2510 .disable
= clk_plle_tegra210_disable
,
2511 .recalc_rate
= clk_pll_recalc_rate
,
2514 struct clk
*tegra_clk_register_plle_tegra210(const char *name
,
2515 const char *parent_name
,
2516 void __iomem
*clk_base
, unsigned long flags
,
2517 struct tegra_clk_pll_params
*pll_params
,
2520 struct tegra_clk_pll
*pll
;
2524 pll
= _tegra_init_pll(clk_base
, NULL
, pll_params
, lock
);
2526 return ERR_CAST(pll
);
2528 /* ensure parent is set to pll_re_vco */
2530 val
= pll_readl_base(pll
);
2531 val_aux
= pll_readl(pll_params
->aux_reg
, pll
);
2533 if (val
& PLLE_BASE_ENABLE
) {
2534 if ((val_aux
& PLLE_AUX_PLLRE_SEL
) ||
2535 (val_aux
& PLLE_AUX_PLLP_SEL
))
2536 WARN(1, "pll_e enabled with unsupported parent %s\n",
2537 (val_aux
& PLLE_AUX_PLLP_SEL
) ? "pllp_out0" :
2540 val_aux
&= ~(PLLE_AUX_PLLRE_SEL
| PLLE_AUX_PLLP_SEL
);
2541 pll_writel(val_aux
, pll_params
->aux_reg
, pll
);
2544 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2545 &tegra_clk_plle_tegra210_ops
);
2552 struct clk
*tegra_clk_register_pllc_tegra210(const char *name
,
2553 const char *parent_name
, void __iomem
*clk_base
,
2554 void __iomem
*pmc
, unsigned long flags
,
2555 struct tegra_clk_pll_params
*pll_params
,
2558 struct clk
*parent
, *clk
;
2559 const struct pdiv_map
*p_tohw
= pll_params
->pdiv_tohw
;
2560 struct tegra_clk_pll
*pll
;
2561 unsigned long parent_rate
;
2564 return ERR_PTR(-EINVAL
);
2566 parent
= __clk_lookup(parent_name
);
2568 WARN(1, "parent clk %s of %s must be registered first\n",
2570 return ERR_PTR(-EINVAL
);
2573 parent_rate
= clk_get_rate(parent
);
2575 pll_params
->vco_min
= _clip_vco_min(pll_params
->vco_min
, parent_rate
);
2577 if (pll_params
->adjust_vco
)
2578 pll_params
->vco_min
= pll_params
->adjust_vco(pll_params
,
2581 pll_params
->flags
|= TEGRA_PLL_BYPASS
;
2582 pll
= _tegra_init_pll(clk_base
, pmc
, pll_params
, lock
);
2584 return ERR_CAST(pll
);
2586 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2587 &tegra_clk_pll_ops
);
2594 struct clk
*tegra_clk_register_pllss_tegra210(const char *name
,
2595 const char *parent_name
, void __iomem
*clk_base
,
2596 unsigned long flags
,
2597 struct tegra_clk_pll_params
*pll_params
,
2600 struct tegra_clk_pll
*pll
;
2601 struct clk
*clk
, *parent
;
2602 unsigned long parent_rate
;
2605 if (!pll_params
->div_nmp
)
2606 return ERR_PTR(-EINVAL
);
2608 parent
= __clk_lookup(parent_name
);
2610 WARN(1, "parent clk %s of %s must be registered first\n",
2612 return ERR_PTR(-EINVAL
);
2615 val
= readl_relaxed(clk_base
+ pll_params
->base_reg
);
2616 if (val
& PLLSS_REF_SRC_SEL_MASK
) {
2617 WARN(1, "not supported reference clock for %s\n", name
);
2618 return ERR_PTR(-EINVAL
);
2621 parent_rate
= clk_get_rate(parent
);
2623 pll_params
->vco_min
= _clip_vco_min(pll_params
->vco_min
, parent_rate
);
2625 if (pll_params
->adjust_vco
)
2626 pll_params
->vco_min
= pll_params
->adjust_vco(pll_params
,
2629 pll_params
->flags
|= TEGRA_PLL_BYPASS
;
2630 pll
= _tegra_init_pll(clk_base
, NULL
, pll_params
, lock
);
2632 return ERR_CAST(pll
);
2634 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2635 &tegra_clk_pll_ops
);
2643 struct clk
*tegra_clk_register_pllmb(const char *name
, const char *parent_name
,
2644 void __iomem
*clk_base
, void __iomem
*pmc
,
2645 unsigned long flags
,
2646 struct tegra_clk_pll_params
*pll_params
,
2649 struct tegra_clk_pll
*pll
;
2650 struct clk
*clk
, *parent
;
2651 unsigned long parent_rate
;
2653 if (!pll_params
->pdiv_tohw
)
2654 return ERR_PTR(-EINVAL
);
2656 parent
= __clk_lookup(parent_name
);
2658 WARN(1, "parent clk %s of %s must be registered first\n",
2660 return ERR_PTR(-EINVAL
);
2663 parent_rate
= clk_get_rate(parent
);
2665 pll_params
->vco_min
= _clip_vco_min(pll_params
->vco_min
, parent_rate
);
2667 if (pll_params
->adjust_vco
)
2668 pll_params
->vco_min
= pll_params
->adjust_vco(pll_params
,
2671 pll_params
->flags
|= TEGRA_PLL_BYPASS
;
2672 pll_params
->flags
|= TEGRA_PLLMB
;
2673 pll
= _tegra_init_pll(clk_base
, pmc
, pll_params
, lock
);
2675 return ERR_CAST(pll
);
2677 clk
= _tegra_clk_register_pll(pll
, name
, parent_name
, flags
,
2678 &tegra_clk_pll_ops
);