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Linux 4.16.11
[linux/fpc-iii.git] / drivers / media / i2c / ov13858.c
blobbf7d06f3f21a29a5e0c2bf49001761893721ceae
1 /*
2 * Copyright (c) 2017 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License version
6 * 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15 #include <linux/acpi.h>
16 #include <linux/i2c.h>
17 #include <linux/module.h>
18 #include <linux/pm_runtime.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
21
22 #define OV13858_REG_VALUE_08BIT 1
23 #define OV13858_REG_VALUE_16BIT 2
24 #define OV13858_REG_VALUE_24BIT 3
25
26 #define OV13858_REG_MODE_SELECT 0x0100
27 #define OV13858_MODE_STANDBY 0x00
28 #define OV13858_MODE_STREAMING 0x01
29
30 #define OV13858_REG_SOFTWARE_RST 0x0103
31 #define OV13858_SOFTWARE_RST 0x01
32
33 /* PLL1 generates PCLK and MIPI_PHY_CLK */
34 #define OV13858_REG_PLL1_CTRL_0 0x0300
35 #define OV13858_REG_PLL1_CTRL_1 0x0301
36 #define OV13858_REG_PLL1_CTRL_2 0x0302
37 #define OV13858_REG_PLL1_CTRL_3 0x0303
38 #define OV13858_REG_PLL1_CTRL_4 0x0304
39 #define OV13858_REG_PLL1_CTRL_5 0x0305
40
41 /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */
42 #define OV13858_REG_PLL2_CTRL_B 0x030b
43 #define OV13858_REG_PLL2_CTRL_C 0x030c
44 #define OV13858_REG_PLL2_CTRL_D 0x030d
45 #define OV13858_REG_PLL2_CTRL_E 0x030e
46 #define OV13858_REG_PLL2_CTRL_F 0x030f
47 #define OV13858_REG_PLL2_CTRL_12 0x0312
48 #define OV13858_REG_MIPI_SC_CTRL0 0x3016
49 #define OV13858_REG_MIPI_SC_CTRL1 0x3022
50
51 /* Chip ID */
52 #define OV13858_REG_CHIP_ID 0x300a
53 #define OV13858_CHIP_ID 0x00d855
54
55 /* V_TIMING internal */
56 #define OV13858_REG_VTS 0x380e
57 #define OV13858_VTS_30FPS 0x0c8e /* 30 fps */
58 #define OV13858_VTS_60FPS 0x0648 /* 60 fps */
59 #define OV13858_VTS_MAX 0x7fff
60
61 /* HBLANK control - read only */
62 #define OV13858_PPL_270MHZ 2244
63 #define OV13858_PPL_540MHZ 4488
64
65 /* Exposure control */
66 #define OV13858_REG_EXPOSURE 0x3500
67 #define OV13858_EXPOSURE_MIN 4
68 #define OV13858_EXPOSURE_STEP 1
69 #define OV13858_EXPOSURE_DEFAULT 0x640
70
71 /* Analog gain control */
72 #define OV13858_REG_ANALOG_GAIN 0x3508
73 #define OV13858_ANA_GAIN_MIN 0
74 #define OV13858_ANA_GAIN_MAX 0x1fff
75 #define OV13858_ANA_GAIN_STEP 1
76 #define OV13858_ANA_GAIN_DEFAULT 0x80
77
78 /* Digital gain control */
79 #define OV13858_REG_B_MWB_GAIN 0x5100
80 #define OV13858_REG_G_MWB_GAIN 0x5102
81 #define OV13858_REG_R_MWB_GAIN 0x5104
82 #define OV13858_DGTL_GAIN_MIN 0
83 #define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */
84 #define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */
85 #define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
86
87 /* Test Pattern Control */
88 #define OV13858_REG_TEST_PATTERN 0x4503
89 #define OV13858_TEST_PATTERN_ENABLE BIT(7)
90 #define OV13858_TEST_PATTERN_MASK 0xfc
91
92 /* Number of frames to skip */
93 #define OV13858_NUM_OF_SKIP_FRAMES 2
94
95 struct ov13858_reg {
96 u16 address;
97 u8 val;
98 };
99
100 struct ov13858_reg_list {
101 u32 num_of_regs;
102 const struct ov13858_reg *regs;
103 };
104
105 /* Link frequency config */
106 struct ov13858_link_freq_config {
107 u32 pixels_per_line;
108
109 /* PLL registers for this link frequency */
110 struct ov13858_reg_list reg_list;
111 };
112
113 /* Mode : resolution and related config&values */
114 struct ov13858_mode {
115 /* Frame width */
116 u32 width;
117 /* Frame height */
118 u32 height;
119
120 /* V-timing */
121 u32 vts_def;
122 u32 vts_min;
123
124 /* Index of Link frequency config to be used */
125 u32 link_freq_index;
126 /* Default register values */
127 struct ov13858_reg_list reg_list;
128 };
129
130 /* 4224x3136 needs 1080Mbps/lane, 4 lanes */
131 static const struct ov13858_reg mipi_data_rate_1080mbps[] = {
132 /* PLL1 registers */
133 {OV13858_REG_PLL1_CTRL_0, 0x07},
134 {OV13858_REG_PLL1_CTRL_1, 0x01},
135 {OV13858_REG_PLL1_CTRL_2, 0xc2},
136 {OV13858_REG_PLL1_CTRL_3, 0x00},
137 {OV13858_REG_PLL1_CTRL_4, 0x00},
138 {OV13858_REG_PLL1_CTRL_5, 0x01},
139
140 /* PLL2 registers */
141 {OV13858_REG_PLL2_CTRL_B, 0x05},
142 {OV13858_REG_PLL2_CTRL_C, 0x01},
143 {OV13858_REG_PLL2_CTRL_D, 0x0e},
144 {OV13858_REG_PLL2_CTRL_E, 0x05},
145 {OV13858_REG_PLL2_CTRL_F, 0x01},
146 {OV13858_REG_PLL2_CTRL_12, 0x01},
147 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
148 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
149 };
150
151 /*
152 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane,
153 * 4 lanes
154 */
155 static const struct ov13858_reg mipi_data_rate_540mbps[] = {
156 /* PLL1 registers */
157 {OV13858_REG_PLL1_CTRL_0, 0x07},
158 {OV13858_REG_PLL1_CTRL_1, 0x01},
159 {OV13858_REG_PLL1_CTRL_2, 0xc2},
160 {OV13858_REG_PLL1_CTRL_3, 0x01},
161 {OV13858_REG_PLL1_CTRL_4, 0x00},
162 {OV13858_REG_PLL1_CTRL_5, 0x01},
163
164 /* PLL2 registers */
165 {OV13858_REG_PLL2_CTRL_B, 0x05},
166 {OV13858_REG_PLL2_CTRL_C, 0x01},
167 {OV13858_REG_PLL2_CTRL_D, 0x0e},
168 {OV13858_REG_PLL2_CTRL_E, 0x05},
169 {OV13858_REG_PLL2_CTRL_F, 0x01},
170 {OV13858_REG_PLL2_CTRL_12, 0x01},
171 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
172 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
173 };
174
175 static const struct ov13858_reg mode_4224x3136_regs[] = {
176 {0x3013, 0x32},
177 {0x301b, 0xf0},
178 {0x301f, 0xd0},
179 {0x3106, 0x15},
180 {0x3107, 0x23},
181 {0x350a, 0x00},
182 {0x350e, 0x00},
183 {0x3510, 0x00},
184 {0x3511, 0x02},
185 {0x3512, 0x00},
186 {0x3600, 0x2b},
187 {0x3601, 0x52},
188 {0x3602, 0x60},
189 {0x3612, 0x05},
190 {0x3613, 0xa4},
191 {0x3620, 0x80},
192 {0x3621, 0x10},
193 {0x3622, 0x30},
194 {0x3624, 0x1c},
195 {0x3640, 0x10},
196 {0x3641, 0x70},
197 {0x3661, 0x80},
198 {0x3662, 0x12},
199 {0x3664, 0x73},
200 {0x3665, 0xa7},
201 {0x366e, 0xff},
202 {0x366f, 0xf4},
203 {0x3674, 0x00},
204 {0x3679, 0x0c},
205 {0x367f, 0x01},
206 {0x3680, 0x0c},
207 {0x3681, 0x50},
208 {0x3682, 0x50},
209 {0x3683, 0xa9},
210 {0x3684, 0xa9},
211 {0x3709, 0x5f},
212 {0x3714, 0x24},
213 {0x371a, 0x3e},
214 {0x3737, 0x04},
215 {0x3738, 0xcc},
216 {0x3739, 0x12},
217 {0x373d, 0x26},
218 {0x3764, 0x20},
219 {0x3765, 0x20},
220 {0x37a1, 0x36},
221 {0x37a8, 0x3b},
222 {0x37ab, 0x31},
223 {0x37c2, 0x04},
224 {0x37c3, 0xf1},
225 {0x37c5, 0x00},
226 {0x37d8, 0x03},
227 {0x37d9, 0x0c},
228 {0x37da, 0xc2},
229 {0x37dc, 0x02},
230 {0x37e0, 0x00},
231 {0x37e1, 0x0a},
232 {0x37e2, 0x14},
233 {0x37e3, 0x04},
234 {0x37e4, 0x2a},
235 {0x37e5, 0x03},
236 {0x37e6, 0x04},
237 {0x3800, 0x00},
238 {0x3801, 0x00},
239 {0x3802, 0x00},
240 {0x3803, 0x08},
241 {0x3804, 0x10},
242 {0x3805, 0x9f},
243 {0x3806, 0x0c},
244 {0x3807, 0x57},
245 {0x3808, 0x10},
246 {0x3809, 0x80},
247 {0x380a, 0x0c},
248 {0x380b, 0x40},
249 {0x380c, 0x04},
250 {0x380d, 0x62},
251 {0x380e, 0x0c},
252 {0x380f, 0x8e},
253 {0x3811, 0x04},
254 {0x3813, 0x05},
255 {0x3814, 0x01},
256 {0x3815, 0x01},
257 {0x3816, 0x01},
258 {0x3817, 0x01},
259 {0x3820, 0xa8},
260 {0x3821, 0x00},
261 {0x3822, 0xc2},
262 {0x3823, 0x18},
263 {0x3826, 0x11},
264 {0x3827, 0x1c},
265 {0x3829, 0x03},
266 {0x3832, 0x00},
267 {0x3c80, 0x00},
268 {0x3c87, 0x01},
269 {0x3c8c, 0x19},
270 {0x3c8d, 0x1c},
271 {0x3c90, 0x00},
272 {0x3c91, 0x00},
273 {0x3c92, 0x00},
274 {0x3c93, 0x00},
275 {0x3c94, 0x40},
276 {0x3c95, 0x54},
277 {0x3c96, 0x34},
278 {0x3c97, 0x04},
279 {0x3c98, 0x00},
280 {0x3d8c, 0x73},
281 {0x3d8d, 0xc0},
282 {0x3f00, 0x0b},
283 {0x3f03, 0x00},
284 {0x4001, 0xe0},
285 {0x4008, 0x00},
286 {0x4009, 0x0f},
287 {0x4011, 0xf0},
288 {0x4017, 0x08},
289 {0x4050, 0x04},
290 {0x4051, 0x0b},
291 {0x4052, 0x00},
292 {0x4053, 0x80},
293 {0x4054, 0x00},
294 {0x4055, 0x80},
295 {0x4056, 0x00},
296 {0x4057, 0x80},
297 {0x4058, 0x00},
298 {0x4059, 0x80},
299 {0x405e, 0x20},
300 {0x4500, 0x07},
301 {0x4503, 0x00},
302 {0x450a, 0x04},
303 {0x4809, 0x04},
304 {0x480c, 0x12},
305 {0x481f, 0x30},
306 {0x4833, 0x10},
307 {0x4837, 0x0e},
308 {0x4902, 0x01},
309 {0x4d00, 0x03},
310 {0x4d01, 0xc9},
311 {0x4d02, 0xbc},
312 {0x4d03, 0xd7},
313 {0x4d04, 0xf0},
314 {0x4d05, 0xa2},
315 {0x5000, 0xfd},
316 {0x5001, 0x01},
317 {0x5040, 0x39},
318 {0x5041, 0x10},
319 {0x5042, 0x10},
320 {0x5043, 0x84},
321 {0x5044, 0x62},
322 {0x5180, 0x00},
323 {0x5181, 0x10},
324 {0x5182, 0x02},
325 {0x5183, 0x0f},
326 {0x5200, 0x1b},
327 {0x520b, 0x07},
328 {0x520c, 0x0f},
329 {0x5300, 0x04},
330 {0x5301, 0x0c},
331 {0x5302, 0x0c},
332 {0x5303, 0x0f},
333 {0x5304, 0x00},
334 {0x5305, 0x70},
335 {0x5306, 0x00},
336 {0x5307, 0x80},
337 {0x5308, 0x00},
338 {0x5309, 0xa5},
339 {0x530a, 0x00},
340 {0x530b, 0xd3},
341 {0x530c, 0x00},
342 {0x530d, 0xf0},
343 {0x530e, 0x01},
344 {0x530f, 0x10},
345 {0x5310, 0x01},
346 {0x5311, 0x20},
347 {0x5312, 0x01},
348 {0x5313, 0x20},
349 {0x5314, 0x01},
350 {0x5315, 0x20},
351 {0x5316, 0x08},
352 {0x5317, 0x08},
353 {0x5318, 0x10},
354 {0x5319, 0x88},
355 {0x531a, 0x88},
356 {0x531b, 0xa9},
357 {0x531c, 0xaa},
358 {0x531d, 0x0a},
359 {0x5405, 0x02},
360 {0x5406, 0x67},
361 {0x5407, 0x01},
362 {0x5408, 0x4a},
363 };
364
365 static const struct ov13858_reg mode_2112x1568_regs[] = {
366 {0x3013, 0x32},
367 {0x301b, 0xf0},
368 {0x301f, 0xd0},
369 {0x3106, 0x15},
370 {0x3107, 0x23},
371 {0x350a, 0x00},
372 {0x350e, 0x00},
373 {0x3510, 0x00},
374 {0x3511, 0x02},
375 {0x3512, 0x00},
376 {0x3600, 0x2b},
377 {0x3601, 0x52},
378 {0x3602, 0x60},
379 {0x3612, 0x05},
380 {0x3613, 0xa4},
381 {0x3620, 0x80},
382 {0x3621, 0x10},
383 {0x3622, 0x30},
384 {0x3624, 0x1c},
385 {0x3640, 0x10},
386 {0x3641, 0x70},
387 {0x3661, 0x80},
388 {0x3662, 0x10},
389 {0x3664, 0x73},
390 {0x3665, 0xa7},
391 {0x366e, 0xff},
392 {0x366f, 0xf4},
393 {0x3674, 0x00},
394 {0x3679, 0x0c},
395 {0x367f, 0x01},
396 {0x3680, 0x0c},
397 {0x3681, 0x50},
398 {0x3682, 0x50},
399 {0x3683, 0xa9},
400 {0x3684, 0xa9},
401 {0x3709, 0x5f},
402 {0x3714, 0x28},
403 {0x371a, 0x3e},
404 {0x3737, 0x08},
405 {0x3738, 0xcc},
406 {0x3739, 0x20},
407 {0x373d, 0x26},
408 {0x3764, 0x20},
409 {0x3765, 0x20},
410 {0x37a1, 0x36},
411 {0x37a8, 0x3b},
412 {0x37ab, 0x31},
413 {0x37c2, 0x14},
414 {0x37c3, 0xf1},
415 {0x37c5, 0x00},
416 {0x37d8, 0x03},
417 {0x37d9, 0x0c},
418 {0x37da, 0xc2},
419 {0x37dc, 0x02},
420 {0x37e0, 0x00},
421 {0x37e1, 0x0a},
422 {0x37e2, 0x14},
423 {0x37e3, 0x08},
424 {0x37e4, 0x38},
425 {0x37e5, 0x03},
426 {0x37e6, 0x08},
427 {0x3800, 0x00},
428 {0x3801, 0x00},
429 {0x3802, 0x00},
430 {0x3803, 0x00},
431 {0x3804, 0x10},
432 {0x3805, 0x9f},
433 {0x3806, 0x0c},
434 {0x3807, 0x5f},
435 {0x3808, 0x08},
436 {0x3809, 0x40},
437 {0x380a, 0x06},
438 {0x380b, 0x20},
439 {0x380c, 0x04},
440 {0x380d, 0x62},
441 {0x380e, 0x0c},
442 {0x380f, 0x8e},
443 {0x3811, 0x04},
444 {0x3813, 0x05},
445 {0x3814, 0x03},
446 {0x3815, 0x01},
447 {0x3816, 0x03},
448 {0x3817, 0x01},
449 {0x3820, 0xab},
450 {0x3821, 0x00},
451 {0x3822, 0xc2},
452 {0x3823, 0x18},
453 {0x3826, 0x04},
454 {0x3827, 0x90},
455 {0x3829, 0x07},
456 {0x3832, 0x00},
457 {0x3c80, 0x00},
458 {0x3c87, 0x01},
459 {0x3c8c, 0x19},
460 {0x3c8d, 0x1c},
461 {0x3c90, 0x00},
462 {0x3c91, 0x00},
463 {0x3c92, 0x00},
464 {0x3c93, 0x00},
465 {0x3c94, 0x40},
466 {0x3c95, 0x54},
467 {0x3c96, 0x34},
468 {0x3c97, 0x04},
469 {0x3c98, 0x00},
470 {0x3d8c, 0x73},
471 {0x3d8d, 0xc0},
472 {0x3f00, 0x0b},
473 {0x3f03, 0x00},
474 {0x4001, 0xe0},
475 {0x4008, 0x00},
476 {0x4009, 0x0d},
477 {0x4011, 0xf0},
478 {0x4017, 0x08},
479 {0x4050, 0x04},
480 {0x4051, 0x0b},
481 {0x4052, 0x00},
482 {0x4053, 0x80},
483 {0x4054, 0x00},
484 {0x4055, 0x80},
485 {0x4056, 0x00},
486 {0x4057, 0x80},
487 {0x4058, 0x00},
488 {0x4059, 0x80},
489 {0x405e, 0x20},
490 {0x4500, 0x07},
491 {0x4503, 0x00},
492 {0x450a, 0x04},
493 {0x4809, 0x04},
494 {0x480c, 0x12},
495 {0x481f, 0x30},
496 {0x4833, 0x10},
497 {0x4837, 0x1c},
498 {0x4902, 0x01},
499 {0x4d00, 0x03},
500 {0x4d01, 0xc9},
501 {0x4d02, 0xbc},
502 {0x4d03, 0xd7},
503 {0x4d04, 0xf0},
504 {0x4d05, 0xa2},
505 {0x5000, 0xfd},
506 {0x5001, 0x01},
507 {0x5040, 0x39},
508 {0x5041, 0x10},
509 {0x5042, 0x10},
510 {0x5043, 0x84},
511 {0x5044, 0x62},
512 {0x5180, 0x00},
513 {0x5181, 0x10},
514 {0x5182, 0x02},
515 {0x5183, 0x0f},
516 {0x5200, 0x1b},
517 {0x520b, 0x07},
518 {0x520c, 0x0f},
519 {0x5300, 0x04},
520 {0x5301, 0x0c},
521 {0x5302, 0x0c},
522 {0x5303, 0x0f},
523 {0x5304, 0x00},
524 {0x5305, 0x70},
525 {0x5306, 0x00},
526 {0x5307, 0x80},
527 {0x5308, 0x00},
528 {0x5309, 0xa5},
529 {0x530a, 0x00},
530 {0x530b, 0xd3},
531 {0x530c, 0x00},
532 {0x530d, 0xf0},
533 {0x530e, 0x01},
534 {0x530f, 0x10},
535 {0x5310, 0x01},
536 {0x5311, 0x20},
537 {0x5312, 0x01},
538 {0x5313, 0x20},
539 {0x5314, 0x01},
540 {0x5315, 0x20},
541 {0x5316, 0x08},
542 {0x5317, 0x08},
543 {0x5318, 0x10},
544 {0x5319, 0x88},
545 {0x531a, 0x88},
546 {0x531b, 0xa9},
547 {0x531c, 0xaa},
548 {0x531d, 0x0a},
549 {0x5405, 0x02},
550 {0x5406, 0x67},
551 {0x5407, 0x01},
552 {0x5408, 0x4a},
553 };
554
555 static const struct ov13858_reg mode_2112x1188_regs[] = {
556 {0x3013, 0x32},
557 {0x301b, 0xf0},
558 {0x301f, 0xd0},
559 {0x3106, 0x15},
560 {0x3107, 0x23},
561 {0x350a, 0x00},
562 {0x350e, 0x00},
563 {0x3510, 0x00},
564 {0x3511, 0x02},
565 {0x3512, 0x00},
566 {0x3600, 0x2b},
567 {0x3601, 0x52},
568 {0x3602, 0x60},
569 {0x3612, 0x05},
570 {0x3613, 0xa4},
571 {0x3620, 0x80},
572 {0x3621, 0x10},
573 {0x3622, 0x30},
574 {0x3624, 0x1c},
575 {0x3640, 0x10},
576 {0x3641, 0x70},
577 {0x3661, 0x80},
578 {0x3662, 0x10},
579 {0x3664, 0x73},
580 {0x3665, 0xa7},
581 {0x366e, 0xff},
582 {0x366f, 0xf4},
583 {0x3674, 0x00},
584 {0x3679, 0x0c},
585 {0x367f, 0x01},
586 {0x3680, 0x0c},
587 {0x3681, 0x50},
588 {0x3682, 0x50},
589 {0x3683, 0xa9},
590 {0x3684, 0xa9},
591 {0x3709, 0x5f},
592 {0x3714, 0x28},
593 {0x371a, 0x3e},
594 {0x3737, 0x08},
595 {0x3738, 0xcc},
596 {0x3739, 0x20},
597 {0x373d, 0x26},
598 {0x3764, 0x20},
599 {0x3765, 0x20},
600 {0x37a1, 0x36},
601 {0x37a8, 0x3b},
602 {0x37ab, 0x31},
603 {0x37c2, 0x14},
604 {0x37c3, 0xf1},
605 {0x37c5, 0x00},
606 {0x37d8, 0x03},
607 {0x37d9, 0x0c},
608 {0x37da, 0xc2},
609 {0x37dc, 0x02},
610 {0x37e0, 0x00},
611 {0x37e1, 0x0a},
612 {0x37e2, 0x14},
613 {0x37e3, 0x08},
614 {0x37e4, 0x38},
615 {0x37e5, 0x03},
616 {0x37e6, 0x08},
617 {0x3800, 0x00},
618 {0x3801, 0x00},
619 {0x3802, 0x01},
620 {0x3803, 0x84},
621 {0x3804, 0x10},
622 {0x3805, 0x9f},
623 {0x3806, 0x0a},
624 {0x3807, 0xd3},
625 {0x3808, 0x08},
626 {0x3809, 0x40},
627 {0x380a, 0x04},
628 {0x380b, 0xa4},
629 {0x380c, 0x04},
630 {0x380d, 0x62},
631 {0x380e, 0x0c},
632 {0x380f, 0x8e},
633 {0x3811, 0x08},
634 {0x3813, 0x03},
635 {0x3814, 0x03},
636 {0x3815, 0x01},
637 {0x3816, 0x03},
638 {0x3817, 0x01},
639 {0x3820, 0xab},
640 {0x3821, 0x00},
641 {0x3822, 0xc2},
642 {0x3823, 0x18},
643 {0x3826, 0x04},
644 {0x3827, 0x90},
645 {0x3829, 0x07},
646 {0x3832, 0x00},
647 {0x3c80, 0x00},
648 {0x3c87, 0x01},
649 {0x3c8c, 0x19},
650 {0x3c8d, 0x1c},
651 {0x3c90, 0x00},
652 {0x3c91, 0x00},
653 {0x3c92, 0x00},
654 {0x3c93, 0x00},
655 {0x3c94, 0x40},
656 {0x3c95, 0x54},
657 {0x3c96, 0x34},
658 {0x3c97, 0x04},
659 {0x3c98, 0x00},
660 {0x3d8c, 0x73},
661 {0x3d8d, 0xc0},
662 {0x3f00, 0x0b},
663 {0x3f03, 0x00},
664 {0x4001, 0xe0},
665 {0x4008, 0x00},
666 {0x4009, 0x0d},
667 {0x4011, 0xf0},
668 {0x4017, 0x08},
669 {0x4050, 0x04},
670 {0x4051, 0x0b},
671 {0x4052, 0x00},
672 {0x4053, 0x80},
673 {0x4054, 0x00},
674 {0x4055, 0x80},
675 {0x4056, 0x00},
676 {0x4057, 0x80},
677 {0x4058, 0x00},
678 {0x4059, 0x80},
679 {0x405e, 0x20},
680 {0x4500, 0x07},
681 {0x4503, 0x00},
682 {0x450a, 0x04},
683 {0x4809, 0x04},
684 {0x480c, 0x12},
685 {0x481f, 0x30},
686 {0x4833, 0x10},
687 {0x4837, 0x1c},
688 {0x4902, 0x01},
689 {0x4d00, 0x03},
690 {0x4d01, 0xc9},
691 {0x4d02, 0xbc},
692 {0x4d03, 0xd7},
693 {0x4d04, 0xf0},
694 {0x4d05, 0xa2},
695 {0x5000, 0xfd},
696 {0x5001, 0x01},
697 {0x5040, 0x39},
698 {0x5041, 0x10},
699 {0x5042, 0x10},
700 {0x5043, 0x84},
701 {0x5044, 0x62},
702 {0x5180, 0x00},
703 {0x5181, 0x10},
704 {0x5182, 0x02},
705 {0x5183, 0x0f},
706 {0x5200, 0x1b},
707 {0x520b, 0x07},
708 {0x520c, 0x0f},
709 {0x5300, 0x04},
710 {0x5301, 0x0c},
711 {0x5302, 0x0c},
712 {0x5303, 0x0f},
713 {0x5304, 0x00},
714 {0x5305, 0x70},
715 {0x5306, 0x00},
716 {0x5307, 0x80},
717 {0x5308, 0x00},
718 {0x5309, 0xa5},
719 {0x530a, 0x00},
720 {0x530b, 0xd3},
721 {0x530c, 0x00},
722 {0x530d, 0xf0},
723 {0x530e, 0x01},
724 {0x530f, 0x10},
725 {0x5310, 0x01},
726 {0x5311, 0x20},
727 {0x5312, 0x01},
728 {0x5313, 0x20},
729 {0x5314, 0x01},
730 {0x5315, 0x20},
731 {0x5316, 0x08},
732 {0x5317, 0x08},
733 {0x5318, 0x10},
734 {0x5319, 0x88},
735 {0x531a, 0x88},
736 {0x531b, 0xa9},
737 {0x531c, 0xaa},
738 {0x531d, 0x0a},
739 {0x5405, 0x02},
740 {0x5406, 0x67},
741 {0x5407, 0x01},
742 {0x5408, 0x4a},
743 };
744
745 static const struct ov13858_reg mode_1056x784_regs[] = {
746 {0x3013, 0x32},
747 {0x301b, 0xf0},
748 {0x301f, 0xd0},
749 {0x3106, 0x15},
750 {0x3107, 0x23},
751 {0x350a, 0x00},
752 {0x350e, 0x00},
753 {0x3510, 0x00},
754 {0x3511, 0x02},
755 {0x3512, 0x00},
756 {0x3600, 0x2b},
757 {0x3601, 0x52},
758 {0x3602, 0x60},
759 {0x3612, 0x05},
760 {0x3613, 0xa4},
761 {0x3620, 0x80},
762 {0x3621, 0x10},
763 {0x3622, 0x30},
764 {0x3624, 0x1c},
765 {0x3640, 0x10},
766 {0x3641, 0x70},
767 {0x3661, 0x80},
768 {0x3662, 0x08},
769 {0x3664, 0x73},
770 {0x3665, 0xa7},
771 {0x366e, 0xff},
772 {0x366f, 0xf4},
773 {0x3674, 0x00},
774 {0x3679, 0x0c},
775 {0x367f, 0x01},
776 {0x3680, 0x0c},
777 {0x3681, 0x50},
778 {0x3682, 0x50},
779 {0x3683, 0xa9},
780 {0x3684, 0xa9},
781 {0x3709, 0x5f},
782 {0x3714, 0x30},
783 {0x371a, 0x3e},
784 {0x3737, 0x08},
785 {0x3738, 0xcc},
786 {0x3739, 0x20},
787 {0x373d, 0x26},
788 {0x3764, 0x20},
789 {0x3765, 0x20},
790 {0x37a1, 0x36},
791 {0x37a8, 0x3b},
792 {0x37ab, 0x31},
793 {0x37c2, 0x2c},
794 {0x37c3, 0xf1},
795 {0x37c5, 0x00},
796 {0x37d8, 0x03},
797 {0x37d9, 0x06},
798 {0x37da, 0xc2},
799 {0x37dc, 0x02},
800 {0x37e0, 0x00},
801 {0x37e1, 0x0a},
802 {0x37e2, 0x14},
803 {0x37e3, 0x08},
804 {0x37e4, 0x36},
805 {0x37e5, 0x03},
806 {0x37e6, 0x08},
807 {0x3800, 0x00},
808 {0x3801, 0x00},
809 {0x3802, 0x00},
810 {0x3803, 0x00},
811 {0x3804, 0x10},
812 {0x3805, 0x9f},
813 {0x3806, 0x0c},
814 {0x3807, 0x5f},
815 {0x3808, 0x04},
816 {0x3809, 0x20},
817 {0x380a, 0x03},
818 {0x380b, 0x10},
819 {0x380c, 0x04},
820 {0x380d, 0x62},
821 {0x380e, 0x0c},
822 {0x380f, 0x8e},
823 {0x3811, 0x04},
824 {0x3813, 0x05},
825 {0x3814, 0x07},
826 {0x3815, 0x01},
827 {0x3816, 0x07},
828 {0x3817, 0x01},
829 {0x3820, 0xac},
830 {0x3821, 0x00},
831 {0x3822, 0xc2},
832 {0x3823, 0x18},
833 {0x3826, 0x04},
834 {0x3827, 0x48},
835 {0x3829, 0x03},
836 {0x3832, 0x00},
837 {0x3c80, 0x00},
838 {0x3c87, 0x01},
839 {0x3c8c, 0x19},
840 {0x3c8d, 0x1c},
841 {0x3c90, 0x00},
842 {0x3c91, 0x00},
843 {0x3c92, 0x00},
844 {0x3c93, 0x00},
845 {0x3c94, 0x40},
846 {0x3c95, 0x54},
847 {0x3c96, 0x34},
848 {0x3c97, 0x04},
849 {0x3c98, 0x00},
850 {0x3d8c, 0x73},
851 {0x3d8d, 0xc0},
852 {0x3f00, 0x0b},
853 {0x3f03, 0x00},
854 {0x4001, 0xe0},
855 {0x4008, 0x00},
856 {0x4009, 0x05},
857 {0x4011, 0xf0},
858 {0x4017, 0x08},
859 {0x4050, 0x02},
860 {0x4051, 0x05},
861 {0x4052, 0x00},
862 {0x4053, 0x80},
863 {0x4054, 0x00},
864 {0x4055, 0x80},
865 {0x4056, 0x00},
866 {0x4057, 0x80},
867 {0x4058, 0x00},
868 {0x4059, 0x80},
869 {0x405e, 0x20},
870 {0x4500, 0x07},
871 {0x4503, 0x00},
872 {0x450a, 0x04},
873 {0x4809, 0x04},
874 {0x480c, 0x12},
875 {0x481f, 0x30},
876 {0x4833, 0x10},
877 {0x4837, 0x1e},
878 {0x4902, 0x02},
879 {0x4d00, 0x03},
880 {0x4d01, 0xc9},
881 {0x4d02, 0xbc},
882 {0x4d03, 0xd7},
883 {0x4d04, 0xf0},
884 {0x4d05, 0xa2},
885 {0x5000, 0xfd},
886 {0x5001, 0x01},
887 {0x5040, 0x39},
888 {0x5041, 0x10},
889 {0x5042, 0x10},
890 {0x5043, 0x84},
891 {0x5044, 0x62},
892 {0x5180, 0x00},
893 {0x5181, 0x10},
894 {0x5182, 0x02},
895 {0x5183, 0x0f},
896 {0x5200, 0x1b},
897 {0x520b, 0x07},
898 {0x520c, 0x0f},
899 {0x5300, 0x04},
900 {0x5301, 0x0c},
901 {0x5302, 0x0c},
902 {0x5303, 0x0f},
903 {0x5304, 0x00},
904 {0x5305, 0x70},
905 {0x5306, 0x00},
906 {0x5307, 0x80},
907 {0x5308, 0x00},
908 {0x5309, 0xa5},
909 {0x530a, 0x00},
910 {0x530b, 0xd3},
911 {0x530c, 0x00},
912 {0x530d, 0xf0},
913 {0x530e, 0x01},
914 {0x530f, 0x10},
915 {0x5310, 0x01},
916 {0x5311, 0x20},
917 {0x5312, 0x01},
918 {0x5313, 0x20},
919 {0x5314, 0x01},
920 {0x5315, 0x20},
921 {0x5316, 0x08},
922 {0x5317, 0x08},
923 {0x5318, 0x10},
924 {0x5319, 0x88},
925 {0x531a, 0x88},
926 {0x531b, 0xa9},
927 {0x531c, 0xaa},
928 {0x531d, 0x0a},
929 {0x5405, 0x02},
930 {0x5406, 0x67},
931 {0x5407, 0x01},
932 {0x5408, 0x4a},
933 };
934
935 static const char * const ov13858_test_pattern_menu[] = {
936 "Disabled",
937 "Vertical Color Bar Type 1",
938 "Vertical Color Bar Type 2",
939 "Vertical Color Bar Type 3",
940 "Vertical Color Bar Type 4"
941 };
942
943 /* Configurations for supported link frequencies */
944 #define OV13858_NUM_OF_LINK_FREQS 2
945 #define OV13858_LINK_FREQ_540MHZ 540000000ULL
946 #define OV13858_LINK_FREQ_270MHZ 270000000ULL
947 #define OV13858_LINK_FREQ_INDEX_0 0
948 #define OV13858_LINK_FREQ_INDEX_1 1
949
950 /*
951 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
952 * data rate => double data rate; number of lanes => 4; bits per pixel => 10
953 */
954 static u64 link_freq_to_pixel_rate(u64 f)
955 {
956 f *= 2 * 4;
957 do_div(f, 10);
958
959 return f;
960 }
961
962 /* Menu items for LINK_FREQ V4L2 control */
963 static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = {
964 OV13858_LINK_FREQ_540MHZ,
965 OV13858_LINK_FREQ_270MHZ
966 };
967
968 /* Link frequency configs */
969 static const struct ov13858_link_freq_config
970 link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = {
971 {
972 .pixels_per_line = OV13858_PPL_540MHZ,
973 .reg_list = {
974 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps),
975 .regs = mipi_data_rate_1080mbps,
976 }
977 },
978 {
979 .pixels_per_line = OV13858_PPL_270MHZ,
980 .reg_list = {
981 .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps),
982 .regs = mipi_data_rate_540mbps,
983 }
984 }
985 };
986
987 /* Mode configs */
988 static const struct ov13858_mode supported_modes[] = {
989 {
990 .width = 4224,
991 .height = 3136,
992 .vts_def = OV13858_VTS_30FPS,
993 .vts_min = OV13858_VTS_30FPS,
994 .reg_list = {
995 .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs),
996 .regs = mode_4224x3136_regs,
997 },
998 .link_freq_index = OV13858_LINK_FREQ_INDEX_0,
999 },
1000 {
1001 .width = 2112,
1002 .height = 1568,
1003 .vts_def = OV13858_VTS_30FPS,
1004 .vts_min = 1608,
1005 .reg_list = {
1006 .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs),
1007 .regs = mode_2112x1568_regs,
1008 },
1009 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1010 },
1011 {
1012 .width = 2112,
1013 .height = 1188,
1014 .vts_def = OV13858_VTS_30FPS,
1015 .vts_min = 1608,
1016 .reg_list = {
1017 .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs),
1018 .regs = mode_2112x1188_regs,
1019 },
1020 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1021 },
1022 {
1023 .width = 1056,
1024 .height = 784,
1025 .vts_def = OV13858_VTS_30FPS,
1026 .vts_min = 804,
1027 .reg_list = {
1028 .num_of_regs = ARRAY_SIZE(mode_1056x784_regs),
1029 .regs = mode_1056x784_regs,
1030 },
1031 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1032 }
1033 };
1034
1035 struct ov13858 {
1036 struct v4l2_subdev sd;
1037 struct media_pad pad;
1038
1039 struct v4l2_ctrl_handler ctrl_handler;
1040 /* V4L2 Controls */
1041 struct v4l2_ctrl *link_freq;
1042 struct v4l2_ctrl *pixel_rate;
1043 struct v4l2_ctrl *vblank;
1044 struct v4l2_ctrl *hblank;
1045 struct v4l2_ctrl *exposure;
1046
1047 /* Current mode */
1048 const struct ov13858_mode *cur_mode;
1049
1050 /* Mutex for serialized access */
1051 struct mutex mutex;
1052
1053 /* Streaming on/off */
1054 bool streaming;
1055 };
1056
1057 #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd)
1058
1059 /* Read registers up to 4 at a time */
1060 static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 *val)
1061 {
1062 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1063 struct i2c_msg msgs[2];
1064 u8 *data_be_p;
1065 int ret;
1066 u32 data_be = 0;
1067 u16 reg_addr_be = cpu_to_be16(reg);
1068
1069 if (len > 4)
1070 return -EINVAL;
1071
1072 data_be_p = (u8 *)&data_be;
1073 /* Write register address */
1074 msgs[0].addr = client->addr;
1075 msgs[0].flags = 0;
1076 msgs[0].len = 2;
1077 msgs[0].buf = (u8 *)&reg_addr_be;
1078
1079 /* Read data from register */
1080 msgs[1].addr = client->addr;
1081 msgs[1].flags = I2C_M_RD;
1082 msgs[1].len = len;
1083 msgs[1].buf = &data_be_p[4 - len];
1084
1085 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1086 if (ret != ARRAY_SIZE(msgs))
1087 return -EIO;
1088
1089 *val = be32_to_cpu(data_be);
1090
1091 return 0;
1092 }
1093
1094 /* Write registers up to 4 at a time */
1095 static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 val)
1096 {
1097 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1098 int buf_i, val_i;
1099 u8 buf[6], *val_p;
1100
1101 if (len > 4)
1102 return -EINVAL;
1103
1104 buf[0] = reg >> 8;
1105 buf[1] = reg & 0xff;
1106
1107 val = cpu_to_be32(val);
1108 val_p = (u8 *)&val;
1109 buf_i = 2;
1110 val_i = 4 - len;
1111
1112 while (val_i < 4)
1113 buf[buf_i++] = val_p[val_i++];
1114
1115 if (i2c_master_send(client, buf, len + 2) != len + 2)
1116 return -EIO;
1117
1118 return 0;
1119 }
1120
1121 /* Write a list of registers */
1122 static int ov13858_write_regs(struct ov13858 *ov13858,
1123 const struct ov13858_reg *regs, u32 len)
1124 {
1125 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1126 int ret;
1127 u32 i;
1128
1129 for (i = 0; i < len; i++) {
1130 ret = ov13858_write_reg(ov13858, regs[i].address, 1,
1131 regs[i].val);
1132 if (ret) {
1133 dev_err_ratelimited(
1134 &client->dev,
1135 "Failed to write reg 0x%4.4x. error = %d\n",
1136 regs[i].address, ret);
1137
1138 return ret;
1139 }
1140 }
1141
1142 return 0;
1143 }
1144
1145 static int ov13858_write_reg_list(struct ov13858 *ov13858,
1146 const struct ov13858_reg_list *r_list)
1147 {
1148 return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs);
1149 }
1150
1151 /* Open sub-device */
1152 static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1153 {
1154 struct ov13858 *ov13858 = to_ov13858(sd);
1155 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
1156 fh->pad,
1157 0);
1158
1159 mutex_lock(&ov13858->mutex);
1160
1161 /* Initialize try_fmt */
1162 try_fmt->width = ov13858->cur_mode->width;
1163 try_fmt->height = ov13858->cur_mode->height;
1164 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1165 try_fmt->field = V4L2_FIELD_NONE;
1166
1167 /* No crop or compose */
1168 mutex_unlock(&ov13858->mutex);
1169
1170 return 0;
1171 }
1172
1173 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
1174 {
1175 int ret;
1176
1177 ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN,
1178 OV13858_REG_VALUE_16BIT, d_gain);
1179 if (ret)
1180 return ret;
1181
1182 ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN,
1183 OV13858_REG_VALUE_16BIT, d_gain);
1184 if (ret)
1185 return ret;
1186
1187 ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN,
1188 OV13858_REG_VALUE_16BIT, d_gain);
1189
1190 return ret;
1191 }
1192
1193 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)
1194 {
1195 int ret;
1196 u32 val;
1197
1198 ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN,
1199 OV13858_REG_VALUE_08BIT, &val);
1200 if (ret)
1201 return ret;
1202
1203 if (pattern) {
1204 val &= OV13858_TEST_PATTERN_MASK;
1205 val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE;
1206 } else {
1207 val &= ~OV13858_TEST_PATTERN_ENABLE;
1208 }
1209
1210 return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN,
1211 OV13858_REG_VALUE_08BIT, val);
1212 }
1213
1214 static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl)
1215 {
1216 struct ov13858 *ov13858 = container_of(ctrl->handler,
1217 struct ov13858, ctrl_handler);
1218 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1219 s64 max;
1220 int ret;
1221
1222 /* Propagate change of current control to all related controls */
1223 switch (ctrl->id) {
1224 case V4L2_CID_VBLANK:
1225 /* Update max exposure while meeting expected vblanking */
1226 max = ov13858->cur_mode->height + ctrl->val - 8;
1227 __v4l2_ctrl_modify_range(ov13858->exposure,
1228 ov13858->exposure->minimum,
1229 max, ov13858->exposure->step, max);
1230 break;
1231 };
1232
1233 /*
1234 * Applying V4L2 control value only happens
1235 * when power is up for streaming
1236 */
1237 if (pm_runtime_get_if_in_use(&client->dev) <= 0)
1238 return 0;
1239
1240 ret = 0;
1241 switch (ctrl->id) {
1242 case V4L2_CID_ANALOGUE_GAIN:
1243 ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN,
1244 OV13858_REG_VALUE_16BIT, ctrl->val);
1245 break;
1246 case V4L2_CID_DIGITAL_GAIN:
1247 ret = ov13858_update_digital_gain(ov13858, ctrl->val);
1248 break;
1249 case V4L2_CID_EXPOSURE:
1250 ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE,
1251 OV13858_REG_VALUE_24BIT,
1252 ctrl->val << 4);
1253 break;
1254 case V4L2_CID_VBLANK:
1255 /* Update VTS that meets expected vertical blanking */
1256 ret = ov13858_write_reg(ov13858, OV13858_REG_VTS,
1257 OV13858_REG_VALUE_16BIT,
1258 ov13858->cur_mode->height
1259 + ctrl->val);
1260 break;
1261 case V4L2_CID_TEST_PATTERN:
1262 ret = ov13858_enable_test_pattern(ov13858, ctrl->val);
1263 break;
1264 default:
1265 dev_info(&client->dev,
1266 "ctrl(id:0x%x,val:0x%x) is not handled\n",
1267 ctrl->id, ctrl->val);
1268 break;
1269 };
1270
1271 pm_runtime_put(&client->dev);
1272
1273 return ret;
1274 }
1275
1276 static const struct v4l2_ctrl_ops ov13858_ctrl_ops = {
1277 .s_ctrl = ov13858_set_ctrl,
1278 };
1279
1280 static int ov13858_enum_mbus_code(struct v4l2_subdev *sd,
1281 struct v4l2_subdev_pad_config *cfg,
1282 struct v4l2_subdev_mbus_code_enum *code)
1283 {
1284 /* Only one bayer order(GRBG) is supported */
1285 if (code->index > 0)
1286 return -EINVAL;
1287
1288 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1289
1290 return 0;
1291 }
1292
1293 static int ov13858_enum_frame_size(struct v4l2_subdev *sd,
1294 struct v4l2_subdev_pad_config *cfg,
1295 struct v4l2_subdev_frame_size_enum *fse)
1296 {
1297 if (fse->index >= ARRAY_SIZE(supported_modes))
1298 return -EINVAL;
1299
1300 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1301 return -EINVAL;
1302
1303 fse->min_width = supported_modes[fse->index].width;
1304 fse->max_width = fse->min_width;
1305 fse->min_height = supported_modes[fse->index].height;
1306 fse->max_height = fse->min_height;
1307
1308 return 0;
1309 }
1310
1311 static void ov13858_update_pad_format(const struct ov13858_mode *mode,
1312 struct v4l2_subdev_format *fmt)
1313 {
1314 fmt->format.width = mode->width;
1315 fmt->format.height = mode->height;
1316 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1317 fmt->format.field = V4L2_FIELD_NONE;
1318 }
1319
1320 static int ov13858_do_get_pad_format(struct ov13858 *ov13858,
1321 struct v4l2_subdev_pad_config *cfg,
1322 struct v4l2_subdev_format *fmt)
1323 {
1324 struct v4l2_mbus_framefmt *framefmt;
1325 struct v4l2_subdev *sd = &ov13858->sd;
1326
1327 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1328 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1329 fmt->format = *framefmt;
1330 } else {
1331 ov13858_update_pad_format(ov13858->cur_mode, fmt);
1332 }
1333
1334 return 0;
1335 }
1336
1337 static int ov13858_get_pad_format(struct v4l2_subdev *sd,
1338 struct v4l2_subdev_pad_config *cfg,
1339 struct v4l2_subdev_format *fmt)
1340 {
1341 struct ov13858 *ov13858 = to_ov13858(sd);
1342 int ret;
1343
1344 mutex_lock(&ov13858->mutex);
1345 ret = ov13858_do_get_pad_format(ov13858, cfg, fmt);
1346 mutex_unlock(&ov13858->mutex);
1347
1348 return ret;
1349 }
1350
1351 /*
1352 * Calculate resolution distance
1353 */
1354 static int
1355 ov13858_get_resolution_dist(const struct ov13858_mode *mode,
1356 struct v4l2_mbus_framefmt *framefmt)
1357 {
1358 return abs(mode->width - framefmt->width) +
1359 abs(mode->height - framefmt->height);
1360 }
1361
1362 /*
1363 * Find the closest supported resolution to the requested resolution
1364 */
1365 static const struct ov13858_mode *
1366 ov13858_find_best_fit(struct ov13858 *ov13858,
1367 struct v4l2_subdev_format *fmt)
1368 {
1369 int i, dist, cur_best_fit = 0, cur_best_fit_dist = -1;
1370 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1371
1372 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1373 dist = ov13858_get_resolution_dist(&supported_modes[i],
1374 framefmt);
1375 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1376 cur_best_fit_dist = dist;
1377 cur_best_fit = i;
1378 }
1379 }
1380
1381 return &supported_modes[cur_best_fit];
1382 }
1383
1384 static int
1385 ov13858_set_pad_format(struct v4l2_subdev *sd,
1386 struct v4l2_subdev_pad_config *cfg,
1387 struct v4l2_subdev_format *fmt)
1388 {
1389 struct ov13858 *ov13858 = to_ov13858(sd);
1390 const struct ov13858_mode *mode;
1391 struct v4l2_mbus_framefmt *framefmt;
1392 s32 vblank_def;
1393 s32 vblank_min;
1394 s64 h_blank;
1395 s64 pixel_rate;
1396 s64 link_freq;
1397
1398 mutex_lock(&ov13858->mutex);
1399
1400 /* Only one raw bayer(GRBG) order is supported */
1401 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1402 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1403
1404 mode = ov13858_find_best_fit(ov13858, fmt);
1405 ov13858_update_pad_format(mode, fmt);
1406 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1407 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1408 *framefmt = fmt->format;
1409 } else {
1410 ov13858->cur_mode = mode;
1411 __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index);
1412 link_freq = link_freq_menu_items[mode->link_freq_index];
1413 pixel_rate = link_freq_to_pixel_rate(link_freq);
1414 __v4l2_ctrl_s_ctrl_int64(ov13858->pixel_rate, pixel_rate);
1415
1416 /* Update limits and set FPS to default */
1417 vblank_def = ov13858->cur_mode->vts_def -
1418 ov13858->cur_mode->height;
1419 vblank_min = ov13858->cur_mode->vts_min -
1420 ov13858->cur_mode->height;
1421 __v4l2_ctrl_modify_range(
1422 ov13858->vblank, vblank_min,
1423 OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
1424 vblank_def);
1425 __v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def);
1426 h_blank =
1427 link_freq_configs[mode->link_freq_index].pixels_per_line
1428 - ov13858->cur_mode->width;
1429 __v4l2_ctrl_modify_range(ov13858->hblank, h_blank,
1430 h_blank, 1, h_blank);
1431 }
1432
1433 mutex_unlock(&ov13858->mutex);
1434
1435 return 0;
1436 }
1437
1438 static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
1439 {
1440 *frames = OV13858_NUM_OF_SKIP_FRAMES;
1441
1442 return 0;
1443 }
1444
1445 /* Start streaming */
1446 static int ov13858_start_streaming(struct ov13858 *ov13858)
1447 {
1448 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1449 const struct ov13858_reg_list *reg_list;
1450 int ret, link_freq_index;
1451
1452 /* Get out of from software reset */
1453 ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST,
1454 OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST);
1455 if (ret) {
1456 dev_err(&client->dev, "%s failed to set powerup registers\n",
1457 __func__);
1458 return ret;
1459 }
1460
1461 /* Setup PLL */
1462 link_freq_index = ov13858->cur_mode->link_freq_index;
1463 reg_list = &link_freq_configs[link_freq_index].reg_list;
1464 ret = ov13858_write_reg_list(ov13858, reg_list);
1465 if (ret) {
1466 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1467 return ret;
1468 }
1469
1470 /* Apply default values of current mode */
1471 reg_list = &ov13858->cur_mode->reg_list;
1472 ret = ov13858_write_reg_list(ov13858, reg_list);
1473 if (ret) {
1474 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1475 return ret;
1476 }
1477
1478 /* Apply customized values from user */
1479 ret = __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler);
1480 if (ret)
1481 return ret;
1482
1483 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1484 OV13858_REG_VALUE_08BIT,
1485 OV13858_MODE_STREAMING);
1486 }
1487
1488 /* Stop streaming */
1489 static int ov13858_stop_streaming(struct ov13858 *ov13858)
1490 {
1491 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1492 OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY);
1493 }
1494
1495 static int ov13858_set_stream(struct v4l2_subdev *sd, int enable)
1496 {
1497 struct ov13858 *ov13858 = to_ov13858(sd);
1498 struct i2c_client *client = v4l2_get_subdevdata(sd);
1499 int ret = 0;
1500
1501 mutex_lock(&ov13858->mutex);
1502 if (ov13858->streaming == enable) {
1503 mutex_unlock(&ov13858->mutex);
1504 return 0;
1505 }
1506
1507 if (enable) {
1508 ret = pm_runtime_get_sync(&client->dev);
1509 if (ret < 0) {
1510 pm_runtime_put_noidle(&client->dev);
1511 goto err_unlock;
1512 }
1513
1514 /*
1515 * Apply default & customized values
1516 * and then start streaming.
1517 */
1518 ret = ov13858_start_streaming(ov13858);
1519 if (ret)
1520 goto err_rpm_put;
1521 } else {
1522 ov13858_stop_streaming(ov13858);
1523 pm_runtime_put(&client->dev);
1524 }
1525
1526 ov13858->streaming = enable;
1527 mutex_unlock(&ov13858->mutex);
1528
1529 return ret;
1530
1531 err_rpm_put:
1532 pm_runtime_put(&client->dev);
1533 err_unlock:
1534 mutex_unlock(&ov13858->mutex);
1535
1536 return ret;
1537 }
1538
1539 static int __maybe_unused ov13858_suspend(struct device *dev)
1540 {
1541 struct i2c_client *client = to_i2c_client(dev);
1542 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1543 struct ov13858 *ov13858 = to_ov13858(sd);
1544
1545 if (ov13858->streaming)
1546 ov13858_stop_streaming(ov13858);
1547
1548 return 0;
1549 }
1550
1551 static int __maybe_unused ov13858_resume(struct device *dev)
1552 {
1553 struct i2c_client *client = to_i2c_client(dev);
1554 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1555 struct ov13858 *ov13858 = to_ov13858(sd);
1556 int ret;
1557
1558 if (ov13858->streaming) {
1559 ret = ov13858_start_streaming(ov13858);
1560 if (ret)
1561 goto error;
1562 }
1563
1564 return 0;
1565
1566 error:
1567 ov13858_stop_streaming(ov13858);
1568 ov13858->streaming = 0;
1569 return ret;
1570 }
1571
1572 /* Verify chip ID */
1573 static int ov13858_identify_module(struct ov13858 *ov13858)
1574 {
1575 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1576 int ret;
1577 u32 val;
1578
1579 ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID,
1580 OV13858_REG_VALUE_24BIT, &val);
1581 if (ret)
1582 return ret;
1583
1584 if (val != OV13858_CHIP_ID) {
1585 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1586 OV13858_CHIP_ID, val);
1587 return -EIO;
1588 }
1589
1590 return 0;
1591 }
1592
1593 static const struct v4l2_subdev_video_ops ov13858_video_ops = {
1594 .s_stream = ov13858_set_stream,
1595 };
1596
1597 static const struct v4l2_subdev_pad_ops ov13858_pad_ops = {
1598 .enum_mbus_code = ov13858_enum_mbus_code,
1599 .get_fmt = ov13858_get_pad_format,
1600 .set_fmt = ov13858_set_pad_format,
1601 .enum_frame_size = ov13858_enum_frame_size,
1602 };
1603
1604 static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = {
1605 .g_skip_frames = ov13858_get_skip_frames,
1606 };
1607
1608 static const struct v4l2_subdev_ops ov13858_subdev_ops = {
1609 .video = &ov13858_video_ops,
1610 .pad = &ov13858_pad_ops,
1611 .sensor = &ov13858_sensor_ops,
1612 };
1613
1614 static const struct media_entity_operations ov13858_subdev_entity_ops = {
1615 .link_validate = v4l2_subdev_link_validate,
1616 };
1617
1618 static const struct v4l2_subdev_internal_ops ov13858_internal_ops = {
1619 .open = ov13858_open,
1620 };
1621
1622 /* Initialize control handlers */
1623 static int ov13858_init_controls(struct ov13858 *ov13858)
1624 {
1625 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1626 struct v4l2_ctrl_handler *ctrl_hdlr;
1627 s64 exposure_max;
1628 s64 vblank_def;
1629 s64 vblank_min;
1630 s64 hblank;
1631 s64 pixel_rate_min;
1632 s64 pixel_rate_max;
1633 const struct ov13858_mode *mode;
1634 int ret;
1635
1636 ctrl_hdlr = &ov13858->ctrl_handler;
1637 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
1638 if (ret)
1639 return ret;
1640
1641 mutex_init(&ov13858->mutex);
1642 ctrl_hdlr->lock = &ov13858->mutex;
1643 ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1644 &ov13858_ctrl_ops,
1645 V4L2_CID_LINK_FREQ,
1646 OV13858_NUM_OF_LINK_FREQS - 1,
1647 0,
1648 link_freq_menu_items);
1649 ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1650
1651 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1652 pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]);
1653 /* By default, PIXEL_RATE is read only */
1654 ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops,
1655 V4L2_CID_PIXEL_RATE,
1656 pixel_rate_min, pixel_rate_max,
1657 1, pixel_rate_max);
1658
1659 mode = ov13858->cur_mode;
1660 vblank_def = mode->vts_def - mode->height;
1661 vblank_min = mode->vts_min - mode->height;
1662 ov13858->vblank = v4l2_ctrl_new_std(
1663 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK,
1664 vblank_min, OV13858_VTS_MAX - mode->height, 1,
1665 vblank_def);
1666
1667 hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
1668 mode->width;
1669 ov13858->hblank = v4l2_ctrl_new_std(
1670 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK,
1671 hblank, hblank, 1, hblank);
1672 ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1673
1674 exposure_max = mode->vts_def - 8;
1675 ov13858->exposure = v4l2_ctrl_new_std(
1676 ctrl_hdlr, &ov13858_ctrl_ops,
1677 V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN,
1678 exposure_max, OV13858_EXPOSURE_STEP,
1679 OV13858_EXPOSURE_DEFAULT);
1680
1681 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1682 OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX,
1683 OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT);
1684
1685 /* Digital gain */
1686 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1687 OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX,
1688 OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT);
1689
1690 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops,
1691 V4L2_CID_TEST_PATTERN,
1692 ARRAY_SIZE(ov13858_test_pattern_menu) - 1,
1693 0, 0, ov13858_test_pattern_menu);
1694 if (ctrl_hdlr->error) {
1695 ret = ctrl_hdlr->error;
1696 dev_err(&client->dev, "%s control init failed (%d)\n",
1697 __func__, ret);
1698 goto error;
1699 }
1700
1701 ov13858->sd.ctrl_handler = ctrl_hdlr;
1702
1703 return 0;
1704
1705 error:
1706 v4l2_ctrl_handler_free(ctrl_hdlr);
1707 mutex_destroy(&ov13858->mutex);
1708
1709 return ret;
1710 }
1711
1712 static void ov13858_free_controls(struct ov13858 *ov13858)
1713 {
1714 v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler);
1715 mutex_destroy(&ov13858->mutex);
1716 }
1717
1718 static int ov13858_probe(struct i2c_client *client,
1719 const struct i2c_device_id *devid)
1720 {
1721 struct ov13858 *ov13858;
1722 int ret;
1723 u32 val = 0;
1724
1725 device_property_read_u32(&client->dev, "clock-frequency", &val);
1726 if (val != 19200000)
1727 return -EINVAL;
1728
1729 ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL);
1730 if (!ov13858)
1731 return -ENOMEM;
1732
1733 /* Initialize subdev */
1734 v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops);
1735
1736 /* Check module identity */
1737 ret = ov13858_identify_module(ov13858);
1738 if (ret) {
1739 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1740 return ret;
1741 }
1742
1743 /* Set default mode to max resolution */
1744 ov13858->cur_mode = &supported_modes[0];
1745
1746 ret = ov13858_init_controls(ov13858);
1747 if (ret)
1748 return ret;
1749
1750 /* Initialize subdev */
1751 ov13858->sd.internal_ops = &ov13858_internal_ops;
1752 ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1753 ov13858->sd.entity.ops = &ov13858_subdev_entity_ops;
1754 ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1755
1756 /* Initialize source pad */
1757 ov13858->pad.flags = MEDIA_PAD_FL_SOURCE;
1758 ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad);
1759 if (ret) {
1760 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1761 goto error_handler_free;
1762 }
1763
1764 ret = v4l2_async_register_subdev_sensor_common(&ov13858->sd);
1765 if (ret < 0)
1766 goto error_media_entity;
1767
1768 /*
1769 * Device is already turned on by i2c-core with ACPI domain PM.
1770 * Enable runtime PM and turn off the device.
1771 */
1772 pm_runtime_get_noresume(&client->dev);
1773 pm_runtime_set_active(&client->dev);
1774 pm_runtime_enable(&client->dev);
1775 pm_runtime_put(&client->dev);
1776
1777 return 0;
1778
1779 error_media_entity:
1780 media_entity_cleanup(&ov13858->sd.entity);
1781
1782 error_handler_free:
1783 ov13858_free_controls(ov13858);
1784 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1785
1786 return ret;
1787 }
1788
1789 static int ov13858_remove(struct i2c_client *client)
1790 {
1791 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1792 struct ov13858 *ov13858 = to_ov13858(sd);
1793
1794 v4l2_async_unregister_subdev(sd);
1795 media_entity_cleanup(&sd->entity);
1796 ov13858_free_controls(ov13858);
1797
1798 /*
1799 * Disable runtime PM but keep the device turned on.
1800 * i2c-core with ACPI domain PM will turn off the device.
1801 */
1802 pm_runtime_get_sync(&client->dev);
1803 pm_runtime_disable(&client->dev);
1804 pm_runtime_set_suspended(&client->dev);
1805 pm_runtime_put_noidle(&client->dev);
1806
1807 return 0;
1808 }
1809
1810 static const struct i2c_device_id ov13858_id_table[] = {
1811 {"ov13858", 0},
1812 {},
1813 };
1814
1815 MODULE_DEVICE_TABLE(i2c, ov13858_id_table);
1816
1817 static const struct dev_pm_ops ov13858_pm_ops = {
1818 SET_SYSTEM_SLEEP_PM_OPS(ov13858_suspend, ov13858_resume)
1819 };
1820
1821 #ifdef CONFIG_ACPI
1822 static const struct acpi_device_id ov13858_acpi_ids[] = {
1823 {"OVTID858"},
1824 { /* sentinel */ }
1825 };
1826
1827 MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids);
1828 #endif
1829
1830 static struct i2c_driver ov13858_i2c_driver = {
1831 .driver = {
1832 .name = "ov13858",
1833 .owner = THIS_MODULE,
1834 .pm = &ov13858_pm_ops,
1835 .acpi_match_table = ACPI_PTR(ov13858_acpi_ids),
1836 },
1837 .probe = ov13858_probe,
1838 .remove = ov13858_remove,
1839 .id_table = ov13858_id_table,
1840 };
1841
1842 module_i2c_driver(ov13858_i2c_driver);
1843
1844 MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>");
1845 MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>");
1846 MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>");
1847 MODULE_DESCRIPTION("Omnivision ov13858 sensor driver");
1848 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support