drivers/pci/hotplug/pciehp_hpc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * PCI Express PCI Hot Plug Driver
   4  *
   5  * Copyright (C) 1995,2001 Compaq Computer Corporation
   6  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   7  * Copyright (C) 2001 IBM Corp.
   8  * Copyright (C) 2003-2004 Intel Corporation
   9  *
  10  * All rights reserved.
  11  *
  12  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  13  *
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/signal.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/timer.h>
  22 #include <linux/pci.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/time.h>
  25 #include <linux/slab.h>
  26
  27 #include "../pci.h"
  28 #include "pciehp.h"
  29
  30 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
  31 {
  32         return ctrl->pcie->port;
  33 }
  34
  35 static irqreturn_t pcie_isr(int irq, void *dev_id);
  36 static void start_int_poll_timer(struct controller *ctrl, int sec);
  37
  38 /* This is the interrupt polling timeout function. */
  39 static void int_poll_timeout(struct timer_list *t)
  40 {
  41         struct controller *ctrl = from_timer(ctrl, t, poll_timer);
  42
  43         /* Poll for interrupt events.  regs == NULL => polling */
  44         pcie_isr(0, ctrl);
  45
  46         if (!pciehp_poll_time)
  47                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
  48
  49         start_int_poll_timer(ctrl, pciehp_poll_time);
  50 }
  51
  52 /* This function starts the interrupt polling timer. */
  53 static void start_int_poll_timer(struct controller *ctrl, int sec)
  54 {
  55         /* Clamp to sane value */
  56         if ((sec <= 0) || (sec > 60))
  57                 sec = 2;
  58
  59         ctrl->poll_timer.expires = jiffies + sec * HZ;
  60         add_timer(&ctrl->poll_timer);
  61 }
  62
  63 static inline int pciehp_request_irq(struct controller *ctrl)
  64 {
  65         int retval, irq = ctrl->pcie->irq;
  66
  67         /* Install interrupt polling timer. Start with 10 sec delay */
  68         if (pciehp_poll_mode) {
  69                 timer_setup(&ctrl->poll_timer, int_poll_timeout, 0);
  70                 start_int_poll_timer(ctrl, 10);
  71                 return 0;
  72         }
  73
  74         /* Installs the interrupt handler */
  75         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
  76         if (retval)
  77                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
  78                          irq);
  79         return retval;
  80 }
  81
  82 static inline void pciehp_free_irq(struct controller *ctrl)
  83 {
  84         if (pciehp_poll_mode)
  85                 del_timer_sync(&ctrl->poll_timer);
  86         else
  87                 free_irq(ctrl->pcie->irq, ctrl);
  88 }
  89
  90 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
  91 {
  92         struct pci_dev *pdev = ctrl_dev(ctrl);
  93         u16 slot_status;
  94
  95         while (true) {
  96                 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
  97                 if (slot_status == (u16) ~0) {
  98                         ctrl_info(ctrl, "%s: no response from device\n",
  99                                   __func__);
 100                         return 0;
 101                 }
 102
 103                 if (slot_status & PCI_EXP_SLTSTA_CC) {
 104                         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 105                                                    PCI_EXP_SLTSTA_CC);
 106                         return 1;
 107                 }
 108                 if (timeout < 0)
 109                         break;
 110                 msleep(10);
 111                 timeout -= 10;
 112         }
 113         return 0;       /* timeout */
 114 }
 115
 116 static void pcie_wait_cmd(struct controller *ctrl)
 117 {
 118         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 119         unsigned long duration = msecs_to_jiffies(msecs);
 120         unsigned long cmd_timeout = ctrl->cmd_started + duration;
 121         unsigned long now, timeout;
 122         int rc;
 123
 124         /*
 125          * If the controller does not generate notifications for command
 126          * completions, we never need to wait between writes.
 127          */
 128         if (NO_CMD_CMPL(ctrl))
 129                 return;
 130
 131         if (!ctrl->cmd_busy)
 132                 return;
 133
 134         /*
 135          * Even if the command has already timed out, we want to call
 136          * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
 137          */
 138         now = jiffies;
 139         if (time_before_eq(cmd_timeout, now))
 140                 timeout = 1;
 141         else
 142                 timeout = cmd_timeout - now;
 143
 144         if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
 145             ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
 146                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 147         else
 148                 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
 149
 150         /*
 151          * Controllers with errata like Intel CF118 don't generate
 152          * completion notifications unless the power/indicator/interlock
 153          * control bits are changed.  On such controllers, we'll emit this
 154          * timeout message when we wait for completion of commands that
 155          * don't change those bits, e.g., commands that merely enable
 156          * interrupts.
 157          */
 158         if (!rc)
 159                 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
 160                           ctrl->slot_ctrl,
 161                           jiffies_to_msecs(jiffies - ctrl->cmd_started));
 162 }
 163
 164 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
 165                               u16 mask, bool wait)
 166 {
 167         struct pci_dev *pdev = ctrl_dev(ctrl);
 168         u16 slot_ctrl;
 169
 170         mutex_lock(&ctrl->ctrl_lock);
 171
 172         /*
 173          * Always wait for any previous command that might still be in progress
 174          */
 175         pcie_wait_cmd(ctrl);
 176
 177         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 178         if (slot_ctrl == (u16) ~0) {
 179                 ctrl_info(ctrl, "%s: no response from device\n", __func__);
 180                 goto out;
 181         }
 182
 183         slot_ctrl &= ~mask;
 184         slot_ctrl |= (cmd & mask);
 185         ctrl->cmd_busy = 1;
 186         smp_mb();
 187         pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
 188         ctrl->cmd_started = jiffies;
 189         ctrl->slot_ctrl = slot_ctrl;
 190
 191         /*
 192          * Optionally wait for the hardware to be ready for a new command,
 193          * indicating completion of the above issued command.
 194          */
 195         if (wait)
 196                 pcie_wait_cmd(ctrl);
 197
 198 out:
 199         mutex_unlock(&ctrl->ctrl_lock);
 200 }
 201
 202 /**
 203  * pcie_write_cmd - Issue controller command
 204  * @ctrl: controller to which the command is issued
 205  * @cmd:  command value written to slot control register
 206  * @mask: bitmask of slot control register to be modified
 207  */
 208 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 209 {
 210         pcie_do_write_cmd(ctrl, cmd, mask, true);
 211 }
 212
 213 /* Same as above without waiting for the hardware to latch */
 214 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
 215 {
 216         pcie_do_write_cmd(ctrl, cmd, mask, false);
 217 }
 218
 219 bool pciehp_check_link_active(struct controller *ctrl)
 220 {
 221         struct pci_dev *pdev = ctrl_dev(ctrl);
 222         u16 lnk_status;
 223         bool ret;
 224
 225         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 226         ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
 227
 228         if (ret)
 229                 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 230
 231         return ret;
 232 }
 233
 234 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
 235 {
 236         int timeout = 1000;
 237
 238         if (pciehp_check_link_active(ctrl) == active)
 239                 return;
 240         while (timeout > 0) {
 241                 msleep(10);
 242                 timeout -= 10;
 243                 if (pciehp_check_link_active(ctrl) == active)
 244                         return;
 245         }
 246         ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
 247                         active ? "set" : "cleared");
 248 }
 249
 250 static void pcie_wait_link_active(struct controller *ctrl)
 251 {
 252         __pcie_wait_link_active(ctrl, true);
 253 }
 254
 255 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
 256 {
 257         u32 l;
 258         int count = 0;
 259         int delay = 1000, step = 20;
 260         bool found = false;
 261
 262         do {
 263                 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
 264                 count++;
 265
 266                 if (found)
 267                         break;
 268
 269                 msleep(step);
 270                 delay -= step;
 271         } while (delay > 0);
 272
 273         if (count > 1 && pciehp_debug)
 274                 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
 275                         pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
 276                         PCI_FUNC(devfn), count, step, l);
 277
 278         return found;
 279 }
 280
 281 int pciehp_check_link_status(struct controller *ctrl)
 282 {
 283         struct pci_dev *pdev = ctrl_dev(ctrl);
 284         bool found;
 285         u16 lnk_status;
 286
 287         /*
 288          * Data Link Layer Link Active Reporting must be capable for
 289          * hot-plug capable downstream port. But old controller might
 290          * not implement it. In this case, we wait for 1000 ms.
 291         */
 292         if (ctrl->link_active_reporting)
 293                 pcie_wait_link_active(ctrl);
 294         else
 295                 msleep(1000);
 296
 297         /* wait 100ms before read pci conf, and try in 1s */
 298         msleep(100);
 299         found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
 300                                         PCI_DEVFN(0, 0));
 301
 302         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 303         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 304         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 305             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 306                 ctrl_err(ctrl, "link training error: status %#06x\n",
 307                          lnk_status);
 308                 return -1;
 309         }
 310
 311         pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 312
 313         if (!found)
 314                 return -1;
 315
 316         return 0;
 317 }
 318
 319 static int __pciehp_link_set(struct controller *ctrl, bool enable)
 320 {
 321         struct pci_dev *pdev = ctrl_dev(ctrl);
 322         u16 lnk_ctrl;
 323
 324         pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
 325
 326         if (enable)
 327                 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
 328         else
 329                 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
 330
 331         pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
 332         ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
 333         return 0;
 334 }
 335
 336 static int pciehp_link_enable(struct controller *ctrl)
 337 {
 338         return __pciehp_link_set(ctrl, true);
 339 }
 340
 341 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
 342                                     u8 *status)
 343 {
 344         struct slot *slot = hotplug_slot->private;
 345         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 346         u16 slot_ctrl;
 347
 348         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 349         *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
 350         return 0;
 351 }
 352
 353 void pciehp_get_attention_status(struct slot *slot, u8 *status)
 354 {
 355         struct controller *ctrl = slot->ctrl;
 356         struct pci_dev *pdev = ctrl_dev(ctrl);
 357         u16 slot_ctrl;
 358
 359         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 360         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 361                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 362
 363         switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
 364         case PCI_EXP_SLTCTL_ATTN_IND_ON:
 365                 *status = 1;    /* On */
 366                 break;
 367         case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
 368                 *status = 2;    /* Blink */
 369                 break;
 370         case PCI_EXP_SLTCTL_ATTN_IND_OFF:
 371                 *status = 0;    /* Off */
 372                 break;
 373         default:
 374                 *status = 0xFF;
 375                 break;
 376         }
 377 }
 378
 379 void pciehp_get_power_status(struct slot *slot, u8 *status)
 380 {
 381         struct controller *ctrl = slot->ctrl;
 382         struct pci_dev *pdev = ctrl_dev(ctrl);
 383         u16 slot_ctrl;
 384
 385         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 386         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 387                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 388
 389         switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
 390         case PCI_EXP_SLTCTL_PWR_ON:
 391                 *status = 1;    /* On */
 392                 break;
 393         case PCI_EXP_SLTCTL_PWR_OFF:
 394                 *status = 0;    /* Off */
 395                 break;
 396         default:
 397                 *status = 0xFF;
 398                 break;
 399         }
 400 }
 401
 402 void pciehp_get_latch_status(struct slot *slot, u8 *status)
 403 {
 404         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 405         u16 slot_status;
 406
 407         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 408         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 409 }
 410
 411 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
 412 {
 413         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 414         u16 slot_status;
 415
 416         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 417         *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
 418 }
 419
 420 int pciehp_query_power_fault(struct slot *slot)
 421 {
 422         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 423         u16 slot_status;
 424
 425         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 426         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 427 }
 428
 429 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
 430                                     u8 status)
 431 {
 432         struct slot *slot = hotplug_slot->private;
 433         struct controller *ctrl = slot->ctrl;
 434
 435         pcie_write_cmd_nowait(ctrl, status << 6,
 436                               PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
 437         return 0;
 438 }
 439
 440 void pciehp_set_attention_status(struct slot *slot, u8 value)
 441 {
 442         struct controller *ctrl = slot->ctrl;
 443         u16 slot_cmd;
 444
 445         if (!ATTN_LED(ctrl))
 446                 return;
 447
 448         switch (value) {
 449         case 0:         /* turn off */
 450                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
 451                 break;
 452         case 1:         /* turn on */
 453                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
 454                 break;
 455         case 2:         /* turn blink */
 456                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
 457                 break;
 458         default:
 459                 return;
 460         }
 461         pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
 462         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 463                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 464 }
 465
 466 void pciehp_green_led_on(struct slot *slot)
 467 {
 468         struct controller *ctrl = slot->ctrl;
 469
 470         if (!PWR_LED(ctrl))
 471                 return;
 472
 473         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
 474                               PCI_EXP_SLTCTL_PIC);
 475         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 476                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 477                  PCI_EXP_SLTCTL_PWR_IND_ON);
 478 }
 479
 480 void pciehp_green_led_off(struct slot *slot)
 481 {
 482         struct controller *ctrl = slot->ctrl;
 483
 484         if (!PWR_LED(ctrl))
 485                 return;
 486
 487         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
 488                               PCI_EXP_SLTCTL_PIC);
 489         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 490                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 491                  PCI_EXP_SLTCTL_PWR_IND_OFF);
 492 }
 493
 494 void pciehp_green_led_blink(struct slot *slot)
 495 {
 496         struct controller *ctrl = slot->ctrl;
 497
 498         if (!PWR_LED(ctrl))
 499                 return;
 500
 501         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
 502                               PCI_EXP_SLTCTL_PIC);
 503         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 504                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 505                  PCI_EXP_SLTCTL_PWR_IND_BLINK);
 506 }
 507
 508 int pciehp_power_on_slot(struct slot *slot)
 509 {
 510         struct controller *ctrl = slot->ctrl;
 511         struct pci_dev *pdev = ctrl_dev(ctrl);
 512         u16 slot_status;
 513         int retval;
 514
 515         /* Clear sticky power-fault bit from previous power failures */
 516         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 517         if (slot_status & PCI_EXP_SLTSTA_PFD)
 518                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 519                                            PCI_EXP_SLTSTA_PFD);
 520         ctrl->power_fault_detected = 0;
 521
 522         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
 523         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 524                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 525                  PCI_EXP_SLTCTL_PWR_ON);
 526
 527         retval = pciehp_link_enable(ctrl);
 528         if (retval)
 529                 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
 530
 531         return retval;
 532 }
 533
 534 void pciehp_power_off_slot(struct slot *slot)
 535 {
 536         struct controller *ctrl = slot->ctrl;
 537
 538         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
 539         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 540                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 541                  PCI_EXP_SLTCTL_PWR_OFF);
 542 }
 543
 544 static irqreturn_t pciehp_isr(int irq, void *dev_id)
 545 {
 546         struct controller *ctrl = (struct controller *)dev_id;
 547         struct pci_dev *pdev = ctrl_dev(ctrl);
 548         struct pci_bus *subordinate = pdev->subordinate;
 549         struct pci_dev *dev;
 550         struct slot *slot = ctrl->slot;
 551         u16 status, events;
 552         u8 present;
 553         bool link;
 554
 555         /* Interrupts cannot originate from a controller that's asleep */
 556         if (pdev->current_state == PCI_D3cold)
 557                 return IRQ_NONE;
 558
 559         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
 560         if (status == (u16) ~0) {
 561                 ctrl_info(ctrl, "%s: no response from device\n", __func__);
 562                 return IRQ_NONE;
 563         }
 564
 565         /*
 566          * Slot Status contains plain status bits as well as event
 567          * notification bits; right now we only want the event bits.
 568          */
 569         events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 570                            PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
 571                            PCI_EXP_SLTSTA_DLLSC);
 572
 573         /*
 574          * If we've already reported a power fault, don't report it again
 575          * until we've done something to handle it.
 576          */
 577         if (ctrl->power_fault_detected)
 578                 events &= ~PCI_EXP_SLTSTA_PFD;
 579
 580         if (!events)
 581                 return IRQ_NONE;
 582
 583         /* Capture link status before clearing interrupts */
 584         if (events & PCI_EXP_SLTSTA_DLLSC)
 585                 link = pciehp_check_link_active(ctrl);
 586
 587         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
 588         ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
 589
 590         /* Check Command Complete Interrupt Pending */
 591         if (events & PCI_EXP_SLTSTA_CC) {
 592                 ctrl->cmd_busy = 0;
 593                 smp_mb();
 594                 wake_up(&ctrl->queue);
 595         }
 596
 597         if (subordinate) {
 598                 list_for_each_entry(dev, &subordinate->devices, bus_list) {
 599                         if (dev->ignore_hotplug) {
 600                                 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
 601                                          events, pci_name(dev));
 602                                 return IRQ_HANDLED;
 603                         }
 604                 }
 605         }
 606
 607         /* Check Attention Button Pressed */
 608         if (events & PCI_EXP_SLTSTA_ABP) {
 609                 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
 610                           slot_name(slot));
 611                 pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS);
 612         }
 613
 614         /*
 615          * Check Link Status Changed at higher precedence than Presence
 616          * Detect Changed.  The PDS value may be set to "card present" from
 617          * out-of-band detection, which may be in conflict with a Link Down
 618          * and cause the wrong event to queue.
 619          */
 620         if (events & PCI_EXP_SLTSTA_DLLSC) {
 621                 ctrl_info(ctrl, "Slot(%s): Link %s\n", slot_name(slot),
 622                           link ? "Up" : "Down");
 623                 pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP :
 624                                              INT_LINK_DOWN);
 625         } else if (events & PCI_EXP_SLTSTA_PDC) {
 626                 present = !!(status & PCI_EXP_SLTSTA_PDS);
 627                 ctrl_info(ctrl, "Slot(%s): Card %spresent\n", slot_name(slot),
 628                           present ? "" : "not ");
 629                 pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON :
 630                                              INT_PRESENCE_OFF);
 631         }
 632
 633         /* Check Power Fault Detected */
 634         if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 635                 ctrl->power_fault_detected = 1;
 636                 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
 637                 pciehp_queue_interrupt_event(slot, INT_POWER_FAULT);
 638         }
 639
 640         return IRQ_HANDLED;
 641 }
 642
 643 static irqreturn_t pcie_isr(int irq, void *dev_id)
 644 {
 645         irqreturn_t rc, handled = IRQ_NONE;
 646
 647         /*
 648          * To guarantee that all interrupt events are serviced, we need to
 649          * re-inspect Slot Status register after clearing what is presumed
 650          * to be the last pending interrupt.
 651          */
 652         do {
 653                 rc = pciehp_isr(irq, dev_id);
 654                 if (rc == IRQ_HANDLED)
 655                         handled = IRQ_HANDLED;
 656         } while (rc == IRQ_HANDLED);
 657
 658         /* Return IRQ_HANDLED if we handled one or more events */
 659         return handled;
 660 }
 661
 662 void pcie_enable_notification(struct controller *ctrl)
 663 {
 664         u16 cmd, mask;
 665
 666         /*
 667          * TBD: Power fault detected software notification support.
 668          *
 669          * Power fault detected software notification is not enabled
 670          * now, because it caused power fault detected interrupt storm
 671          * on some machines. On those machines, power fault detected
 672          * bit in the slot status register was set again immediately
 673          * when it is cleared in the interrupt service routine, and
 674          * next power fault detected interrupt was notified again.
 675          */
 676
 677         /*
 678          * Always enable link events: thus link-up and link-down shall
 679          * always be treated as hotplug and unplug respectively. Enable
 680          * presence detect only if Attention Button is not present.
 681          */
 682         cmd = PCI_EXP_SLTCTL_DLLSCE;
 683         if (ATTN_BUTTN(ctrl))
 684                 cmd |= PCI_EXP_SLTCTL_ABPE;
 685         else
 686                 cmd |= PCI_EXP_SLTCTL_PDCE;
 687         if (!pciehp_poll_mode)
 688                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 689
 690         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 691                 PCI_EXP_SLTCTL_PFDE |
 692                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 693                 PCI_EXP_SLTCTL_DLLSCE);
 694
 695         pcie_write_cmd_nowait(ctrl, cmd, mask);
 696         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 697                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
 698 }
 699
 700 static void pcie_disable_notification(struct controller *ctrl)
 701 {
 702         u16 mask;
 703
 704         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 705                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 706                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 707                 PCI_EXP_SLTCTL_DLLSCE);
 708         pcie_write_cmd(ctrl, 0, mask);
 709         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 710                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 711 }
 712
 713 /*
 714  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
 715  * bus reset of the bridge, but at the same time we want to ensure that it is
 716  * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
 717  * disable link state notification and presence detection change notification
 718  * momentarily, if we see that they could interfere. Also, clear any spurious
 719  * events after.
 720  */
 721 int pciehp_reset_slot(struct slot *slot, int probe)
 722 {
 723         struct controller *ctrl = slot->ctrl;
 724         struct pci_dev *pdev = ctrl_dev(ctrl);
 725         u16 stat_mask = 0, ctrl_mask = 0;
 726
 727         if (probe)
 728                 return 0;
 729
 730         if (!ATTN_BUTTN(ctrl)) {
 731                 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
 732                 stat_mask |= PCI_EXP_SLTSTA_PDC;
 733         }
 734         ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
 735         stat_mask |= PCI_EXP_SLTSTA_DLLSC;
 736
 737         pcie_write_cmd(ctrl, 0, ctrl_mask);
 738         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 739                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 740         if (pciehp_poll_mode)
 741                 del_timer_sync(&ctrl->poll_timer);
 742
 743         pci_reset_bridge_secondary_bus(ctrl->pcie->port);
 744
 745         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
 746         pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
 747         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 748                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
 749         if (pciehp_poll_mode)
 750                 int_poll_timeout(&ctrl->poll_timer);
 751         return 0;
 752 }
 753
 754 int pcie_init_notification(struct controller *ctrl)
 755 {
 756         if (pciehp_request_irq(ctrl))
 757                 return -1;
 758         pcie_enable_notification(ctrl);
 759         ctrl->notification_enabled = 1;
 760         return 0;
 761 }
 762
 763 static void pcie_shutdown_notification(struct controller *ctrl)
 764 {
 765         if (ctrl->notification_enabled) {
 766                 pcie_disable_notification(ctrl);
 767                 pciehp_free_irq(ctrl);
 768                 ctrl->notification_enabled = 0;
 769         }
 770 }
 771
 772 static int pcie_init_slot(struct controller *ctrl)
 773 {
 774         struct slot *slot;
 775
 776         slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 777         if (!slot)
 778                 return -ENOMEM;
 779
 780         slot->wq = alloc_ordered_workqueue("pciehp-%u", 0, PSN(ctrl));
 781         if (!slot->wq)
 782                 goto abort;
 783
 784         slot->ctrl = ctrl;
 785         mutex_init(&slot->lock);
 786         mutex_init(&slot->hotplug_lock);
 787         INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
 788         ctrl->slot = slot;
 789         return 0;
 790 abort:
 791         kfree(slot);
 792         return -ENOMEM;
 793 }
 794
 795 static void pcie_cleanup_slot(struct controller *ctrl)
 796 {
 797         struct slot *slot = ctrl->slot;
 798         cancel_delayed_work(&slot->work);
 799         destroy_workqueue(slot->wq);
 800         kfree(slot);
 801 }
 802
 803 static inline void dbg_ctrl(struct controller *ctrl)
 804 {
 805         struct pci_dev *pdev = ctrl->pcie->port;
 806         u16 reg16;
 807
 808         if (!pciehp_debug)
 809                 return;
 810
 811         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 812         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
 813         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
 814         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
 815         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
 816 }
 817
 818 #define FLAG(x, y)      (((x) & (y)) ? '+' : '-')
 819
 820 struct controller *pcie_init(struct pcie_device *dev)
 821 {
 822         struct controller *ctrl;
 823         u32 slot_cap, link_cap;
 824         struct pci_dev *pdev = dev->port;
 825
 826         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 827         if (!ctrl)
 828                 goto abort;
 829
 830         ctrl->pcie = dev;
 831         pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 832
 833         if (pdev->hotplug_user_indicators)
 834                 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
 835
 836         /*
 837          * We assume no Thunderbolt controllers support Command Complete events,
 838          * but some controllers falsely claim they do.
 839          */
 840         if (pdev->is_thunderbolt)
 841                 slot_cap |= PCI_EXP_SLTCAP_NCCS;
 842
 843         ctrl->slot_cap = slot_cap;
 844         mutex_init(&ctrl->ctrl_lock);
 845         init_waitqueue_head(&ctrl->queue);
 846         dbg_ctrl(ctrl);
 847
 848         /* Check if Data Link Layer Link Active Reporting is implemented */
 849         pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
 850         if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
 851                 ctrl->link_active_reporting = 1;
 852
 853         /*
 854          * Clear all remaining event bits in Slot Status register except
 855          * Presence Detect Changed. We want to make sure possible
 856          * hotplug event is triggered when the interrupt is unmasked so
 857          * that we don't lose that event.
 858          */
 859         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 860                 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 861                 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
 862                 PCI_EXP_SLTSTA_DLLSC);
 863
 864         ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
 865                 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
 866                 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
 867                 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
 868                 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
 869                 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
 870                 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
 871                 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
 872                 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
 873                 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
 874                 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
 875                 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
 876
 877         if (pcie_init_slot(ctrl))
 878                 goto abort_ctrl;
 879
 880         return ctrl;
 881
 882 abort_ctrl:
 883         kfree(ctrl);
 884 abort:
 885         return NULL;
 886 }
 887
 888 void pciehp_release_ctrl(struct controller *ctrl)
 889 {
 890         pcie_shutdown_notification(ctrl);
 891         pcie_cleanup_slot(ctrl);
 892         kfree(ctrl);
 893 }