1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * 2011 - 2014 (C) Xilinx Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16 #include <linux/platform_device.h>
17 #include <linux/serial.h>
18 #include <linux/console.h>
19 #include <linux/serial_core.h>
20 #include <linux/slab.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/clk.h>
24 #include <linux/irq.h>
27 #include <linux/module.h>
28 #include <linux/pm_runtime.h>
30 #define CDNS_UART_TTY_NAME "ttyPS"
31 #define CDNS_UART_NAME "xuartps"
32 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
33 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
34 #define CDNS_UART_NR_PORTS 2
35 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
36 #define CDNS_UART_REGISTER_SPACE 0x1000
38 /* Rx Trigger level */
39 static int rx_trigger_level
= 56;
40 module_param(rx_trigger_level
, uint
, S_IRUGO
);
41 MODULE_PARM_DESC(rx_trigger_level
, "Rx trigger level, 1-63 bytes");
44 static int rx_timeout
= 10;
45 module_param(rx_timeout
, uint
, S_IRUGO
);
46 MODULE_PARM_DESC(rx_timeout
, "Rx timeout, 1-255");
48 /* Register offsets for the UART. */
49 #define CDNS_UART_CR 0x00 /* Control Register */
50 #define CDNS_UART_MR 0x04 /* Mode Register */
51 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
52 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
53 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
54 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
55 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
56 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
57 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
58 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
59 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
60 #define CDNS_UART_SR 0x2C /* Channel Status */
61 #define CDNS_UART_FIFO 0x30 /* FIFO */
62 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
63 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
64 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
65 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
66 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
67 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
69 /* Control Register Bit Definitions */
70 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
71 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
72 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
73 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
74 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
75 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
76 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
77 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
78 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
79 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
80 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
81 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
89 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
94 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
95 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
97 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
98 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
99 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
100 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
101 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
103 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
104 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
105 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
108 * Interrupt Registers:
109 * Interrupt control logic uses the interrupt enable register (IER) and the
110 * interrupt disable register (IDR) to set the value of the bits in the
111 * interrupt mask register (IMR). The IMR determines whether to pass an
112 * interrupt to the interrupt status register (ISR).
113 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
114 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
115 * Reading either IER or IDR returns 0x00.
116 * All four registers have the same bit definitions.
118 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
119 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
120 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
121 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
122 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
123 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
124 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
125 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
126 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
127 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
128 #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
131 * Do not enable parity error interrupt for the following
132 * reason: When parity error interrupt is enabled, each Rx
133 * parity error always results in 2 events. The first one
134 * being parity error interrupt and the second one with a
135 * proper Rx interrupt with the incoming data. Disabling
136 * parity error interrupt ensures better handling of parity
137 * error events. With this change, for a parity error case, we
138 * get a Rx interrupt with parity error set in ISR register
139 * and we still handle parity errors in the desired way.
142 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
143 CDNS_UART_IXR_OVERRUN | \
144 CDNS_UART_IXR_RXTRIG | \
147 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
148 #define CDNS_UART_IXR_BRK 0x00002000
150 #define CDNS_UART_RXBS_SUPPORT BIT(1)
152 * Modem Control register:
153 * The read/write Modem Control register controls the interface with the modem
154 * or data set, or a peripheral device emulating a modem.
156 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
157 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
158 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
161 * Channel Status Register:
162 * The channel status register (CSR) is provided to enable the control logic
163 * to monitor the status of bits in the channel interrupt status register,
164 * even if these are masked out by the interrupt mask register.
166 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
167 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
168 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
169 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
171 /* baud dividers min/max values */
172 #define CDNS_UART_BDIV_MIN 4
173 #define CDNS_UART_BDIV_MAX 255
174 #define CDNS_UART_CD_MAX 65535
175 #define UART_AUTOSUSPEND_TIMEOUT 3000
178 * struct cdns_uart - device data
179 * @port: Pointer to the UART port
180 * @uartclk: Reference clock
182 * @baud: Current baud rate
183 * @clk_rate_change_nb: Notifier block for clock changes
184 * @quirks: Flags for RXBS support.
187 struct uart_port
*port
;
191 struct notifier_block clk_rate_change_nb
;
194 struct cdns_platform_data
{
197 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
201 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
202 * @dev_id: Id of the UART port
203 * @isrstatus: The interrupt status register value as read
206 static void cdns_uart_handle_rx(void *dev_id
, unsigned int isrstatus
)
208 struct uart_port
*port
= (struct uart_port
*)dev_id
;
209 struct cdns_uart
*cdns_uart
= port
->private_data
;
211 unsigned int rxbs_status
= 0;
212 unsigned int status_mask
;
213 unsigned int framerrprocessed
= 0;
214 char status
= TTY_NORMAL
;
215 bool is_rxbs_support
;
217 is_rxbs_support
= cdns_uart
->quirks
& CDNS_UART_RXBS_SUPPORT
;
219 while ((readl(port
->membase
+ CDNS_UART_SR
) &
220 CDNS_UART_SR_RXEMPTY
) != CDNS_UART_SR_RXEMPTY
) {
222 rxbs_status
= readl(port
->membase
+ CDNS_UART_RXBS
);
223 data
= readl(port
->membase
+ CDNS_UART_FIFO
);
226 * There is no hardware break detection in Zynq, so we interpret
227 * framing error with all-zeros data as a break sequence.
228 * Most of the time, there's another non-zero byte at the
229 * end of the sequence.
231 if (!is_rxbs_support
&& (isrstatus
& CDNS_UART_IXR_FRAMING
)) {
233 port
->read_status_mask
|= CDNS_UART_IXR_BRK
;
234 framerrprocessed
= 1;
238 if (is_rxbs_support
&& (rxbs_status
& CDNS_UART_RXBS_BRK
)) {
241 if (uart_handle_break(port
))
245 isrstatus
&= port
->read_status_mask
;
246 isrstatus
&= ~port
->ignore_status_mask
;
247 status_mask
= port
->read_status_mask
;
248 status_mask
&= ~port
->ignore_status_mask
;
251 (port
->read_status_mask
& CDNS_UART_IXR_BRK
)) {
252 port
->read_status_mask
&= ~CDNS_UART_IXR_BRK
;
254 if (uart_handle_break(port
))
258 if (uart_handle_sysrq_char(port
, data
))
261 if (is_rxbs_support
) {
262 if ((rxbs_status
& CDNS_UART_RXBS_PARITY
)
263 && (status_mask
& CDNS_UART_IXR_PARITY
)) {
264 port
->icount
.parity
++;
267 if ((rxbs_status
& CDNS_UART_RXBS_FRAMING
)
268 && (status_mask
& CDNS_UART_IXR_PARITY
)) {
269 port
->icount
.frame
++;
273 if (isrstatus
& CDNS_UART_IXR_PARITY
) {
274 port
->icount
.parity
++;
277 if ((isrstatus
& CDNS_UART_IXR_FRAMING
) &&
279 port
->icount
.frame
++;
283 if (isrstatus
& CDNS_UART_IXR_OVERRUN
) {
284 port
->icount
.overrun
++;
285 tty_insert_flip_char(&port
->state
->port
, 0,
288 tty_insert_flip_char(&port
->state
->port
, data
, status
);
291 spin_unlock(&port
->lock
);
292 tty_flip_buffer_push(&port
->state
->port
);
293 spin_lock(&port
->lock
);
297 * cdns_uart_handle_tx - Handle the bytes to be Txed.
298 * @dev_id: Id of the UART port
301 static void cdns_uart_handle_tx(void *dev_id
)
303 struct uart_port
*port
= (struct uart_port
*)dev_id
;
304 unsigned int numbytes
;
306 if (uart_circ_empty(&port
->state
->xmit
)) {
307 writel(CDNS_UART_IXR_TXEMPTY
, port
->membase
+ CDNS_UART_IDR
);
309 numbytes
= port
->fifosize
;
310 while (numbytes
&& !uart_circ_empty(&port
->state
->xmit
) &&
311 !(readl(port
->membase
+ CDNS_UART_SR
) & CDNS_UART_SR_TXFULL
)) {
313 * Get the data from the UART circular buffer
314 * and write it to the cdns_uart's TX_FIFO
318 port
->state
->xmit
.buf
[port
->state
->xmit
.
319 tail
], port
->membase
+ CDNS_UART_FIFO
);
324 * Adjust the tail of the UART buffer and wrap
325 * the buffer if it reaches limit.
327 port
->state
->xmit
.tail
=
328 (port
->state
->xmit
.tail
+ 1) &
329 (UART_XMIT_SIZE
- 1);
334 if (uart_circ_chars_pending(
335 &port
->state
->xmit
) < WAKEUP_CHARS
)
336 uart_write_wakeup(port
);
341 * cdns_uart_isr - Interrupt handler
343 * @dev_id: Id of the port
347 static irqreturn_t
cdns_uart_isr(int irq
, void *dev_id
)
349 struct uart_port
*port
= (struct uart_port
*)dev_id
;
350 unsigned int isrstatus
;
352 spin_lock(&port
->lock
);
354 /* Read the interrupt status register to determine which
355 * interrupt(s) is/are active and clear them.
357 isrstatus
= readl(port
->membase
+ CDNS_UART_ISR
);
358 writel(isrstatus
, port
->membase
+ CDNS_UART_ISR
);
360 if (isrstatus
& CDNS_UART_IXR_TXEMPTY
) {
361 cdns_uart_handle_tx(dev_id
);
362 isrstatus
&= ~CDNS_UART_IXR_TXEMPTY
;
364 if (isrstatus
& CDNS_UART_IXR_MASK
)
365 cdns_uart_handle_rx(dev_id
, isrstatus
);
367 spin_unlock(&port
->lock
);
372 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
373 * @clk: UART module input clock
374 * @baud: Desired baud rate
375 * @rbdiv: BDIV value (return value)
376 * @rcd: CD value (return value)
377 * @div8: Value for clk_sel bit in mod (return value)
378 * Return: baud rate, requested baud when possible, or actual baud when there
379 * was too much error, zero if no valid divisors are found.
381 * Formula to obtain baud rate is
382 * baud_tx/rx rate = clk/CD * (BDIV + 1)
383 * input_clk = (Uart User Defined Clock or Apb Clock)
384 * depends on UCLKEN in MR Reg
385 * clk = input_clk or input_clk/8;
386 * depends on CLKS in MR reg
387 * CD and BDIV depends on values in
388 * baud rate generate register
389 * baud rate clock divisor register
391 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk
,
392 unsigned int baud
, u32
*rbdiv
, u32
*rcd
, int *div8
)
395 unsigned int calc_baud
;
396 unsigned int bestbaud
= 0;
397 unsigned int bauderror
;
398 unsigned int besterror
= ~0;
400 if (baud
< clk
/ ((CDNS_UART_BDIV_MAX
+ 1) * CDNS_UART_CD_MAX
)) {
407 for (bdiv
= CDNS_UART_BDIV_MIN
; bdiv
<= CDNS_UART_BDIV_MAX
; bdiv
++) {
408 cd
= DIV_ROUND_CLOSEST(clk
, baud
* (bdiv
+ 1));
409 if (cd
< 1 || cd
> CDNS_UART_CD_MAX
)
412 calc_baud
= clk
/ (cd
* (bdiv
+ 1));
414 if (baud
> calc_baud
)
415 bauderror
= baud
- calc_baud
;
417 bauderror
= calc_baud
- baud
;
419 if (besterror
> bauderror
) {
422 bestbaud
= calc_baud
;
423 besterror
= bauderror
;
426 /* use the values when percent error is acceptable */
427 if (((besterror
* 100) / baud
) < 3)
434 * cdns_uart_set_baud_rate - Calculate and set the baud rate
435 * @port: Handle to the uart port structure
436 * @baud: Baud rate to set
437 * Return: baud rate, requested baud when possible, or actual baud when there
438 * was too much error, zero if no valid divisors are found.
440 static unsigned int cdns_uart_set_baud_rate(struct uart_port
*port
,
443 unsigned int calc_baud
;
444 u32 cd
= 0, bdiv
= 0;
447 struct cdns_uart
*cdns_uart
= port
->private_data
;
449 calc_baud
= cdns_uart_calc_baud_divs(port
->uartclk
, baud
, &bdiv
, &cd
,
452 /* Write new divisors to hardware */
453 mreg
= readl(port
->membase
+ CDNS_UART_MR
);
455 mreg
|= CDNS_UART_MR_CLKSEL
;
457 mreg
&= ~CDNS_UART_MR_CLKSEL
;
458 writel(mreg
, port
->membase
+ CDNS_UART_MR
);
459 writel(cd
, port
->membase
+ CDNS_UART_BAUDGEN
);
460 writel(bdiv
, port
->membase
+ CDNS_UART_BAUDDIV
);
461 cdns_uart
->baud
= baud
;
466 #ifdef CONFIG_COMMON_CLK
468 * cdns_uart_clk_notitifer_cb - Clock notifier callback
469 * @nb: Notifier block
470 * @event: Notify event
471 * @data: Notifier data
472 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
474 static int cdns_uart_clk_notifier_cb(struct notifier_block
*nb
,
475 unsigned long event
, void *data
)
478 struct uart_port
*port
;
480 struct clk_notifier_data
*ndata
= data
;
481 unsigned long flags
= 0;
482 struct cdns_uart
*cdns_uart
= to_cdns_uart(nb
);
484 port
= cdns_uart
->port
;
489 case PRE_RATE_CHANGE
:
495 * Find out if current baud-rate can be achieved with new clock
498 if (!cdns_uart_calc_baud_divs(ndata
->new_rate
, cdns_uart
->baud
,
499 &bdiv
, &cd
, &div8
)) {
500 dev_warn(port
->dev
, "clock rate change rejected\n");
504 spin_lock_irqsave(&cdns_uart
->port
->lock
, flags
);
506 /* Disable the TX and RX to set baud rate */
507 ctrl_reg
= readl(port
->membase
+ CDNS_UART_CR
);
508 ctrl_reg
|= CDNS_UART_CR_TX_DIS
| CDNS_UART_CR_RX_DIS
;
509 writel(ctrl_reg
, port
->membase
+ CDNS_UART_CR
);
511 spin_unlock_irqrestore(&cdns_uart
->port
->lock
, flags
);
515 case POST_RATE_CHANGE
:
517 * Set clk dividers to generate correct baud with new clock
521 spin_lock_irqsave(&cdns_uart
->port
->lock
, flags
);
524 port
->uartclk
= ndata
->new_rate
;
526 cdns_uart
->baud
= cdns_uart_set_baud_rate(cdns_uart
->port
,
529 case ABORT_RATE_CHANGE
:
531 spin_lock_irqsave(&cdns_uart
->port
->lock
, flags
);
533 /* Set TX/RX Reset */
534 ctrl_reg
= readl(port
->membase
+ CDNS_UART_CR
);
535 ctrl_reg
|= CDNS_UART_CR_TXRST
| CDNS_UART_CR_RXRST
;
536 writel(ctrl_reg
, port
->membase
+ CDNS_UART_CR
);
538 while (readl(port
->membase
+ CDNS_UART_CR
) &
539 (CDNS_UART_CR_TXRST
| CDNS_UART_CR_RXRST
))
543 * Clear the RX disable and TX disable bits and then set the TX
544 * enable bit and RX enable bit to enable the transmitter and
547 writel(rx_timeout
, port
->membase
+ CDNS_UART_RXTOUT
);
548 ctrl_reg
= readl(port
->membase
+ CDNS_UART_CR
);
549 ctrl_reg
&= ~(CDNS_UART_CR_TX_DIS
| CDNS_UART_CR_RX_DIS
);
550 ctrl_reg
|= CDNS_UART_CR_TX_EN
| CDNS_UART_CR_RX_EN
;
551 writel(ctrl_reg
, port
->membase
+ CDNS_UART_CR
);
553 spin_unlock_irqrestore(&cdns_uart
->port
->lock
, flags
);
563 * cdns_uart_start_tx - Start transmitting bytes
564 * @port: Handle to the uart port structure
566 static void cdns_uart_start_tx(struct uart_port
*port
)
570 if (uart_tx_stopped(port
))
574 * Set the TX enable bit and clear the TX disable bit to enable the
577 status
= readl(port
->membase
+ CDNS_UART_CR
);
578 status
&= ~CDNS_UART_CR_TX_DIS
;
579 status
|= CDNS_UART_CR_TX_EN
;
580 writel(status
, port
->membase
+ CDNS_UART_CR
);
582 if (uart_circ_empty(&port
->state
->xmit
))
585 cdns_uart_handle_tx(port
);
587 writel(CDNS_UART_IXR_TXEMPTY
, port
->membase
+ CDNS_UART_ISR
);
588 /* Enable the TX Empty interrupt */
589 writel(CDNS_UART_IXR_TXEMPTY
, port
->membase
+ CDNS_UART_IER
);
593 * cdns_uart_stop_tx - Stop TX
594 * @port: Handle to the uart port structure
596 static void cdns_uart_stop_tx(struct uart_port
*port
)
600 regval
= readl(port
->membase
+ CDNS_UART_CR
);
601 regval
|= CDNS_UART_CR_TX_DIS
;
602 /* Disable the transmitter */
603 writel(regval
, port
->membase
+ CDNS_UART_CR
);
607 * cdns_uart_stop_rx - Stop RX
608 * @port: Handle to the uart port structure
610 static void cdns_uart_stop_rx(struct uart_port
*port
)
614 /* Disable RX IRQs */
615 writel(CDNS_UART_RX_IRQS
, port
->membase
+ CDNS_UART_IDR
);
617 /* Disable the receiver */
618 regval
= readl(port
->membase
+ CDNS_UART_CR
);
619 regval
|= CDNS_UART_CR_RX_DIS
;
620 writel(regval
, port
->membase
+ CDNS_UART_CR
);
624 * cdns_uart_tx_empty - Check whether TX is empty
625 * @port: Handle to the uart port structure
627 * Return: TIOCSER_TEMT on success, 0 otherwise
629 static unsigned int cdns_uart_tx_empty(struct uart_port
*port
)
633 status
= readl(port
->membase
+ CDNS_UART_SR
) &
634 CDNS_UART_SR_TXEMPTY
;
635 return status
? TIOCSER_TEMT
: 0;
639 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
640 * transmitting char breaks
641 * @port: Handle to the uart port structure
642 * @ctl: Value based on which start or stop decision is taken
644 static void cdns_uart_break_ctl(struct uart_port
*port
, int ctl
)
649 spin_lock_irqsave(&port
->lock
, flags
);
651 status
= readl(port
->membase
+ CDNS_UART_CR
);
654 writel(CDNS_UART_CR_STARTBRK
| status
,
655 port
->membase
+ CDNS_UART_CR
);
657 if ((status
& CDNS_UART_CR_STOPBRK
) == 0)
658 writel(CDNS_UART_CR_STOPBRK
| status
,
659 port
->membase
+ CDNS_UART_CR
);
661 spin_unlock_irqrestore(&port
->lock
, flags
);
665 * cdns_uart_set_termios - termios operations, handling data length, parity,
666 * stop bits, flow control, baud rate
667 * @port: Handle to the uart port structure
668 * @termios: Handle to the input termios structure
669 * @old: Values of the previously saved termios structure
671 static void cdns_uart_set_termios(struct uart_port
*port
,
672 struct ktermios
*termios
, struct ktermios
*old
)
674 unsigned int cval
= 0;
675 unsigned int baud
, minbaud
, maxbaud
;
677 unsigned int ctrl_reg
, mode_reg
;
679 spin_lock_irqsave(&port
->lock
, flags
);
681 /* Wait for the transmit FIFO to empty before making changes */
682 if (!(readl(port
->membase
+ CDNS_UART_CR
) &
683 CDNS_UART_CR_TX_DIS
)) {
684 while (!(readl(port
->membase
+ CDNS_UART_SR
) &
685 CDNS_UART_SR_TXEMPTY
)) {
690 /* Disable the TX and RX to set baud rate */
691 ctrl_reg
= readl(port
->membase
+ CDNS_UART_CR
);
692 ctrl_reg
|= CDNS_UART_CR_TX_DIS
| CDNS_UART_CR_RX_DIS
;
693 writel(ctrl_reg
, port
->membase
+ CDNS_UART_CR
);
696 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
697 * min and max baud should be calculated here based on port->uartclk.
698 * this way we get a valid baud and can safely call set_baud()
700 minbaud
= port
->uartclk
/
701 ((CDNS_UART_BDIV_MAX
+ 1) * CDNS_UART_CD_MAX
* 8);
702 maxbaud
= port
->uartclk
/ (CDNS_UART_BDIV_MIN
+ 1);
703 baud
= uart_get_baud_rate(port
, termios
, old
, minbaud
, maxbaud
);
704 baud
= cdns_uart_set_baud_rate(port
, baud
);
705 if (tty_termios_baud_rate(termios
))
706 tty_termios_encode_baud_rate(termios
, baud
, baud
);
708 /* Update the per-port timeout. */
709 uart_update_timeout(port
, termios
->c_cflag
, baud
);
711 /* Set TX/RX Reset */
712 ctrl_reg
= readl(port
->membase
+ CDNS_UART_CR
);
713 ctrl_reg
|= CDNS_UART_CR_TXRST
| CDNS_UART_CR_RXRST
;
714 writel(ctrl_reg
, port
->membase
+ CDNS_UART_CR
);
716 while (readl(port
->membase
+ CDNS_UART_CR
) &
717 (CDNS_UART_CR_TXRST
| CDNS_UART_CR_RXRST
))
721 * Clear the RX disable and TX disable bits and then set the TX enable
722 * bit and RX enable bit to enable the transmitter and receiver.
724 ctrl_reg
= readl(port
->membase
+ CDNS_UART_CR
);
725 ctrl_reg
&= ~(CDNS_UART_CR_TX_DIS
| CDNS_UART_CR_RX_DIS
);
726 ctrl_reg
|= CDNS_UART_CR_TX_EN
| CDNS_UART_CR_RX_EN
;
727 writel(ctrl_reg
, port
->membase
+ CDNS_UART_CR
);
729 writel(rx_timeout
, port
->membase
+ CDNS_UART_RXTOUT
);
731 port
->read_status_mask
= CDNS_UART_IXR_TXEMPTY
| CDNS_UART_IXR_RXTRIG
|
732 CDNS_UART_IXR_OVERRUN
| CDNS_UART_IXR_TOUT
;
733 port
->ignore_status_mask
= 0;
735 if (termios
->c_iflag
& INPCK
)
736 port
->read_status_mask
|= CDNS_UART_IXR_PARITY
|
737 CDNS_UART_IXR_FRAMING
;
739 if (termios
->c_iflag
& IGNPAR
)
740 port
->ignore_status_mask
|= CDNS_UART_IXR_PARITY
|
741 CDNS_UART_IXR_FRAMING
| CDNS_UART_IXR_OVERRUN
;
743 /* ignore all characters if CREAD is not set */
744 if ((termios
->c_cflag
& CREAD
) == 0)
745 port
->ignore_status_mask
|= CDNS_UART_IXR_RXTRIG
|
746 CDNS_UART_IXR_TOUT
| CDNS_UART_IXR_PARITY
|
747 CDNS_UART_IXR_FRAMING
| CDNS_UART_IXR_OVERRUN
;
749 mode_reg
= readl(port
->membase
+ CDNS_UART_MR
);
751 /* Handling Data Size */
752 switch (termios
->c_cflag
& CSIZE
) {
754 cval
|= CDNS_UART_MR_CHARLEN_6_BIT
;
757 cval
|= CDNS_UART_MR_CHARLEN_7_BIT
;
761 cval
|= CDNS_UART_MR_CHARLEN_8_BIT
;
762 termios
->c_cflag
&= ~CSIZE
;
763 termios
->c_cflag
|= CS8
;
767 /* Handling Parity and Stop Bits length */
768 if (termios
->c_cflag
& CSTOPB
)
769 cval
|= CDNS_UART_MR_STOPMODE_2_BIT
; /* 2 STOP bits */
771 cval
|= CDNS_UART_MR_STOPMODE_1_BIT
; /* 1 STOP bit */
773 if (termios
->c_cflag
& PARENB
) {
774 /* Mark or Space parity */
775 if (termios
->c_cflag
& CMSPAR
) {
776 if (termios
->c_cflag
& PARODD
)
777 cval
|= CDNS_UART_MR_PARITY_MARK
;
779 cval
|= CDNS_UART_MR_PARITY_SPACE
;
781 if (termios
->c_cflag
& PARODD
)
782 cval
|= CDNS_UART_MR_PARITY_ODD
;
784 cval
|= CDNS_UART_MR_PARITY_EVEN
;
787 cval
|= CDNS_UART_MR_PARITY_NONE
;
789 cval
|= mode_reg
& 1;
790 writel(cval
, port
->membase
+ CDNS_UART_MR
);
792 spin_unlock_irqrestore(&port
->lock
, flags
);
796 * cdns_uart_startup - Called when an application opens a cdns_uart port
797 * @port: Handle to the uart port structure
799 * Return: 0 on success, negative errno otherwise
801 static int cdns_uart_startup(struct uart_port
*port
)
803 struct cdns_uart
*cdns_uart
= port
->private_data
;
807 unsigned int status
= 0;
809 is_brk_support
= cdns_uart
->quirks
& CDNS_UART_RXBS_SUPPORT
;
811 spin_lock_irqsave(&port
->lock
, flags
);
813 /* Disable the TX and RX */
814 writel(CDNS_UART_CR_TX_DIS
| CDNS_UART_CR_RX_DIS
,
815 port
->membase
+ CDNS_UART_CR
);
817 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
820 writel(CDNS_UART_CR_TXRST
| CDNS_UART_CR_RXRST
,
821 port
->membase
+ CDNS_UART_CR
);
823 while (readl(port
->membase
+ CDNS_UART_CR
) &
824 (CDNS_UART_CR_TXRST
| CDNS_UART_CR_RXRST
))
828 * Clear the RX disable bit and then set the RX enable bit to enable
831 status
= readl(port
->membase
+ CDNS_UART_CR
);
832 status
&= CDNS_UART_CR_RX_DIS
;
833 status
|= CDNS_UART_CR_RX_EN
;
834 writel(status
, port
->membase
+ CDNS_UART_CR
);
836 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
839 writel(CDNS_UART_MR_CHMODE_NORM
| CDNS_UART_MR_STOPMODE_1_BIT
840 | CDNS_UART_MR_PARITY_NONE
| CDNS_UART_MR_CHARLEN_8_BIT
,
841 port
->membase
+ CDNS_UART_MR
);
844 * Set the RX FIFO Trigger level to use most of the FIFO, but it
845 * can be tuned with a module parameter
847 writel(rx_trigger_level
, port
->membase
+ CDNS_UART_RXWM
);
850 * Receive Timeout register is enabled but it
851 * can be tuned with a module parameter
853 writel(rx_timeout
, port
->membase
+ CDNS_UART_RXTOUT
);
855 /* Clear out any pending interrupts before enabling them */
856 writel(readl(port
->membase
+ CDNS_UART_ISR
),
857 port
->membase
+ CDNS_UART_ISR
);
859 spin_unlock_irqrestore(&port
->lock
, flags
);
861 ret
= request_irq(port
->irq
, cdns_uart_isr
, 0, CDNS_UART_NAME
, port
);
863 dev_err(port
->dev
, "request_irq '%d' failed with %d\n",
868 /* Set the Interrupt Registers with desired interrupts */
870 writel(CDNS_UART_RX_IRQS
| CDNS_UART_IXR_BRK
,
871 port
->membase
+ CDNS_UART_IER
);
873 writel(CDNS_UART_RX_IRQS
, port
->membase
+ CDNS_UART_IER
);
879 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
880 * @port: Handle to the uart port structure
882 static void cdns_uart_shutdown(struct uart_port
*port
)
887 spin_lock_irqsave(&port
->lock
, flags
);
889 /* Disable interrupts */
890 status
= readl(port
->membase
+ CDNS_UART_IMR
);
891 writel(status
, port
->membase
+ CDNS_UART_IDR
);
892 writel(0xffffffff, port
->membase
+ CDNS_UART_ISR
);
894 /* Disable the TX and RX */
895 writel(CDNS_UART_CR_TX_DIS
| CDNS_UART_CR_RX_DIS
,
896 port
->membase
+ CDNS_UART_CR
);
898 spin_unlock_irqrestore(&port
->lock
, flags
);
900 free_irq(port
->irq
, port
);
904 * cdns_uart_type - Set UART type to cdns_uart port
905 * @port: Handle to the uart port structure
907 * Return: string on success, NULL otherwise
909 static const char *cdns_uart_type(struct uart_port
*port
)
911 return port
->type
== PORT_XUARTPS
? CDNS_UART_NAME
: NULL
;
915 * cdns_uart_verify_port - Verify the port params
916 * @port: Handle to the uart port structure
917 * @ser: Handle to the structure whose members are compared
919 * Return: 0 on success, negative errno otherwise.
921 static int cdns_uart_verify_port(struct uart_port
*port
,
922 struct serial_struct
*ser
)
924 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_XUARTPS
)
926 if (port
->irq
!= ser
->irq
)
928 if (ser
->io_type
!= UPIO_MEM
)
930 if (port
->iobase
!= ser
->port
)
938 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
939 * called when the driver adds a cdns_uart port via
940 * uart_add_one_port()
941 * @port: Handle to the uart port structure
943 * Return: 0 on success, negative errno otherwise.
945 static int cdns_uart_request_port(struct uart_port
*port
)
947 if (!request_mem_region(port
->mapbase
, CDNS_UART_REGISTER_SPACE
,
952 port
->membase
= ioremap(port
->mapbase
, CDNS_UART_REGISTER_SPACE
);
953 if (!port
->membase
) {
954 dev_err(port
->dev
, "Unable to map registers\n");
955 release_mem_region(port
->mapbase
, CDNS_UART_REGISTER_SPACE
);
962 * cdns_uart_release_port - Release UART port
963 * @port: Handle to the uart port structure
965 * Release the memory region attached to a cdns_uart port. Called when the
966 * driver removes a cdns_uart port via uart_remove_one_port().
968 static void cdns_uart_release_port(struct uart_port
*port
)
970 release_mem_region(port
->mapbase
, CDNS_UART_REGISTER_SPACE
);
971 iounmap(port
->membase
);
972 port
->membase
= NULL
;
976 * cdns_uart_config_port - Configure UART port
977 * @port: Handle to the uart port structure
980 static void cdns_uart_config_port(struct uart_port
*port
, int flags
)
982 if (flags
& UART_CONFIG_TYPE
&& cdns_uart_request_port(port
) == 0)
983 port
->type
= PORT_XUARTPS
;
987 * cdns_uart_get_mctrl - Get the modem control state
988 * @port: Handle to the uart port structure
990 * Return: the modem control state
992 static unsigned int cdns_uart_get_mctrl(struct uart_port
*port
)
994 return TIOCM_CTS
| TIOCM_DSR
| TIOCM_CAR
;
997 static void cdns_uart_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1002 val
= readl(port
->membase
+ CDNS_UART_MODEMCR
);
1003 mode_reg
= readl(port
->membase
+ CDNS_UART_MR
);
1005 val
&= ~(CDNS_UART_MODEMCR_RTS
| CDNS_UART_MODEMCR_DTR
);
1006 mode_reg
&= ~CDNS_UART_MR_CHMODE_MASK
;
1008 if (mctrl
& TIOCM_RTS
)
1009 val
|= CDNS_UART_MODEMCR_RTS
;
1010 if (mctrl
& TIOCM_DTR
)
1011 val
|= CDNS_UART_MODEMCR_DTR
;
1012 if (mctrl
& TIOCM_LOOP
)
1013 mode_reg
|= CDNS_UART_MR_CHMODE_L_LOOP
;
1015 mode_reg
|= CDNS_UART_MR_CHMODE_NORM
;
1017 writel(val
, port
->membase
+ CDNS_UART_MODEMCR
);
1018 writel(mode_reg
, port
->membase
+ CDNS_UART_MR
);
1021 #ifdef CONFIG_CONSOLE_POLL
1022 static int cdns_uart_poll_get_char(struct uart_port
*port
)
1025 unsigned long flags
;
1027 spin_lock_irqsave(&port
->lock
, flags
);
1029 /* Check if FIFO is empty */
1030 if (readl(port
->membase
+ CDNS_UART_SR
) & CDNS_UART_SR_RXEMPTY
)
1032 else /* Read a character */
1033 c
= (unsigned char) readl(port
->membase
+ CDNS_UART_FIFO
);
1035 spin_unlock_irqrestore(&port
->lock
, flags
);
1040 static void cdns_uart_poll_put_char(struct uart_port
*port
, unsigned char c
)
1042 unsigned long flags
;
1044 spin_lock_irqsave(&port
->lock
, flags
);
1046 /* Wait until FIFO is empty */
1047 while (!(readl(port
->membase
+ CDNS_UART_SR
) & CDNS_UART_SR_TXEMPTY
))
1050 /* Write a character */
1051 writel(c
, port
->membase
+ CDNS_UART_FIFO
);
1053 /* Wait until FIFO is empty */
1054 while (!(readl(port
->membase
+ CDNS_UART_SR
) & CDNS_UART_SR_TXEMPTY
))
1057 spin_unlock_irqrestore(&port
->lock
, flags
);
1063 static void cdns_uart_pm(struct uart_port
*port
, unsigned int state
,
1064 unsigned int oldstate
)
1067 case UART_PM_STATE_OFF
:
1068 pm_runtime_mark_last_busy(port
->dev
);
1069 pm_runtime_put_autosuspend(port
->dev
);
1072 pm_runtime_get_sync(port
->dev
);
1077 static const struct uart_ops cdns_uart_ops
= {
1078 .set_mctrl
= cdns_uart_set_mctrl
,
1079 .get_mctrl
= cdns_uart_get_mctrl
,
1080 .start_tx
= cdns_uart_start_tx
,
1081 .stop_tx
= cdns_uart_stop_tx
,
1082 .stop_rx
= cdns_uart_stop_rx
,
1083 .tx_empty
= cdns_uart_tx_empty
,
1084 .break_ctl
= cdns_uart_break_ctl
,
1085 .set_termios
= cdns_uart_set_termios
,
1086 .startup
= cdns_uart_startup
,
1087 .shutdown
= cdns_uart_shutdown
,
1089 .type
= cdns_uart_type
,
1090 .verify_port
= cdns_uart_verify_port
,
1091 .request_port
= cdns_uart_request_port
,
1092 .release_port
= cdns_uart_release_port
,
1093 .config_port
= cdns_uart_config_port
,
1094 #ifdef CONFIG_CONSOLE_POLL
1095 .poll_get_char
= cdns_uart_poll_get_char
,
1096 .poll_put_char
= cdns_uart_poll_put_char
,
1100 static struct uart_port cdns_uart_port
[CDNS_UART_NR_PORTS
];
1103 * cdns_uart_get_port - Configure the port from platform device resource info
1106 * Return: a pointer to a uart_port or NULL for failure
1108 static struct uart_port
*cdns_uart_get_port(int id
)
1110 struct uart_port
*port
;
1112 /* Try the given port id if failed use default method */
1113 if (cdns_uart_port
[id
].mapbase
!= 0) {
1114 /* Find the next unused port */
1115 for (id
= 0; id
< CDNS_UART_NR_PORTS
; id
++)
1116 if (cdns_uart_port
[id
].mapbase
== 0)
1120 if (id
>= CDNS_UART_NR_PORTS
)
1123 port
= &cdns_uart_port
[id
];
1125 /* At this point, we've got an empty uart_port struct, initialize it */
1126 spin_lock_init(&port
->lock
);
1127 port
->membase
= NULL
;
1129 port
->type
= PORT_UNKNOWN
;
1130 port
->iotype
= UPIO_MEM32
;
1131 port
->flags
= UPF_BOOT_AUTOCONF
;
1132 port
->ops
= &cdns_uart_ops
;
1133 port
->fifosize
= CDNS_UART_FIFO_SIZE
;
1139 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1141 * cdns_uart_console_wait_tx - Wait for the TX to be full
1142 * @port: Handle to the uart port structure
1144 static void cdns_uart_console_wait_tx(struct uart_port
*port
)
1146 while (!(readl(port
->membase
+ CDNS_UART_SR
) & CDNS_UART_SR_TXEMPTY
))
1151 * cdns_uart_console_putchar - write the character to the FIFO buffer
1152 * @port: Handle to the uart port structure
1153 * @ch: Character to be written
1155 static void cdns_uart_console_putchar(struct uart_port
*port
, int ch
)
1157 cdns_uart_console_wait_tx(port
);
1158 writel(ch
, port
->membase
+ CDNS_UART_FIFO
);
1161 static void cdns_early_write(struct console
*con
, const char *s
,
1164 struct earlycon_device
*dev
= con
->data
;
1166 uart_console_write(&dev
->port
, s
, n
, cdns_uart_console_putchar
);
1169 static int __init
cdns_early_console_setup(struct earlycon_device
*device
,
1172 struct uart_port
*port
= &device
->port
;
1177 /* initialise control register */
1178 writel(CDNS_UART_CR_TX_EN
|CDNS_UART_CR_TXRST
|CDNS_UART_CR_RXRST
,
1179 port
->membase
+ CDNS_UART_CR
);
1181 /* only set baud if specified on command line - otherwise
1182 * assume it has been initialized by a boot loader.
1185 u32 cd
= 0, bdiv
= 0;
1189 cdns_uart_calc_baud_divs(port
->uartclk
, device
->baud
,
1191 mr
= CDNS_UART_MR_PARITY_NONE
;
1193 mr
|= CDNS_UART_MR_CLKSEL
;
1195 writel(mr
, port
->membase
+ CDNS_UART_MR
);
1196 writel(cd
, port
->membase
+ CDNS_UART_BAUDGEN
);
1197 writel(bdiv
, port
->membase
+ CDNS_UART_BAUDDIV
);
1200 device
->con
->write
= cdns_early_write
;
1204 OF_EARLYCON_DECLARE(cdns
, "xlnx,xuartps", cdns_early_console_setup
);
1205 OF_EARLYCON_DECLARE(cdns
, "cdns,uart-r1p8", cdns_early_console_setup
);
1206 OF_EARLYCON_DECLARE(cdns
, "cdns,uart-r1p12", cdns_early_console_setup
);
1207 OF_EARLYCON_DECLARE(cdns
, "xlnx,zynqmp-uart", cdns_early_console_setup
);
1210 * cdns_uart_console_write - perform write operation
1211 * @co: Console handle
1212 * @s: Pointer to character array
1213 * @count: No of characters
1215 static void cdns_uart_console_write(struct console
*co
, const char *s
,
1218 struct uart_port
*port
= &cdns_uart_port
[co
->index
];
1219 unsigned long flags
;
1220 unsigned int imr
, ctrl
;
1225 else if (oops_in_progress
)
1226 locked
= spin_trylock_irqsave(&port
->lock
, flags
);
1228 spin_lock_irqsave(&port
->lock
, flags
);
1230 /* save and disable interrupt */
1231 imr
= readl(port
->membase
+ CDNS_UART_IMR
);
1232 writel(imr
, port
->membase
+ CDNS_UART_IDR
);
1235 * Make sure that the tx part is enabled. Set the TX enable bit and
1236 * clear the TX disable bit to enable the transmitter.
1238 ctrl
= readl(port
->membase
+ CDNS_UART_CR
);
1239 ctrl
&= ~CDNS_UART_CR_TX_DIS
;
1240 ctrl
|= CDNS_UART_CR_TX_EN
;
1241 writel(ctrl
, port
->membase
+ CDNS_UART_CR
);
1243 uart_console_write(port
, s
, count
, cdns_uart_console_putchar
);
1244 cdns_uart_console_wait_tx(port
);
1246 writel(ctrl
, port
->membase
+ CDNS_UART_CR
);
1248 /* restore interrupt state */
1249 writel(imr
, port
->membase
+ CDNS_UART_IER
);
1252 spin_unlock_irqrestore(&port
->lock
, flags
);
1256 * cdns_uart_console_setup - Initialize the uart to default config
1257 * @co: Console handle
1258 * @options: Initial settings of uart
1260 * Return: 0 on success, negative errno otherwise.
1262 static int __init
cdns_uart_console_setup(struct console
*co
, char *options
)
1264 struct uart_port
*port
= &cdns_uart_port
[co
->index
];
1270 if (co
->index
< 0 || co
->index
>= CDNS_UART_NR_PORTS
)
1273 if (!port
->membase
) {
1274 pr_debug("console on " CDNS_UART_TTY_NAME
"%i not present\n",
1280 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1282 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
1285 static struct uart_driver cdns_uart_uart_driver
;
1287 static struct console cdns_uart_console
= {
1288 .name
= CDNS_UART_TTY_NAME
,
1289 .write
= cdns_uart_console_write
,
1290 .device
= uart_console_device
,
1291 .setup
= cdns_uart_console_setup
,
1292 .flags
= CON_PRINTBUFFER
,
1293 .index
= -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1294 .data
= &cdns_uart_uart_driver
,
1298 * cdns_uart_console_init - Initialization call
1300 * Return: 0 on success, negative errno otherwise
1302 static int __init
cdns_uart_console_init(void)
1304 register_console(&cdns_uart_console
);
1308 console_initcall(cdns_uart_console_init
);
1310 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1312 static struct uart_driver cdns_uart_uart_driver
= {
1313 .owner
= THIS_MODULE
,
1314 .driver_name
= CDNS_UART_NAME
,
1315 .dev_name
= CDNS_UART_TTY_NAME
,
1316 .major
= CDNS_UART_MAJOR
,
1317 .minor
= CDNS_UART_MINOR
,
1318 .nr
= CDNS_UART_NR_PORTS
,
1319 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1320 .cons
= &cdns_uart_console
,
1324 #ifdef CONFIG_PM_SLEEP
1326 * cdns_uart_suspend - suspend event
1327 * @device: Pointer to the device structure
1331 static int cdns_uart_suspend(struct device
*device
)
1333 struct uart_port
*port
= dev_get_drvdata(device
);
1334 struct tty_struct
*tty
;
1335 struct device
*tty_dev
;
1338 /* Get the tty which could be NULL so don't assume it's valid */
1339 tty
= tty_port_tty_get(&port
->state
->port
);
1342 may_wake
= device_may_wakeup(tty_dev
);
1347 * Call the API provided in serial_core.c file which handles
1350 uart_suspend_port(&cdns_uart_uart_driver
, port
);
1351 if (!(console_suspend_enabled
&& !may_wake
)) {
1352 unsigned long flags
= 0;
1354 spin_lock_irqsave(&port
->lock
, flags
);
1355 /* Empty the receive FIFO 1st before making changes */
1356 while (!(readl(port
->membase
+ CDNS_UART_SR
) &
1357 CDNS_UART_SR_RXEMPTY
))
1358 readl(port
->membase
+ CDNS_UART_FIFO
);
1359 /* set RX trigger level to 1 */
1360 writel(1, port
->membase
+ CDNS_UART_RXWM
);
1361 /* disable RX timeout interrups */
1362 writel(CDNS_UART_IXR_TOUT
, port
->membase
+ CDNS_UART_IDR
);
1363 spin_unlock_irqrestore(&port
->lock
, flags
);
1370 * cdns_uart_resume - Resume after a previous suspend
1371 * @device: Pointer to the device structure
1375 static int cdns_uart_resume(struct device
*device
)
1377 struct uart_port
*port
= dev_get_drvdata(device
);
1378 unsigned long flags
= 0;
1380 struct tty_struct
*tty
;
1381 struct device
*tty_dev
;
1384 /* Get the tty which could be NULL so don't assume it's valid */
1385 tty
= tty_port_tty_get(&port
->state
->port
);
1388 may_wake
= device_may_wakeup(tty_dev
);
1392 if (console_suspend_enabled
&& !may_wake
) {
1393 struct cdns_uart
*cdns_uart
= port
->private_data
;
1395 clk_enable(cdns_uart
->pclk
);
1396 clk_enable(cdns_uart
->uartclk
);
1398 spin_lock_irqsave(&port
->lock
, flags
);
1400 /* Set TX/RX Reset */
1401 ctrl_reg
= readl(port
->membase
+ CDNS_UART_CR
);
1402 ctrl_reg
|= CDNS_UART_CR_TXRST
| CDNS_UART_CR_RXRST
;
1403 writel(ctrl_reg
, port
->membase
+ CDNS_UART_CR
);
1404 while (readl(port
->membase
+ CDNS_UART_CR
) &
1405 (CDNS_UART_CR_TXRST
| CDNS_UART_CR_RXRST
))
1408 /* restore rx timeout value */
1409 writel(rx_timeout
, port
->membase
+ CDNS_UART_RXTOUT
);
1411 ctrl_reg
= readl(port
->membase
+ CDNS_UART_CR
);
1412 ctrl_reg
&= ~(CDNS_UART_CR_TX_DIS
| CDNS_UART_CR_RX_DIS
);
1413 ctrl_reg
|= CDNS_UART_CR_TX_EN
| CDNS_UART_CR_RX_EN
;
1414 writel(ctrl_reg
, port
->membase
+ CDNS_UART_CR
);
1416 clk_disable(cdns_uart
->uartclk
);
1417 clk_disable(cdns_uart
->pclk
);
1418 spin_unlock_irqrestore(&port
->lock
, flags
);
1420 spin_lock_irqsave(&port
->lock
, flags
);
1421 /* restore original rx trigger level */
1422 writel(rx_trigger_level
, port
->membase
+ CDNS_UART_RXWM
);
1423 /* enable RX timeout interrupt */
1424 writel(CDNS_UART_IXR_TOUT
, port
->membase
+ CDNS_UART_IER
);
1425 spin_unlock_irqrestore(&port
->lock
, flags
);
1428 return uart_resume_port(&cdns_uart_uart_driver
, port
);
1430 #endif /* ! CONFIG_PM_SLEEP */
1431 static int __maybe_unused
cdns_runtime_suspend(struct device
*dev
)
1433 struct platform_device
*pdev
= to_platform_device(dev
);
1434 struct uart_port
*port
= platform_get_drvdata(pdev
);
1435 struct cdns_uart
*cdns_uart
= port
->private_data
;
1437 clk_disable(cdns_uart
->uartclk
);
1438 clk_disable(cdns_uart
->pclk
);
1442 static int __maybe_unused
cdns_runtime_resume(struct device
*dev
)
1444 struct platform_device
*pdev
= to_platform_device(dev
);
1445 struct uart_port
*port
= platform_get_drvdata(pdev
);
1446 struct cdns_uart
*cdns_uart
= port
->private_data
;
1448 clk_enable(cdns_uart
->pclk
);
1449 clk_enable(cdns_uart
->uartclk
);
1453 static const struct dev_pm_ops cdns_uart_dev_pm_ops
= {
1454 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend
, cdns_uart_resume
)
1455 SET_RUNTIME_PM_OPS(cdns_runtime_suspend
,
1456 cdns_runtime_resume
, NULL
)
1459 static const struct cdns_platform_data zynqmp_uart_def
= {
1460 .quirks
= CDNS_UART_RXBS_SUPPORT
, };
1462 /* Match table for of_platform binding */
1463 static const struct of_device_id cdns_uart_of_match
[] = {
1464 { .compatible
= "xlnx,xuartps", },
1465 { .compatible
= "cdns,uart-r1p8", },
1466 { .compatible
= "cdns,uart-r1p12", .data
= &zynqmp_uart_def
},
1467 { .compatible
= "xlnx,zynqmp-uart", .data
= &zynqmp_uart_def
},
1470 MODULE_DEVICE_TABLE(of
, cdns_uart_of_match
);
1473 * cdns_uart_probe - Platform driver probe
1474 * @pdev: Pointer to the platform device structure
1476 * Return: 0 on success, negative errno otherwise
1478 static int cdns_uart_probe(struct platform_device
*pdev
)
1481 struct uart_port
*port
;
1482 struct resource
*res
;
1483 struct cdns_uart
*cdns_uart_data
;
1484 const struct of_device_id
*match
;
1486 cdns_uart_data
= devm_kzalloc(&pdev
->dev
, sizeof(*cdns_uart_data
),
1488 if (!cdns_uart_data
)
1491 match
= of_match_node(cdns_uart_of_match
, pdev
->dev
.of_node
);
1492 if (match
&& match
->data
) {
1493 const struct cdns_platform_data
*data
= match
->data
;
1495 cdns_uart_data
->quirks
= data
->quirks
;
1498 cdns_uart_data
->pclk
= devm_clk_get(&pdev
->dev
, "pclk");
1499 if (IS_ERR(cdns_uart_data
->pclk
)) {
1500 cdns_uart_data
->pclk
= devm_clk_get(&pdev
->dev
, "aper_clk");
1501 if (!IS_ERR(cdns_uart_data
->pclk
))
1502 dev_err(&pdev
->dev
, "clock name 'aper_clk' is deprecated.\n");
1504 if (IS_ERR(cdns_uart_data
->pclk
)) {
1505 dev_err(&pdev
->dev
, "pclk clock not found.\n");
1506 return PTR_ERR(cdns_uart_data
->pclk
);
1509 cdns_uart_data
->uartclk
= devm_clk_get(&pdev
->dev
, "uart_clk");
1510 if (IS_ERR(cdns_uart_data
->uartclk
)) {
1511 cdns_uart_data
->uartclk
= devm_clk_get(&pdev
->dev
, "ref_clk");
1512 if (!IS_ERR(cdns_uart_data
->uartclk
))
1513 dev_err(&pdev
->dev
, "clock name 'ref_clk' is deprecated.\n");
1515 if (IS_ERR(cdns_uart_data
->uartclk
)) {
1516 dev_err(&pdev
->dev
, "uart_clk clock not found.\n");
1517 return PTR_ERR(cdns_uart_data
->uartclk
);
1520 rc
= clk_prepare_enable(cdns_uart_data
->pclk
);
1522 dev_err(&pdev
->dev
, "Unable to enable pclk clock.\n");
1525 rc
= clk_prepare_enable(cdns_uart_data
->uartclk
);
1527 dev_err(&pdev
->dev
, "Unable to enable device clock.\n");
1528 goto err_out_clk_dis_pclk
;
1531 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1534 goto err_out_clk_disable
;
1537 irq
= platform_get_irq(pdev
, 0);
1540 goto err_out_clk_disable
;
1543 #ifdef CONFIG_COMMON_CLK
1544 cdns_uart_data
->clk_rate_change_nb
.notifier_call
=
1545 cdns_uart_clk_notifier_cb
;
1546 if (clk_notifier_register(cdns_uart_data
->uartclk
,
1547 &cdns_uart_data
->clk_rate_change_nb
))
1548 dev_warn(&pdev
->dev
, "Unable to register clock notifier.\n");
1550 /* Look for a serialN alias */
1551 id
= of_alias_get_id(pdev
->dev
.of_node
, "serial");
1555 /* Initialize the port structure */
1556 port
= cdns_uart_get_port(id
);
1559 dev_err(&pdev
->dev
, "Cannot get uart_port structure\n");
1561 goto err_out_notif_unreg
;
1565 * Register the port.
1566 * This function also registers this device with the tty layer
1567 * and triggers invocation of the config_port() entry point.
1569 port
->mapbase
= res
->start
;
1571 port
->dev
= &pdev
->dev
;
1572 port
->uartclk
= clk_get_rate(cdns_uart_data
->uartclk
);
1573 port
->private_data
= cdns_uart_data
;
1574 cdns_uart_data
->port
= port
;
1575 platform_set_drvdata(pdev
, port
);
1577 pm_runtime_use_autosuspend(&pdev
->dev
);
1578 pm_runtime_set_autosuspend_delay(&pdev
->dev
, UART_AUTOSUSPEND_TIMEOUT
);
1579 pm_runtime_set_active(&pdev
->dev
);
1580 pm_runtime_enable(&pdev
->dev
);
1582 rc
= uart_add_one_port(&cdns_uart_uart_driver
, port
);
1585 "uart_add_one_port() failed; err=%i\n", rc
);
1586 goto err_out_pm_disable
;
1592 pm_runtime_disable(&pdev
->dev
);
1593 pm_runtime_set_suspended(&pdev
->dev
);
1594 pm_runtime_dont_use_autosuspend(&pdev
->dev
);
1595 err_out_notif_unreg
:
1596 #ifdef CONFIG_COMMON_CLK
1597 clk_notifier_unregister(cdns_uart_data
->uartclk
,
1598 &cdns_uart_data
->clk_rate_change_nb
);
1600 err_out_clk_disable
:
1601 clk_disable_unprepare(cdns_uart_data
->uartclk
);
1602 err_out_clk_dis_pclk
:
1603 clk_disable_unprepare(cdns_uart_data
->pclk
);
1609 * cdns_uart_remove - called when the platform driver is unregistered
1610 * @pdev: Pointer to the platform device structure
1612 * Return: 0 on success, negative errno otherwise
1614 static int cdns_uart_remove(struct platform_device
*pdev
)
1616 struct uart_port
*port
= platform_get_drvdata(pdev
);
1617 struct cdns_uart
*cdns_uart_data
= port
->private_data
;
1620 /* Remove the cdns_uart port from the serial core */
1621 #ifdef CONFIG_COMMON_CLK
1622 clk_notifier_unregister(cdns_uart_data
->uartclk
,
1623 &cdns_uart_data
->clk_rate_change_nb
);
1625 rc
= uart_remove_one_port(&cdns_uart_uart_driver
, port
);
1627 clk_disable_unprepare(cdns_uart_data
->uartclk
);
1628 clk_disable_unprepare(cdns_uart_data
->pclk
);
1629 pm_runtime_disable(&pdev
->dev
);
1630 pm_runtime_set_suspended(&pdev
->dev
);
1631 pm_runtime_dont_use_autosuspend(&pdev
->dev
);
1635 static struct platform_driver cdns_uart_platform_driver
= {
1636 .probe
= cdns_uart_probe
,
1637 .remove
= cdns_uart_remove
,
1639 .name
= CDNS_UART_NAME
,
1640 .of_match_table
= cdns_uart_of_match
,
1641 .pm
= &cdns_uart_dev_pm_ops
,
1645 static int __init
cdns_uart_init(void)
1649 /* Register the cdns_uart driver with the serial core */
1650 retval
= uart_register_driver(&cdns_uart_uart_driver
);
1654 /* Register the platform driver */
1655 retval
= platform_driver_register(&cdns_uart_platform_driver
);
1657 uart_unregister_driver(&cdns_uart_uart_driver
);
1662 static void __exit
cdns_uart_exit(void)
1664 /* Unregister the platform driver */
1665 platform_driver_unregister(&cdns_uart_platform_driver
);
1667 /* Unregister the cdns_uart driver */
1668 uart_unregister_driver(&cdns_uart_uart_driver
);
1671 arch_initcall(cdns_uart_init
);
1672 module_exit(cdns_uart_exit
);
1674 MODULE_DESCRIPTION("Driver for Cadence UART");
1675 MODULE_AUTHOR("Xilinx Inc.");
1676 MODULE_LICENSE("GPL");