1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016 MediaTek Inc.
5 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
9 #include <linux/dma-mapping.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/platform_device.h>
20 /* u2-port0 should be powered on and enabled; */
21 int ssusb_check_clocks(struct ssusb_mtk
*ssusb
, u32 ex_clks
)
23 void __iomem
*ibase
= ssusb
->ippc_base
;
27 check_val
= ex_clks
| SSUSB_SYS125_RST_B_STS
| SSUSB_SYSPLL_STABLE
|
30 ret
= readl_poll_timeout(ibase
+ U3D_SSUSB_IP_PW_STS1
, value
,
31 (check_val
== (value
& check_val
)), 100, 20000);
33 dev_err(ssusb
->dev
, "clks of sts1 are not stable!\n");
37 ret
= readl_poll_timeout(ibase
+ U3D_SSUSB_IP_PW_STS2
, value
,
38 (value
& SSUSB_U2_MAC_SYS_RST_B_STS
), 100, 10000);
40 dev_err(ssusb
->dev
, "mac2 clock is not stable\n");
47 static int ssusb_phy_init(struct ssusb_mtk
*ssusb
)
52 for (i
= 0; i
< ssusb
->num_phys
; i
++) {
53 ret
= phy_init(ssusb
->phys
[i
]);
61 phy_exit(ssusb
->phys
[i
- 1]);
66 static int ssusb_phy_exit(struct ssusb_mtk
*ssusb
)
70 for (i
= 0; i
< ssusb
->num_phys
; i
++)
71 phy_exit(ssusb
->phys
[i
]);
76 static int ssusb_phy_power_on(struct ssusb_mtk
*ssusb
)
81 for (i
= 0; i
< ssusb
->num_phys
; i
++) {
82 ret
= phy_power_on(ssusb
->phys
[i
]);
90 phy_power_off(ssusb
->phys
[i
- 1]);
95 static void ssusb_phy_power_off(struct ssusb_mtk
*ssusb
)
99 for (i
= 0; i
< ssusb
->num_phys
; i
++)
100 phy_power_off(ssusb
->phys
[i
]);
103 static int ssusb_clks_enable(struct ssusb_mtk
*ssusb
)
107 ret
= clk_prepare_enable(ssusb
->sys_clk
);
109 dev_err(ssusb
->dev
, "failed to enable sys_clk\n");
113 ret
= clk_prepare_enable(ssusb
->ref_clk
);
115 dev_err(ssusb
->dev
, "failed to enable ref_clk\n");
119 ret
= clk_prepare_enable(ssusb
->mcu_clk
);
121 dev_err(ssusb
->dev
, "failed to enable mcu_clk\n");
125 ret
= clk_prepare_enable(ssusb
->dma_clk
);
127 dev_err(ssusb
->dev
, "failed to enable dma_clk\n");
134 clk_disable_unprepare(ssusb
->mcu_clk
);
136 clk_disable_unprepare(ssusb
->ref_clk
);
138 clk_disable_unprepare(ssusb
->sys_clk
);
143 static void ssusb_clks_disable(struct ssusb_mtk
*ssusb
)
145 clk_disable_unprepare(ssusb
->dma_clk
);
146 clk_disable_unprepare(ssusb
->mcu_clk
);
147 clk_disable_unprepare(ssusb
->ref_clk
);
148 clk_disable_unprepare(ssusb
->sys_clk
);
151 static int ssusb_rscs_init(struct ssusb_mtk
*ssusb
)
155 ret
= regulator_enable(ssusb
->vusb33
);
157 dev_err(ssusb
->dev
, "failed to enable vusb33\n");
161 ret
= ssusb_clks_enable(ssusb
);
165 ret
= ssusb_phy_init(ssusb
);
167 dev_err(ssusb
->dev
, "failed to init phy\n");
171 ret
= ssusb_phy_power_on(ssusb
);
173 dev_err(ssusb
->dev
, "failed to power on phy\n");
180 ssusb_phy_exit(ssusb
);
182 ssusb_clks_disable(ssusb
);
184 regulator_disable(ssusb
->vusb33
);
189 static void ssusb_rscs_exit(struct ssusb_mtk
*ssusb
)
191 ssusb_clks_disable(ssusb
);
192 regulator_disable(ssusb
->vusb33
);
193 ssusb_phy_power_off(ssusb
);
194 ssusb_phy_exit(ssusb
);
197 static void ssusb_ip_sw_reset(struct ssusb_mtk
*ssusb
)
199 /* reset whole ip (xhci & u3d) */
200 mtu3_setbits(ssusb
->ippc_base
, U3D_SSUSB_IP_PW_CTRL0
, SSUSB_IP_SW_RST
);
202 mtu3_clrbits(ssusb
->ippc_base
, U3D_SSUSB_IP_PW_CTRL0
, SSUSB_IP_SW_RST
);
205 /* ignore the error if the clock does not exist */
206 static struct clk
*get_optional_clk(struct device
*dev
, const char *id
)
210 opt_clk
= devm_clk_get(dev
, id
);
211 /* ignore error number except EPROBE_DEFER */
212 if (IS_ERR(opt_clk
) && (PTR_ERR(opt_clk
) != -EPROBE_DEFER
))
218 static int get_ssusb_rscs(struct platform_device
*pdev
, struct ssusb_mtk
*ssusb
)
220 struct device_node
*node
= pdev
->dev
.of_node
;
221 struct otg_switch_mtk
*otg_sx
= &ssusb
->otg_switch
;
222 struct device
*dev
= &pdev
->dev
;
223 struct regulator
*vbus
;
224 struct resource
*res
;
228 ssusb
->vusb33
= devm_regulator_get(&pdev
->dev
, "vusb33");
229 if (IS_ERR(ssusb
->vusb33
)) {
230 dev_err(dev
, "failed to get vusb33\n");
231 return PTR_ERR(ssusb
->vusb33
);
234 ssusb
->sys_clk
= devm_clk_get(dev
, "sys_ck");
235 if (IS_ERR(ssusb
->sys_clk
)) {
236 dev_err(dev
, "failed to get sys clock\n");
237 return PTR_ERR(ssusb
->sys_clk
);
240 ssusb
->ref_clk
= get_optional_clk(dev
, "ref_ck");
241 if (IS_ERR(ssusb
->ref_clk
))
242 return PTR_ERR(ssusb
->ref_clk
);
244 ssusb
->mcu_clk
= get_optional_clk(dev
, "mcu_ck");
245 if (IS_ERR(ssusb
->mcu_clk
))
246 return PTR_ERR(ssusb
->mcu_clk
);
248 ssusb
->dma_clk
= get_optional_clk(dev
, "dma_ck");
249 if (IS_ERR(ssusb
->dma_clk
))
250 return PTR_ERR(ssusb
->dma_clk
);
252 ssusb
->num_phys
= of_count_phandle_with_args(node
,
253 "phys", "#phy-cells");
254 if (ssusb
->num_phys
> 0) {
255 ssusb
->phys
= devm_kcalloc(dev
, ssusb
->num_phys
,
256 sizeof(*ssusb
->phys
), GFP_KERNEL
);
263 for (i
= 0; i
< ssusb
->num_phys
; i
++) {
264 ssusb
->phys
[i
] = devm_of_phy_get_by_index(dev
, node
, i
);
265 if (IS_ERR(ssusb
->phys
[i
])) {
266 dev_err(dev
, "failed to get phy-%d\n", i
);
267 return PTR_ERR(ssusb
->phys
[i
]);
271 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "ippc");
272 ssusb
->ippc_base
= devm_ioremap_resource(dev
, res
);
273 if (IS_ERR(ssusb
->ippc_base
))
274 return PTR_ERR(ssusb
->ippc_base
);
276 ssusb
->dr_mode
= usb_get_dr_mode(dev
);
277 if (ssusb
->dr_mode
== USB_DR_MODE_UNKNOWN
)
278 ssusb
->dr_mode
= USB_DR_MODE_OTG
;
280 if (ssusb
->dr_mode
== USB_DR_MODE_PERIPHERAL
)
283 /* if host role is supported */
284 ret
= ssusb_wakeup_of_property_parse(ssusb
, node
);
286 dev_err(dev
, "failed to parse uwk property\n");
290 /* optional property, ignore the error if it does not exist */
291 of_property_read_u32(node
, "mediatek,u3p-dis-msk",
292 &ssusb
->u3p_dis_msk
);
294 vbus
= devm_regulator_get(&pdev
->dev
, "vbus");
296 dev_err(dev
, "failed to get vbus\n");
297 return PTR_ERR(vbus
);
301 if (ssusb
->dr_mode
== USB_DR_MODE_HOST
)
304 /* if dual-role mode is supported */
305 otg_sx
->is_u3_drd
= of_property_read_bool(node
, "mediatek,usb3-drd");
306 otg_sx
->manual_drd_enabled
=
307 of_property_read_bool(node
, "enable-manual-drd");
309 if (of_property_read_bool(node
, "extcon")) {
310 otg_sx
->edev
= extcon_get_edev_by_phandle(ssusb
->dev
, 0);
311 if (IS_ERR(otg_sx
->edev
)) {
312 dev_err(ssusb
->dev
, "couldn't get extcon device\n");
313 return PTR_ERR(otg_sx
->edev
);
317 dev_info(dev
, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
318 ssusb
->dr_mode
, otg_sx
->is_u3_drd
, ssusb
->u3p_dis_msk
,
319 otg_sx
->manual_drd_enabled
? "manual" : "auto");
324 static int mtu3_probe(struct platform_device
*pdev
)
326 struct device_node
*node
= pdev
->dev
.of_node
;
327 struct device
*dev
= &pdev
->dev
;
328 struct ssusb_mtk
*ssusb
;
331 /* all elements are set to ZERO as default value */
332 ssusb
= devm_kzalloc(dev
, sizeof(*ssusb
), GFP_KERNEL
);
336 ret
= dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(32));
338 dev_err(dev
, "No suitable DMA config available\n");
342 platform_set_drvdata(pdev
, ssusb
);
345 ret
= get_ssusb_rscs(pdev
, ssusb
);
349 /* enable power domain */
350 pm_runtime_enable(dev
);
351 pm_runtime_get_sync(dev
);
352 device_enable_async_suspend(dev
);
354 ret
= ssusb_rscs_init(ssusb
);
358 ssusb_ip_sw_reset(ssusb
);
360 if (IS_ENABLED(CONFIG_USB_MTU3_HOST
))
361 ssusb
->dr_mode
= USB_DR_MODE_HOST
;
362 else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET
))
363 ssusb
->dr_mode
= USB_DR_MODE_PERIPHERAL
;
365 /* default as host */
366 ssusb
->is_host
= !(ssusb
->dr_mode
== USB_DR_MODE_PERIPHERAL
);
368 switch (ssusb
->dr_mode
) {
369 case USB_DR_MODE_PERIPHERAL
:
370 ret
= ssusb_gadget_init(ssusb
);
372 dev_err(dev
, "failed to initialize gadget\n");
376 case USB_DR_MODE_HOST
:
377 ret
= ssusb_host_init(ssusb
, node
);
379 dev_err(dev
, "failed to initialize host\n");
383 case USB_DR_MODE_OTG
:
384 ret
= ssusb_gadget_init(ssusb
);
386 dev_err(dev
, "failed to initialize gadget\n");
390 ret
= ssusb_host_init(ssusb
, node
);
392 dev_err(dev
, "failed to initialize host\n");
396 ssusb_otg_switch_init(ssusb
);
399 dev_err(dev
, "unsupported mode: %d\n", ssusb
->dr_mode
);
407 ssusb_gadget_exit(ssusb
);
409 ssusb_rscs_exit(ssusb
);
411 pm_runtime_put_sync(dev
);
412 pm_runtime_disable(dev
);
417 static int mtu3_remove(struct platform_device
*pdev
)
419 struct ssusb_mtk
*ssusb
= platform_get_drvdata(pdev
);
421 switch (ssusb
->dr_mode
) {
422 case USB_DR_MODE_PERIPHERAL
:
423 ssusb_gadget_exit(ssusb
);
425 case USB_DR_MODE_HOST
:
426 ssusb_host_exit(ssusb
);
428 case USB_DR_MODE_OTG
:
429 ssusb_otg_switch_exit(ssusb
);
430 ssusb_gadget_exit(ssusb
);
431 ssusb_host_exit(ssusb
);
437 ssusb_rscs_exit(ssusb
);
438 pm_runtime_put_sync(&pdev
->dev
);
439 pm_runtime_disable(&pdev
->dev
);
445 * when support dual-role mode, we reject suspend when
446 * it works as device mode;
448 static int __maybe_unused
mtu3_suspend(struct device
*dev
)
450 struct platform_device
*pdev
= to_platform_device(dev
);
451 struct ssusb_mtk
*ssusb
= platform_get_drvdata(pdev
);
453 dev_dbg(dev
, "%s\n", __func__
);
455 /* REVISIT: disconnect it for only device mode? */
459 ssusb_host_disable(ssusb
, true);
460 ssusb_phy_power_off(ssusb
);
461 ssusb_clks_disable(ssusb
);
462 ssusb_wakeup_set(ssusb
, true);
467 static int __maybe_unused
mtu3_resume(struct device
*dev
)
469 struct platform_device
*pdev
= to_platform_device(dev
);
470 struct ssusb_mtk
*ssusb
= platform_get_drvdata(pdev
);
473 dev_dbg(dev
, "%s\n", __func__
);
478 ssusb_wakeup_set(ssusb
, false);
479 ret
= ssusb_clks_enable(ssusb
);
483 ret
= ssusb_phy_power_on(ssusb
);
487 ssusb_host_enable(ssusb
);
492 ssusb_clks_disable(ssusb
);
497 static const struct dev_pm_ops mtu3_pm_ops
= {
498 SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend
, mtu3_resume
)
501 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
505 static const struct of_device_id mtu3_of_match
[] = {
506 {.compatible
= "mediatek,mt8173-mtu3",},
507 {.compatible
= "mediatek,mtu3",},
511 MODULE_DEVICE_TABLE(of
, mtu3_of_match
);
515 static struct platform_driver mtu3_driver
= {
517 .remove
= mtu3_remove
,
519 .name
= MTU3_DRIVER_NAME
,
521 .of_match_table
= of_match_ptr(mtu3_of_match
),
524 module_platform_driver(mtu3_driver
);
526 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
527 MODULE_LICENSE("GPL v2");
528 MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");