drivers/clk/samsung/clk-exynos-audss.c

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Author: Padmavathi Venna <padma.v@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for Audio Subsystem Clock Controller.
  10 */
  11
  12 #include <linux/clkdev.h>
  13 #include <linux/io.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/of_address.h>
  16 #include <linux/syscore_ops.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19
  20 #include <dt-bindings/clk/exynos-audss-clk.h>
  21
  22 enum exynos_audss_clk_type {
  23         TYPE_EXYNOS4210,
  24         TYPE_EXYNOS5250,
  25         TYPE_EXYNOS5420,
  26 };
  27
  28 static DEFINE_SPINLOCK(lock);
  29 static struct clk **clk_table;
  30 static void __iomem *reg_base;
  31 static struct clk_onecell_data clk_data;
  32
  33 #define ASS_CLK_SRC 0x0
  34 #define ASS_CLK_DIV 0x4
  35 #define ASS_CLK_GATE 0x8
  36
  37 #ifdef CONFIG_PM_SLEEP
  38 static unsigned long reg_save[][2] = {
  39         {ASS_CLK_SRC,  0},
  40         {ASS_CLK_DIV,  0},
  41         {ASS_CLK_GATE, 0},
  42 };
  43
  44 static int exynos_audss_clk_suspend(void)
  45 {
  46         int i;
  47
  48         for (i = 0; i < ARRAY_SIZE(reg_save); i++)
  49                 reg_save[i][1] = readl(reg_base + reg_save[i][0]);
  50
  51         return 0;
  52 }
  53
  54 static void exynos_audss_clk_resume(void)
  55 {
  56         int i;
  57
  58         for (i = 0; i < ARRAY_SIZE(reg_save); i++)
  59                 writel(reg_save[i][1], reg_base + reg_save[i][0]);
  60 }
  61
  62 static struct syscore_ops exynos_audss_clk_syscore_ops = {
  63         .suspend        = exynos_audss_clk_suspend,
  64         .resume         = exynos_audss_clk_resume,
  65 };
  66 #endif /* CONFIG_PM_SLEEP */
  67
  68 static const struct of_device_id exynos_audss_clk_of_match[] = {
  69         { .compatible = "samsung,exynos4210-audss-clock",
  70           .data = (void *)TYPE_EXYNOS4210, },
  71         { .compatible = "samsung,exynos5250-audss-clock",
  72           .data = (void *)TYPE_EXYNOS5250, },
  73         { .compatible = "samsung,exynos5420-audss-clock",
  74           .data = (void *)TYPE_EXYNOS5420, },
  75         {},
  76 };
  77
  78 /* register exynos_audss clocks */
  79 static int exynos_audss_clk_probe(struct platform_device *pdev)
  80 {
  81         int i, ret = 0;
  82         struct resource *res;
  83         const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
  84         const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
  85         const char *sclk_pcm_p = "sclk_pcm0";
  86         struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
  87         const struct of_device_id *match;
  88         enum exynos_audss_clk_type variant;
  89
  90         match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node);
  91         if (!match)
  92                 return -EINVAL;
  93         variant = (enum exynos_audss_clk_type)match->data;
  94
  95         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  96         reg_base = devm_ioremap_resource(&pdev->dev, res);
  97         if (IS_ERR(reg_base)) {
  98                 dev_err(&pdev->dev, "failed to map audss registers\n");
  99                 return PTR_ERR(reg_base);
 100         }
 101
 102         clk_table = devm_kzalloc(&pdev->dev,
 103                                 sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
 104                                 GFP_KERNEL);
 105         if (!clk_table)
 106                 return -ENOMEM;
 107
 108         clk_data.clks = clk_table;
 109         if (variant == TYPE_EXYNOS5420)
 110                 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
 111         else
 112                 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
 113
 114         pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
 115         pll_in = devm_clk_get(&pdev->dev, "pll_in");
 116         if (!IS_ERR(pll_ref))
 117                 mout_audss_p[0] = __clk_get_name(pll_ref);
 118         if (!IS_ERR(pll_in))
 119                 mout_audss_p[1] = __clk_get_name(pll_in);
 120         clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
 121                                 mout_audss_p, ARRAY_SIZE(mout_audss_p),
 122                                 CLK_SET_RATE_NO_REPARENT,
 123                                 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
 124
 125         cdclk = devm_clk_get(&pdev->dev, "cdclk");
 126         sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
 127         if (!IS_ERR(cdclk))
 128                 mout_i2s_p[1] = __clk_get_name(cdclk);
 129         if (!IS_ERR(sclk_audio))
 130                 mout_i2s_p[2] = __clk_get_name(sclk_audio);
 131         clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
 132                                 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
 133                                 CLK_SET_RATE_NO_REPARENT,
 134                                 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
 135
 136         clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
 137                                 "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
 138                                 0, &lock);
 139
 140         clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
 141                                 "dout_aud_bus", "dout_srp", 0,
 142                                 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
 143
 144         clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
 145                                 "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
 146                                 &lock);
 147
 148         clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
 149                                 "dout_srp", CLK_SET_RATE_PARENT,
 150                                 reg_base + ASS_CLK_GATE, 0, 0, &lock);
 151
 152         clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
 153                                 "dout_aud_bus", CLK_SET_RATE_PARENT,
 154                                 reg_base + ASS_CLK_GATE, 2, 0, &lock);
 155
 156         clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
 157                                 "dout_i2s", CLK_SET_RATE_PARENT,
 158                                 reg_base + ASS_CLK_GATE, 3, 0, &lock);
 159
 160         clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
 161                                  "sclk_pcm", CLK_SET_RATE_PARENT,
 162                                 reg_base + ASS_CLK_GATE, 4, 0, &lock);
 163
 164         sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
 165         if (!IS_ERR(sclk_pcm_in))
 166                 sclk_pcm_p = __clk_get_name(sclk_pcm_in);
 167         clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
 168                                 sclk_pcm_p, CLK_SET_RATE_PARENT,
 169                                 reg_base + ASS_CLK_GATE, 5, 0, &lock);
 170
 171         if (variant == TYPE_EXYNOS5420) {
 172                 clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
 173                                 "dout_srp", CLK_SET_RATE_PARENT,
 174                                 reg_base + ASS_CLK_GATE, 9, 0, &lock);
 175         }
 176
 177         for (i = 0; i < clk_data.clk_num; i++) {
 178                 if (IS_ERR(clk_table[i])) {
 179                         dev_err(&pdev->dev, "failed to register clock %d\n", i);
 180                         ret = PTR_ERR(clk_table[i]);
 181                         goto unregister;
 182                 }
 183         }
 184
 185         ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
 186                                         &clk_data);
 187         if (ret) {
 188                 dev_err(&pdev->dev, "failed to add clock provider\n");
 189                 goto unregister;
 190         }
 191
 192 #ifdef CONFIG_PM_SLEEP
 193         register_syscore_ops(&exynos_audss_clk_syscore_ops);
 194 #endif
 195
 196         dev_info(&pdev->dev, "setup completed\n");
 197
 198         return 0;
 199
 200 unregister:
 201         for (i = 0; i < clk_data.clk_num; i++) {
 202                 if (!IS_ERR(clk_table[i]))
 203                         clk_unregister(clk_table[i]);
 204         }
 205
 206         return ret;
 207 }
 208
 209 static int exynos_audss_clk_remove(struct platform_device *pdev)
 210 {
 211         int i;
 212
 213         of_clk_del_provider(pdev->dev.of_node);
 214
 215         for (i = 0; i < clk_data.clk_num; i++) {
 216                 if (!IS_ERR(clk_table[i]))
 217                         clk_unregister(clk_table[i]);
 218         }
 219
 220         return 0;
 221 }
 222
 223 static struct platform_driver exynos_audss_clk_driver = {
 224         .driver = {
 225                 .name = "exynos-audss-clk",
 226                 .owner = THIS_MODULE,
 227                 .of_match_table = exynos_audss_clk_of_match,
 228         },
 229         .probe = exynos_audss_clk_probe,
 230         .remove = exynos_audss_clk_remove,
 231 };
 232
 233 static int __init exynos_audss_clk_init(void)
 234 {
 235         return platform_driver_register(&exynos_audss_clk_driver);
 236 }
 237 core_initcall(exynos_audss_clk_init);
 238
 239 static void __exit exynos_audss_clk_exit(void)
 240 {
 241         platform_driver_unregister(&exynos_audss_clk_driver);
 242 }
 243 module_exit(exynos_audss_clk_exit);
 244
 245 MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
 246 MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
 247 MODULE_LICENSE("GPL v2");
 248 MODULE_ALIAS("platform:exynos-audss-clk");