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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / clk / tegra / clk-pll.c
blob0d20241e07704df196c72ef22510775d22f5bfde
1 /*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/slab.h>
18 #include <linux/io.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/clk-provider.h>
22 #include <linux/clk.h>
23
24 #include "clk.h"
25
26 #define PLL_BASE_BYPASS BIT(31)
27 #define PLL_BASE_ENABLE BIT(30)
28 #define PLL_BASE_REF_ENABLE BIT(29)
29 #define PLL_BASE_OVERRIDE BIT(28)
30
31 #define PLL_BASE_DIVP_SHIFT 20
32 #define PLL_BASE_DIVP_WIDTH 3
33 #define PLL_BASE_DIVN_SHIFT 8
34 #define PLL_BASE_DIVN_WIDTH 10
35 #define PLL_BASE_DIVM_SHIFT 0
36 #define PLL_BASE_DIVM_WIDTH 5
37 #define PLLU_POST_DIVP_MASK 0x1
38
39 #define PLL_MISC_DCCON_SHIFT 20
40 #define PLL_MISC_CPCON_SHIFT 8
41 #define PLL_MISC_CPCON_WIDTH 4
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43 #define PLL_MISC_LFCON_SHIFT 4
44 #define PLL_MISC_LFCON_WIDTH 4
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46 #define PLL_MISC_VCOCON_SHIFT 0
47 #define PLL_MISC_VCOCON_WIDTH 4
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
49
50 #define OUT_OF_TABLE_CPCON 8
51
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
55
56 #define PLL_POST_LOCK_DELAY 50
57
58 #define PLLDU_LFCON_SET_DIVN 600
59
60 #define PLLE_BASE_DIVCML_SHIFT 24
61 #define PLLE_BASE_DIVCML_WIDTH 4
62 #define PLLE_BASE_DIVP_SHIFT 16
63 #define PLLE_BASE_DIVP_WIDTH 7
64 #define PLLE_BASE_DIVN_SHIFT 8
65 #define PLLE_BASE_DIVN_WIDTH 8
66 #define PLLE_BASE_DIVM_SHIFT 0
67 #define PLLE_BASE_DIVM_WIDTH 8
68
69 #define PLLE_MISC_SETUP_BASE_SHIFT 16
70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
71 #define PLLE_MISC_LOCK_ENABLE BIT(9)
72 #define PLLE_MISC_READY BIT(15)
73 #define PLLE_MISC_SETUP_EX_SHIFT 2
74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
76 PLLE_MISC_SETUP_EX_MASK)
77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
78
79 #define PLLE_SS_CTRL 0x68
80 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
81 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
82 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
83 #define PLLE_SS_CNTL_CENTER BIT(14)
84 #define PLLE_SS_CNTL_INVERT BIT(15)
85 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
86 PLLE_SS_CNTL_SSC_BYP)
87 #define PLLE_SS_MAX_MASK 0x1ff
88 #define PLLE_SS_MAX_VAL 0x25
89 #define PLLE_SS_INC_MASK (0xff << 16)
90 #define PLLE_SS_INC_VAL (0x1 << 16)
91 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
92 #define PLLE_SS_INCINTRV_VAL (0x20 << 24)
93 #define PLLE_SS_COEFFICIENTS_MASK \
94 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
95 #define PLLE_SS_COEFFICIENTS_VAL \
96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
97
98 #define PLLE_AUX_PLLP_SEL BIT(2)
99 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
100 #define PLLE_AUX_SEQ_ENABLE BIT(24)
101 #define PLLE_AUX_PLLRE_SEL BIT(28)
102
103 #define PLLE_MISC_PLLE_PTS BIT(8)
104 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
105 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
106 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
107 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
108 #define PLLE_MISC_VREG_CTRL_SHIFT 2
109 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
110
111 #define PLLCX_MISC_STROBE BIT(31)
112 #define PLLCX_MISC_RESET BIT(30)
113 #define PLLCX_MISC_SDM_DIV_SHIFT 28
114 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
115 #define PLLCX_MISC_FILT_DIV_SHIFT 26
116 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
117 #define PLLCX_MISC_ALPHA_SHIFT 18
118 #define PLLCX_MISC_DIV_LOW_RANGE \
119 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
120 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
121 #define PLLCX_MISC_DIV_HIGH_RANGE \
122 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
123 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
124 #define PLLCX_MISC_COEF_LOW_RANGE \
125 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
126 #define PLLCX_MISC_KA_SHIFT 2
127 #define PLLCX_MISC_KB_SHIFT 9
128 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
129 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
130 PLLCX_MISC_DIV_LOW_RANGE | \
131 PLLCX_MISC_RESET)
132 #define PLLCX_MISC1_DEFAULT 0x000d2308
133 #define PLLCX_MISC2_DEFAULT 0x30211200
134 #define PLLCX_MISC3_DEFAULT 0x200
135
136 #define PMC_SATA_PWRGT 0x1ac
137 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
138 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
139
140 #define PLLSS_MISC_KCP 0
141 #define PLLSS_MISC_KVCO 0
142 #define PLLSS_MISC_SETUP 0
143 #define PLLSS_EN_SDM 0
144 #define PLLSS_EN_SSC 0
145 #define PLLSS_EN_DITHER2 0
146 #define PLLSS_EN_DITHER 1
147 #define PLLSS_SDM_RESET 0
148 #define PLLSS_CLAMP 0
149 #define PLLSS_SDM_SSC_MAX 0
150 #define PLLSS_SDM_SSC_MIN 0
151 #define PLLSS_SDM_SSC_STEP 0
152 #define PLLSS_SDM_DIN 0
153 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
154 (PLLSS_MISC_KVCO << 24) | \
155 PLLSS_MISC_SETUP)
156 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
157 (PLLSS_EN_SSC << 30) | \
158 (PLLSS_EN_DITHER2 << 29) | \
159 (PLLSS_EN_DITHER << 28) | \
160 (PLLSS_SDM_RESET) << 27 | \
161 (PLLSS_CLAMP << 22))
162 #define PLLSS_CTRL1_DEFAULT \
163 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
164 #define PLLSS_CTRL2_DEFAULT \
165 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
166 #define PLLSS_LOCK_OVERRIDE BIT(24)
167 #define PLLSS_REF_SRC_SEL_SHIFT 25
168 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
169
170 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
171 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
172 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
173 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
174
175 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
176 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
177 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
178 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
179
180 #define mask(w) ((1 << (w)) - 1)
181 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
182 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
183 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
184 mask(p->params->div_nmp->divp_width))
185
186 #define divm_max(p) (divm_mask(p))
187 #define divn_max(p) (divn_mask(p))
188 #define divp_max(p) (1 << (divp_mask(p)))
189
190 static struct div_nmp default_nmp = {
191 .divn_shift = PLL_BASE_DIVN_SHIFT,
192 .divn_width = PLL_BASE_DIVN_WIDTH,
193 .divm_shift = PLL_BASE_DIVM_SHIFT,
194 .divm_width = PLL_BASE_DIVM_WIDTH,
195 .divp_shift = PLL_BASE_DIVP_SHIFT,
196 .divp_width = PLL_BASE_DIVP_WIDTH,
197 };
198
199 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
200 {
201 u32 val;
202
203 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
204 return;
205
206 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
207 return;
208
209 val = pll_readl_misc(pll);
210 val |= BIT(pll->params->lock_enable_bit_idx);
211 pll_writel_misc(val, pll);
212 }
213
214 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
215 {
216 int i;
217 u32 val, lock_mask;
218 void __iomem *lock_addr;
219
220 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
221 udelay(pll->params->lock_delay);
222 return 0;
223 }
224
225 lock_addr = pll->clk_base;
226 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
227 lock_addr += pll->params->misc_reg;
228 else
229 lock_addr += pll->params->base_reg;
230
231 lock_mask = pll->params->lock_mask;
232
233 for (i = 0; i < pll->params->lock_delay; i++) {
234 val = readl_relaxed(lock_addr);
235 if ((val & lock_mask) == lock_mask) {
236 udelay(PLL_POST_LOCK_DELAY);
237 return 0;
238 }
239 udelay(2); /* timeout = 2 * lock time */
240 }
241
242 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
243 __clk_get_name(pll->hw.clk));
244
245 return -1;
246 }
247
248 static int clk_pll_is_enabled(struct clk_hw *hw)
249 {
250 struct tegra_clk_pll *pll = to_clk_pll(hw);
251 u32 val;
252
253 if (pll->params->flags & TEGRA_PLLM) {
254 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
255 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
256 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
257 }
258
259 val = pll_readl_base(pll);
260
261 return val & PLL_BASE_ENABLE ? 1 : 0;
262 }
263
264 static void _clk_pll_enable(struct clk_hw *hw)
265 {
266 struct tegra_clk_pll *pll = to_clk_pll(hw);
267 u32 val;
268
269 clk_pll_enable_lock(pll);
270
271 val = pll_readl_base(pll);
272 if (pll->params->flags & TEGRA_PLL_BYPASS)
273 val &= ~PLL_BASE_BYPASS;
274 val |= PLL_BASE_ENABLE;
275 pll_writel_base(val, pll);
276
277 if (pll->params->flags & TEGRA_PLLM) {
278 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
279 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
280 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
281 }
282 }
283
284 static void _clk_pll_disable(struct clk_hw *hw)
285 {
286 struct tegra_clk_pll *pll = to_clk_pll(hw);
287 u32 val;
288
289 val = pll_readl_base(pll);
290 if (pll->params->flags & TEGRA_PLL_BYPASS)
291 val &= ~PLL_BASE_BYPASS;
292 val &= ~PLL_BASE_ENABLE;
293 pll_writel_base(val, pll);
294
295 if (pll->params->flags & TEGRA_PLLM) {
296 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
297 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
298 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
299 }
300 }
301
302 static int clk_pll_enable(struct clk_hw *hw)
303 {
304 struct tegra_clk_pll *pll = to_clk_pll(hw);
305 unsigned long flags = 0;
306 int ret;
307
308 if (pll->lock)
309 spin_lock_irqsave(pll->lock, flags);
310
311 _clk_pll_enable(hw);
312
313 ret = clk_pll_wait_for_lock(pll);
314
315 if (pll->lock)
316 spin_unlock_irqrestore(pll->lock, flags);
317
318 return ret;
319 }
320
321 static void clk_pll_disable(struct clk_hw *hw)
322 {
323 struct tegra_clk_pll *pll = to_clk_pll(hw);
324 unsigned long flags = 0;
325
326 if (pll->lock)
327 spin_lock_irqsave(pll->lock, flags);
328
329 _clk_pll_disable(hw);
330
331 if (pll->lock)
332 spin_unlock_irqrestore(pll->lock, flags);
333 }
334
335 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
336 {
337 struct tegra_clk_pll *pll = to_clk_pll(hw);
338 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
339
340 if (p_tohw) {
341 while (p_tohw->pdiv) {
342 if (p_div <= p_tohw->pdiv)
343 return p_tohw->hw_val;
344 p_tohw++;
345 }
346 return -EINVAL;
347 }
348 return -EINVAL;
349 }
350
351 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
352 {
353 struct tegra_clk_pll *pll = to_clk_pll(hw);
354 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
355
356 if (p_tohw) {
357 while (p_tohw->pdiv) {
358 if (p_div_hw == p_tohw->hw_val)
359 return p_tohw->pdiv;
360 p_tohw++;
361 }
362 return -EINVAL;
363 }
364
365 return 1 << p_div_hw;
366 }
367
368 static int _get_table_rate(struct clk_hw *hw,
369 struct tegra_clk_pll_freq_table *cfg,
370 unsigned long rate, unsigned long parent_rate)
371 {
372 struct tegra_clk_pll *pll = to_clk_pll(hw);
373 struct tegra_clk_pll_freq_table *sel;
374
375 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
376 if (sel->input_rate == parent_rate &&
377 sel->output_rate == rate)
378 break;
379
380 if (sel->input_rate == 0)
381 return -EINVAL;
382
383 cfg->input_rate = sel->input_rate;
384 cfg->output_rate = sel->output_rate;
385 cfg->m = sel->m;
386 cfg->n = sel->n;
387 cfg->p = sel->p;
388 cfg->cpcon = sel->cpcon;
389
390 return 0;
391 }
392
393 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
394 unsigned long rate, unsigned long parent_rate)
395 {
396 struct tegra_clk_pll *pll = to_clk_pll(hw);
397 unsigned long cfreq;
398 u32 p_div = 0;
399 int ret;
400
401 switch (parent_rate) {
402 case 12000000:
403 case 26000000:
404 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
405 break;
406 case 13000000:
407 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
408 break;
409 case 16800000:
410 case 19200000:
411 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
412 break;
413 case 9600000:
414 case 28800000:
415 /*
416 * PLL_P_OUT1 rate is not listed in PLLA table
417 */
418 cfreq = parent_rate/(parent_rate/1000000);
419 break;
420 default:
421 pr_err("%s Unexpected reference rate %lu\n",
422 __func__, parent_rate);
423 BUG();
424 }
425
426 /* Raise VCO to guarantee 0.5% accuracy */
427 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
428 cfg->output_rate <<= 1)
429 p_div++;
430
431 cfg->m = parent_rate / cfreq;
432 cfg->n = cfg->output_rate / cfreq;
433 cfg->cpcon = OUT_OF_TABLE_CPCON;
434
435 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
436 (1 << p_div) > divp_max(pll)
437 || cfg->output_rate > pll->params->vco_max) {
438 return -EINVAL;
439 }
440
441 cfg->output_rate >>= p_div;
442
443 if (pll->params->pdiv_tohw) {
444 ret = _p_div_to_hw(hw, 1 << p_div);
445 if (ret < 0)
446 return ret;
447 else
448 cfg->p = ret;
449 } else
450 cfg->p = p_div;
451
452 return 0;
453 }
454
455 static void _update_pll_mnp(struct tegra_clk_pll *pll,
456 struct tegra_clk_pll_freq_table *cfg)
457 {
458 u32 val;
459 struct tegra_clk_pll_params *params = pll->params;
460 struct div_nmp *div_nmp = params->div_nmp;
461
462 if ((params->flags & TEGRA_PLLM) &&
463 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
464 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
465 val = pll_override_readl(params->pmc_divp_reg, pll);
466 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
467 val |= cfg->p << div_nmp->override_divp_shift;
468 pll_override_writel(val, params->pmc_divp_reg, pll);
469
470 val = pll_override_readl(params->pmc_divnm_reg, pll);
471 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
472 ~(divn_mask(pll) << div_nmp->override_divn_shift);
473 val |= (cfg->m << div_nmp->override_divm_shift) |
474 (cfg->n << div_nmp->override_divn_shift);
475 pll_override_writel(val, params->pmc_divnm_reg, pll);
476 } else {
477 val = pll_readl_base(pll);
478
479 val &= ~((divm_mask(pll) << div_nmp->divm_shift) |
480 (divn_mask(pll) << div_nmp->divn_shift) |
481 (divp_mask(pll) << div_nmp->divp_shift));
482
483 val |= ((cfg->m << div_nmp->divm_shift) |
484 (cfg->n << div_nmp->divn_shift) |
485 (cfg->p << div_nmp->divp_shift));
486
487 pll_writel_base(val, pll);
488 }
489 }
490
491 static void _get_pll_mnp(struct tegra_clk_pll *pll,
492 struct tegra_clk_pll_freq_table *cfg)
493 {
494 u32 val;
495 struct tegra_clk_pll_params *params = pll->params;
496 struct div_nmp *div_nmp = params->div_nmp;
497
498 if ((params->flags & TEGRA_PLLM) &&
499 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
500 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
501 val = pll_override_readl(params->pmc_divp_reg, pll);
502 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
503
504 val = pll_override_readl(params->pmc_divnm_reg, pll);
505 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
506 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
507 } else {
508 val = pll_readl_base(pll);
509
510 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
511 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
512 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
513 }
514 }
515
516 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
517 struct tegra_clk_pll_freq_table *cfg,
518 unsigned long rate)
519 {
520 u32 val;
521
522 val = pll_readl_misc(pll);
523
524 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
525 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
526
527 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
528 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
529 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
530 val |= 1 << PLL_MISC_LFCON_SHIFT;
531 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
532 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
533 if (rate >= (pll->params->vco_max >> 1))
534 val |= 1 << PLL_MISC_DCCON_SHIFT;
535 }
536
537 pll_writel_misc(val, pll);
538 }
539
540 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
541 unsigned long rate)
542 {
543 struct tegra_clk_pll *pll = to_clk_pll(hw);
544 int state, ret = 0;
545
546 state = clk_pll_is_enabled(hw);
547
548 if (state)
549 _clk_pll_disable(hw);
550
551 _update_pll_mnp(pll, cfg);
552
553 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
554 _update_pll_cpcon(pll, cfg, rate);
555
556 if (state) {
557 _clk_pll_enable(hw);
558 ret = clk_pll_wait_for_lock(pll);
559 }
560
561 return ret;
562 }
563
564 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
565 unsigned long parent_rate)
566 {
567 struct tegra_clk_pll *pll = to_clk_pll(hw);
568 struct tegra_clk_pll_freq_table cfg, old_cfg;
569 unsigned long flags = 0;
570 int ret = 0;
571
572 if (pll->params->flags & TEGRA_PLL_FIXED) {
573 if (rate != pll->params->fixed_rate) {
574 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
575 __func__, __clk_get_name(hw->clk),
576 pll->params->fixed_rate, rate);
577 return -EINVAL;
578 }
579 return 0;
580 }
581
582 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
583 _calc_rate(hw, &cfg, rate, parent_rate)) {
584 pr_err("%s: Failed to set %s rate %lu\n", __func__,
585 __clk_get_name(hw->clk), rate);
586 WARN_ON(1);
587 return -EINVAL;
588 }
589 if (pll->lock)
590 spin_lock_irqsave(pll->lock, flags);
591
592 _get_pll_mnp(pll, &old_cfg);
593
594 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
595 ret = _program_pll(hw, &cfg, rate);
596
597 if (pll->lock)
598 spin_unlock_irqrestore(pll->lock, flags);
599
600 return ret;
601 }
602
603 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
604 unsigned long *prate)
605 {
606 struct tegra_clk_pll *pll = to_clk_pll(hw);
607 struct tegra_clk_pll_freq_table cfg;
608
609 if (pll->params->flags & TEGRA_PLL_FIXED)
610 return pll->params->fixed_rate;
611
612 /* PLLM is used for memory; we do not change rate */
613 if (pll->params->flags & TEGRA_PLLM)
614 return __clk_get_rate(hw->clk);
615
616 if (_get_table_rate(hw, &cfg, rate, *prate) &&
617 _calc_rate(hw, &cfg, rate, *prate))
618 return -EINVAL;
619
620 return cfg.output_rate;
621 }
622
623 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
624 unsigned long parent_rate)
625 {
626 struct tegra_clk_pll *pll = to_clk_pll(hw);
627 struct tegra_clk_pll_freq_table cfg;
628 u32 val;
629 u64 rate = parent_rate;
630 int pdiv;
631
632 val = pll_readl_base(pll);
633
634 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
635 return parent_rate;
636
637 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
638 !(val & PLL_BASE_OVERRIDE)) {
639 struct tegra_clk_pll_freq_table sel;
640 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
641 parent_rate)) {
642 pr_err("Clock %s has unknown fixed frequency\n",
643 __clk_get_name(hw->clk));
644 BUG();
645 }
646 return pll->params->fixed_rate;
647 }
648
649 _get_pll_mnp(pll, &cfg);
650
651 pdiv = _hw_to_p_div(hw, cfg.p);
652 if (pdiv < 0) {
653 WARN_ON(1);
654 pdiv = 1;
655 }
656
657 cfg.m *= pdiv;
658
659 rate *= cfg.n;
660 do_div(rate, cfg.m);
661
662 return rate;
663 }
664
665 static int clk_plle_training(struct tegra_clk_pll *pll)
666 {
667 u32 val;
668 unsigned long timeout;
669
670 if (!pll->pmc)
671 return -ENOSYS;
672
673 /*
674 * PLLE is already disabled, and setup cleared;
675 * create falling edge on PLLE IDDQ input.
676 */
677 val = readl(pll->pmc + PMC_SATA_PWRGT);
678 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
679 writel(val, pll->pmc + PMC_SATA_PWRGT);
680
681 val = readl(pll->pmc + PMC_SATA_PWRGT);
682 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
683 writel(val, pll->pmc + PMC_SATA_PWRGT);
684
685 val = readl(pll->pmc + PMC_SATA_PWRGT);
686 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
687 writel(val, pll->pmc + PMC_SATA_PWRGT);
688
689 val = pll_readl_misc(pll);
690
691 timeout = jiffies + msecs_to_jiffies(100);
692 while (1) {
693 val = pll_readl_misc(pll);
694 if (val & PLLE_MISC_READY)
695 break;
696 if (time_after(jiffies, timeout)) {
697 pr_err("%s: timeout waiting for PLLE\n", __func__);
698 return -EBUSY;
699 }
700 udelay(300);
701 }
702
703 return 0;
704 }
705
706 static int clk_plle_enable(struct clk_hw *hw)
707 {
708 struct tegra_clk_pll *pll = to_clk_pll(hw);
709 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
710 struct tegra_clk_pll_freq_table sel;
711 u32 val;
712 int err;
713
714 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
715 return -EINVAL;
716
717 clk_pll_disable(hw);
718
719 val = pll_readl_misc(pll);
720 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
721 pll_writel_misc(val, pll);
722
723 val = pll_readl_misc(pll);
724 if (!(val & PLLE_MISC_READY)) {
725 err = clk_plle_training(pll);
726 if (err)
727 return err;
728 }
729
730 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
731 /* configure dividers */
732 val = pll_readl_base(pll);
733 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
734 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
735 val |= sel.m << pll->params->div_nmp->divm_shift;
736 val |= sel.n << pll->params->div_nmp->divn_shift;
737 val |= sel.p << pll->params->div_nmp->divp_shift;
738 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
739 pll_writel_base(val, pll);
740 }
741
742 val = pll_readl_misc(pll);
743 val |= PLLE_MISC_SETUP_VALUE;
744 val |= PLLE_MISC_LOCK_ENABLE;
745 pll_writel_misc(val, pll);
746
747 val = readl(pll->clk_base + PLLE_SS_CTRL);
748 val |= PLLE_SS_DISABLE;
749 writel(val, pll->clk_base + PLLE_SS_CTRL);
750
751 val |= pll_readl_base(pll);
752 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
753 pll_writel_base(val, pll);
754
755 clk_pll_wait_for_lock(pll);
756
757 return 0;
758 }
759
760 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
761 unsigned long parent_rate)
762 {
763 struct tegra_clk_pll *pll = to_clk_pll(hw);
764 u32 val = pll_readl_base(pll);
765 u32 divn = 0, divm = 0, divp = 0;
766 u64 rate = parent_rate;
767
768 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
769 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
770 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
771 divm *= divp;
772
773 rate *= divn;
774 do_div(rate, divm);
775 return rate;
776 }
777
778 const struct clk_ops tegra_clk_pll_ops = {
779 .is_enabled = clk_pll_is_enabled,
780 .enable = clk_pll_enable,
781 .disable = clk_pll_disable,
782 .recalc_rate = clk_pll_recalc_rate,
783 .round_rate = clk_pll_round_rate,
784 .set_rate = clk_pll_set_rate,
785 };
786
787 const struct clk_ops tegra_clk_plle_ops = {
788 .recalc_rate = clk_plle_recalc_rate,
789 .is_enabled = clk_pll_is_enabled,
790 .disable = clk_pll_disable,
791 .enable = clk_plle_enable,
792 };
793
794 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
795
796 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
797 unsigned long parent_rate)
798 {
799 if (parent_rate > pll_params->cf_max)
800 return 2;
801 else
802 return 1;
803 }
804
805 static unsigned long _clip_vco_min(unsigned long vco_min,
806 unsigned long parent_rate)
807 {
808 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
809 }
810
811 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
812 void __iomem *clk_base,
813 unsigned long parent_rate)
814 {
815 u32 val;
816 u32 step_a, step_b;
817
818 switch (parent_rate) {
819 case 12000000:
820 case 13000000:
821 case 26000000:
822 step_a = 0x2B;
823 step_b = 0x0B;
824 break;
825 case 16800000:
826 step_a = 0x1A;
827 step_b = 0x09;
828 break;
829 case 19200000:
830 step_a = 0x12;
831 step_b = 0x08;
832 break;
833 default:
834 pr_err("%s: Unexpected reference rate %lu\n",
835 __func__, parent_rate);
836 WARN_ON(1);
837 return -EINVAL;
838 }
839
840 val = step_a << pll_params->stepa_shift;
841 val |= step_b << pll_params->stepb_shift;
842 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
843
844 return 0;
845 }
846
847 static int clk_pll_iddq_enable(struct clk_hw *hw)
848 {
849 struct tegra_clk_pll *pll = to_clk_pll(hw);
850 unsigned long flags = 0;
851
852 u32 val;
853 int ret;
854
855 if (pll->lock)
856 spin_lock_irqsave(pll->lock, flags);
857
858 val = pll_readl(pll->params->iddq_reg, pll);
859 val &= ~BIT(pll->params->iddq_bit_idx);
860 pll_writel(val, pll->params->iddq_reg, pll);
861 udelay(2);
862
863 _clk_pll_enable(hw);
864
865 ret = clk_pll_wait_for_lock(pll);
866
867 if (pll->lock)
868 spin_unlock_irqrestore(pll->lock, flags);
869
870 return 0;
871 }
872
873 static void clk_pll_iddq_disable(struct clk_hw *hw)
874 {
875 struct tegra_clk_pll *pll = to_clk_pll(hw);
876 unsigned long flags = 0;
877 u32 val;
878
879 if (pll->lock)
880 spin_lock_irqsave(pll->lock, flags);
881
882 _clk_pll_disable(hw);
883
884 val = pll_readl(pll->params->iddq_reg, pll);
885 val |= BIT(pll->params->iddq_bit_idx);
886 pll_writel(val, pll->params->iddq_reg, pll);
887 udelay(2);
888
889 if (pll->lock)
890 spin_unlock_irqrestore(pll->lock, flags);
891 }
892
893 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
894 struct tegra_clk_pll_freq_table *cfg,
895 unsigned long rate, unsigned long parent_rate)
896 {
897 struct tegra_clk_pll *pll = to_clk_pll(hw);
898 unsigned int p;
899 int p_div;
900
901 if (!rate)
902 return -EINVAL;
903
904 p = DIV_ROUND_UP(pll->params->vco_min, rate);
905 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
906 cfg->output_rate = rate * p;
907 cfg->n = cfg->output_rate * cfg->m / parent_rate;
908
909 p_div = _p_div_to_hw(hw, p);
910 if (p_div < 0)
911 return p_div;
912 else
913 cfg->p = p_div;
914
915 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
916 return -EINVAL;
917
918 return 0;
919 }
920
921 static int _pll_ramp_calc_pll(struct clk_hw *hw,
922 struct tegra_clk_pll_freq_table *cfg,
923 unsigned long rate, unsigned long parent_rate)
924 {
925 struct tegra_clk_pll *pll = to_clk_pll(hw);
926 int err = 0, p_div;
927
928 err = _get_table_rate(hw, cfg, rate, parent_rate);
929 if (err < 0)
930 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
931 else {
932 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
933 WARN_ON(1);
934 err = -EINVAL;
935 goto out;
936 }
937 p_div = _p_div_to_hw(hw, cfg->p);
938 if (p_div < 0)
939 return p_div;
940 else
941 cfg->p = p_div;
942 }
943
944 if (cfg->p > pll->params->max_p)
945 err = -EINVAL;
946
947 out:
948 return err;
949 }
950
951 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
952 unsigned long parent_rate)
953 {
954 struct tegra_clk_pll *pll = to_clk_pll(hw);
955 struct tegra_clk_pll_freq_table cfg, old_cfg;
956 unsigned long flags = 0;
957 int ret = 0;
958
959 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
960 if (ret < 0)
961 return ret;
962
963 if (pll->lock)
964 spin_lock_irqsave(pll->lock, flags);
965
966 _get_pll_mnp(pll, &old_cfg);
967
968 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
969 ret = _program_pll(hw, &cfg, rate);
970
971 if (pll->lock)
972 spin_unlock_irqrestore(pll->lock, flags);
973
974 return ret;
975 }
976
977 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
978 unsigned long *prate)
979 {
980 struct tegra_clk_pll_freq_table cfg;
981 int ret = 0, p_div;
982 u64 output_rate = *prate;
983
984 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
985 if (ret < 0)
986 return ret;
987
988 p_div = _hw_to_p_div(hw, cfg.p);
989 if (p_div < 0)
990 return p_div;
991
992 output_rate *= cfg.n;
993 do_div(output_rate, cfg.m * p_div);
994
995 return output_rate;
996 }
997
998 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
999 unsigned long parent_rate)
1000 {
1001 struct tegra_clk_pll_freq_table cfg;
1002 struct tegra_clk_pll *pll = to_clk_pll(hw);
1003 unsigned long flags = 0;
1004 int state, ret = 0;
1005
1006 if (pll->lock)
1007 spin_lock_irqsave(pll->lock, flags);
1008
1009 state = clk_pll_is_enabled(hw);
1010 if (state) {
1011 if (rate != clk_get_rate(hw->clk)) {
1012 pr_err("%s: Cannot change active PLLM\n", __func__);
1013 ret = -EINVAL;
1014 goto out;
1015 }
1016 goto out;
1017 }
1018
1019 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1020 if (ret < 0)
1021 goto out;
1022
1023 _update_pll_mnp(pll, &cfg);
1024
1025 out:
1026 if (pll->lock)
1027 spin_unlock_irqrestore(pll->lock, flags);
1028
1029 return ret;
1030 }
1031
1032 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1033 {
1034 u32 val;
1035
1036 val = pll_readl_misc(pll);
1037 val |= PLLCX_MISC_STROBE;
1038 pll_writel_misc(val, pll);
1039 udelay(2);
1040
1041 val &= ~PLLCX_MISC_STROBE;
1042 pll_writel_misc(val, pll);
1043 }
1044
1045 static int clk_pllc_enable(struct clk_hw *hw)
1046 {
1047 struct tegra_clk_pll *pll = to_clk_pll(hw);
1048 u32 val;
1049 int ret = 0;
1050 unsigned long flags = 0;
1051
1052 if (pll->lock)
1053 spin_lock_irqsave(pll->lock, flags);
1054
1055 _clk_pll_enable(hw);
1056 udelay(2);
1057
1058 val = pll_readl_misc(pll);
1059 val &= ~PLLCX_MISC_RESET;
1060 pll_writel_misc(val, pll);
1061 udelay(2);
1062
1063 _pllcx_strobe(pll);
1064
1065 ret = clk_pll_wait_for_lock(pll);
1066
1067 if (pll->lock)
1068 spin_unlock_irqrestore(pll->lock, flags);
1069
1070 return ret;
1071 }
1072
1073 static void _clk_pllc_disable(struct clk_hw *hw)
1074 {
1075 struct tegra_clk_pll *pll = to_clk_pll(hw);
1076 u32 val;
1077
1078 _clk_pll_disable(hw);
1079
1080 val = pll_readl_misc(pll);
1081 val |= PLLCX_MISC_RESET;
1082 pll_writel_misc(val, pll);
1083 udelay(2);
1084 }
1085
1086 static void clk_pllc_disable(struct clk_hw *hw)
1087 {
1088 struct tegra_clk_pll *pll = to_clk_pll(hw);
1089 unsigned long flags = 0;
1090
1091 if (pll->lock)
1092 spin_lock_irqsave(pll->lock, flags);
1093
1094 _clk_pllc_disable(hw);
1095
1096 if (pll->lock)
1097 spin_unlock_irqrestore(pll->lock, flags);
1098 }
1099
1100 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1101 unsigned long input_rate, u32 n)
1102 {
1103 u32 val, n_threshold;
1104
1105 switch (input_rate) {
1106 case 12000000:
1107 n_threshold = 70;
1108 break;
1109 case 13000000:
1110 case 26000000:
1111 n_threshold = 71;
1112 break;
1113 case 16800000:
1114 n_threshold = 55;
1115 break;
1116 case 19200000:
1117 n_threshold = 48;
1118 break;
1119 default:
1120 pr_err("%s: Unexpected reference rate %lu\n",
1121 __func__, input_rate);
1122 return -EINVAL;
1123 }
1124
1125 val = pll_readl_misc(pll);
1126 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1127 val |= n <= n_threshold ?
1128 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1129 pll_writel_misc(val, pll);
1130
1131 return 0;
1132 }
1133
1134 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1135 unsigned long parent_rate)
1136 {
1137 struct tegra_clk_pll_freq_table cfg, old_cfg;
1138 struct tegra_clk_pll *pll = to_clk_pll(hw);
1139 unsigned long flags = 0;
1140 int state, ret = 0;
1141
1142 if (pll->lock)
1143 spin_lock_irqsave(pll->lock, flags);
1144
1145 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1146 if (ret < 0)
1147 goto out;
1148
1149 _get_pll_mnp(pll, &old_cfg);
1150
1151 if (cfg.m != old_cfg.m) {
1152 WARN_ON(1);
1153 goto out;
1154 }
1155
1156 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1157 goto out;
1158
1159 state = clk_pll_is_enabled(hw);
1160 if (state)
1161 _clk_pllc_disable(hw);
1162
1163 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1164 if (ret < 0)
1165 goto out;
1166
1167 _update_pll_mnp(pll, &cfg);
1168
1169 if (state)
1170 ret = clk_pllc_enable(hw);
1171
1172 out:
1173 if (pll->lock)
1174 spin_unlock_irqrestore(pll->lock, flags);
1175
1176 return ret;
1177 }
1178
1179 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1180 struct tegra_clk_pll_freq_table *cfg,
1181 unsigned long rate, unsigned long parent_rate)
1182 {
1183 u16 m, n;
1184 u64 output_rate = parent_rate;
1185
1186 m = _pll_fixed_mdiv(pll->params, parent_rate);
1187 n = rate * m / parent_rate;
1188
1189 output_rate *= n;
1190 do_div(output_rate, m);
1191
1192 if (cfg) {
1193 cfg->m = m;
1194 cfg->n = n;
1195 }
1196
1197 return output_rate;
1198 }
1199 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1200 unsigned long parent_rate)
1201 {
1202 struct tegra_clk_pll_freq_table cfg, old_cfg;
1203 struct tegra_clk_pll *pll = to_clk_pll(hw);
1204 unsigned long flags = 0;
1205 int state, ret = 0;
1206
1207 if (pll->lock)
1208 spin_lock_irqsave(pll->lock, flags);
1209
1210 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1211 _get_pll_mnp(pll, &old_cfg);
1212 cfg.p = old_cfg.p;
1213
1214 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1215 state = clk_pll_is_enabled(hw);
1216 if (state)
1217 _clk_pll_disable(hw);
1218
1219 _update_pll_mnp(pll, &cfg);
1220
1221 if (state) {
1222 _clk_pll_enable(hw);
1223 ret = clk_pll_wait_for_lock(pll);
1224 }
1225 }
1226
1227 if (pll->lock)
1228 spin_unlock_irqrestore(pll->lock, flags);
1229
1230 return ret;
1231 }
1232
1233 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1234 unsigned long parent_rate)
1235 {
1236 struct tegra_clk_pll_freq_table cfg;
1237 struct tegra_clk_pll *pll = to_clk_pll(hw);
1238 u64 rate = parent_rate;
1239
1240 _get_pll_mnp(pll, &cfg);
1241
1242 rate *= cfg.n;
1243 do_div(rate, cfg.m);
1244
1245 return rate;
1246 }
1247
1248 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1249 unsigned long *prate)
1250 {
1251 struct tegra_clk_pll *pll = to_clk_pll(hw);
1252
1253 return _pllre_calc_rate(pll, NULL, rate, *prate);
1254 }
1255
1256 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1257 {
1258 struct tegra_clk_pll *pll = to_clk_pll(hw);
1259 struct tegra_clk_pll_freq_table sel;
1260 u32 val;
1261 int ret;
1262 unsigned long flags = 0;
1263 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1264
1265 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1266 return -EINVAL;
1267
1268 if (pll->lock)
1269 spin_lock_irqsave(pll->lock, flags);
1270
1271 val = pll_readl_base(pll);
1272 val &= ~BIT(29); /* Disable lock override */
1273 pll_writel_base(val, pll);
1274
1275 val = pll_readl(pll->params->aux_reg, pll);
1276 val |= PLLE_AUX_ENABLE_SWCTL;
1277 val &= ~PLLE_AUX_SEQ_ENABLE;
1278 pll_writel(val, pll->params->aux_reg, pll);
1279 udelay(1);
1280
1281 val = pll_readl_misc(pll);
1282 val |= PLLE_MISC_LOCK_ENABLE;
1283 val |= PLLE_MISC_IDDQ_SW_CTRL;
1284 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1285 val |= PLLE_MISC_PLLE_PTS;
1286 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1287 pll_writel_misc(val, pll);
1288 udelay(5);
1289
1290 val = pll_readl(PLLE_SS_CTRL, pll);
1291 val |= PLLE_SS_DISABLE;
1292 pll_writel(val, PLLE_SS_CTRL, pll);
1293
1294 val = pll_readl_base(pll);
1295 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
1296 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
1297 val |= sel.m << pll->params->div_nmp->divm_shift;
1298 val |= sel.n << pll->params->div_nmp->divn_shift;
1299 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1300 pll_writel_base(val, pll);
1301 udelay(1);
1302
1303 _clk_pll_enable(hw);
1304 ret = clk_pll_wait_for_lock(pll);
1305
1306 if (ret < 0)
1307 goto out;
1308
1309 val = pll_readl(PLLE_SS_CTRL, pll);
1310 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1311 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1312 val |= PLLE_SS_COEFFICIENTS_VAL;
1313 pll_writel(val, PLLE_SS_CTRL, pll);
1314 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1315 pll_writel(val, PLLE_SS_CTRL, pll);
1316 udelay(1);
1317 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1318 pll_writel(val, PLLE_SS_CTRL, pll);
1319 udelay(1);
1320
1321 /* TODO: enable hw control of xusb brick pll */
1322
1323 out:
1324 if (pll->lock)
1325 spin_unlock_irqrestore(pll->lock, flags);
1326
1327 return ret;
1328 }
1329
1330 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1331 {
1332 struct tegra_clk_pll *pll = to_clk_pll(hw);
1333 unsigned long flags = 0;
1334 u32 val;
1335
1336 if (pll->lock)
1337 spin_lock_irqsave(pll->lock, flags);
1338
1339 _clk_pll_disable(hw);
1340
1341 val = pll_readl_misc(pll);
1342 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1343 pll_writel_misc(val, pll);
1344 udelay(1);
1345
1346 if (pll->lock)
1347 spin_unlock_irqrestore(pll->lock, flags);
1348 }
1349 #endif
1350
1351 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1352 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1353 spinlock_t *lock)
1354 {
1355 struct tegra_clk_pll *pll;
1356
1357 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1358 if (!pll)
1359 return ERR_PTR(-ENOMEM);
1360
1361 pll->clk_base = clk_base;
1362 pll->pmc = pmc;
1363
1364 pll->params = pll_params;
1365 pll->lock = lock;
1366
1367 if (!pll_params->div_nmp)
1368 pll_params->div_nmp = &default_nmp;
1369
1370 return pll;
1371 }
1372
1373 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1374 const char *name, const char *parent_name, unsigned long flags,
1375 const struct clk_ops *ops)
1376 {
1377 struct clk_init_data init;
1378
1379 init.name = name;
1380 init.ops = ops;
1381 init.flags = flags;
1382 init.parent_names = (parent_name ? &parent_name : NULL);
1383 init.num_parents = (parent_name ? 1 : 0);
1384
1385 /* Data in .init is copied by clk_register(), so stack variable OK */
1386 pll->hw.init = &init;
1387
1388 return clk_register(NULL, &pll->hw);
1389 }
1390
1391 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1392 void __iomem *clk_base, void __iomem *pmc,
1393 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1394 spinlock_t *lock)
1395 {
1396 struct tegra_clk_pll *pll;
1397 struct clk *clk;
1398
1399 pll_params->flags |= TEGRA_PLL_BYPASS;
1400 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1401 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1402 if (IS_ERR(pll))
1403 return ERR_CAST(pll);
1404
1405 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1406 &tegra_clk_pll_ops);
1407 if (IS_ERR(clk))
1408 kfree(pll);
1409
1410 return clk;
1411 }
1412
1413 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1414 void __iomem *clk_base, void __iomem *pmc,
1415 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1416 spinlock_t *lock)
1417 {
1418 struct tegra_clk_pll *pll;
1419 struct clk *clk;
1420
1421 pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1422 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1423 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1424 if (IS_ERR(pll))
1425 return ERR_CAST(pll);
1426
1427 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1428 &tegra_clk_plle_ops);
1429 if (IS_ERR(clk))
1430 kfree(pll);
1431
1432 return clk;
1433 }
1434
1435 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
1436 static const struct clk_ops tegra_clk_pllxc_ops = {
1437 .is_enabled = clk_pll_is_enabled,
1438 .enable = clk_pll_iddq_enable,
1439 .disable = clk_pll_iddq_disable,
1440 .recalc_rate = clk_pll_recalc_rate,
1441 .round_rate = clk_pll_ramp_round_rate,
1442 .set_rate = clk_pllxc_set_rate,
1443 };
1444
1445 static const struct clk_ops tegra_clk_pllm_ops = {
1446 .is_enabled = clk_pll_is_enabled,
1447 .enable = clk_pll_iddq_enable,
1448 .disable = clk_pll_iddq_disable,
1449 .recalc_rate = clk_pll_recalc_rate,
1450 .round_rate = clk_pll_ramp_round_rate,
1451 .set_rate = clk_pllm_set_rate,
1452 };
1453
1454 static const struct clk_ops tegra_clk_pllc_ops = {
1455 .is_enabled = clk_pll_is_enabled,
1456 .enable = clk_pllc_enable,
1457 .disable = clk_pllc_disable,
1458 .recalc_rate = clk_pll_recalc_rate,
1459 .round_rate = clk_pll_ramp_round_rate,
1460 .set_rate = clk_pllc_set_rate,
1461 };
1462
1463 static const struct clk_ops tegra_clk_pllre_ops = {
1464 .is_enabled = clk_pll_is_enabled,
1465 .enable = clk_pll_iddq_enable,
1466 .disable = clk_pll_iddq_disable,
1467 .recalc_rate = clk_pllre_recalc_rate,
1468 .round_rate = clk_pllre_round_rate,
1469 .set_rate = clk_pllre_set_rate,
1470 };
1471
1472 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1473 .is_enabled = clk_pll_is_enabled,
1474 .enable = clk_plle_tegra114_enable,
1475 .disable = clk_plle_tegra114_disable,
1476 .recalc_rate = clk_pll_recalc_rate,
1477 };
1478
1479
1480 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1481 void __iomem *clk_base, void __iomem *pmc,
1482 unsigned long flags,
1483 struct tegra_clk_pll_params *pll_params,
1484 spinlock_t *lock)
1485 {
1486 struct tegra_clk_pll *pll;
1487 struct clk *clk, *parent;
1488 unsigned long parent_rate;
1489 int err;
1490 u32 val, val_iddq;
1491
1492 parent = __clk_lookup(parent_name);
1493 if (!parent) {
1494 WARN(1, "parent clk %s of %s must be registered first\n",
1495 name, parent_name);
1496 return ERR_PTR(-EINVAL);
1497 }
1498
1499 if (!pll_params->pdiv_tohw)
1500 return ERR_PTR(-EINVAL);
1501
1502 parent_rate = __clk_get_rate(parent);
1503
1504 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1505
1506 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1507 if (err)
1508 return ERR_PTR(err);
1509
1510 val = readl_relaxed(clk_base + pll_params->base_reg);
1511 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1512
1513 if (val & PLL_BASE_ENABLE)
1514 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1515 else {
1516 val_iddq |= BIT(pll_params->iddq_bit_idx);
1517 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1518 }
1519
1520 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1521 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1522 if (IS_ERR(pll))
1523 return ERR_CAST(pll);
1524
1525 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1526 &tegra_clk_pllxc_ops);
1527 if (IS_ERR(clk))
1528 kfree(pll);
1529
1530 return clk;
1531 }
1532
1533 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1534 void __iomem *clk_base, void __iomem *pmc,
1535 unsigned long flags,
1536 struct tegra_clk_pll_params *pll_params,
1537 spinlock_t *lock, unsigned long parent_rate)
1538 {
1539 u32 val;
1540 struct tegra_clk_pll *pll;
1541 struct clk *clk;
1542
1543 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
1544
1545 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1546
1547 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1548 if (IS_ERR(pll))
1549 return ERR_CAST(pll);
1550
1551 /* program minimum rate by default */
1552
1553 val = pll_readl_base(pll);
1554 if (val & PLL_BASE_ENABLE)
1555 WARN_ON(val & pll_params->iddq_bit_idx);
1556 else {
1557 int m;
1558
1559 m = _pll_fixed_mdiv(pll_params, parent_rate);
1560 val = m << PLL_BASE_DIVM_SHIFT;
1561 val |= (pll_params->vco_min / parent_rate)
1562 << PLL_BASE_DIVN_SHIFT;
1563 pll_writel_base(val, pll);
1564 }
1565
1566 /* disable lock override */
1567
1568 val = pll_readl_misc(pll);
1569 val &= ~BIT(29);
1570 pll_writel_misc(val, pll);
1571
1572 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1573 &tegra_clk_pllre_ops);
1574 if (IS_ERR(clk))
1575 kfree(pll);
1576
1577 return clk;
1578 }
1579
1580 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1581 void __iomem *clk_base, void __iomem *pmc,
1582 unsigned long flags,
1583 struct tegra_clk_pll_params *pll_params,
1584 spinlock_t *lock)
1585 {
1586 struct tegra_clk_pll *pll;
1587 struct clk *clk, *parent;
1588 unsigned long parent_rate;
1589
1590 if (!pll_params->pdiv_tohw)
1591 return ERR_PTR(-EINVAL);
1592
1593 parent = __clk_lookup(parent_name);
1594 if (!parent) {
1595 WARN(1, "parent clk %s of %s must be registered first\n",
1596 name, parent_name);
1597 return ERR_PTR(-EINVAL);
1598 }
1599
1600 parent_rate = __clk_get_rate(parent);
1601
1602 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1603
1604 pll_params->flags |= TEGRA_PLL_BYPASS;
1605 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1606 pll_params->flags |= TEGRA_PLLM;
1607 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1608 if (IS_ERR(pll))
1609 return ERR_CAST(pll);
1610
1611 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1612 &tegra_clk_pllm_ops);
1613 if (IS_ERR(clk))
1614 kfree(pll);
1615
1616 return clk;
1617 }
1618
1619 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1620 void __iomem *clk_base, void __iomem *pmc,
1621 unsigned long flags,
1622 struct tegra_clk_pll_params *pll_params,
1623 spinlock_t *lock)
1624 {
1625 struct clk *parent, *clk;
1626 struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1627 struct tegra_clk_pll *pll;
1628 struct tegra_clk_pll_freq_table cfg;
1629 unsigned long parent_rate;
1630
1631 if (!p_tohw)
1632 return ERR_PTR(-EINVAL);
1633
1634 parent = __clk_lookup(parent_name);
1635 if (!parent) {
1636 WARN(1, "parent clk %s of %s must be registered first\n",
1637 name, parent_name);
1638 return ERR_PTR(-EINVAL);
1639 }
1640
1641 parent_rate = __clk_get_rate(parent);
1642
1643 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1644
1645 pll_params->flags |= TEGRA_PLL_BYPASS;
1646 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1647 if (IS_ERR(pll))
1648 return ERR_CAST(pll);
1649
1650 /*
1651 * Most of PLLC register fields are shadowed, and can not be read
1652 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1653 * Initialize PLL to default state: disabled, reset; shadow registers
1654 * loaded with default parameters; dividers are preset for half of
1655 * minimum VCO rate (the latter assured that shadowed divider settings
1656 * are within supported range).
1657 */
1658
1659 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1660 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1661
1662 while (p_tohw->pdiv) {
1663 if (p_tohw->pdiv == 2) {
1664 cfg.p = p_tohw->hw_val;
1665 break;
1666 }
1667 p_tohw++;
1668 }
1669
1670 if (!p_tohw->pdiv) {
1671 WARN_ON(1);
1672 return ERR_PTR(-EINVAL);
1673 }
1674
1675 pll_writel_base(0, pll);
1676 _update_pll_mnp(pll, &cfg);
1677
1678 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1679 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1680 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1681 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1682
1683 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1684
1685 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1686 &tegra_clk_pllc_ops);
1687 if (IS_ERR(clk))
1688 kfree(pll);
1689
1690 return clk;
1691 }
1692
1693 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1694 const char *parent_name,
1695 void __iomem *clk_base, unsigned long flags,
1696 struct tegra_clk_pll_params *pll_params,
1697 spinlock_t *lock)
1698 {
1699 struct tegra_clk_pll *pll;
1700 struct clk *clk;
1701 u32 val, val_aux;
1702
1703 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1704 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1705 if (IS_ERR(pll))
1706 return ERR_CAST(pll);
1707
1708 /* ensure parent is set to pll_re_vco */
1709
1710 val = pll_readl_base(pll);
1711 val_aux = pll_readl(pll_params->aux_reg, pll);
1712
1713 if (val & PLL_BASE_ENABLE) {
1714 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1715 (val_aux & PLLE_AUX_PLLP_SEL))
1716 WARN(1, "pll_e enabled with unsupported parent %s\n",
1717 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1718 "pll_re_vco");
1719 } else {
1720 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1721 pll_writel(val, pll_params->aux_reg, pll);
1722 }
1723
1724 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1725 &tegra_clk_plle_tegra114_ops);
1726 if (IS_ERR(clk))
1727 kfree(pll);
1728
1729 return clk;
1730 }
1731 #endif
1732
1733 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1734 static const struct clk_ops tegra_clk_pllss_ops = {
1735 .is_enabled = clk_pll_is_enabled,
1736 .enable = clk_pll_iddq_enable,
1737 .disable = clk_pll_iddq_disable,
1738 .recalc_rate = clk_pll_recalc_rate,
1739 .round_rate = clk_pll_ramp_round_rate,
1740 .set_rate = clk_pllxc_set_rate,
1741 };
1742
1743 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1744 void __iomem *clk_base, unsigned long flags,
1745 struct tegra_clk_pll_params *pll_params,
1746 spinlock_t *lock)
1747 {
1748 struct tegra_clk_pll *pll;
1749 struct clk *clk, *parent;
1750 struct tegra_clk_pll_freq_table cfg;
1751 unsigned long parent_rate;
1752 u32 val;
1753 int i;
1754
1755 if (!pll_params->div_nmp)
1756 return ERR_PTR(-EINVAL);
1757
1758 parent = __clk_lookup(parent_name);
1759 if (!parent) {
1760 WARN(1, "parent clk %s of %s must be registered first\n",
1761 name, parent_name);
1762 return ERR_PTR(-EINVAL);
1763 }
1764
1765 pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK;
1766 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1767 if (IS_ERR(pll))
1768 return ERR_CAST(pll);
1769
1770 val = pll_readl_base(pll);
1771 val &= ~PLLSS_REF_SRC_SEL_MASK;
1772 pll_writel_base(val, pll);
1773
1774 parent_rate = __clk_get_rate(parent);
1775
1776 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1777
1778 /* initialize PLL to minimum rate */
1779
1780 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1781 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1782
1783 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
1784 ;
1785 if (!i) {
1786 kfree(pll);
1787 return ERR_PTR(-EINVAL);
1788 }
1789
1790 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
1791
1792 _update_pll_mnp(pll, &cfg);
1793
1794 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
1795 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
1796 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
1797 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1798
1799 val = pll_readl_base(pll);
1800 if (val & PLL_BASE_ENABLE) {
1801 if (val & BIT(pll_params->iddq_bit_idx)) {
1802 WARN(1, "%s is on but IDDQ set\n", name);
1803 kfree(pll);
1804 return ERR_PTR(-EINVAL);
1805 }
1806 } else
1807 val |= BIT(pll_params->iddq_bit_idx);
1808
1809 val &= ~PLLSS_LOCK_OVERRIDE;
1810 pll_writel_base(val, pll);
1811
1812 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1813 &tegra_clk_pllss_ops);
1814
1815 if (IS_ERR(clk))
1816 kfree(pll);
1817
1818 return clk;
1819 }
1820 #endif
Linux with added FPC-III support