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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / tty / serial / bcm63xx_uart.c
blob78e82b017b928bb55982cb4b015a2e81a6862c46
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from many drivers using generic_serial interface.
7 *
8 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
9 *
10 * Serial driver for BCM63xx integrated UART.
11 *
12 * Hardware flow control was _not_ tested since I only have RX/TX on
13 * my board.
14 */
15
16 #if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
17 #define SUPPORT_SYSRQ
18 #endif
19
20 #include <linux/kernel.h>
21 #include <linux/platform_device.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/console.h>
26 #include <linux/clk.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/sysrq.h>
30 #include <linux/serial.h>
31 #include <linux/serial_core.h>
32 #include <linux/serial_bcm63xx.h>
33
34 #define BCM63XX_NR_UARTS 2
35
36 static struct uart_port ports[BCM63XX_NR_UARTS];
37
38 /*
39 * rx interrupt mask / stat
40 *
41 * mask:
42 * - rx fifo full
43 * - rx fifo above threshold
44 * - rx fifo not empty for too long
45 */
46 #define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \
47 UART_IR_MASK(UART_IR_RXTHRESH) | \
48 UART_IR_MASK(UART_IR_RXTIMEOUT))
49
50 #define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \
51 UART_IR_STAT(UART_IR_RXTHRESH) | \
52 UART_IR_STAT(UART_IR_RXTIMEOUT))
53
54 /*
55 * tx interrupt mask / stat
56 *
57 * mask:
58 * - tx fifo empty
59 * - tx fifo below threshold
60 */
61 #define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \
62 UART_IR_MASK(UART_IR_TXTRESH))
63
64 #define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \
65 UART_IR_STAT(UART_IR_TXTRESH))
66
67 /*
68 * external input interrupt
69 *
70 * mask: any edge on CTS, DCD
71 */
72 #define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
73 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
74
75 /*
76 * handy uart register accessor
77 */
78 static inline unsigned int bcm_uart_readl(struct uart_port *port,
79 unsigned int offset)
80 {
81 return __raw_readl(port->membase + offset);
82 }
83
84 static inline void bcm_uart_writel(struct uart_port *port,
85 unsigned int value, unsigned int offset)
86 {
87 __raw_writel(value, port->membase + offset);
88 }
89
90 /*
91 * serial core request to check if uart tx fifo is empty
92 */
93 static unsigned int bcm_uart_tx_empty(struct uart_port *port)
94 {
95 unsigned int val;
96
97 val = bcm_uart_readl(port, UART_IR_REG);
98 return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
99 }
100
101 /*
102 * serial core request to set RTS and DTR pin state and loopback mode
103 */
104 static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
105 {
106 unsigned int val;
107
108 val = bcm_uart_readl(port, UART_MCTL_REG);
109 val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
110 /* invert of written value is reflected on the pin */
111 if (!(mctrl & TIOCM_DTR))
112 val |= UART_MCTL_DTR_MASK;
113 if (!(mctrl & TIOCM_RTS))
114 val |= UART_MCTL_RTS_MASK;
115 bcm_uart_writel(port, val, UART_MCTL_REG);
116
117 val = bcm_uart_readl(port, UART_CTL_REG);
118 if (mctrl & TIOCM_LOOP)
119 val |= UART_CTL_LOOPBACK_MASK;
120 else
121 val &= ~UART_CTL_LOOPBACK_MASK;
122 bcm_uart_writel(port, val, UART_CTL_REG);
123 }
124
125 /*
126 * serial core request to return RI, CTS, DCD and DSR pin state
127 */
128 static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
129 {
130 unsigned int val, mctrl;
131
132 mctrl = 0;
133 val = bcm_uart_readl(port, UART_EXTINP_REG);
134 if (val & UART_EXTINP_RI_MASK)
135 mctrl |= TIOCM_RI;
136 if (val & UART_EXTINP_CTS_MASK)
137 mctrl |= TIOCM_CTS;
138 if (val & UART_EXTINP_DCD_MASK)
139 mctrl |= TIOCM_CD;
140 if (val & UART_EXTINP_DSR_MASK)
141 mctrl |= TIOCM_DSR;
142 return mctrl;
143 }
144
145 /*
146 * serial core request to disable tx ASAP (used for flow control)
147 */
148 static void bcm_uart_stop_tx(struct uart_port *port)
149 {
150 unsigned int val;
151
152 val = bcm_uart_readl(port, UART_CTL_REG);
153 val &= ~(UART_CTL_TXEN_MASK);
154 bcm_uart_writel(port, val, UART_CTL_REG);
155
156 val = bcm_uart_readl(port, UART_IR_REG);
157 val &= ~UART_TX_INT_MASK;
158 bcm_uart_writel(port, val, UART_IR_REG);
159 }
160
161 /*
162 * serial core request to (re)enable tx
163 */
164 static void bcm_uart_start_tx(struct uart_port *port)
165 {
166 unsigned int val;
167
168 val = bcm_uart_readl(port, UART_IR_REG);
169 val |= UART_TX_INT_MASK;
170 bcm_uart_writel(port, val, UART_IR_REG);
171
172 val = bcm_uart_readl(port, UART_CTL_REG);
173 val |= UART_CTL_TXEN_MASK;
174 bcm_uart_writel(port, val, UART_CTL_REG);
175 }
176
177 /*
178 * serial core request to stop rx, called before port shutdown
179 */
180 static void bcm_uart_stop_rx(struct uart_port *port)
181 {
182 unsigned int val;
183
184 val = bcm_uart_readl(port, UART_IR_REG);
185 val &= ~UART_RX_INT_MASK;
186 bcm_uart_writel(port, val, UART_IR_REG);
187 }
188
189 /*
190 * serial core request to enable modem status interrupt reporting
191 */
192 static void bcm_uart_enable_ms(struct uart_port *port)
193 {
194 unsigned int val;
195
196 val = bcm_uart_readl(port, UART_IR_REG);
197 val |= UART_IR_MASK(UART_IR_EXTIP);
198 bcm_uart_writel(port, val, UART_IR_REG);
199 }
200
201 /*
202 * serial core request to start/stop emitting break char
203 */
204 static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
205 {
206 unsigned long flags;
207 unsigned int val;
208
209 spin_lock_irqsave(&port->lock, flags);
210
211 val = bcm_uart_readl(port, UART_CTL_REG);
212 if (ctl)
213 val |= UART_CTL_XMITBRK_MASK;
214 else
215 val &= ~UART_CTL_XMITBRK_MASK;
216 bcm_uart_writel(port, val, UART_CTL_REG);
217
218 spin_unlock_irqrestore(&port->lock, flags);
219 }
220
221 /*
222 * return port type in string format
223 */
224 static const char *bcm_uart_type(struct uart_port *port)
225 {
226 return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
227 }
228
229 /*
230 * read all chars in rx fifo and send them to core
231 */
232 static void bcm_uart_do_rx(struct uart_port *port)
233 {
234 struct tty_port *tty_port = &port->state->port;
235 unsigned int max_count;
236
237 /* limit number of char read in interrupt, should not be
238 * higher than fifo size anyway since we're much faster than
239 * serial port */
240 max_count = 32;
241 do {
242 unsigned int iestat, c, cstat;
243 char flag;
244
245 /* get overrun/fifo empty information from ier
246 * register */
247 iestat = bcm_uart_readl(port, UART_IR_REG);
248
249 if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
250 unsigned int val;
251
252 /* fifo reset is required to clear
253 * interrupt */
254 val = bcm_uart_readl(port, UART_CTL_REG);
255 val |= UART_CTL_RSTRXFIFO_MASK;
256 bcm_uart_writel(port, val, UART_CTL_REG);
257
258 port->icount.overrun++;
259 tty_insert_flip_char(tty_port, 0, TTY_OVERRUN);
260 }
261
262 if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
263 break;
264
265 cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
266 port->icount.rx++;
267 flag = TTY_NORMAL;
268 c &= 0xff;
269
270 if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
271 /* do stats first */
272 if (cstat & UART_FIFO_BRKDET_MASK) {
273 port->icount.brk++;
274 if (uart_handle_break(port))
275 continue;
276 }
277
278 if (cstat & UART_FIFO_PARERR_MASK)
279 port->icount.parity++;
280 if (cstat & UART_FIFO_FRAMEERR_MASK)
281 port->icount.frame++;
282
283 /* update flag wrt read_status_mask */
284 cstat &= port->read_status_mask;
285 if (cstat & UART_FIFO_BRKDET_MASK)
286 flag = TTY_BREAK;
287 if (cstat & UART_FIFO_FRAMEERR_MASK)
288 flag = TTY_FRAME;
289 if (cstat & UART_FIFO_PARERR_MASK)
290 flag = TTY_PARITY;
291 }
292
293 if (uart_handle_sysrq_char(port, c))
294 continue;
295
296
297 if ((cstat & port->ignore_status_mask) == 0)
298 tty_insert_flip_char(tty_port, c, flag);
299
300 } while (--max_count);
301
302 spin_unlock(&port->lock);
303 tty_flip_buffer_push(tty_port);
304 spin_lock(&port->lock);
305 }
306
307 /*
308 * fill tx fifo with chars to send, stop when fifo is about to be full
309 * or when all chars have been sent.
310 */
311 static void bcm_uart_do_tx(struct uart_port *port)
312 {
313 struct circ_buf *xmit;
314 unsigned int val, max_count;
315
316 if (port->x_char) {
317 bcm_uart_writel(port, port->x_char, UART_FIFO_REG);
318 port->icount.tx++;
319 port->x_char = 0;
320 return;
321 }
322
323 if (uart_tx_stopped(port)) {
324 bcm_uart_stop_tx(port);
325 return;
326 }
327
328 xmit = &port->state->xmit;
329 if (uart_circ_empty(xmit))
330 goto txq_empty;
331
332 val = bcm_uart_readl(port, UART_MCTL_REG);
333 val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
334 max_count = port->fifosize - val;
335
336 while (max_count--) {
337 unsigned int c;
338
339 c = xmit->buf[xmit->tail];
340 bcm_uart_writel(port, c, UART_FIFO_REG);
341 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
342 port->icount.tx++;
343 if (uart_circ_empty(xmit))
344 break;
345 }
346
347 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
348 uart_write_wakeup(port);
349
350 if (uart_circ_empty(xmit))
351 goto txq_empty;
352 return;
353
354 txq_empty:
355 /* nothing to send, disable transmit interrupt */
356 val = bcm_uart_readl(port, UART_IR_REG);
357 val &= ~UART_TX_INT_MASK;
358 bcm_uart_writel(port, val, UART_IR_REG);
359 return;
360 }
361
362 /*
363 * process uart interrupt
364 */
365 static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
366 {
367 struct uart_port *port;
368 unsigned int irqstat;
369
370 port = dev_id;
371 spin_lock(&port->lock);
372
373 irqstat = bcm_uart_readl(port, UART_IR_REG);
374 if (irqstat & UART_RX_INT_STAT)
375 bcm_uart_do_rx(port);
376
377 if (irqstat & UART_TX_INT_STAT)
378 bcm_uart_do_tx(port);
379
380 if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
381 unsigned int estat;
382
383 estat = bcm_uart_readl(port, UART_EXTINP_REG);
384 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
385 uart_handle_cts_change(port,
386 estat & UART_EXTINP_CTS_MASK);
387 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
388 uart_handle_dcd_change(port,
389 estat & UART_EXTINP_DCD_MASK);
390 }
391
392 spin_unlock(&port->lock);
393 return IRQ_HANDLED;
394 }
395
396 /*
397 * enable rx & tx operation on uart
398 */
399 static void bcm_uart_enable(struct uart_port *port)
400 {
401 unsigned int val;
402
403 val = bcm_uart_readl(port, UART_CTL_REG);
404 val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
405 bcm_uart_writel(port, val, UART_CTL_REG);
406 }
407
408 /*
409 * disable rx & tx operation on uart
410 */
411 static void bcm_uart_disable(struct uart_port *port)
412 {
413 unsigned int val;
414
415 val = bcm_uart_readl(port, UART_CTL_REG);
416 val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
417 UART_CTL_RXEN_MASK);
418 bcm_uart_writel(port, val, UART_CTL_REG);
419 }
420
421 /*
422 * clear all unread data in rx fifo and unsent data in tx fifo
423 */
424 static void bcm_uart_flush(struct uart_port *port)
425 {
426 unsigned int val;
427
428 /* empty rx and tx fifo */
429 val = bcm_uart_readl(port, UART_CTL_REG);
430 val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
431 bcm_uart_writel(port, val, UART_CTL_REG);
432
433 /* read any pending char to make sure all irq status are
434 * cleared */
435 (void)bcm_uart_readl(port, UART_FIFO_REG);
436 }
437
438 /*
439 * serial core request to initialize uart and start rx operation
440 */
441 static int bcm_uart_startup(struct uart_port *port)
442 {
443 unsigned int val;
444 int ret;
445
446 /* mask all irq and flush port */
447 bcm_uart_disable(port);
448 bcm_uart_writel(port, 0, UART_IR_REG);
449 bcm_uart_flush(port);
450
451 /* clear any pending external input interrupt */
452 (void)bcm_uart_readl(port, UART_EXTINP_REG);
453
454 /* set rx/tx fifo thresh to fifo half size */
455 val = bcm_uart_readl(port, UART_MCTL_REG);
456 val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
457 val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
458 val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
459 bcm_uart_writel(port, val, UART_MCTL_REG);
460
461 /* set rx fifo timeout to 1 char time */
462 val = bcm_uart_readl(port, UART_CTL_REG);
463 val &= ~UART_CTL_RXTMOUTCNT_MASK;
464 val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
465 bcm_uart_writel(port, val, UART_CTL_REG);
466
467 /* report any edge on dcd and cts */
468 val = UART_EXTINP_INT_MASK;
469 val |= UART_EXTINP_DCD_NOSENSE_MASK;
470 val |= UART_EXTINP_CTS_NOSENSE_MASK;
471 bcm_uart_writel(port, val, UART_EXTINP_REG);
472
473 /* register irq and enable rx interrupts */
474 ret = request_irq(port->irq, bcm_uart_interrupt, 0,
475 bcm_uart_type(port), port);
476 if (ret)
477 return ret;
478 bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
479 bcm_uart_enable(port);
480 return 0;
481 }
482
483 /*
484 * serial core request to flush & disable uart
485 */
486 static void bcm_uart_shutdown(struct uart_port *port)
487 {
488 unsigned long flags;
489
490 spin_lock_irqsave(&port->lock, flags);
491 bcm_uart_writel(port, 0, UART_IR_REG);
492 spin_unlock_irqrestore(&port->lock, flags);
493
494 bcm_uart_disable(port);
495 bcm_uart_flush(port);
496 free_irq(port->irq, port);
497 }
498
499 /*
500 * serial core request to change current uart setting
501 */
502 static void bcm_uart_set_termios(struct uart_port *port,
503 struct ktermios *new,
504 struct ktermios *old)
505 {
506 unsigned int ctl, baud, quot, ier;
507 unsigned long flags;
508
509 spin_lock_irqsave(&port->lock, flags);
510
511 /* disable uart while changing speed */
512 bcm_uart_disable(port);
513 bcm_uart_flush(port);
514
515 /* update Control register */
516 ctl = bcm_uart_readl(port, UART_CTL_REG);
517 ctl &= ~UART_CTL_BITSPERSYM_MASK;
518
519 switch (new->c_cflag & CSIZE) {
520 case CS5:
521 ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
522 break;
523 case CS6:
524 ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
525 break;
526 case CS7:
527 ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
528 break;
529 default:
530 ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
531 break;
532 }
533
534 ctl &= ~UART_CTL_STOPBITS_MASK;
535 if (new->c_cflag & CSTOPB)
536 ctl |= UART_CTL_STOPBITS_2;
537 else
538 ctl |= UART_CTL_STOPBITS_1;
539
540 ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
541 if (new->c_cflag & PARENB)
542 ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
543 ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
544 if (new->c_cflag & PARODD)
545 ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
546 bcm_uart_writel(port, ctl, UART_CTL_REG);
547
548 /* update Baudword register */
549 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
550 quot = uart_get_divisor(port, baud) - 1;
551 bcm_uart_writel(port, quot, UART_BAUD_REG);
552
553 /* update Interrupt register */
554 ier = bcm_uart_readl(port, UART_IR_REG);
555
556 ier &= ~UART_IR_MASK(UART_IR_EXTIP);
557 if (UART_ENABLE_MS(port, new->c_cflag))
558 ier |= UART_IR_MASK(UART_IR_EXTIP);
559
560 bcm_uart_writel(port, ier, UART_IR_REG);
561
562 /* update read/ignore mask */
563 port->read_status_mask = UART_FIFO_VALID_MASK;
564 if (new->c_iflag & INPCK) {
565 port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
566 port->read_status_mask |= UART_FIFO_PARERR_MASK;
567 }
568 if (new->c_iflag & (BRKINT))
569 port->read_status_mask |= UART_FIFO_BRKDET_MASK;
570
571 port->ignore_status_mask = 0;
572 if (new->c_iflag & IGNPAR)
573 port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
574 if (new->c_iflag & IGNBRK)
575 port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
576 if (!(new->c_cflag & CREAD))
577 port->ignore_status_mask |= UART_FIFO_VALID_MASK;
578
579 uart_update_timeout(port, new->c_cflag, baud);
580 bcm_uart_enable(port);
581 spin_unlock_irqrestore(&port->lock, flags);
582 }
583
584 /*
585 * serial core request to claim uart iomem
586 */
587 static int bcm_uart_request_port(struct uart_port *port)
588 {
589 unsigned int size;
590
591 size = RSET_UART_SIZE;
592 if (!request_mem_region(port->mapbase, size, "bcm63xx")) {
593 dev_err(port->dev, "Memory region busy\n");
594 return -EBUSY;
595 }
596
597 port->membase = ioremap(port->mapbase, size);
598 if (!port->membase) {
599 dev_err(port->dev, "Unable to map registers\n");
600 release_mem_region(port->mapbase, size);
601 return -EBUSY;
602 }
603 return 0;
604 }
605
606 /*
607 * serial core request to release uart iomem
608 */
609 static void bcm_uart_release_port(struct uart_port *port)
610 {
611 release_mem_region(port->mapbase, RSET_UART_SIZE);
612 iounmap(port->membase);
613 }
614
615 /*
616 * serial core request to do any port required autoconfiguration
617 */
618 static void bcm_uart_config_port(struct uart_port *port, int flags)
619 {
620 if (flags & UART_CONFIG_TYPE) {
621 if (bcm_uart_request_port(port))
622 return;
623 port->type = PORT_BCM63XX;
624 }
625 }
626
627 /*
628 * serial core request to check that port information in serinfo are
629 * suitable
630 */
631 static int bcm_uart_verify_port(struct uart_port *port,
632 struct serial_struct *serinfo)
633 {
634 if (port->type != PORT_BCM63XX)
635 return -EINVAL;
636 if (port->irq != serinfo->irq)
637 return -EINVAL;
638 if (port->iotype != serinfo->io_type)
639 return -EINVAL;
640 if (port->mapbase != (unsigned long)serinfo->iomem_base)
641 return -EINVAL;
642 return 0;
643 }
644
645 /* serial core callbacks */
646 static struct uart_ops bcm_uart_ops = {
647 .tx_empty = bcm_uart_tx_empty,
648 .get_mctrl = bcm_uart_get_mctrl,
649 .set_mctrl = bcm_uart_set_mctrl,
650 .start_tx = bcm_uart_start_tx,
651 .stop_tx = bcm_uart_stop_tx,
652 .stop_rx = bcm_uart_stop_rx,
653 .enable_ms = bcm_uart_enable_ms,
654 .break_ctl = bcm_uart_break_ctl,
655 .startup = bcm_uart_startup,
656 .shutdown = bcm_uart_shutdown,
657 .set_termios = bcm_uart_set_termios,
658 .type = bcm_uart_type,
659 .release_port = bcm_uart_release_port,
660 .request_port = bcm_uart_request_port,
661 .config_port = bcm_uart_config_port,
662 .verify_port = bcm_uart_verify_port,
663 };
664
665
666
667 #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
668 static inline void wait_for_xmitr(struct uart_port *port)
669 {
670 unsigned int tmout;
671
672 /* Wait up to 10ms for the character(s) to be sent. */
673 tmout = 10000;
674 while (--tmout) {
675 unsigned int val;
676
677 val = bcm_uart_readl(port, UART_IR_REG);
678 if (val & UART_IR_STAT(UART_IR_TXEMPTY))
679 break;
680 udelay(1);
681 }
682
683 /* Wait up to 1s for flow control if necessary */
684 if (port->flags & UPF_CONS_FLOW) {
685 tmout = 1000000;
686 while (--tmout) {
687 unsigned int val;
688
689 val = bcm_uart_readl(port, UART_EXTINP_REG);
690 if (val & UART_EXTINP_CTS_MASK)
691 break;
692 udelay(1);
693 }
694 }
695 }
696
697 /*
698 * output given char
699 */
700 static void bcm_console_putchar(struct uart_port *port, int ch)
701 {
702 wait_for_xmitr(port);
703 bcm_uart_writel(port, ch, UART_FIFO_REG);
704 }
705
706 /*
707 * console core request to output given string
708 */
709 static void bcm_console_write(struct console *co, const char *s,
710 unsigned int count)
711 {
712 struct uart_port *port;
713 unsigned long flags;
714 int locked;
715
716 port = &ports[co->index];
717
718 local_irq_save(flags);
719 if (port->sysrq) {
720 /* bcm_uart_interrupt() already took the lock */
721 locked = 0;
722 } else if (oops_in_progress) {
723 locked = spin_trylock(&port->lock);
724 } else {
725 spin_lock(&port->lock);
726 locked = 1;
727 }
728
729 /* call helper to deal with \r\n */
730 uart_console_write(port, s, count, bcm_console_putchar);
731
732 /* and wait for char to be transmitted */
733 wait_for_xmitr(port);
734
735 if (locked)
736 spin_unlock(&port->lock);
737 local_irq_restore(flags);
738 }
739
740 /*
741 * console core request to setup given console, find matching uart
742 * port and setup it.
743 */
744 static int bcm_console_setup(struct console *co, char *options)
745 {
746 struct uart_port *port;
747 int baud = 9600;
748 int bits = 8;
749 int parity = 'n';
750 int flow = 'n';
751
752 if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
753 return -EINVAL;
754 port = &ports[co->index];
755 if (!port->membase)
756 return -ENODEV;
757 if (options)
758 uart_parse_options(options, &baud, &parity, &bits, &flow);
759
760 return uart_set_options(port, co, baud, parity, bits, flow);
761 }
762
763 static struct uart_driver bcm_uart_driver;
764
765 static struct console bcm63xx_console = {
766 .name = "ttyS",
767 .write = bcm_console_write,
768 .device = uart_console_device,
769 .setup = bcm_console_setup,
770 .flags = CON_PRINTBUFFER,
771 .index = -1,
772 .data = &bcm_uart_driver,
773 };
774
775 static int __init bcm63xx_console_init(void)
776 {
777 register_console(&bcm63xx_console);
778 return 0;
779 }
780
781 console_initcall(bcm63xx_console_init);
782
783 #define BCM63XX_CONSOLE (&bcm63xx_console)
784 #else
785 #define BCM63XX_CONSOLE NULL
786 #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
787
788 static struct uart_driver bcm_uart_driver = {
789 .owner = THIS_MODULE,
790 .driver_name = "bcm63xx_uart",
791 .dev_name = "ttyS",
792 .major = TTY_MAJOR,
793 .minor = 64,
794 .nr = BCM63XX_NR_UARTS,
795 .cons = BCM63XX_CONSOLE,
796 };
797
798 /*
799 * platform driver probe/remove callback
800 */
801 static int bcm_uart_probe(struct platform_device *pdev)
802 {
803 struct resource *res_mem, *res_irq;
804 struct uart_port *port;
805 struct clk *clk;
806 int ret;
807
808 if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
809 return -EINVAL;
810
811 if (ports[pdev->id].membase)
812 return -EBUSY;
813
814 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
815 if (!res_mem)
816 return -ENODEV;
817
818 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
819 if (!res_irq)
820 return -ENODEV;
821
822 clk = clk_get(&pdev->dev, "periph");
823 if (IS_ERR(clk))
824 return -ENODEV;
825
826 port = &ports[pdev->id];
827 memset(port, 0, sizeof(*port));
828 port->iotype = UPIO_MEM;
829 port->mapbase = res_mem->start;
830 port->irq = res_irq->start;
831 port->ops = &bcm_uart_ops;
832 port->flags = UPF_BOOT_AUTOCONF;
833 port->dev = &pdev->dev;
834 port->fifosize = 16;
835 port->uartclk = clk_get_rate(clk) / 2;
836 port->line = pdev->id;
837 clk_put(clk);
838
839 ret = uart_add_one_port(&bcm_uart_driver, port);
840 if (ret) {
841 ports[pdev->id].membase = 0;
842 return ret;
843 }
844 platform_set_drvdata(pdev, port);
845 return 0;
846 }
847
848 static int bcm_uart_remove(struct platform_device *pdev)
849 {
850 struct uart_port *port;
851
852 port = platform_get_drvdata(pdev);
853 uart_remove_one_port(&bcm_uart_driver, port);
854 /* mark port as free */
855 ports[pdev->id].membase = 0;
856 return 0;
857 }
858
859 /*
860 * platform driver stuff
861 */
862 static struct platform_driver bcm_uart_platform_driver = {
863 .probe = bcm_uart_probe,
864 .remove = bcm_uart_remove,
865 .driver = {
866 .owner = THIS_MODULE,
867 .name = "bcm63xx_uart",
868 },
869 };
870
871 static int __init bcm_uart_init(void)
872 {
873 int ret;
874
875 ret = uart_register_driver(&bcm_uart_driver);
876 if (ret)
877 return ret;
878
879 ret = platform_driver_register(&bcm_uart_platform_driver);
880 if (ret)
881 uart_unregister_driver(&bcm_uart_driver);
882
883 return ret;
884 }
885
886 static void __exit bcm_uart_exit(void)
887 {
888 platform_driver_unregister(&bcm_uart_platform_driver);
889 uart_unregister_driver(&bcm_uart_driver);
890 }
891
892 module_init(bcm_uart_init);
893 module_exit(bcm_uart_exit);
894
895 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
896 MODULE_DESCRIPTION("Broadcom 63<xx integrated uart driver");
897 MODULE_LICENSE("GPL");
Linux with added FPC-III support