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blk-mq: always free hctx after request queue is freed
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_fw.h
blob50c1e6c62e31f06c42a63a2602b6b7ca22d0735d
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_FW_H
8 #define __QLA_FW_H
9
10 #include <linux/nvme.h>
11 #include <linux/nvme-fc.h>
12
13 #define MBS_CHECKSUM_ERROR 0x4010
14 #define MBS_INVALID_PRODUCT_KEY 0x4020
15
16 /*
17 * Firmware Options.
18 */
19 #define FO1_ENABLE_PUREX BIT_10
20 #define FO1_DISABLE_LED_CTRL BIT_6
21 #define FO1_ENABLE_8016 BIT_0
22 #define FO2_ENABLE_SEL_CLASS2 BIT_5
23 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14
24 #define FO3_HOLD_STS_IOCB BIT_12
25
26 /*
27 * Port Database structure definition for ISP 24xx.
28 */
29 #define PDO_FORCE_ADISC BIT_1
30 #define PDO_FORCE_PLOGI BIT_0
31
32
33 #define PORT_DATABASE_24XX_SIZE 64
34 struct port_database_24xx {
35 uint16_t flags;
36 #define PDF_TASK_RETRY_ID BIT_14
37 #define PDF_FC_TAPE BIT_7
38 #define PDF_ACK0_CAPABLE BIT_6
39 #define PDF_FCP2_CONF BIT_5
40 #define PDF_CLASS_2 BIT_4
41 #define PDF_HARD_ADDR BIT_1
42
43 /*
44 * for NVMe, the login_state field has been
45 * split into nibbles.
46 * The lower nibble is for FCP.
47 * The upper nibble is for NVMe.
48 */
49 uint8_t current_login_state;
50 uint8_t last_login_state;
51 #define PDS_PLOGI_PENDING 0x03
52 #define PDS_PLOGI_COMPLETE 0x04
53 #define PDS_PRLI_PENDING 0x05
54 #define PDS_PRLI_COMPLETE 0x06
55 #define PDS_PORT_UNAVAILABLE 0x07
56 #define PDS_PRLO_PENDING 0x09
57 #define PDS_LOGO_PENDING 0x11
58 #define PDS_PRLI2_PENDING 0x12
59
60 uint8_t hard_address[3];
61 uint8_t reserved_1;
62
63 uint8_t port_id[3];
64 uint8_t sequence_id;
65
66 uint16_t port_timer;
67
68 uint16_t nport_handle; /* N_PORT handle. */
69
70 uint16_t receive_data_size;
71 uint16_t reserved_2;
72
73 uint8_t prli_svc_param_word_0[2]; /* Big endian */
74 /* Bits 15-0 of word 0 */
75 uint8_t prli_svc_param_word_3[2]; /* Big endian */
76 /* Bits 15-0 of word 3 */
77
78 uint8_t port_name[WWN_SIZE];
79 uint8_t node_name[WWN_SIZE];
80
81 uint8_t reserved_3[4];
82 uint16_t prli_nvme_svc_param_word_0; /* Bits 15-0 of word 0 */
83 uint16_t prli_nvme_svc_param_word_3; /* Bits 15-0 of word 3 */
84 uint16_t nvme_first_burst_size;
85 uint8_t reserved_4[14];
86 };
87
88 /*
89 * MB 75h returns a list of DB entries similar to port_database_24xx(64B).
90 * However, in this case it returns 1st 40 bytes.
91 */
92 struct get_name_list_extended {
93 __le16 flags;
94 u8 current_login_state;
95 u8 last_login_state;
96 u8 hard_address[3];
97 u8 reserved_1;
98 u8 port_id[3];
99 u8 sequence_id;
100 __le16 port_timer;
101 __le16 nport_handle; /* N_PORT handle. */
102 __le16 receive_data_size;
103 __le16 reserved_2;
104
105 /* PRLI SVC Param are Big endian */
106 u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */
107 u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */
108 u8 port_name[WWN_SIZE];
109 u8 node_name[WWN_SIZE];
110 };
111
112 /* MB 75h: This is the short version of the database */
113 struct get_name_list {
114 u8 port_node_name[WWN_SIZE]; /* B7 most sig, B0 least sig */
115 __le16 nport_handle;
116 u8 reserved;
117 };
118
119 struct vp_database_24xx {
120 uint16_t vp_status;
121 uint8_t options;
122 uint8_t id;
123 uint8_t port_name[WWN_SIZE];
124 uint8_t node_name[WWN_SIZE];
125 uint16_t port_id_low;
126 uint16_t port_id_high;
127 };
128
129 struct nvram_24xx {
130 /* NVRAM header. */
131 uint8_t id[4];
132 uint16_t nvram_version;
133 uint16_t reserved_0;
134
135 /* Firmware Initialization Control Block. */
136 uint16_t version;
137 uint16_t reserved_1;
138 __le16 frame_payload_size;
139 uint16_t execution_throttle;
140 uint16_t exchange_count;
141 uint16_t hard_address;
142
143 uint8_t port_name[WWN_SIZE];
144 uint8_t node_name[WWN_SIZE];
145
146 uint16_t login_retry_count;
147 uint16_t link_down_on_nos;
148 uint16_t interrupt_delay_timer;
149 uint16_t login_timeout;
150
151 uint32_t firmware_options_1;
152 uint32_t firmware_options_2;
153 uint32_t firmware_options_3;
154
155 /* Offset 56. */
156
157 /*
158 * BIT 0 = Control Enable
159 * BIT 1-15 =
160 *
161 * BIT 0-7 = Reserved
162 * BIT 8-10 = Output Swing 1G
163 * BIT 11-13 = Output Emphasis 1G
164 * BIT 14-15 = Reserved
165 *
166 * BIT 0-7 = Reserved
167 * BIT 8-10 = Output Swing 2G
168 * BIT 11-13 = Output Emphasis 2G
169 * BIT 14-15 = Reserved
170 *
171 * BIT 0-7 = Reserved
172 * BIT 8-10 = Output Swing 4G
173 * BIT 11-13 = Output Emphasis 4G
174 * BIT 14-15 = Reserved
175 */
176 uint16_t seriallink_options[4];
177
178 uint16_t reserved_2[16];
179
180 /* Offset 96. */
181 uint16_t reserved_3[16];
182
183 /* PCIe table entries. */
184 uint16_t reserved_4[16];
185
186 /* Offset 160. */
187 uint16_t reserved_5[16];
188
189 /* Offset 192. */
190 uint16_t reserved_6[16];
191
192 /* Offset 224. */
193 uint16_t reserved_7[16];
194
195 /*
196 * BIT 0 = Enable spinup delay
197 * BIT 1 = Disable BIOS
198 * BIT 2 = Enable Memory Map BIOS
199 * BIT 3 = Enable Selectable Boot
200 * BIT 4 = Disable RISC code load
201 * BIT 5 = Disable Serdes
202 * BIT 6 =
203 * BIT 7 =
204 *
205 * BIT 8 =
206 * BIT 9 =
207 * BIT 10 = Enable lip full login
208 * BIT 11 = Enable target reset
209 * BIT 12 =
210 * BIT 13 =
211 * BIT 14 =
212 * BIT 15 = Enable alternate WWN
213 *
214 * BIT 16-31 =
215 */
216 uint32_t host_p;
217
218 uint8_t alternate_port_name[WWN_SIZE];
219 uint8_t alternate_node_name[WWN_SIZE];
220
221 uint8_t boot_port_name[WWN_SIZE];
222 uint16_t boot_lun_number;
223 uint16_t reserved_8;
224
225 uint8_t alt1_boot_port_name[WWN_SIZE];
226 uint16_t alt1_boot_lun_number;
227 uint16_t reserved_9;
228
229 uint8_t alt2_boot_port_name[WWN_SIZE];
230 uint16_t alt2_boot_lun_number;
231 uint16_t reserved_10;
232
233 uint8_t alt3_boot_port_name[WWN_SIZE];
234 uint16_t alt3_boot_lun_number;
235 uint16_t reserved_11;
236
237 /*
238 * BIT 0 = Selective Login
239 * BIT 1 = Alt-Boot Enable
240 * BIT 2 = Reserved
241 * BIT 3 = Boot Order List
242 * BIT 4 = Reserved
243 * BIT 5 = Selective LUN
244 * BIT 6 = Reserved
245 * BIT 7-31 =
246 */
247 uint32_t efi_parameters;
248
249 uint8_t reset_delay;
250 uint8_t reserved_12;
251 uint16_t reserved_13;
252
253 uint16_t boot_id_number;
254 uint16_t reserved_14;
255
256 uint16_t max_luns_per_target;
257 uint16_t reserved_15;
258
259 uint16_t port_down_retry_count;
260 uint16_t link_down_timeout;
261
262 /* FCode parameters. */
263 uint16_t fcode_parameter;
264
265 uint16_t reserved_16[3];
266
267 /* Offset 352. */
268 uint8_t prev_drv_ver_major;
269 uint8_t prev_drv_ver_submajob;
270 uint8_t prev_drv_ver_minor;
271 uint8_t prev_drv_ver_subminor;
272
273 uint16_t prev_bios_ver_major;
274 uint16_t prev_bios_ver_minor;
275
276 uint16_t prev_efi_ver_major;
277 uint16_t prev_efi_ver_minor;
278
279 uint16_t prev_fw_ver_major;
280 uint8_t prev_fw_ver_minor;
281 uint8_t prev_fw_ver_subminor;
282
283 uint16_t reserved_17[8];
284
285 /* Offset 384. */
286 uint16_t reserved_18[16];
287
288 /* Offset 416. */
289 uint16_t reserved_19[16];
290
291 /* Offset 448. */
292 uint16_t reserved_20[16];
293
294 /* Offset 480. */
295 uint8_t model_name[16];
296
297 uint16_t reserved_21[2];
298
299 /* Offset 500. */
300 /* HW Parameter Block. */
301 uint16_t pcie_table_sig;
302 uint16_t pcie_table_offset;
303
304 uint16_t subsystem_vendor_id;
305 uint16_t subsystem_device_id;
306
307 uint32_t checksum;
308 };
309
310 /*
311 * ISP Initialization Control Block.
312 * Little endian except where noted.
313 */
314 #define ICB_VERSION 1
315 struct init_cb_24xx {
316 uint16_t version;
317 uint16_t reserved_1;
318
319 uint16_t frame_payload_size;
320 uint16_t execution_throttle;
321 uint16_t exchange_count;
322
323 uint16_t hard_address;
324
325 uint8_t port_name[WWN_SIZE]; /* Big endian. */
326 uint8_t node_name[WWN_SIZE]; /* Big endian. */
327
328 uint16_t response_q_inpointer;
329 uint16_t request_q_outpointer;
330
331 uint16_t login_retry_count;
332
333 uint16_t prio_request_q_outpointer;
334
335 uint16_t response_q_length;
336 uint16_t request_q_length;
337
338 uint16_t link_down_on_nos; /* Milliseconds. */
339
340 uint16_t prio_request_q_length;
341
342 uint32_t request_q_address[2];
343 uint32_t response_q_address[2];
344 uint32_t prio_request_q_address[2];
345
346 uint16_t msix;
347 uint16_t msix_atio;
348 uint8_t reserved_2[4];
349
350 uint16_t atio_q_inpointer;
351 uint16_t atio_q_length;
352 uint32_t atio_q_address[2];
353
354 uint16_t interrupt_delay_timer; /* 100us increments. */
355 uint16_t login_timeout;
356
357 /*
358 * BIT 0 = Enable Hard Loop Id
359 * BIT 1 = Enable Fairness
360 * BIT 2 = Enable Full-Duplex
361 * BIT 3 = Reserved
362 * BIT 4 = Enable Target Mode
363 * BIT 5 = Disable Initiator Mode
364 * BIT 6 = Acquire FA-WWN
365 * BIT 7 = Enable D-port Diagnostics
366 *
367 * BIT 8 = Reserved
368 * BIT 9 = Non Participating LIP
369 * BIT 10 = Descending Loop ID Search
370 * BIT 11 = Acquire Loop ID in LIPA
371 * BIT 12 = Reserved
372 * BIT 13 = Full Login after LIP
373 * BIT 14 = Node Name Option
374 * BIT 15-31 = Reserved
375 */
376 uint32_t firmware_options_1;
377
378 /*
379 * BIT 0 = Operation Mode bit 0
380 * BIT 1 = Operation Mode bit 1
381 * BIT 2 = Operation Mode bit 2
382 * BIT 3 = Operation Mode bit 3
383 * BIT 4 = Connection Options bit 0
384 * BIT 5 = Connection Options bit 1
385 * BIT 6 = Connection Options bit 2
386 * BIT 7 = Enable Non part on LIHA failure
387 *
388 * BIT 8 = Enable Class 2
389 * BIT 9 = Enable ACK0
390 * BIT 10 = Reserved
391 * BIT 11 = Enable FC-SP Security
392 * BIT 12 = FC Tape Enable
393 * BIT 13 = Reserved
394 * BIT 14 = Enable Target PRLI Control
395 * BIT 15-31 = Reserved
396 */
397 uint32_t firmware_options_2;
398
399 /*
400 * BIT 0 = Reserved
401 * BIT 1 = Soft ID only
402 * BIT 2 = Reserved
403 * BIT 3 = Reserved
404 * BIT 4 = FCP RSP Payload bit 0
405 * BIT 5 = FCP RSP Payload bit 1
406 * BIT 6 = Enable Receive Out-of-Order data frame handling
407 * BIT 7 = Disable Automatic PLOGI on Local Loop
408 *
409 * BIT 8 = Reserved
410 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
411 * BIT 10 = Reserved
412 * BIT 11 = Reserved
413 * BIT 12 = Reserved
414 * BIT 13 = Data Rate bit 0
415 * BIT 14 = Data Rate bit 1
416 * BIT 15 = Data Rate bit 2
417 * BIT 16 = Enable 75 ohm Termination Select
418 * BIT 17-28 = Reserved
419 * BIT 29 = Enable response queue 0 in index shadowing
420 * BIT 30 = Enable request queue 0 out index shadowing
421 * BIT 31 = Reserved
422 */
423 uint32_t firmware_options_3;
424 uint16_t qos;
425 uint16_t rid;
426 uint8_t reserved_3[20];
427 };
428
429 /*
430 * ISP queue - command entry structure definition.
431 */
432 #define COMMAND_BIDIRECTIONAL 0x75
433 struct cmd_bidir {
434 uint8_t entry_type; /* Entry type. */
435 uint8_t entry_count; /* Entry count. */
436 uint8_t sys_define; /* System defined */
437 uint8_t entry_status; /* Entry status. */
438
439 uint32_t handle; /* System handle. */
440
441 uint16_t nport_handle; /* N_PORT hanlde. */
442
443 uint16_t timeout; /* Commnad timeout. */
444
445 uint16_t wr_dseg_count; /* Write Data segment count. */
446 uint16_t rd_dseg_count; /* Read Data segment count. */
447
448 struct scsi_lun lun; /* FCP LUN (BE). */
449
450 uint16_t control_flags; /* Control flags. */
451 #define BD_WRAP_BACK BIT_3
452 #define BD_READ_DATA BIT_1
453 #define BD_WRITE_DATA BIT_0
454
455 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
456 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
457
458 uint16_t reserved[2]; /* Reserved */
459
460 uint32_t rd_byte_count; /* Total Byte count Read. */
461 uint32_t wr_byte_count; /* Total Byte count write. */
462
463 uint8_t port_id[3]; /* PortID of destination port.*/
464 uint8_t vp_index;
465
466 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
467 uint16_t fcp_data_dseg_len; /* Data segment length. */
468 };
469
470 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
471 struct cmd_type_6 {
472 uint8_t entry_type; /* Entry type. */
473 uint8_t entry_count; /* Entry count. */
474 uint8_t sys_define; /* System defined. */
475 uint8_t entry_status; /* Entry Status. */
476
477 uint32_t handle; /* System handle. */
478
479 uint16_t nport_handle; /* N_PORT handle. */
480 uint16_t timeout; /* Command timeout. */
481
482 uint16_t dseg_count; /* Data segment count. */
483
484 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */
485
486 struct scsi_lun lun; /* FCP LUN (BE). */
487
488 uint16_t control_flags; /* Control flags. */
489 #define CF_DIF_SEG_DESCR_ENABLE BIT_3
490 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
491 #define CF_READ_DATA BIT_1
492 #define CF_WRITE_DATA BIT_0
493
494 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
495 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
496
497 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
498
499 uint32_t byte_count; /* Total byte count. */
500
501 uint8_t port_id[3]; /* PortID of destination port. */
502 uint8_t vp_index;
503
504 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
505 uint32_t fcp_data_dseg_len; /* Data segment length. */
506 };
507
508 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
509 struct cmd_type_7 {
510 uint8_t entry_type; /* Entry type. */
511 uint8_t entry_count; /* Entry count. */
512 uint8_t sys_define; /* System defined. */
513 uint8_t entry_status; /* Entry Status. */
514
515 uint32_t handle; /* System handle. */
516
517 uint16_t nport_handle; /* N_PORT handle. */
518 uint16_t timeout; /* Command timeout. */
519 #define FW_MAX_TIMEOUT 0x1999
520
521 uint16_t dseg_count; /* Data segment count. */
522 uint16_t reserved_1;
523
524 struct scsi_lun lun; /* FCP LUN (BE). */
525
526 uint16_t task_mgmt_flags; /* Task management flags. */
527 #define TMF_CLEAR_ACA BIT_14
528 #define TMF_TARGET_RESET BIT_13
529 #define TMF_LUN_RESET BIT_12
530 #define TMF_CLEAR_TASK_SET BIT_10
531 #define TMF_ABORT_TASK_SET BIT_9
532 #define TMF_DSD_LIST_ENABLE BIT_2
533 #define TMF_READ_DATA BIT_1
534 #define TMF_WRITE_DATA BIT_0
535
536 uint8_t task;
537 #define TSK_SIMPLE 0
538 #define TSK_HEAD_OF_QUEUE 1
539 #define TSK_ORDERED 2
540 #define TSK_ACA 4
541 #define TSK_UNTAGGED 5
542
543 uint8_t crn;
544
545 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
546 uint32_t byte_count; /* Total byte count. */
547
548 uint8_t port_id[3]; /* PortID of destination port. */
549 uint8_t vp_index;
550
551 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
552 uint32_t dseg_0_len; /* Data segment 0 length. */
553 };
554
555 #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6)
556 * (T10-DIF) */
557 struct cmd_type_crc_2 {
558 uint8_t entry_type; /* Entry type. */
559 uint8_t entry_count; /* Entry count. */
560 uint8_t sys_define; /* System defined. */
561 uint8_t entry_status; /* Entry Status. */
562
563 uint32_t handle; /* System handle. */
564
565 uint16_t nport_handle; /* N_PORT handle. */
566 uint16_t timeout; /* Command timeout. */
567
568 uint16_t dseg_count; /* Data segment count. */
569
570 uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */
571
572 struct scsi_lun lun; /* FCP LUN (BE). */
573
574 uint16_t control_flags; /* Control flags. */
575
576 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
577 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
578
579 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
580
581 uint32_t byte_count; /* Total byte count. */
582
583 uint8_t port_id[3]; /* PortID of destination port. */
584 uint8_t vp_index;
585
586 uint32_t crc_context_address[2]; /* Data segment address. */
587 uint16_t crc_context_len; /* Data segment length. */
588 uint16_t reserved_1; /* MUST be set to 0. */
589 };
590
591
592 /*
593 * ISP queue - status entry structure definition.
594 */
595 #define STATUS_TYPE 0x03 /* Status entry. */
596 struct sts_entry_24xx {
597 uint8_t entry_type; /* Entry type. */
598 uint8_t entry_count; /* Entry count. */
599 uint8_t sys_define; /* System defined. */
600 uint8_t entry_status; /* Entry Status. */
601
602 uint32_t handle; /* System handle. */
603
604 uint16_t comp_status; /* Completion status. */
605 uint16_t ox_id; /* OX_ID used by the firmware. */
606
607 uint32_t residual_len; /* FW calc residual transfer length. */
608
609 union {
610 uint16_t reserved_1;
611 uint16_t nvme_rsp_pyld_len;
612 };
613
614 uint16_t state_flags; /* State flags. */
615 #define SF_TRANSFERRED_DATA BIT_11
616 #define SF_NVME_ERSP BIT_6
617 #define SF_FCP_RSP_DMA BIT_0
618
619 uint16_t retry_delay;
620 uint16_t scsi_status; /* SCSI status. */
621 #define SS_CONFIRMATION_REQ BIT_12
622
623 uint32_t rsp_residual_count; /* FCP RSP residual count. */
624
625 uint32_t sense_len; /* FCP SENSE length. */
626
627 union {
628 struct {
629 uint32_t rsp_data_len; /* FCP response data length */
630 uint8_t data[28]; /* FCP rsp/sense information */
631 };
632 struct nvme_fc_ersp_iu nvme_ersp;
633 uint8_t nvme_ersp_data[32];
634 };
635
636 /*
637 * If DIF Error is set in comp_status, these additional fields are
638 * defined:
639 *
640 * !!! NOTE: Firmware sends expected/actual DIF data in big endian
641 * format; but all of the "data" field gets swab32-d in the beginning
642 * of qla2x00_status_entry().
643 *
644 * &data[10] : uint8_t report_runt_bg[2]; - computed guard
645 * &data[12] : uint8_t actual_dif[8]; - DIF Data received
646 * &data[20] : uint8_t expected_dif[8]; - DIF Data computed
647 */
648 };
649
650
651 /*
652 * Status entry completion status
653 */
654 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
655 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
656 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
657 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
658 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
659
660 /*
661 * ISP queue - marker entry structure definition.
662 */
663 #define MARKER_TYPE 0x04 /* Marker entry. */
664 struct mrk_entry_24xx {
665 uint8_t entry_type; /* Entry type. */
666 uint8_t entry_count; /* Entry count. */
667 uint8_t handle_count; /* Handle count. */
668 uint8_t entry_status; /* Entry Status. */
669
670 uint32_t handle; /* System handle. */
671
672 uint16_t nport_handle; /* N_PORT handle. */
673
674 uint8_t modifier; /* Modifier (7-0). */
675 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
676 #define MK_SYNC_ID 1 /* Synchronize ID */
677 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
678 uint8_t reserved_1;
679
680 uint8_t reserved_2;
681 uint8_t vp_index;
682
683 uint16_t reserved_3;
684
685 uint8_t lun[8]; /* FCP LUN (BE). */
686 uint8_t reserved_4[40];
687 };
688
689 /*
690 * ISP queue - CT Pass-Through entry structure definition.
691 */
692 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
693 struct ct_entry_24xx {
694 uint8_t entry_type; /* Entry type. */
695 uint8_t entry_count; /* Entry count. */
696 uint8_t sys_define; /* System Defined. */
697 uint8_t entry_status; /* Entry Status. */
698
699 uint32_t handle; /* System handle. */
700
701 uint16_t comp_status; /* Completion status. */
702
703 uint16_t nport_handle; /* N_PORT handle. */
704
705 uint16_t cmd_dsd_count;
706
707 uint8_t vp_index;
708 uint8_t reserved_1;
709
710 uint16_t timeout; /* Command timeout. */
711 uint16_t reserved_2;
712
713 uint16_t rsp_dsd_count;
714
715 uint8_t reserved_3[10];
716
717 uint32_t rsp_byte_count;
718 uint32_t cmd_byte_count;
719
720 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
721 uint32_t dseg_0_len; /* Data segment 0 length. */
722 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
723 uint32_t dseg_1_len; /* Data segment 1 length. */
724 };
725
726 /*
727 * ISP queue - ELS Pass-Through entry structure definition.
728 */
729 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
730 struct els_entry_24xx {
731 uint8_t entry_type; /* Entry type. */
732 uint8_t entry_count; /* Entry count. */
733 uint8_t sys_define; /* System Defined. */
734 uint8_t entry_status; /* Entry Status. */
735
736 uint32_t handle; /* System handle. */
737
738 uint16_t reserved_1;
739
740 uint16_t nport_handle; /* N_PORT handle. */
741
742 uint16_t tx_dsd_count;
743
744 uint8_t vp_index;
745 uint8_t sof_type;
746 #define EST_SOFI3 (1 << 4)
747 #define EST_SOFI2 (3 << 4)
748
749 uint32_t rx_xchg_address; /* Receive exchange address. */
750 uint16_t rx_dsd_count;
751
752 uint8_t opcode;
753 uint8_t reserved_2;
754
755 uint8_t port_id[3];
756 uint8_t s_id[3];
757
758 uint16_t control_flags; /* Control flags. */
759 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
760 #define EPD_ELS_COMMAND (0 << 13)
761 #define EPD_ELS_ACC (1 << 13)
762 #define EPD_ELS_RJT (2 << 13)
763 #define EPD_RX_XCHG (3 << 13)
764 #define ECF_CLR_PASSTHRU_PEND BIT_12
765 #define ECF_INCL_FRAME_HDR BIT_11
766
767 uint32_t rx_byte_count;
768 uint32_t tx_byte_count;
769
770 uint32_t tx_address[2]; /* Data segment 0 address. */
771 uint32_t tx_len; /* Data segment 0 length. */
772 uint32_t rx_address[2]; /* Data segment 1 address. */
773 uint32_t rx_len; /* Data segment 1 length. */
774 };
775
776 struct els_sts_entry_24xx {
777 uint8_t entry_type; /* Entry type. */
778 uint8_t entry_count; /* Entry count. */
779 uint8_t sys_define; /* System Defined. */
780 uint8_t entry_status; /* Entry Status. */
781
782 uint32_t handle; /* System handle. */
783
784 uint16_t comp_status;
785
786 uint16_t nport_handle; /* N_PORT handle. */
787
788 uint16_t reserved_1;
789
790 uint8_t vp_index;
791 uint8_t sof_type;
792
793 uint32_t rx_xchg_address; /* Receive exchange address. */
794 uint16_t reserved_2;
795
796 uint8_t opcode;
797 uint8_t reserved_3;
798
799 uint8_t port_id[3];
800 uint8_t reserved_4;
801
802 uint16_t reserved_5;
803
804 uint16_t control_flags; /* Control flags. */
805 uint32_t total_byte_count;
806 uint32_t error_subcode_1;
807 uint32_t error_subcode_2;
808 };
809 /*
810 * ISP queue - Mailbox Command entry structure definition.
811 */
812 #define MBX_IOCB_TYPE 0x39
813 struct mbx_entry_24xx {
814 uint8_t entry_type; /* Entry type. */
815 uint8_t entry_count; /* Entry count. */
816 uint8_t handle_count; /* Handle count. */
817 uint8_t entry_status; /* Entry Status. */
818
819 uint32_t handle; /* System handle. */
820
821 uint16_t mbx[28];
822 };
823
824
825 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
826 struct logio_entry_24xx {
827 uint8_t entry_type; /* Entry type. */
828 uint8_t entry_count; /* Entry count. */
829 uint8_t sys_define; /* System defined. */
830 uint8_t entry_status; /* Entry Status. */
831
832 uint32_t handle; /* System handle. */
833
834 uint16_t comp_status; /* Completion status. */
835 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
836
837 uint16_t nport_handle; /* N_PORT handle. */
838
839 uint16_t control_flags; /* Control flags. */
840 /* Modifiers. */
841 #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */
842 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
843 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */
844 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */
845 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */
846 #define LCF_NVME_PRLI BIT_6 /* Perform NVME FC4 PRLI */
847 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */
848 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */
849 #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */
850 #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */
851 #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */
852 /* Commands. */
853 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
854 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */
855 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */
856 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */
857 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */
858 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */
859 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
860
861 uint8_t vp_index;
862 uint8_t reserved_1;
863
864 uint8_t port_id[3]; /* PortID of destination port. */
865
866 uint8_t rsp_size; /* Response size in 32bit words. */
867
868 uint32_t io_parameter[11]; /* General I/O parameters. */
869 #define LSC_SCODE_NOLINK 0x01
870 #define LSC_SCODE_NOIOCB 0x02
871 #define LSC_SCODE_NOXCB 0x03
872 #define LSC_SCODE_CMD_FAILED 0x04
873 #define LSC_SCODE_NOFABRIC 0x05
874 #define LSC_SCODE_FW_NOT_READY 0x07
875 #define LSC_SCODE_NOT_LOGGED_IN 0x09
876 #define LSC_SCODE_NOPCB 0x0A
877
878 #define LSC_SCODE_ELS_REJECT 0x18
879 #define LSC_SCODE_CMD_PARAM_ERR 0x19
880 #define LSC_SCODE_PORTID_USED 0x1A
881 #define LSC_SCODE_NPORT_USED 0x1B
882 #define LSC_SCODE_NONPORT 0x1C
883 #define LSC_SCODE_LOGGED_IN 0x1D
884 #define LSC_SCODE_NOFLOGI_ACC 0x1F
885 };
886
887 #define TSK_MGMT_IOCB_TYPE 0x14
888 struct tsk_mgmt_entry {
889 uint8_t entry_type; /* Entry type. */
890 uint8_t entry_count; /* Entry count. */
891 uint8_t handle_count; /* Handle count. */
892 uint8_t entry_status; /* Entry Status. */
893
894 uint32_t handle; /* System handle. */
895
896 uint16_t nport_handle; /* N_PORT handle. */
897
898 uint16_t reserved_1;
899
900 uint16_t delay; /* Activity delay in seconds. */
901
902 uint16_t timeout; /* Command timeout. */
903
904 struct scsi_lun lun; /* FCP LUN (BE). */
905
906 uint32_t control_flags; /* Control Flags. */
907 #define TCF_NOTMCMD_TO_TARGET BIT_31
908 #define TCF_LUN_RESET BIT_4
909 #define TCF_ABORT_TASK_SET BIT_3
910 #define TCF_CLEAR_TASK_SET BIT_2
911 #define TCF_TARGET_RESET BIT_1
912 #define TCF_CLEAR_ACA BIT_0
913
914 uint8_t reserved_2[20];
915
916 uint8_t port_id[3]; /* PortID of destination port. */
917 uint8_t vp_index;
918
919 uint8_t reserved_3[12];
920 };
921
922 #define ABORT_IOCB_TYPE 0x33
923 struct abort_entry_24xx {
924 uint8_t entry_type; /* Entry type. */
925 uint8_t entry_count; /* Entry count. */
926 uint8_t handle_count; /* Handle count. */
927 uint8_t entry_status; /* Entry Status. */
928
929 uint32_t handle; /* System handle. */
930
931 uint16_t nport_handle; /* N_PORT handle. */
932 /* or Completion status. */
933
934 uint16_t options; /* Options. */
935 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
936
937 uint32_t handle_to_abort; /* System handle to abort. */
938
939 uint16_t req_que_no;
940 uint8_t reserved_1[30];
941
942 uint8_t port_id[3]; /* PortID of destination port. */
943 uint8_t vp_index;
944
945 uint8_t reserved_2[12];
946 };
947
948 /*
949 * ISP I/O Register Set structure definitions.
950 */
951 struct device_reg_24xx {
952 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */
953 #define FARX_DATA_FLAG BIT_31
954 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
955 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
956 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
957 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
958
959 #define FA_NVRAM_FUNC0_ADDR 0x80
960 #define FA_NVRAM_FUNC1_ADDR 0x180
961
962 #define FA_NVRAM_VPD_SIZE 0x200
963 #define FA_NVRAM_VPD0_ADDR 0x00
964 #define FA_NVRAM_VPD1_ADDR 0x100
965
966 #define FA_BOOT_CODE_ADDR 0x00000
967 /*
968 * RISC code begins at offset 512KB
969 * within flash. Consisting of two
970 * contiguous RISC code segments.
971 */
972 #define FA_RISC_CODE_ADDR 0x20000
973 #define FA_RISC_CODE_SEGMENTS 2
974
975 #define FA_FLASH_DESCR_ADDR_24 0x11000
976 #define FA_FLASH_LAYOUT_ADDR_24 0x11400
977 #define FA_NPIV_CONF0_ADDR_24 0x16000
978 #define FA_NPIV_CONF1_ADDR_24 0x17000
979
980 #define FA_FW_AREA_ADDR 0x40000
981 #define FA_VPD_NVRAM_ADDR 0x48000
982 #define FA_FEATURE_ADDR 0x4C000
983 #define FA_FLASH_DESCR_ADDR 0x50000
984 #define FA_FLASH_LAYOUT_ADDR 0x50400
985 #define FA_HW_EVENT0_ADDR 0x54000
986 #define FA_HW_EVENT1_ADDR 0x54400
987 #define FA_HW_EVENT_SIZE 0x200
988 #define FA_HW_EVENT_ENTRY_SIZE 4
989 #define FA_NPIV_CONF0_ADDR 0x5C000
990 #define FA_NPIV_CONF1_ADDR 0x5D000
991 #define FA_FCP_PRIO0_ADDR 0x10000
992 #define FA_FCP_PRIO1_ADDR 0x12000
993
994 /*
995 * Flash Error Log Event Codes.
996 */
997 #define HW_EVENT_RESET_ERR 0xF00B
998 #define HW_EVENT_ISP_ERR 0xF020
999 #define HW_EVENT_PARITY_ERR 0xF022
1000 #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023
1001 #define HW_EVENT_FLASH_FW_ERR 0xF024
1002
1003 uint32_t flash_data; /* Flash/NVRAM BIOS data. */
1004
1005 uint32_t ctrl_status; /* Control/Status. */
1006 #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */
1007 #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */
1008 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
1009 #define CSRX_FUNCTION BIT_15 /* Function number. */
1010 /* PCI-X Bus Mode. */
1011 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
1012 #define PBM_PCI_33MHZ (0 << 8)
1013 #define PBM_PCIX_M1_66MHZ (1 << 8)
1014 #define PBM_PCIX_M1_100MHZ (2 << 8)
1015 #define PBM_PCIX_M1_133MHZ (3 << 8)
1016 #define PBM_PCIX_M2_66MHZ (5 << 8)
1017 #define PBM_PCIX_M2_100MHZ (6 << 8)
1018 #define PBM_PCIX_M2_133MHZ (7 << 8)
1019 #define PBM_PCI_66MHZ (8 << 8)
1020 /* Max Write Burst byte count. */
1021 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
1022 #define MWB_512_BYTES (0 << 4)
1023 #define MWB_1024_BYTES (1 << 4)
1024 #define MWB_2048_BYTES (2 << 4)
1025 #define MWB_4096_BYTES (3 << 4)
1026
1027 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
1028 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1029 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
1030
1031 uint32_t ictrl; /* Interrupt control. */
1032 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
1033
1034 uint32_t istatus; /* Interrupt status. */
1035 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
1036
1037 uint32_t unused_1[2]; /* Gap. */
1038
1039 /* Request Queue. */
1040 uint32_t req_q_in; /* In-Pointer. */
1041 uint32_t req_q_out; /* Out-Pointer. */
1042 /* Response Queue. */
1043 uint32_t rsp_q_in; /* In-Pointer. */
1044 uint32_t rsp_q_out; /* Out-Pointer. */
1045 /* Priority Request Queue. */
1046 uint32_t preq_q_in; /* In-Pointer. */
1047 uint32_t preq_q_out; /* Out-Pointer. */
1048
1049 uint32_t unused_2[2]; /* Gap. */
1050
1051 /* ATIO Queue. */
1052 uint32_t atio_q_in; /* In-Pointer. */
1053 uint32_t atio_q_out; /* Out-Pointer. */
1054
1055 uint32_t host_status;
1056 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
1057 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
1058
1059 uint32_t hccr; /* Host command & control register. */
1060 /* HCCR statuses. */
1061 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
1062 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
1063 /* HCCR commands. */
1064 /* NOOP. */
1065 #define HCCRX_NOOP 0x00000000
1066 /* Set RISC Reset. */
1067 #define HCCRX_SET_RISC_RESET 0x10000000
1068 /* Clear RISC Reset. */
1069 #define HCCRX_CLR_RISC_RESET 0x20000000
1070 /* Set RISC Pause. */
1071 #define HCCRX_SET_RISC_PAUSE 0x30000000
1072 /* Releases RISC Pause. */
1073 #define HCCRX_REL_RISC_PAUSE 0x40000000
1074 /* Set HOST to RISC interrupt. */
1075 #define HCCRX_SET_HOST_INT 0x50000000
1076 /* Clear HOST to RISC interrupt. */
1077 #define HCCRX_CLR_HOST_INT 0x60000000
1078 /* Clear RISC to PCI interrupt. */
1079 #define HCCRX_CLR_RISC_INT 0xA0000000
1080
1081 uint32_t gpiod; /* GPIO Data register. */
1082
1083 /* LED update mask. */
1084 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18)
1085 /* Data update mask. */
1086 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
1087 /* Data update mask. */
1088 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1089 /* LED control mask. */
1090 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
1091 /* LED bit values. Color names as
1092 * referenced in fw spec.
1093 */
1094 #define GPDX_LED_YELLOW_ON BIT_2
1095 #define GPDX_LED_GREEN_ON BIT_3
1096 #define GPDX_LED_AMBER_ON BIT_4
1097 /* Data in/out. */
1098 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1099
1100 uint32_t gpioe; /* GPIO Enable register. */
1101 /* Enable update mask. */
1102 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
1103 /* Enable update mask. */
1104 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1105 /* Enable. */
1106 #define GPEX_ENABLE (BIT_1|BIT_0)
1107
1108 uint32_t iobase_addr; /* I/O Bus Base Address register. */
1109
1110 uint32_t unused_3[10]; /* Gap. */
1111
1112 uint16_t mailbox0;
1113 uint16_t mailbox1;
1114 uint16_t mailbox2;
1115 uint16_t mailbox3;
1116 uint16_t mailbox4;
1117 uint16_t mailbox5;
1118 uint16_t mailbox6;
1119 uint16_t mailbox7;
1120 uint16_t mailbox8;
1121 uint16_t mailbox9;
1122 uint16_t mailbox10;
1123 uint16_t mailbox11;
1124 uint16_t mailbox12;
1125 uint16_t mailbox13;
1126 uint16_t mailbox14;
1127 uint16_t mailbox15;
1128 uint16_t mailbox16;
1129 uint16_t mailbox17;
1130 uint16_t mailbox18;
1131 uint16_t mailbox19;
1132 uint16_t mailbox20;
1133 uint16_t mailbox21;
1134 uint16_t mailbox22;
1135 uint16_t mailbox23;
1136 uint16_t mailbox24;
1137 uint16_t mailbox25;
1138 uint16_t mailbox26;
1139 uint16_t mailbox27;
1140 uint16_t mailbox28;
1141 uint16_t mailbox29;
1142 uint16_t mailbox30;
1143 uint16_t mailbox31;
1144
1145 uint32_t iobase_window;
1146 uint32_t iobase_c4;
1147 uint32_t iobase_c8;
1148 uint32_t unused_4_1[6]; /* Gap. */
1149 uint32_t iobase_q;
1150 uint32_t unused_5[2]; /* Gap. */
1151 uint32_t iobase_select;
1152 uint32_t unused_6[2]; /* Gap. */
1153 uint32_t iobase_sdata;
1154 };
1155 /* RISC-RISC semaphore register PCI offet */
1156 #define RISC_REGISTER_BASE_OFFSET 0x7010
1157 #define RISC_REGISTER_WINDOW_OFFET 0x6
1158
1159 /* RISC-RISC semaphore/flag register (risc address 0x7016) */
1160
1161 #define RISC_SEMAPHORE 0x1UL
1162 #define RISC_SEMAPHORE_WE (RISC_SEMAPHORE << 16)
1163 #define RISC_SEMAPHORE_CLR (RISC_SEMAPHORE_WE | 0x0UL)
1164 #define RISC_SEMAPHORE_SET (RISC_SEMAPHORE_WE | RISC_SEMAPHORE)
1165
1166 #define RISC_SEMAPHORE_FORCE 0x8000UL
1167 #define RISC_SEMAPHORE_FORCE_WE (RISC_SEMAPHORE_FORCE << 16)
1168 #define RISC_SEMAPHORE_FORCE_CLR (RISC_SEMAPHORE_FORCE_WE | 0x0UL)
1169 #define RISC_SEMAPHORE_FORCE_SET \
1170 (RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE)
1171
1172 /* RISC semaphore timeouts (ms) */
1173 #define TIMEOUT_SEMAPHORE 2500
1174 #define TIMEOUT_SEMAPHORE_FORCE 2000
1175 #define TIMEOUT_TOTAL_ELAPSED 4500
1176
1177 /* Trace Control *************************************************************/
1178
1179 #define TC_AEN_DISABLE 0
1180
1181 #define TC_EFT_ENABLE 4
1182 #define TC_EFT_DISABLE 5
1183
1184 #define TC_FCE_ENABLE 8
1185 #define TC_FCE_OPTIONS 0
1186 #define TC_FCE_DEFAULT_RX_SIZE 2112
1187 #define TC_FCE_DEFAULT_TX_SIZE 2112
1188 #define TC_FCE_DISABLE 9
1189 #define TC_FCE_DISABLE_TRACE BIT_0
1190
1191 /* MID Support ***************************************************************/
1192
1193 #define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */
1194 #define MAX_MULTI_ID_FABRIC 256 /* ... */
1195
1196 struct mid_conf_entry_24xx {
1197 uint16_t reserved_1;
1198
1199 /*
1200 * BIT 0 = Enable Hard Loop Id
1201 * BIT 1 = Acquire Loop ID in LIPA
1202 * BIT 2 = ID not Acquired
1203 * BIT 3 = Enable VP
1204 * BIT 4 = Enable Initiator Mode
1205 * BIT 5 = Disable Target Mode
1206 * BIT 6-7 = Reserved
1207 */
1208 uint8_t options;
1209
1210 uint8_t hard_address;
1211
1212 uint8_t port_name[WWN_SIZE];
1213 uint8_t node_name[WWN_SIZE];
1214 };
1215
1216 struct mid_init_cb_24xx {
1217 struct init_cb_24xx init_cb;
1218
1219 uint16_t count;
1220 uint16_t options;
1221
1222 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1223 };
1224
1225
1226 struct mid_db_entry_24xx {
1227 uint16_t status;
1228 #define MDBS_NON_PARTIC BIT_3
1229 #define MDBS_ID_ACQUIRED BIT_1
1230 #define MDBS_ENABLED BIT_0
1231
1232 uint8_t options;
1233 uint8_t hard_address;
1234
1235 uint8_t port_name[WWN_SIZE];
1236 uint8_t node_name[WWN_SIZE];
1237
1238 uint8_t port_id[3];
1239 uint8_t reserved_1;
1240 };
1241
1242 /*
1243 * Virtual Port Control IOCB
1244 */
1245 #define VP_CTRL_IOCB_TYPE 0x30 /* Virtual Port Control entry. */
1246 struct vp_ctrl_entry_24xx {
1247 uint8_t entry_type; /* Entry type. */
1248 uint8_t entry_count; /* Entry count. */
1249 uint8_t sys_define; /* System defined. */
1250 uint8_t entry_status; /* Entry Status. */
1251
1252 uint32_t handle; /* System handle. */
1253
1254 uint16_t vp_idx_failed;
1255
1256 uint16_t comp_status; /* Completion status. */
1257 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */
1258 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
1259 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
1260
1261 uint16_t command;
1262 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
1263 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
1264 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
1265 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1266 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */
1267
1268 uint16_t vp_count;
1269
1270 uint8_t vp_idx_map[16];
1271 uint16_t flags;
1272 uint16_t id;
1273 uint16_t reserved_4;
1274 uint16_t hopct;
1275 uint8_t reserved_5[24];
1276 };
1277
1278 /*
1279 * Modify Virtual Port Configuration IOCB
1280 */
1281 #define VP_CONFIG_IOCB_TYPE 0x31 /* Virtual Port Config entry. */
1282 struct vp_config_entry_24xx {
1283 uint8_t entry_type; /* Entry type. */
1284 uint8_t entry_count; /* Entry count. */
1285 uint8_t handle_count;
1286 uint8_t entry_status; /* Entry Status. */
1287
1288 uint32_t handle; /* System handle. */
1289
1290 uint16_t flags;
1291 #define CS_VF_BIND_VPORTS_TO_VF BIT_0
1292 #define CS_VF_SET_QOS_OF_VPORTS BIT_1
1293 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2
1294
1295 uint16_t comp_status; /* Completion status. */
1296 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1297 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1298 #define CS_VCT_ERROR 0x03 /* Unknown error. */
1299 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
1300 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
1301
1302 uint8_t command;
1303 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */
1304 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1305
1306 uint8_t vp_count;
1307
1308 uint8_t vp_index1;
1309 uint8_t vp_index2;
1310
1311 uint8_t options_idx1;
1312 uint8_t hard_address_idx1;
1313 uint16_t reserved_vp1;
1314 uint8_t port_name_idx1[WWN_SIZE];
1315 uint8_t node_name_idx1[WWN_SIZE];
1316
1317 uint8_t options_idx2;
1318 uint8_t hard_address_idx2;
1319 uint16_t reserved_vp2;
1320 uint8_t port_name_idx2[WWN_SIZE];
1321 uint8_t node_name_idx2[WWN_SIZE];
1322 uint16_t id;
1323 uint16_t reserved_4;
1324 uint16_t hopct;
1325 uint8_t reserved_5[2];
1326 };
1327
1328 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
1329 enum VP_STATUS {
1330 VP_STAT_COMPL,
1331 VP_STAT_FAIL,
1332 VP_STAT_ID_CHG,
1333 VP_STAT_SNS_TO, /* timeout */
1334 VP_STAT_SNS_RJT,
1335 VP_STAT_SCR_TO, /* timeout */
1336 VP_STAT_SCR_RJT,
1337 };
1338
1339 enum VP_FLAGS {
1340 VP_FLAGS_CON_FLOOP = 1,
1341 VP_FLAGS_CON_P2P = 2,
1342 VP_FLAGS_CON_FABRIC = 3,
1343 VP_FLAGS_NAME_VALID = BIT_5,
1344 };
1345
1346 struct vp_rpt_id_entry_24xx {
1347 uint8_t entry_type; /* Entry type. */
1348 uint8_t entry_count; /* Entry count. */
1349 uint8_t sys_define; /* System defined. */
1350 uint8_t entry_status; /* Entry Status. */
1351 uint32_t resv1;
1352 uint8_t vp_acquired;
1353 uint8_t vp_setup;
1354 uint8_t vp_idx; /* Format 0=reserved */
1355 uint8_t vp_status; /* Format 0=reserved */
1356
1357 uint8_t port_id[3];
1358 uint8_t format;
1359 union {
1360 struct {
1361 /* format 0 loop */
1362 uint8_t vp_idx_map[16];
1363 uint8_t reserved_4[32];
1364 } f0;
1365 struct {
1366 /* format 1 fabric */
1367 uint8_t vpstat1_subcode; /* vp_status=1 subcode */
1368 uint8_t flags;
1369 #define TOPO_MASK 0xE
1370 #define TOPO_FL 0x2
1371 #define TOPO_N2N 0x4
1372 #define TOPO_F 0x6
1373
1374 uint16_t fip_flags;
1375 uint8_t rsv2[12];
1376
1377 uint8_t ls_rjt_vendor;
1378 uint8_t ls_rjt_explanation;
1379 uint8_t ls_rjt_reason;
1380 uint8_t rsv3[5];
1381
1382 uint8_t port_name[8];
1383 uint8_t node_name[8];
1384 uint16_t bbcr;
1385 uint8_t reserved_5[6];
1386 } f1;
1387 struct { /* format 2: N2N direct connect */
1388 uint8_t vpstat1_subcode;
1389 uint8_t flags;
1390 uint16_t rsv6;
1391 uint8_t rsv2[12];
1392
1393 uint8_t ls_rjt_vendor;
1394 uint8_t ls_rjt_explanation;
1395 uint8_t ls_rjt_reason;
1396 uint8_t rsv3[5];
1397
1398 uint8_t port_name[8];
1399 uint8_t node_name[8];
1400 uint8_t remote_nport_id[4];
1401 uint32_t reserved_5;
1402 } f2;
1403 } u;
1404 };
1405
1406 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */
1407 struct vf_evfp_entry_24xx {
1408 uint8_t entry_type; /* Entry type. */
1409 uint8_t entry_count; /* Entry count. */
1410 uint8_t sys_define; /* System defined. */
1411 uint8_t entry_status; /* Entry Status. */
1412
1413 uint32_t handle; /* System handle. */
1414 uint16_t comp_status; /* Completion status. */
1415 uint16_t timeout; /* timeout */
1416 uint16_t adim_tagging_mode;
1417
1418 uint16_t vfport_id;
1419 uint32_t exch_addr;
1420
1421 uint16_t nport_handle; /* N_PORT handle. */
1422 uint16_t control_flags;
1423 uint32_t io_parameter_0;
1424 uint32_t io_parameter_1;
1425 uint32_t tx_address[2]; /* Data segment 0 address. */
1426 uint32_t tx_len; /* Data segment 0 length. */
1427 uint32_t rx_address[2]; /* Data segment 1 address. */
1428 uint32_t rx_len; /* Data segment 1 length. */
1429 };
1430
1431 /* END MID Support ***********************************************************/
1432
1433 /* Flash Description Table ***************************************************/
1434
1435 struct qla_fdt_layout {
1436 uint8_t sig[4];
1437 uint16_t version;
1438 uint16_t len;
1439 uint16_t checksum;
1440 uint8_t unused1[2];
1441 uint8_t model[16];
1442 uint16_t man_id;
1443 uint16_t id;
1444 uint8_t flags;
1445 uint8_t erase_cmd;
1446 uint8_t alt_erase_cmd;
1447 uint8_t wrt_enable_cmd;
1448 uint8_t wrt_enable_bits;
1449 uint8_t wrt_sts_reg_cmd;
1450 uint8_t unprotect_sec_cmd;
1451 uint8_t read_man_id_cmd;
1452 uint32_t block_size;
1453 uint32_t alt_block_size;
1454 uint32_t flash_size;
1455 uint32_t wrt_enable_data;
1456 uint8_t read_id_addr_len;
1457 uint8_t wrt_disable_bits;
1458 uint8_t read_dev_id_len;
1459 uint8_t chip_erase_cmd;
1460 uint16_t read_timeout;
1461 uint8_t protect_sec_cmd;
1462 uint8_t unused2[65];
1463 };
1464
1465 /* Flash Layout Table ********************************************************/
1466
1467 struct qla_flt_location {
1468 uint8_t sig[4];
1469 uint16_t start_lo;
1470 uint16_t start_hi;
1471 uint8_t version;
1472 uint8_t unused[5];
1473 uint16_t checksum;
1474 };
1475
1476 struct qla_flt_header {
1477 uint16_t version;
1478 uint16_t length;
1479 uint16_t checksum;
1480 uint16_t unused;
1481 };
1482
1483 #define FLT_REG_FW 0x01
1484 #define FLT_REG_BOOT_CODE 0x07
1485 #define FLT_REG_VPD_0 0x14
1486 #define FLT_REG_NVRAM_0 0x15
1487 #define FLT_REG_VPD_1 0x16
1488 #define FLT_REG_NVRAM_1 0x17
1489 #define FLT_REG_VPD_2 0xD4
1490 #define FLT_REG_NVRAM_2 0xD5
1491 #define FLT_REG_VPD_3 0xD6
1492 #define FLT_REG_NVRAM_3 0xD7
1493 #define FLT_REG_FDT 0x1a
1494 #define FLT_REG_FLT 0x1c
1495 #define FLT_REG_HW_EVENT_0 0x1d
1496 #define FLT_REG_HW_EVENT_1 0x1f
1497 #define FLT_REG_NPIV_CONF_0 0x29
1498 #define FLT_REG_NPIV_CONF_1 0x2a
1499 #define FLT_REG_GOLD_FW 0x2f
1500 #define FLT_REG_FCP_PRIO_0 0x87
1501 #define FLT_REG_FCP_PRIO_1 0x88
1502 #define FLT_REG_CNA_FW 0x97
1503 #define FLT_REG_BOOT_CODE_8044 0xA2
1504 #define FLT_REG_FCOE_FW 0xA4
1505 #define FLT_REG_FCOE_NVRAM_0 0xAA
1506 #define FLT_REG_FCOE_NVRAM_1 0xAC
1507
1508 /* 27xx */
1509 #define FLT_REG_IMG_PRI_27XX 0x95
1510 #define FLT_REG_IMG_SEC_27XX 0x96
1511 #define FLT_REG_FW_SEC_27XX 0x02
1512 #define FLT_REG_BOOTLOAD_SEC_27XX 0x9
1513 #define FLT_REG_VPD_SEC_27XX_0 0x50
1514 #define FLT_REG_VPD_SEC_27XX_1 0x52
1515 #define FLT_REG_VPD_SEC_27XX_2 0xD8
1516 #define FLT_REG_VPD_SEC_27XX_3 0xDA
1517
1518 struct qla_flt_region {
1519 uint32_t code;
1520 uint32_t size;
1521 uint32_t start;
1522 uint32_t end;
1523 };
1524
1525 /* Flash NPIV Configuration Table ********************************************/
1526
1527 struct qla_npiv_header {
1528 uint8_t sig[2];
1529 uint16_t version;
1530 uint16_t entries;
1531 uint16_t unused[4];
1532 uint16_t checksum;
1533 };
1534
1535 struct qla_npiv_entry {
1536 uint16_t flags;
1537 uint16_t vf_id;
1538 uint8_t q_qos;
1539 uint8_t f_qos;
1540 uint16_t unused1;
1541 uint8_t port_name[WWN_SIZE];
1542 uint8_t node_name[WWN_SIZE];
1543 };
1544
1545 /* 84XX Support **************************************************************/
1546
1547 #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */
1548 #define A84_PANIC_RECOVERY 0x1
1549 #define A84_OP_LOGIN_COMPLETE 0x2
1550 #define A84_DIAG_LOGIN_COMPLETE 0x3
1551 #define A84_GOLD_LOGIN_COMPLETE 0x4
1552
1553 #define MBC_ISP84XX_RESET 0x3a /* Reset. */
1554
1555 #define FSTATE_REMOTE_FC_DOWN BIT_0
1556 #define FSTATE_NSL_LINK_DOWN BIT_1
1557 #define FSTATE_IS_DIAG_FW BIT_2
1558 #define FSTATE_LOGGED_IN BIT_3
1559 #define FSTATE_WAITING_FOR_VERIFY BIT_4
1560
1561 #define VERIFY_CHIP_IOCB_TYPE 0x1B
1562 struct verify_chip_entry_84xx {
1563 uint8_t entry_type;
1564 uint8_t entry_count;
1565 uint8_t sys_defined;
1566 uint8_t entry_status;
1567
1568 uint32_t handle;
1569
1570 uint16_t options;
1571 #define VCO_DONT_UPDATE_FW BIT_0
1572 #define VCO_FORCE_UPDATE BIT_1
1573 #define VCO_DONT_RESET_UPDATE BIT_2
1574 #define VCO_DIAG_FW BIT_3
1575 #define VCO_END_OF_DATA BIT_14
1576 #define VCO_ENABLE_DSD BIT_15
1577
1578 uint16_t reserved_1;
1579
1580 uint16_t data_seg_cnt;
1581 uint16_t reserved_2[3];
1582
1583 uint32_t fw_ver;
1584 uint32_t exchange_address;
1585
1586 uint32_t reserved_3[3];
1587 uint32_t fw_size;
1588 uint32_t fw_seq_size;
1589 uint32_t relative_offset;
1590
1591 uint32_t dseg_address[2];
1592 uint32_t dseg_length;
1593 };
1594
1595 struct verify_chip_rsp_84xx {
1596 uint8_t entry_type;
1597 uint8_t entry_count;
1598 uint8_t sys_defined;
1599 uint8_t entry_status;
1600
1601 uint32_t handle;
1602
1603 uint16_t comp_status;
1604 #define CS_VCS_CHIP_FAILURE 0x3
1605 #define CS_VCS_BAD_EXCHANGE 0x8
1606 #define CS_VCS_SEQ_COMPLETEi 0x40
1607
1608 uint16_t failure_code;
1609 #define VFC_CHECKSUM_ERROR 0x1
1610 #define VFC_INVALID_LEN 0x2
1611 #define VFC_ALREADY_IN_PROGRESS 0x8
1612
1613 uint16_t reserved_1[4];
1614
1615 uint32_t fw_ver;
1616 uint32_t exchange_address;
1617
1618 uint32_t reserved_2[6];
1619 };
1620
1621 #define ACCESS_CHIP_IOCB_TYPE 0x2B
1622 struct access_chip_84xx {
1623 uint8_t entry_type;
1624 uint8_t entry_count;
1625 uint8_t sys_defined;
1626 uint8_t entry_status;
1627
1628 uint32_t handle;
1629
1630 uint16_t options;
1631 #define ACO_DUMP_MEMORY 0x0
1632 #define ACO_LOAD_MEMORY 0x1
1633 #define ACO_CHANGE_CONFIG_PARAM 0x2
1634 #define ACO_REQUEST_INFO 0x3
1635
1636 uint16_t reserved1;
1637
1638 uint16_t dseg_count;
1639 uint16_t reserved2[3];
1640
1641 uint32_t parameter1;
1642 uint32_t parameter2;
1643 uint32_t parameter3;
1644
1645 uint32_t reserved3[3];
1646 uint32_t total_byte_cnt;
1647 uint32_t reserved4;
1648
1649 uint32_t dseg_address[2];
1650 uint32_t dseg_length;
1651 };
1652
1653 struct access_chip_rsp_84xx {
1654 uint8_t entry_type;
1655 uint8_t entry_count;
1656 uint8_t sys_defined;
1657 uint8_t entry_status;
1658
1659 uint32_t handle;
1660
1661 uint16_t comp_status;
1662 uint16_t failure_code;
1663 uint32_t residual_count;
1664
1665 uint32_t reserved[12];
1666 };
1667
1668 /* 81XX Support **************************************************************/
1669
1670 #define MBA_DCBX_START 0x8016
1671 #define MBA_DCBX_COMPLETE 0x8030
1672 #define MBA_FCF_CONF_ERR 0x8031
1673 #define MBA_DCBX_PARAM_UPDATE 0x8032
1674 #define MBA_IDC_COMPLETE 0x8100
1675 #define MBA_IDC_NOTIFY 0x8101
1676 #define MBA_IDC_TIME_EXT 0x8102
1677
1678 #define MBC_IDC_ACK 0x101
1679 #define MBC_RESTART_MPI_FW 0x3d
1680 #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */
1681 #define MBC_GET_XGMAC_STATS 0x7a
1682 #define MBC_GET_DCBX_PARAMS 0x51
1683
1684 /*
1685 * ISP83xx mailbox commands
1686 */
1687 #define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */
1688 #define MBC_READ_REMOTE_REG 0x0009 /* Read remote register */
1689 #define MBC_RESTART_NIC_FIRMWARE 0x003d /* Restart NIC firmware */
1690 #define MBC_SET_ACCESS_CONTROL 0x003e /* Access control command */
1691
1692 /* Flash access control option field bit definitions */
1693 #define FAC_OPT_FORCE_SEMAPHORE BIT_15
1694 #define FAC_OPT_REQUESTOR_ID BIT_14
1695 #define FAC_OPT_CMD_SUBCODE 0xff
1696
1697 /* Flash access control command subcodes */
1698 #define FAC_OPT_CMD_WRITE_PROTECT 0x00
1699 #define FAC_OPT_CMD_WRITE_ENABLE 0x01
1700 #define FAC_OPT_CMD_ERASE_SECTOR 0x02
1701 #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03
1702 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04
1703 #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05
1704
1705 /* enhanced features bit definitions */
1706 #define NEF_LR_DIST_ENABLE BIT_0
1707
1708 /* LR Distance bit positions */
1709 #define LR_DIST_NV_POS 2
1710 #define LR_DIST_FW_POS 12
1711 #define LR_DIST_FW_SHIFT (LR_DIST_FW_POS - LR_DIST_NV_POS)
1712 #define LR_DIST_FW_FIELD(x) ((x) << LR_DIST_FW_SHIFT & 0xf000)
1713
1714 struct nvram_81xx {
1715 /* NVRAM header. */
1716 uint8_t id[4];
1717 uint16_t nvram_version;
1718 uint16_t reserved_0;
1719
1720 /* Firmware Initialization Control Block. */
1721 uint16_t version;
1722 uint16_t reserved_1;
1723 uint16_t frame_payload_size;
1724 uint16_t execution_throttle;
1725 uint16_t exchange_count;
1726 uint16_t reserved_2;
1727
1728 uint8_t port_name[WWN_SIZE];
1729 uint8_t node_name[WWN_SIZE];
1730
1731 uint16_t login_retry_count;
1732 uint16_t reserved_3;
1733 uint16_t interrupt_delay_timer;
1734 uint16_t login_timeout;
1735
1736 uint32_t firmware_options_1;
1737 uint32_t firmware_options_2;
1738 uint32_t firmware_options_3;
1739
1740 uint16_t reserved_4[4];
1741
1742 /* Offset 64. */
1743 uint8_t enode_mac[6];
1744 uint16_t reserved_5[5];
1745
1746 /* Offset 80. */
1747 uint16_t reserved_6[24];
1748
1749 /* Offset 128. */
1750 uint16_t ex_version;
1751 uint8_t prio_fcf_matching_flags;
1752 uint8_t reserved_6_1[3];
1753 uint16_t pri_fcf_vlan_id;
1754 uint8_t pri_fcf_fabric_name[8];
1755 uint16_t reserved_6_2[7];
1756 uint8_t spma_mac_addr[6];
1757 uint16_t reserved_6_3[14];
1758
1759 /* Offset 192. */
1760 uint8_t min_link_speed;
1761 uint8_t reserved_7_0;
1762 uint16_t reserved_7[31];
1763
1764 /*
1765 * BIT 0 = Enable spinup delay
1766 * BIT 1 = Disable BIOS
1767 * BIT 2 = Enable Memory Map BIOS
1768 * BIT 3 = Enable Selectable Boot
1769 * BIT 4 = Disable RISC code load
1770 * BIT 5 = Disable Serdes
1771 * BIT 6 = Opt boot mode
1772 * BIT 7 = Interrupt enable
1773 *
1774 * BIT 8 = EV Control enable
1775 * BIT 9 = Enable lip reset
1776 * BIT 10 = Enable lip full login
1777 * BIT 11 = Enable target reset
1778 * BIT 12 = Stop firmware
1779 * BIT 13 = Enable nodename option
1780 * BIT 14 = Default WWPN valid
1781 * BIT 15 = Enable alternate WWN
1782 *
1783 * BIT 16 = CLP LUN string
1784 * BIT 17 = CLP Target string
1785 * BIT 18 = CLP BIOS enable string
1786 * BIT 19 = CLP Serdes string
1787 * BIT 20 = CLP WWPN string
1788 * BIT 21 = CLP WWNN string
1789 * BIT 22 =
1790 * BIT 23 =
1791 * BIT 24 = Keep WWPN
1792 * BIT 25 = Temp WWPN
1793 * BIT 26-31 =
1794 */
1795 uint32_t host_p;
1796
1797 uint8_t alternate_port_name[WWN_SIZE];
1798 uint8_t alternate_node_name[WWN_SIZE];
1799
1800 uint8_t boot_port_name[WWN_SIZE];
1801 uint16_t boot_lun_number;
1802 uint16_t reserved_8;
1803
1804 uint8_t alt1_boot_port_name[WWN_SIZE];
1805 uint16_t alt1_boot_lun_number;
1806 uint16_t reserved_9;
1807
1808 uint8_t alt2_boot_port_name[WWN_SIZE];
1809 uint16_t alt2_boot_lun_number;
1810 uint16_t reserved_10;
1811
1812 uint8_t alt3_boot_port_name[WWN_SIZE];
1813 uint16_t alt3_boot_lun_number;
1814 uint16_t reserved_11;
1815
1816 /*
1817 * BIT 0 = Selective Login
1818 * BIT 1 = Alt-Boot Enable
1819 * BIT 2 = Reserved
1820 * BIT 3 = Boot Order List
1821 * BIT 4 = Reserved
1822 * BIT 5 = Selective LUN
1823 * BIT 6 = Reserved
1824 * BIT 7-31 =
1825 */
1826 uint32_t efi_parameters;
1827
1828 uint8_t reset_delay;
1829 uint8_t reserved_12;
1830 uint16_t reserved_13;
1831
1832 uint16_t boot_id_number;
1833 uint16_t reserved_14;
1834
1835 uint16_t max_luns_per_target;
1836 uint16_t reserved_15;
1837
1838 uint16_t port_down_retry_count;
1839 uint16_t link_down_timeout;
1840
1841 /* FCode parameters. */
1842 uint16_t fcode_parameter;
1843
1844 uint16_t reserved_16[3];
1845
1846 /* Offset 352. */
1847 uint8_t reserved_17[4];
1848 uint16_t reserved_18[5];
1849 uint8_t reserved_19[2];
1850 uint16_t reserved_20[8];
1851
1852 /* Offset 384. */
1853 uint8_t reserved_21[16];
1854 uint16_t reserved_22[3];
1855
1856 /* Offset 406 (0x196) Enhanced Features
1857 * BIT 0 = Extended BB credits for LR
1858 * BIT 1 = Virtual Fabric Enable
1859 * BIT 2-5 = Distance Support if BIT 0 is on
1860 * BIT 6-15 = Unused
1861 */
1862 uint16_t enhanced_features;
1863 uint16_t reserved_24[4];
1864
1865 /* Offset 416. */
1866 uint16_t reserved_25[32];
1867
1868 /* Offset 480. */
1869 uint8_t model_name[16];
1870
1871 /* Offset 496. */
1872 uint16_t feature_mask_l;
1873 uint16_t feature_mask_h;
1874 uint16_t reserved_26[2];
1875
1876 uint16_t subsystem_vendor_id;
1877 uint16_t subsystem_device_id;
1878
1879 uint32_t checksum;
1880 };
1881
1882 /*
1883 * ISP Initialization Control Block.
1884 * Little endian except where noted.
1885 */
1886 #define ICB_VERSION 1
1887 struct init_cb_81xx {
1888 uint16_t version;
1889 uint16_t reserved_1;
1890
1891 uint16_t frame_payload_size;
1892 uint16_t execution_throttle;
1893 uint16_t exchange_count;
1894
1895 uint16_t reserved_2;
1896
1897 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1898 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1899
1900 uint16_t response_q_inpointer;
1901 uint16_t request_q_outpointer;
1902
1903 uint16_t login_retry_count;
1904
1905 uint16_t prio_request_q_outpointer;
1906
1907 uint16_t response_q_length;
1908 uint16_t request_q_length;
1909
1910 uint16_t reserved_3;
1911
1912 uint16_t prio_request_q_length;
1913
1914 uint32_t request_q_address[2];
1915 uint32_t response_q_address[2];
1916 uint32_t prio_request_q_address[2];
1917
1918 uint8_t reserved_4[8];
1919
1920 uint16_t atio_q_inpointer;
1921 uint16_t atio_q_length;
1922 uint32_t atio_q_address[2];
1923
1924 uint16_t interrupt_delay_timer; /* 100us increments. */
1925 uint16_t login_timeout;
1926
1927 /*
1928 * BIT 0-3 = Reserved
1929 * BIT 4 = Enable Target Mode
1930 * BIT 5 = Disable Initiator Mode
1931 * BIT 6 = Reserved
1932 * BIT 7 = Reserved
1933 *
1934 * BIT 8-13 = Reserved
1935 * BIT 14 = Node Name Option
1936 * BIT 15-31 = Reserved
1937 */
1938 uint32_t firmware_options_1;
1939
1940 /*
1941 * BIT 0 = Operation Mode bit 0
1942 * BIT 1 = Operation Mode bit 1
1943 * BIT 2 = Operation Mode bit 2
1944 * BIT 3 = Operation Mode bit 3
1945 * BIT 4-7 = Reserved
1946 *
1947 * BIT 8 = Enable Class 2
1948 * BIT 9 = Enable ACK0
1949 * BIT 10 = Reserved
1950 * BIT 11 = Enable FC-SP Security
1951 * BIT 12 = FC Tape Enable
1952 * BIT 13 = Reserved
1953 * BIT 14 = Enable Target PRLI Control
1954 * BIT 15-31 = Reserved
1955 */
1956 uint32_t firmware_options_2;
1957
1958 /*
1959 * BIT 0-3 = Reserved
1960 * BIT 4 = FCP RSP Payload bit 0
1961 * BIT 5 = FCP RSP Payload bit 1
1962 * BIT 6 = Enable Receive Out-of-Order data frame handling
1963 * BIT 7 = Reserved
1964 *
1965 * BIT 8 = Reserved
1966 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
1967 * BIT 10-16 = Reserved
1968 * BIT 17 = Enable multiple FCFs
1969 * BIT 18-20 = MAC addressing mode
1970 * BIT 21-25 = Ethernet data rate
1971 * BIT 26 = Enable ethernet header rx IOCB for ATIO q
1972 * BIT 27 = Enable ethernet header rx IOCB for response q
1973 * BIT 28 = SPMA selection bit 0
1974 * BIT 28 = SPMA selection bit 1
1975 * BIT 30-31 = Reserved
1976 */
1977 uint32_t firmware_options_3;
1978
1979 uint8_t reserved_5[8];
1980
1981 uint8_t enode_mac[6];
1982
1983 uint8_t reserved_6[10];
1984 };
1985
1986 struct mid_init_cb_81xx {
1987 struct init_cb_81xx init_cb;
1988
1989 uint16_t count;
1990 uint16_t options;
1991
1992 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1993 };
1994
1995 struct ex_init_cb_81xx {
1996 uint16_t ex_version;
1997 uint8_t prio_fcf_matching_flags;
1998 uint8_t reserved_1[3];
1999 uint16_t pri_fcf_vlan_id;
2000 uint8_t pri_fcf_fabric_name[8];
2001 uint16_t reserved_2[7];
2002 uint8_t spma_mac_addr[6];
2003 uint16_t reserved_3[14];
2004 };
2005
2006 #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
2007 #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
2008
2009 /* FCP priority config defines *************************************/
2010 /* operations */
2011 #define QLFC_FCP_PRIO_DISABLE 0x0
2012 #define QLFC_FCP_PRIO_ENABLE 0x1
2013 #define QLFC_FCP_PRIO_GET_CONFIG 0x2
2014 #define QLFC_FCP_PRIO_SET_CONFIG 0x3
2015
2016 struct qla_fcp_prio_entry {
2017 uint16_t flags; /* Describes parameter(s) in FCP */
2018 /* priority entry that are valid */
2019 #define FCP_PRIO_ENTRY_VALID 0x1
2020 #define FCP_PRIO_ENTRY_TAG_VALID 0x2
2021 #define FCP_PRIO_ENTRY_SPID_VALID 0x4
2022 #define FCP_PRIO_ENTRY_DPID_VALID 0x8
2023 #define FCP_PRIO_ENTRY_LUNB_VALID 0x10
2024 #define FCP_PRIO_ENTRY_LUNE_VALID 0x20
2025 #define FCP_PRIO_ENTRY_SWWN_VALID 0x40
2026 #define FCP_PRIO_ENTRY_DWWN_VALID 0x80
2027 uint8_t tag; /* Priority value */
2028 uint8_t reserved; /* Reserved for future use */
2029 uint32_t src_pid; /* Src port id. high order byte */
2030 /* unused; -1 (wild card) */
2031 uint32_t dst_pid; /* Src port id. high order byte */
2032 /* unused; -1 (wild card) */
2033 uint16_t lun_beg; /* 1st lun num of lun range. */
2034 /* -1 (wild card) */
2035 uint16_t lun_end; /* 2nd lun num of lun range. */
2036 /* -1 (wild card) */
2037 uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */
2038 uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */
2039 };
2040
2041 struct qla_fcp_prio_cfg {
2042 uint8_t signature[4]; /* "HQOS" signature of config data */
2043 uint16_t version; /* 1: Initial version */
2044 uint16_t length; /* config data size in num bytes */
2045 uint16_t checksum; /* config data bytes checksum */
2046 uint16_t num_entries; /* Number of entries */
2047 uint16_t size_of_entry; /* Size of each entry in num bytes */
2048 uint8_t attributes; /* enable/disable, persistence */
2049 #define FCP_PRIO_ATTR_DISABLE 0x0
2050 #define FCP_PRIO_ATTR_ENABLE 0x1
2051 #define FCP_PRIO_ATTR_PERSIST 0x2
2052 uint8_t reserved; /* Reserved for future use */
2053 #define FCP_PRIO_CFG_HDR_SIZE 0x10
2054 struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */
2055 #define FCP_PRIO_CFG_ENTRY_SIZE 0x20
2056 };
2057
2058 #define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/
2059
2060 /* 25XX Support ****************************************************/
2061 #define FA_FCP_PRIO0_ADDR_25 0x3C000
2062 #define FA_FCP_PRIO1_ADDR_25 0x3E000
2063
2064 /* 81XX Flash locations -- occupies second 2MB region. */
2065 #define FA_BOOT_CODE_ADDR_81 0x80000
2066 #define FA_RISC_CODE_ADDR_81 0xA0000
2067 #define FA_FW_AREA_ADDR_81 0xC0000
2068 #define FA_VPD_NVRAM_ADDR_81 0xD0000
2069 #define FA_VPD0_ADDR_81 0xD0000
2070 #define FA_VPD1_ADDR_81 0xD0400
2071 #define FA_NVRAM0_ADDR_81 0xD0080
2072 #define FA_NVRAM1_ADDR_81 0xD0180
2073 #define FA_FEATURE_ADDR_81 0xD4000
2074 #define FA_FLASH_DESCR_ADDR_81 0xD8000
2075 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400
2076 #define FA_HW_EVENT0_ADDR_81 0xDC000
2077 #define FA_HW_EVENT1_ADDR_81 0xDC400
2078 #define FA_NPIV_CONF0_ADDR_81 0xD1000
2079 #define FA_NPIV_CONF1_ADDR_81 0xD2000
2080
2081 /* 83XX Flash locations -- occupies second 8MB region. */
2082 #define FA_FLASH_LAYOUT_ADDR_83 0xFC400
2083
2084 #endif
Linux with added FPC-III support