2 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 /include/ "skeleton_hs_idu.dtsi"
13 model = "snps,zebu_hs-smp";
14 compatible = "snps,zebu_hs";
17 interrupt-parent = <&core_intc>;
20 device_type = "memory";
21 reg = <0x80000000 0x20000000>; /* 512 */
25 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
33 compatible = "simple-bus";
37 /* child and parent address space 1:1 mapped */
42 compatible = "fixed-clock";
43 clock-frequency = <50000000>; /* 50 MHZ */
46 core_intc: interrupt-controller {
47 compatible = "snps,archs-intc";
49 #interrupt-cells = <1>;
52 idu_intc: idu-interrupt-controller {
53 compatible = "snps,archs-idu-intc";
55 interrupt-parent = <&core_intc>;
56 #interrupt-cells = <1>;
59 uart0: serial@f0000000 {
60 /* compatible = "ns8250"; Doesn't use FIFOs */
61 compatible = "ns16550a";
62 reg = <0xf0000000 0x2000>;
63 interrupt-parent = <&idu_intc>;
65 clock-frequency = <50000000>;
69 no-loopback-test = <1>;
73 compatible = "snps,archs-pct";
74 #interrupt-cells = <1>;