2 * Based on arch/arm/kernel/process.c
4 * Original Copyright (C) 1995 Linus Torvalds
5 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6 * Copyright (C) 2012 ARM Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/compat.h>
24 #include <linux/efi.h>
25 #include <linux/export.h>
26 #include <linux/sched.h>
27 #include <linux/sched/debug.h>
28 #include <linux/sched/task.h>
29 #include <linux/sched/task_stack.h>
30 #include <linux/kernel.h>
32 #include <linux/stddef.h>
33 #include <linux/unistd.h>
34 #include <linux/user.h>
35 #include <linux/delay.h>
36 #include <linux/reboot.h>
37 #include <linux/interrupt.h>
38 #include <linux/init.h>
39 #include <linux/cpu.h>
40 #include <linux/elfcore.h>
42 #include <linux/tick.h>
43 #include <linux/utsname.h>
44 #include <linux/uaccess.h>
45 #include <linux/random.h>
46 #include <linux/hw_breakpoint.h>
47 #include <linux/personality.h>
48 #include <linux/notifier.h>
49 #include <trace/events/power.h>
50 #include <linux/percpu.h>
51 #include <linux/thread_info.h>
53 #include <asm/alternative.h>
54 #include <asm/arch_gicv3.h>
55 #include <asm/compat.h>
56 #include <asm/cacheflush.h>
58 #include <asm/fpsimd.h>
59 #include <asm/mmu_context.h>
60 #include <asm/processor.h>
61 #include <asm/pointer_auth.h>
62 #include <asm/stacktrace.h>
64 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
65 #include <linux/stackprotector.h>
66 unsigned long __stack_chk_guard __read_mostly
;
67 EXPORT_SYMBOL(__stack_chk_guard
);
71 * Function pointers to optional machine specific functions
73 void (*pm_power_off
)(void);
74 EXPORT_SYMBOL_GPL(pm_power_off
);
76 void (*arm_pm_restart
)(enum reboot_mode reboot_mode
, const char *cmd
);
78 static void __cpu_do_idle(void)
84 static void __cpu_do_idle_irqprio(void)
87 unsigned long daif_bits
;
89 daif_bits
= read_sysreg(daif
);
90 write_sysreg(daif_bits
| PSR_I_BIT
, daif
);
93 * Unmask PMR before going idle to make sure interrupts can
97 gic_write_pmr(GIC_PRIO_IRQON
);
102 write_sysreg(daif_bits
, daif
);
108 * Idle the processor (wait for interrupt).
110 * If the CPU supports priority masking we must do additional work to
111 * ensure that interrupts are not masked at the PMR (because the core will
112 * not wake up if we block the wake up signal in the interrupt controller).
114 void cpu_do_idle(void)
116 if (system_uses_irq_prio_masking())
117 __cpu_do_idle_irqprio();
123 * This is our default idle handler.
125 void arch_cpu_idle(void)
128 * This should do all the clock switching and wait for interrupt
131 trace_cpu_idle_rcuidle(1, smp_processor_id());
134 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT
, smp_processor_id());
137 #ifdef CONFIG_HOTPLUG_CPU
138 void arch_cpu_idle_dead(void)
145 * Called by kexec, immediately prior to machine_kexec().
147 * This must completely disable all secondary CPUs; simply causing those CPUs
148 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
149 * kexec'd kernel to use any and all RAM as it sees fit, without having to
150 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
151 * functionality embodied in disable_nonboot_cpus() to achieve this.
153 void machine_shutdown(void)
155 disable_nonboot_cpus();
159 * Halting simply requires that the secondary CPUs stop performing any
160 * activity (executing tasks, handling interrupts). smp_send_stop()
163 void machine_halt(void)
171 * Power-off simply requires that the secondary CPUs stop performing any
172 * activity (executing tasks, handling interrupts). smp_send_stop()
173 * achieves this. When the system power is turned off, it will take all CPUs
176 void machine_power_off(void)
185 * Restart requires that the secondary CPUs stop performing any activity
186 * while the primary CPU resets the system. Systems with multiple CPUs must
187 * provide a HW restart implementation, to ensure that all CPUs reset at once.
188 * This is required so that any code running after reset on the primary CPU
189 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
190 * executing pre-reset code, and using RAM that the primary CPU's code wishes
191 * to use. Implementing such co-ordination would be essentially impossible.
193 void machine_restart(char *cmd
)
195 /* Disable interrupts first */
200 * UpdateCapsule() depends on the system being reset via
203 if (efi_enabled(EFI_RUNTIME_SERVICES
))
204 efi_reboot(reboot_mode
, NULL
);
206 /* Now call the architecture specific reboot code. */
208 arm_pm_restart(reboot_mode
, cmd
);
210 do_kernel_restart(cmd
);
213 * Whoops - the architecture was unable to reboot.
215 printk("Reboot failed -- System halted\n");
219 static void print_pstate(struct pt_regs
*regs
)
221 u64 pstate
= regs
->pstate
;
223 if (compat_user_mode(regs
)) {
224 printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c)\n",
226 pstate
& PSR_AA32_N_BIT
? 'N' : 'n',
227 pstate
& PSR_AA32_Z_BIT
? 'Z' : 'z',
228 pstate
& PSR_AA32_C_BIT
? 'C' : 'c',
229 pstate
& PSR_AA32_V_BIT
? 'V' : 'v',
230 pstate
& PSR_AA32_Q_BIT
? 'Q' : 'q',
231 pstate
& PSR_AA32_T_BIT
? "T32" : "A32",
232 pstate
& PSR_AA32_E_BIT
? "BE" : "LE",
233 pstate
& PSR_AA32_A_BIT
? 'A' : 'a',
234 pstate
& PSR_AA32_I_BIT
? 'I' : 'i',
235 pstate
& PSR_AA32_F_BIT
? 'F' : 'f');
237 printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO)\n",
239 pstate
& PSR_N_BIT
? 'N' : 'n',
240 pstate
& PSR_Z_BIT
? 'Z' : 'z',
241 pstate
& PSR_C_BIT
? 'C' : 'c',
242 pstate
& PSR_V_BIT
? 'V' : 'v',
243 pstate
& PSR_D_BIT
? 'D' : 'd',
244 pstate
& PSR_A_BIT
? 'A' : 'a',
245 pstate
& PSR_I_BIT
? 'I' : 'i',
246 pstate
& PSR_F_BIT
? 'F' : 'f',
247 pstate
& PSR_PAN_BIT
? '+' : '-',
248 pstate
& PSR_UAO_BIT
? '+' : '-');
252 void __show_regs(struct pt_regs
*regs
)
257 if (compat_user_mode(regs
)) {
258 lr
= regs
->compat_lr
;
259 sp
= regs
->compat_sp
;
267 show_regs_print_info(KERN_DEFAULT
);
270 if (!user_mode(regs
)) {
271 printk("pc : %pS\n", (void *)regs
->pc
);
272 printk("lr : %pS\n", (void *)lr
);
274 printk("pc : %016llx\n", regs
->pc
);
275 printk("lr : %016llx\n", lr
);
278 printk("sp : %016llx\n", sp
);
280 if (system_uses_irq_prio_masking())
281 printk("pmr_save: %08llx\n", regs
->pmr_save
);
286 printk("x%-2d: %016llx ", i
, regs
->regs
[i
]);
290 pr_cont("x%-2d: %016llx ", i
, regs
->regs
[i
]);
298 void show_regs(struct pt_regs
* regs
)
301 dump_backtrace(regs
, NULL
);
304 static void tls_thread_flush(void)
306 write_sysreg(0, tpidr_el0
);
308 if (is_compat_task()) {
309 current
->thread
.uw
.tp_value
= 0;
312 * We need to ensure ordering between the shadow state and the
313 * hardware state, so that we don't corrupt the hardware state
314 * with a stale shadow state during context switch.
317 write_sysreg(0, tpidrro_el0
);
321 void flush_thread(void)
323 fpsimd_flush_thread();
325 flush_ptrace_hw_breakpoint(current
);
328 void release_thread(struct task_struct
*dead_task
)
332 void arch_release_task_struct(struct task_struct
*tsk
)
334 fpsimd_release_task(tsk
);
338 * src and dst may temporarily have aliased sve_state after task_struct
339 * is copied. We cannot fix this properly here, because src may have
340 * live SVE state and dst's thread_info may not exist yet, so tweaking
341 * either src's or dst's TIF_SVE is not safe.
343 * The unaliasing is done in copy_thread() instead. This works because
344 * dst is not schedulable or traceable until both of these functions
347 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
350 fpsimd_preserve_current_state();
356 asmlinkage
void ret_from_fork(void) asm("ret_from_fork");
358 int copy_thread(unsigned long clone_flags
, unsigned long stack_start
,
359 unsigned long stk_sz
, struct task_struct
*p
)
361 struct pt_regs
*childregs
= task_pt_regs(p
);
363 memset(&p
->thread
.cpu_context
, 0, sizeof(struct cpu_context
));
366 * Unalias p->thread.sve_state (if any) from the parent task
367 * and disable discard SVE state for p:
369 clear_tsk_thread_flag(p
, TIF_SVE
);
370 p
->thread
.sve_state
= NULL
;
373 * In case p was allocated the same task_struct pointer as some
374 * other recently-exited task, make sure p is disassociated from
375 * any cpu that may have run that now-exited task recently.
376 * Otherwise we could erroneously skip reloading the FPSIMD
379 fpsimd_flush_task_state(p
);
381 if (likely(!(p
->flags
& PF_KTHREAD
))) {
382 *childregs
= *current_pt_regs();
383 childregs
->regs
[0] = 0;
386 * Read the current TLS pointer from tpidr_el0 as it may be
387 * out-of-sync with the saved value.
389 *task_user_tls(p
) = read_sysreg(tpidr_el0
);
392 if (is_compat_thread(task_thread_info(p
)))
393 childregs
->compat_sp
= stack_start
;
395 childregs
->sp
= stack_start
;
399 * If a TLS pointer was passed to clone (4th argument), use it
400 * for the new thread.
402 if (clone_flags
& CLONE_SETTLS
)
403 p
->thread
.uw
.tp_value
= childregs
->regs
[3];
405 memset(childregs
, 0, sizeof(struct pt_regs
));
406 childregs
->pstate
= PSR_MODE_EL1h
;
407 if (IS_ENABLED(CONFIG_ARM64_UAO
) &&
408 cpus_have_const_cap(ARM64_HAS_UAO
))
409 childregs
->pstate
|= PSR_UAO_BIT
;
411 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE
)
412 childregs
->pstate
|= PSR_SSBS_BIT
;
414 if (system_uses_irq_prio_masking())
415 childregs
->pmr_save
= GIC_PRIO_IRQON
;
417 p
->thread
.cpu_context
.x19
= stack_start
;
418 p
->thread
.cpu_context
.x20
= stk_sz
;
420 p
->thread
.cpu_context
.pc
= (unsigned long)ret_from_fork
;
421 p
->thread
.cpu_context
.sp
= (unsigned long)childregs
;
423 ptrace_hw_copy_thread(p
);
428 void tls_preserve_current_state(void)
430 *task_user_tls(current
) = read_sysreg(tpidr_el0
);
433 static void tls_thread_switch(struct task_struct
*next
)
435 tls_preserve_current_state();
437 if (is_compat_thread(task_thread_info(next
)))
438 write_sysreg(next
->thread
.uw
.tp_value
, tpidrro_el0
);
439 else if (!arm64_kernel_unmapped_at_el0())
440 write_sysreg(0, tpidrro_el0
);
442 write_sysreg(*task_user_tls(next
), tpidr_el0
);
445 /* Restore the UAO state depending on next's addr_limit */
446 void uao_thread_switch(struct task_struct
*next
)
448 if (IS_ENABLED(CONFIG_ARM64_UAO
)) {
449 if (task_thread_info(next
)->addr_limit
== KERNEL_DS
)
450 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO
));
452 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO
));
457 * We store our current task in sp_el0, which is clobbered by userspace. Keep a
458 * shadow copy so that we can restore this upon entry from userspace.
460 * This is *only* for exception entry from EL0, and is not valid until we
461 * __switch_to() a user task.
463 DEFINE_PER_CPU(struct task_struct
*, __entry_task
);
465 static void entry_task_switch(struct task_struct
*next
)
467 __this_cpu_write(__entry_task
, next
);
473 __notrace_funcgraph
struct task_struct
*__switch_to(struct task_struct
*prev
,
474 struct task_struct
*next
)
476 struct task_struct
*last
;
478 fpsimd_thread_switch(next
);
479 tls_thread_switch(next
);
480 hw_breakpoint_thread_switch(next
);
481 contextidr_thread_switch(next
);
482 entry_task_switch(next
);
483 uao_thread_switch(next
);
484 ptrauth_thread_switch(next
);
487 * Complete any pending TLB or cache maintenance on this CPU in case
488 * the thread migrates to a different CPU.
489 * This full barrier is also required by the membarrier system
494 /* the actual thread switch */
495 last
= cpu_switch_to(prev
, next
);
500 unsigned long get_wchan(struct task_struct
*p
)
502 struct stackframe frame
;
503 unsigned long stack_page
, ret
= 0;
505 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
508 stack_page
= (unsigned long)try_get_task_stack(p
);
512 frame
.fp
= thread_saved_fp(p
);
513 frame
.pc
= thread_saved_pc(p
);
514 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
518 if (unwind_frame(p
, &frame
))
520 if (!in_sched_functions(frame
.pc
)) {
524 } while (count
++ < 16);
531 unsigned long arch_align_stack(unsigned long sp
)
533 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
534 sp
-= get_random_int() & ~PAGE_MASK
;
538 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
540 if (is_compat_task())
541 return randomize_page(mm
->brk
, SZ_32M
);
543 return randomize_page(mm
->brk
, SZ_1G
);
547 * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
549 void arch_setup_new_exec(void)
551 current
->mm
->context
.flags
= is_compat_task() ? MMCF_AARCH32
: 0;
553 ptrauth_thread_init_user(current
);