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drm/exynos: Stop using drm_framebuffer_unregister_private
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-octeon-core.c
blob1d87757990568c40b9cebe4df7dda54fe21918f7
1 /*
2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
4 *
5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
6 *
7 * This file contains the shared part of the driver for the i2c adapter in
8 * Cavium Networks' OCTEON processors and ThunderX SOCs.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20
21 #include "i2c-octeon-core.h"
22
23 /* interrupt service routine */
24 irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
25 {
26 struct octeon_i2c *i2c = dev_id;
27
28 i2c->int_disable(i2c);
29 wake_up(&i2c->queue);
30
31 return IRQ_HANDLED;
32 }
33
34 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c)
35 {
36 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);
37 }
38
39 /**
40 * octeon_i2c_wait - wait for the IFLG to be set
41 * @i2c: The struct octeon_i2c
42 *
43 * Returns 0 on success, otherwise a negative errno.
44 */
45 static int octeon_i2c_wait(struct octeon_i2c *i2c)
46 {
47 long time_left;
48
49 /*
50 * Some chip revisions don't assert the irq in the interrupt
51 * controller. So we must poll for the IFLG change.
52 */
53 if (i2c->broken_irq_mode) {
54 u64 end = get_jiffies_64() + i2c->adap.timeout;
55
56 while (!octeon_i2c_test_iflg(i2c) &&
57 time_before64(get_jiffies_64(), end))
58 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
59
60 return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;
61 }
62
63 i2c->int_enable(i2c);
64 time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
65 i2c->adap.timeout);
66 i2c->int_disable(i2c);
67
68 if (i2c->broken_irq_check && !time_left &&
69 octeon_i2c_test_iflg(i2c)) {
70 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
71 i2c->broken_irq_mode = true;
72 return 0;
73 }
74
75 if (!time_left)
76 return -ETIMEDOUT;
77
78 return 0;
79 }
80
81 static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)
82 {
83 return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0;
84 }
85
86 static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
87 {
88 /* clear ST/TS events, listen for neither */
89 octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
90 }
91
92 /*
93 * Cleanup low-level state & enable high-level controller.
94 */
95 static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)
96 {
97 int try = 0;
98 u64 val;
99
100 if (i2c->hlc_enabled)
101 return;
102 i2c->hlc_enabled = true;
103
104 while (1) {
105 val = octeon_i2c_ctl_read(i2c);
106 if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP)))
107 break;
108
109 /* clear IFLG event */
110 if (val & TWSI_CTL_IFLG)
111 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
112
113 if (try++ > 100) {
114 pr_err("%s: giving up\n", __func__);
115 break;
116 }
117
118 /* spin until any start/stop has finished */
119 udelay(10);
120 }
121 octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
122 }
123
124 static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)
125 {
126 if (!i2c->hlc_enabled)
127 return;
128
129 i2c->hlc_enabled = false;
130 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
131 }
132
133 /**
134 * octeon_i2c_hlc_wait - wait for an HLC operation to complete
135 * @i2c: The struct octeon_i2c
136 *
137 * Returns 0 on success, otherwise -ETIMEDOUT.
138 */
139 static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
140 {
141 int time_left;
142
143 /*
144 * Some cn38xx boards don't assert the irq in the interrupt
145 * controller. So we must poll for the valid bit change.
146 */
147 if (i2c->broken_irq_mode) {
148 u64 end = get_jiffies_64() + i2c->adap.timeout;
149
150 while (!octeon_i2c_hlc_test_valid(i2c) &&
151 time_before64(get_jiffies_64(), end))
152 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
153
154 return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT;
155 }
156
157 i2c->hlc_int_enable(i2c);
158 time_left = wait_event_timeout(i2c->queue,
159 octeon_i2c_hlc_test_valid(i2c),
160 i2c->adap.timeout);
161 i2c->hlc_int_disable(i2c);
162 if (!time_left)
163 octeon_i2c_hlc_int_clear(i2c);
164
165 if (i2c->broken_irq_check && !time_left &&
166 octeon_i2c_hlc_test_valid(i2c)) {
167 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
168 i2c->broken_irq_mode = true;
169 return 0;
170 }
171
172 if (!time_left)
173 return -ETIMEDOUT;
174 return 0;
175 }
176
177 static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
178 {
179 u8 stat;
180
181 /*
182 * This is ugly... in HLC mode the status is not in the status register
183 * but in the lower 8 bits of SW_TWSI.
184 */
185 if (i2c->hlc_enabled)
186 stat = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
187 else
188 stat = octeon_i2c_stat_read(i2c);
189
190 switch (stat) {
191 /* Everything is fine */
192 case STAT_IDLE:
193 case STAT_AD2W_ACK:
194 case STAT_RXADDR_ACK:
195 case STAT_TXADDR_ACK:
196 case STAT_TXDATA_ACK:
197 return 0;
198
199 /* ACK allowed on pre-terminal bytes only */
200 case STAT_RXDATA_ACK:
201 if (!final_read)
202 return 0;
203 return -EIO;
204
205 /* NAK allowed on terminal byte only */
206 case STAT_RXDATA_NAK:
207 if (final_read)
208 return 0;
209 return -EIO;
210
211 /* Arbitration lost */
212 case STAT_LOST_ARB_38:
213 case STAT_LOST_ARB_68:
214 case STAT_LOST_ARB_78:
215 case STAT_LOST_ARB_B0:
216 return -EAGAIN;
217
218 /* Being addressed as slave, should back off & listen */
219 case STAT_SLAVE_60:
220 case STAT_SLAVE_70:
221 case STAT_GENDATA_ACK:
222 case STAT_GENDATA_NAK:
223 return -EOPNOTSUPP;
224
225 /* Core busy as slave */
226 case STAT_SLAVE_80:
227 case STAT_SLAVE_88:
228 case STAT_SLAVE_A0:
229 case STAT_SLAVE_A8:
230 case STAT_SLAVE_LOST:
231 case STAT_SLAVE_NAK:
232 case STAT_SLAVE_ACK:
233 return -EOPNOTSUPP;
234
235 case STAT_TXDATA_NAK:
236 return -EIO;
237 case STAT_TXADDR_NAK:
238 case STAT_RXADDR_NAK:
239 case STAT_AD2W_NAK:
240 return -ENXIO;
241 default:
242 dev_err(i2c->dev, "unhandled state: %d\n", stat);
243 return -EIO;
244 }
245 }
246
247 static int octeon_i2c_recovery(struct octeon_i2c *i2c)
248 {
249 int ret;
250
251 ret = i2c_recover_bus(&i2c->adap);
252 if (ret)
253 /* recover failed, try hardware re-init */
254 ret = octeon_i2c_init_lowlevel(i2c);
255 return ret;
256 }
257
258 /**
259 * octeon_i2c_start - send START to the bus
260 * @i2c: The struct octeon_i2c
261 *
262 * Returns 0 on success, otherwise a negative errno.
263 */
264 static int octeon_i2c_start(struct octeon_i2c *i2c)
265 {
266 int ret;
267 u8 stat;
268
269 octeon_i2c_hlc_disable(i2c);
270
271 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);
272 ret = octeon_i2c_wait(i2c);
273 if (ret)
274 goto error;
275
276 stat = octeon_i2c_stat_read(i2c);
277 if (stat == STAT_START || stat == STAT_REP_START)
278 /* START successful, bail out */
279 return 0;
280
281 error:
282 /* START failed, try to recover */
283 ret = octeon_i2c_recovery(i2c);
284 return (ret) ? ret : -EAGAIN;
285 }
286
287 /* send STOP to the bus */
288 static void octeon_i2c_stop(struct octeon_i2c *i2c)
289 {
290 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);
291 }
292
293 /**
294 * octeon_i2c_read - receive data from the bus via low-level controller
295 * @i2c: The struct octeon_i2c
296 * @target: Target address
297 * @data: Pointer to the location to store the data
298 * @rlength: Length of the data
299 * @recv_len: flag for length byte
300 *
301 * The address is sent over the bus, then the data is read.
302 *
303 * Returns 0 on success, otherwise a negative errno.
304 */
305 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
306 u8 *data, u16 *rlength, bool recv_len)
307 {
308 int i, result, length = *rlength;
309 bool final_read = false;
310
311 octeon_i2c_data_write(i2c, (target << 1) | 1);
312 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
313
314 result = octeon_i2c_wait(i2c);
315 if (result)
316 return result;
317
318 /* address OK ? */
319 result = octeon_i2c_check_status(i2c, false);
320 if (result)
321 return result;
322
323 for (i = 0; i < length; i++) {
324 /*
325 * For the last byte to receive TWSI_CTL_AAK must not be set.
326 *
327 * A special case is I2C_M_RECV_LEN where we don't know the
328 * additional length yet. If recv_len is set we assume we're
329 * not reading the final byte and therefore need to set
330 * TWSI_CTL_AAK.
331 */
332 if ((i + 1 == length) && !(recv_len && i == 0))
333 final_read = true;
334
335 /* clear iflg to allow next event */
336 if (final_read)
337 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
338 else
339 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);
340
341 result = octeon_i2c_wait(i2c);
342 if (result)
343 return result;
344
345 data[i] = octeon_i2c_data_read(i2c, &result);
346 if (result)
347 return result;
348 if (recv_len && i == 0) {
349 if (data[i] > I2C_SMBUS_BLOCK_MAX + 1)
350 return -EPROTO;
351 length += data[i];
352 }
353
354 result = octeon_i2c_check_status(i2c, final_read);
355 if (result)
356 return result;
357 }
358 *rlength = length;
359 return 0;
360 }
361
362 /**
363 * octeon_i2c_write - send data to the bus via low-level controller
364 * @i2c: The struct octeon_i2c
365 * @target: Target address
366 * @data: Pointer to the data to be sent
367 * @length: Length of the data
368 *
369 * The address is sent over the bus, then the data.
370 *
371 * Returns 0 on success, otherwise a negative errno.
372 */
373 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
374 const u8 *data, int length)
375 {
376 int i, result;
377
378 octeon_i2c_data_write(i2c, target << 1);
379 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
380
381 result = octeon_i2c_wait(i2c);
382 if (result)
383 return result;
384
385 for (i = 0; i < length; i++) {
386 result = octeon_i2c_check_status(i2c, false);
387 if (result)
388 return result;
389
390 octeon_i2c_data_write(i2c, data[i]);
391 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
392
393 result = octeon_i2c_wait(i2c);
394 if (result)
395 return result;
396 }
397
398 return 0;
399 }
400
401 /* high-level-controller pure read of up to 8 bytes */
402 static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
403 {
404 int i, j, ret = 0;
405 u64 cmd;
406
407 octeon_i2c_hlc_enable(i2c);
408 octeon_i2c_hlc_int_clear(i2c);
409
410 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
411 /* SIZE */
412 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
413 /* A */
414 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
415
416 if (msgs[0].flags & I2C_M_TEN)
417 cmd |= SW_TWSI_OP_10;
418 else
419 cmd |= SW_TWSI_OP_7;
420
421 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
422 ret = octeon_i2c_hlc_wait(i2c);
423 if (ret)
424 goto err;
425
426 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
427 if ((cmd & SW_TWSI_R) == 0)
428 return octeon_i2c_check_status(i2c, false);
429
430 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
431 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
432
433 if (msgs[0].len > 4) {
434 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
435 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
436 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
437 }
438
439 err:
440 return ret;
441 }
442
443 /* high-level-controller pure write of up to 8 bytes */
444 static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
445 {
446 int i, j, ret = 0;
447 u64 cmd;
448
449 octeon_i2c_hlc_enable(i2c);
450 octeon_i2c_hlc_int_clear(i2c);
451
452 cmd = SW_TWSI_V | SW_TWSI_SOVR;
453 /* SIZE */
454 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
455 /* A */
456 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
457
458 if (msgs[0].flags & I2C_M_TEN)
459 cmd |= SW_TWSI_OP_10;
460 else
461 cmd |= SW_TWSI_OP_7;
462
463 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
464 cmd |= (u64)msgs[0].buf[j] << (8 * i);
465
466 if (msgs[0].len > 4) {
467 u64 ext = 0;
468
469 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
470 ext |= (u64)msgs[0].buf[j] << (8 * i);
471 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
472 }
473
474 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
475 ret = octeon_i2c_hlc_wait(i2c);
476 if (ret)
477 goto err;
478
479 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
480 if ((cmd & SW_TWSI_R) == 0)
481 return octeon_i2c_check_status(i2c, false);
482
483 err:
484 return ret;
485 }
486
487 /* high-level-controller composite write+read, msg0=addr, msg1=data */
488 static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
489 {
490 int i, j, ret = 0;
491 u64 cmd;
492
493 octeon_i2c_hlc_enable(i2c);
494
495 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
496 /* SIZE */
497 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
498 /* A */
499 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
500
501 if (msgs[0].flags & I2C_M_TEN)
502 cmd |= SW_TWSI_OP_10_IA;
503 else
504 cmd |= SW_TWSI_OP_7_IA;
505
506 if (msgs[0].len == 2) {
507 u64 ext = 0;
508
509 cmd |= SW_TWSI_EIA;
510 ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
511 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
512 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
513 } else {
514 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
515 }
516
517 octeon_i2c_hlc_int_clear(i2c);
518 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
519
520 ret = octeon_i2c_hlc_wait(i2c);
521 if (ret)
522 goto err;
523
524 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
525 if ((cmd & SW_TWSI_R) == 0)
526 return octeon_i2c_check_status(i2c, false);
527
528 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
529 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
530
531 if (msgs[1].len > 4) {
532 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
533 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
534 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
535 }
536
537 err:
538 return ret;
539 }
540
541 /* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
542 static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
543 {
544 bool set_ext = false;
545 int i, j, ret = 0;
546 u64 cmd, ext = 0;
547
548 octeon_i2c_hlc_enable(i2c);
549
550 cmd = SW_TWSI_V | SW_TWSI_SOVR;
551 /* SIZE */
552 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
553 /* A */
554 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
555
556 if (msgs[0].flags & I2C_M_TEN)
557 cmd |= SW_TWSI_OP_10_IA;
558 else
559 cmd |= SW_TWSI_OP_7_IA;
560
561 if (msgs[0].len == 2) {
562 cmd |= SW_TWSI_EIA;
563 ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
564 set_ext = true;
565 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
566 } else {
567 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
568 }
569
570 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
571 cmd |= (u64)msgs[1].buf[j] << (8 * i);
572
573 if (msgs[1].len > 4) {
574 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
575 ext |= (u64)msgs[1].buf[j] << (8 * i);
576 set_ext = true;
577 }
578 if (set_ext)
579 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
580
581 octeon_i2c_hlc_int_clear(i2c);
582 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
583
584 ret = octeon_i2c_hlc_wait(i2c);
585 if (ret)
586 goto err;
587
588 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
589 if ((cmd & SW_TWSI_R) == 0)
590 return octeon_i2c_check_status(i2c, false);
591
592 err:
593 return ret;
594 }
595
596 /**
597 * octeon_i2c_xfer - The driver's master_xfer function
598 * @adap: Pointer to the i2c_adapter structure
599 * @msgs: Pointer to the messages to be processed
600 * @num: Length of the MSGS array
601 *
602 * Returns the number of messages processed, or a negative errno on failure.
603 */
604 int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
605 {
606 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
607 int i, ret = 0;
608
609 if (num == 1) {
610 if (msgs[0].len > 0 && msgs[0].len <= 8) {
611 if (msgs[0].flags & I2C_M_RD)
612 ret = octeon_i2c_hlc_read(i2c, msgs);
613 else
614 ret = octeon_i2c_hlc_write(i2c, msgs);
615 goto out;
616 }
617 } else if (num == 2) {
618 if ((msgs[0].flags & I2C_M_RD) == 0 &&
619 (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
620 msgs[0].len > 0 && msgs[0].len <= 2 &&
621 msgs[1].len > 0 && msgs[1].len <= 8 &&
622 msgs[0].addr == msgs[1].addr) {
623 if (msgs[1].flags & I2C_M_RD)
624 ret = octeon_i2c_hlc_comp_read(i2c, msgs);
625 else
626 ret = octeon_i2c_hlc_comp_write(i2c, msgs);
627 goto out;
628 }
629 }
630
631 for (i = 0; ret == 0 && i < num; i++) {
632 struct i2c_msg *pmsg = &msgs[i];
633
634 /* zero-length messages are not supported */
635 if (!pmsg->len) {
636 ret = -EOPNOTSUPP;
637 break;
638 }
639
640 ret = octeon_i2c_start(i2c);
641 if (ret)
642 return ret;
643
644 if (pmsg->flags & I2C_M_RD)
645 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
646 &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
647 else
648 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
649 pmsg->len);
650 }
651 octeon_i2c_stop(i2c);
652 out:
653 return (ret != 0) ? ret : num;
654 }
655
656 /* calculate and set clock divisors */
657 void octeon_i2c_set_clock(struct octeon_i2c *i2c)
658 {
659 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
660 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
661
662 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
663 /*
664 * An mdiv value of less than 2 seems to not work well
665 * with ds1337 RTCs, so we constrain it to larger values.
666 */
667 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
668 /*
669 * For given ndiv and mdiv values check the
670 * two closest thp values.
671 */
672 tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
673 tclk *= (1 << ndiv_idx);
674 thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
675
676 for (inc = 0; inc <= 1; inc++) {
677 thp_idx = thp_base + inc;
678 if (thp_idx < 5 || thp_idx > 0xff)
679 continue;
680
681 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
682 foscl = foscl / (1 << ndiv_idx);
683 foscl = foscl / (mdiv_idx + 1) / 10;
684 diff = abs(foscl - i2c->twsi_freq);
685 if (diff < delta_hz) {
686 delta_hz = diff;
687 thp = thp_idx;
688 mdiv = mdiv_idx;
689 ndiv = ndiv_idx;
690 }
691 }
692 }
693 }
694 octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
695 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
696 }
697
698 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
699 {
700 u8 status = 0;
701 int tries;
702
703 /* reset controller */
704 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
705
706 for (tries = 10; tries && status != STAT_IDLE; tries--) {
707 udelay(1);
708 status = octeon_i2c_stat_read(i2c);
709 if (status == STAT_IDLE)
710 break;
711 }
712
713 if (status != STAT_IDLE) {
714 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
715 __func__, status);
716 return -EIO;
717 }
718
719 /* toggle twice to force both teardowns */
720 octeon_i2c_hlc_enable(i2c);
721 octeon_i2c_hlc_disable(i2c);
722 return 0;
723 }
724
725 static int octeon_i2c_get_scl(struct i2c_adapter *adap)
726 {
727 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
728 u64 state;
729
730 state = octeon_i2c_read_int(i2c);
731 return state & TWSI_INT_SCL;
732 }
733
734 static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val)
735 {
736 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
737
738 octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR);
739 }
740
741 static int octeon_i2c_get_sda(struct i2c_adapter *adap)
742 {
743 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
744 u64 state;
745
746 state = octeon_i2c_read_int(i2c);
747 return state & TWSI_INT_SDA;
748 }
749
750 static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)
751 {
752 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
753
754 octeon_i2c_hlc_disable(i2c);
755 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
756 /* wait for software reset to settle */
757 udelay(5);
758
759 /*
760 * Bring control register to a good state regardless
761 * of HLC state.
762 */
763 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
764
765 octeon_i2c_write_int(i2c, 0);
766 }
767
768 static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap)
769 {
770 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
771
772 /*
773 * Generate STOP to finish the unfinished transaction.
774 * Can't generate STOP via the TWSI CTL register
775 * since it could bring the TWSI controller into an inoperable state.
776 */
777 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);
778 udelay(5);
779 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
780 udelay(5);
781 octeon_i2c_write_int(i2c, 0);
782 }
783
784 struct i2c_bus_recovery_info octeon_i2c_recovery_info = {
785 .recover_bus = i2c_generic_scl_recovery,
786 .get_scl = octeon_i2c_get_scl,
787 .set_scl = octeon_i2c_set_scl,
788 .get_sda = octeon_i2c_get_sda,
789 .prepare_recovery = octeon_i2c_prepare_recovery,
790 .unprepare_recovery = octeon_i2c_unprepare_recovery,
791 };
Linux with added FPC-III support