| blob | ff59897a946363442d657e84784962c6a600a45b |
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ip.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
53 #ifdef CONFIG_IGB_DCA
54 #include <linux/dca.h>
55 #endif
56 #include <linux/i2c.h>
59 #define MAJ 5
60 #define MIN 2
61 #define BUILD 15
73 };
111 /* required last entry */
113 };
148 #ifdef CONFIG_IGB_DCA
159 netdev_features_t features);
179 #ifdef CONFIG_PCI_IOV
182 #endif
184 #ifdef CONFIG_PM
185 #ifdef CONFIG_PM_SLEEP
187 #endif
195 igb_runtime_idle)
196 };
197 #endif
200 #ifdef CONFIG_IGB_DCA
206 };
207 #endif
208 #ifdef CONFIG_NET_POLL_CONTROLLER
209 /* for netdump / net console */
211 #endif
212 #ifdef CONFIG_PCI_IOV
215 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
219 pci_channel_state_t);
227 };
236 #ifdef CONFIG_PM
238 #endif
242 };
249 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
255 u32 ofs;
257 };
261 /* General Registers */
266 /* Interrupt Registers */
269 /* RX Registers */
278 /* TX Registers */
291 /* List Terminator */
292 {}
293 };
295 /* igb_regdump - register printout routine */
297 {
354 }
359 }
361 /* igb_dump - Print registers, Tx-rings and Rx-rings */
363 {
372 u32 staterr;
378 /* Print netdevice Info */
384 }
386 /* Print Registers */
392 }
394 /* Print TX Ring Summary */
410 }
412 /* Print TX Rings */
418 /* Transmit Descriptor Formats
419 *
420 * Advanced Transmit Descriptor
421 * +--------------------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +--------------------------------------------------------------+
424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
425 * +--------------------------------------------------------------+
426 * 63 46 45 40 39 38 36 35 32 31 24 15 0
427 */
449 else
463 DUMP_PREFIX_ADDRESS,
467 }
468 }
470 /* Print RX Rings Summary */
471 rx_ring_summary:
478 }
480 /* Print RX Rings */
486 /* Advanced Receive Descriptor (Read) Format
487 * 63 1 0
488 * +-----------------------------------------------------+
489 * 0 | Packet Buffer Address [63:1] |A0/NSE|
490 * +----------------------------------------------+------+
491 * 8 | Header Buffer Address [63:1] | DD |
492 * +-----------------------------------------------------+
493 *
494 *
495 * Advanced Receive Descriptor (Write-Back) Format
496 *
497 * 63 48 47 32 31 30 21 20 17 16 4 3 0
498 * +------------------------------------------------------+
499 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
500 * | Checksum Ident | | | | Type | Type |
501 * +------------------------------------------------------+
502 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
503 * +------------------------------------------------------+
504 * 63 48 47 32 31 20 19 0
505 */
513 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
527 else
531 /* Descriptor Done */
536 next_desc);
543 next_desc);
548 DUMP_PREFIX_ADDRESS,
553 }
554 }
555 }
556 }
558 exit:
560 }
562 /**
563 * igb_get_i2c_data - Reads the I2C SDA data bit
564 * @hw: pointer to hardware structure
565 * @i2cctl: Current value of I2CCTL register
566 *
567 * Returns the I2C data bit value
568 **/
570 {
576 }
578 /**
579 * igb_set_i2c_data - Sets the I2C data bit
580 * @data: pointer to hardware structure
581 * @state: I2C data value (0 or 1) to set
582 *
583 * Sets the I2C data bit
584 **/
586 {
593 else
601 }
603 /**
604 * igb_set_i2c_clk - Sets the I2C SCL clock
605 * @data: pointer to hardware structure
606 * @state: state to set clock
607 *
608 * Sets the I2C clock line to state
609 **/
611 {
622 }
625 }
627 /**
628 * igb_get_i2c_clk - Gets the I2C SCL clock state
629 * @data: pointer to hardware structure
630 *
631 * Gets the I2C clock state
632 **/
634 {
640 }
649 };
651 /**
652 * igb_get_hw_dev - return device
653 * @hw: pointer to hardware structure
654 *
655 * used by hardware layer to print debugging information
656 **/
658 {
661 }
663 /**
664 * igb_init_module - Driver Registration Routine
665 *
666 * igb_init_module is the first routine called when the driver is
667 * loaded. All it does is register with the PCI subsystem.
668 **/
670 {
677 #ifdef CONFIG_IGB_DCA
679 #endif
682 }
686 /**
687 * igb_exit_module - Driver Exit Cleanup Routine
688 *
689 * igb_exit_module is called just before the driver is removed
690 * from memory.
691 **/
693 {
694 #ifdef CONFIG_IGB_DCA
696 #endif
698 }
702 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
703 /**
704 * igb_cache_ring_register - Descriptor ring to register mapping
705 * @adapter: board private structure to initialize
706 *
707 * Once we know the feature-set enabled for the device, we'll cache
708 * the register offset the descriptor ring is assigned to.
709 **/
711 {
717 /* The queues are allocated for virtualization such that VF 0
718 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
719 * In order to avoid collision we start at the first free queue
720 * and continue consuming queues in the same sequence
721 */
726 }
727 /* Fall through */
734 /* Fall through */
741 }
742 }
745 {
755 /* reads should not return all F's */
761 }
764 }
766 /**
767 * igb_write_ivar - configure ivar for given MSI-X vector
768 * @hw: pointer to the HW structure
769 * @msix_vector: vector number we are allocating to a given ring
770 * @index: row index of IVAR register to write within IVAR table
771 * @offset: column offset of in IVAR, should be multiple of 8
772 *
773 * This function is intended to handle the writing of the IVAR register
774 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
775 * each containing an cause allocation for an Rx and Tx ring, and a
776 * variable number of rows depending on the number of queues supported.
777 **/
780 {
783 /* clear any bits that are currently set */
786 /* write vector and valid bit */
790 }
792 #define IGB_N0_QUEUE -1
794 {
808 /* The 82575 assigns vectors using a bitmask, which matches the
809 * bitmask for the EICR/EIMS/EIMC registers. To assign one
810 * or more queues to a vector, we write the appropriate bits
811 * into the MSIXBM register for that vector.
812 */
823 /* 82576 uses a table that essentially consists of 2 columns
824 * with 8 rows. The ordering is column-major so we use the
825 * lower 3 bits as the row index, and the 4th bit as the
826 * column offset.
827 */
843 /* On 82580 and newer adapters the scheme is similar to 82576
844 * however instead of ordering column-major we have things
845 * ordered row-major. So we traverse the table by using
846 * bit 0 as the column offset, and the remaining bits as the
847 * row index.
848 */
862 }
864 /* add q_vector eims value to global eims_enable_mask */
867 /* configure q_vector to set itr on first interrupt */
869 }
871 /**
872 * igb_configure_msix - Configure MSI-X hardware
873 * @adapter: board private structure to initialize
874 *
875 * igb_configure_msix sets up the hardware to properly
876 * generate MSI-X interrupts.
877 **/
879 {
880 u32 tmp;
886 /* set vector for other causes, i.e. link changes */
890 /* enable MSI-X PBA support*/
893 /* Auto-Mask interrupts upon ICR read. */
899 /* enable msix_other interrupt */
911 /* Turn on MSI-X capability first, or our settings
912 * won't stick. And it will take days to debug.
913 */
916 E1000_GPIE_NSICR);
918 /* enable msix_other interrupt */
925 /* do nothing, since nothing else supports MSI-X */
935 }
937 /**
938 * igb_request_msix - Initialize MSI-X interrupts
939 * @adapter: board private structure to initialize
940 *
941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
942 * kernel.
943 **/
945 {
958 vector++;
971 else
976 q_vector);
979 }
984 err_free:
985 /* free already assigned IRQs */
988 vector--;
992 }
993 err_out:
995 }
997 /**
998 * igb_free_q_vector - Free memory allocated for specific interrupt vector
999 * @adapter: board private structure to initialize
1000 * @v_idx: Index of vector to be freed
1001 *
1002 * This function frees the memory allocated to the q_vector.
1003 **/
1005 {
1010 /* igb_get_stats64() might access the rings on this vector,
1011 * we must wait a grace period before freeing it.
1012 */
1015 }
1017 /**
1018 * igb_reset_q_vector - Reset config for interrupt vector
1019 * @adapter: board private structure to initialize
1020 * @v_idx: Index of vector to be reset
1021 *
1022 * If NAPI is enabled it will delete any references to the
1023 * NAPI struct. This is preparation for igb_free_q_vector.
1024 **/
1026 {
1029 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1030 * allocated. So, q_vector is NULL so we should stop here.
1031 */
1043 }
1046 {
1056 }
1058 /**
1059 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1060 * @adapter: board private structure to initialize
1061 *
1062 * This function frees the memory allocated to the q_vectors. In addition if
1063 * NAPI is enabled it will delete any references to the NAPI struct prior
1064 * to freeing the q_vector.
1065 **/
1067 {
1077 }
1078 }
1080 /**
1081 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1082 * @adapter: board private structure to initialize
1083 *
1084 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1085 * MSI-X interrupts allocated.
1086 */
1088 {
1091 }
1093 /**
1094 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1095 * @adapter: board private structure to initialize
1096 * @msix: boolean value of MSIX capability
1097 *
1098 * Attempt to configure interrupts using the best available
1099 * capabilities of the hardware and kernel.
1100 **/
1102 {
1110 /* Number of supported queues. */
1114 else
1117 /* start with one vector for every Rx queue */
1120 /* if Tx handler is separate add 1 for every Tx queue */
1124 /* store the number of vectors reserved for queues */
1127 /* add 1 vector for link status interrupts */
1128 numvecs++;
1134 numvecs,
1135 numvecs);
1141 /* If we can't do MSI-X, try MSI */
1142 msi_only:
1144 #ifdef CONFIG_PCI_IOV
1145 /* disable SR-IOV for non MSI-X configurations */
1148 /* disable iov and allow time for transactions to clear */
1158 }
1159 #endif
1168 }
1172 {
1175 }
1177 /**
1178 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1179 * @adapter: board private structure to initialize
1180 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1181 * @v_idx: index of vector in adapter struct
1182 * @txr_count: total number of Tx rings to allocate
1183 * @txr_idx: index of first Tx ring to allocate
1184 * @rxr_count: total number of Rx rings to allocate
1185 * @rxr_idx: index of first Rx ring to allocate
1186 *
1187 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1188 **/
1193 {
1198 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1206 /* allocate q_vector and rings */
1213 /* initialize NAPI */
1217 /* tie q_vector and adapter together */
1221 /* initialize work limits */
1224 /* initialize ITR configuration */
1228 /* initialize pointer to rings */
1231 /* intialize ITR */
1233 /* rx or rx/tx vector */
1237 /* tx only vector */
1240 }
1243 /* assign generic ring traits */
1247 /* configure backlink on ring */
1250 /* update q_vector Tx values */
1253 /* For 82575, context index must be unique per ring. */
1257 /* apply Tx specific ring traits */
1264 /* assign ring to adapter */
1267 /* push pointer to next ring */
1268 ring++;
1269 }
1272 /* assign generic ring traits */
1276 /* configure backlink on ring */
1279 /* update q_vector Rx values */
1282 /* set flag indicating ring supports SCTP checksum offload */
1286 /* On i350, i354, i210, and i211, loopback VLAN packets
1287 * have the tag byte-swapped.
1288 */
1292 /* apply Rx specific ring traits */
1298 /* assign ring to adapter */
1300 }
1303 }
1306 /**
1307 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1308 * @adapter: board private structure to initialize
1309 *
1310 * We allocate one q_vector per queue interrupt. If allocation fails we
1311 * return -ENOMEM.
1312 **/
1314 {
1329 /* update counts and index */
1330 rxr_remaining--;
1331 rxr_idx++;
1332 }
1333 }
1345 /* update counts and index */
1348 rxr_idx++;
1349 txr_idx++;
1350 }
1354 err_out:
1363 }
1365 /**
1366 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1367 * @adapter: board private structure to initialize
1368 * @msix: boolean value of MSIX capability
1369 *
1370 * This function initializes the interrupts and allocates all of the queues.
1371 **/
1373 {
1383 }
1389 err_alloc_q_vectors:
1392 }
1394 /**
1395 * igb_request_irq - initialize interrupts
1396 * @adapter: board private structure to initialize
1397 *
1398 * Attempts to configure interrupts using the best available
1399 * capabilities of the hardware and kernel.
1400 **/
1402 {
1411 /* fall back to MSI */
1423 }
1433 /* fall back to legacy interrupts */
1436 }
1443 err);
1445 request_done:
1447 }
1450 {
1461 }
1462 }
1464 /**
1465 * igb_irq_disable - Mask off interrupt generation on the NIC
1466 * @adapter: board private structure
1467 **/
1469 {
1472 /* we need to be careful when disabling interrupts. The VFs are also
1473 * mapped into these registers and so clearing the bits can cause
1474 * issues on the VF drivers so we only need to clear what we set
1475 */
1483 }
1495 }
1496 }
1498 /**
1499 * igb_irq_enable - Enable default interrupt generation settings
1500 * @adapter: board private structure
1501 **/
1503 {
1517 }
1521 E1000_IMS_DRSTA);
1523 E1000_IMS_DRSTA);
1524 }
1525 }
1528 {
1534 /* add VID to filter table */
1539 }
1544 /* remove VID from filter table */
1546 }
1547 }
1549 /**
1550 * igb_release_hw_control - release control of the h/w to f/w
1551 * @adapter: address of board private structure
1552 *
1553 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1554 * For ASF and Pass Through versions of f/w this means that the
1555 * driver is no longer loaded.
1556 **/
1558 {
1560 u32 ctrl_ext;
1562 /* Let firmware take over control of h/w */
1566 }
1568 /**
1569 * igb_get_hw_control - get control of the h/w from f/w
1570 * @adapter: address of board private structure
1571 *
1572 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1573 * For ASF and Pass Through versions of f/w this means that
1574 * the driver is loaded.
1575 **/
1577 {
1579 u32 ctrl_ext;
1581 /* Let firmware know the driver has taken over */
1585 }
1587 /**
1588 * igb_configure - configure the hardware for RX and TX
1589 * @adapter: private board structure
1590 **/
1592 {
1610 /* call igb_desc_unused which always leaves
1611 * at least 1 descriptor unused to make sure
1612 * next_to_use != next_to_clean
1613 */
1617 }
1618 }
1620 /**
1621 * igb_power_up_link - Power up the phy/serdes link
1622 * @adapter: address of board private structure
1623 **/
1625 {
1630 else
1634 }
1636 /**
1637 * igb_power_down_link - Power down the phy/serdes link
1638 * @adapter: address of board private structure
1639 */
1641 {
1644 else
1646 }
1648 /**
1649 * Detect and switch function for Media Auto Sense
1650 * @adapter: address of the board private structure
1651 **/
1653 {
1661 /* need to live swap if current media is copper and we have fiber/serdes
1662 * to go to.
1663 */
1669 /* copper signal takes time to appear */
1682 }
1683 }
1684 }
1693 ctrl_ext |=
1694 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1702 ctrl_ext &=
1707 /* shouldn't get here during regular operation */
1711 }
1713 }
1715 /**
1716 * igb_up - Open the interface and prepare it to handle traffic
1717 * @adapter: board private structure
1718 **/
1720 {
1724 /* hardware has been reset, we need to reload some things */
1734 else
1737 /* Clear any pending interrupts. */
1741 /* notify VFs that reset has been completed */
1747 }
1751 /* start the watchdog. */
1760 }
1763 {
1769 /* signal that we're down so the interrupt handler does not
1770 * reschedule our watchdog timer
1771 */
1774 /* disable receives in the hardware */
1777 /* flush and sleep below */
1781 /* disable transmits in the hardware */
1785 /* flush both disables and wait for them to finish */
1797 }
1798 }
1806 /* record the stats before reset*/
1818 #ifdef CONFIG_IGB_DCA
1820 /* since we reset the hardware DCA settings were cleared */
1822 #endif
1823 }
1826 {
1833 }
1835 /** igb_enable_mas - Media Autosense re-enable after swap
1836 *
1837 * @adapter: adapter struct
1838 **/
1840 {
1842 u32 connsw;
1849 /* configure for SerDes media detect */
1856 /* already SerDes, no need to enable anything */
1862 }
1864 }
1867 {
1874 /* Repartition Pba for greater than 9k mtu
1875 * To take effect CTRL.RST is required.
1876 */
1894 }
1898 /* adjust PBA for jumbo frames */
1901 /* To maintain wire speed transmits, the Tx FIFO should be
1902 * large enough to accommodate two full transmit packets,
1903 * rounded up to the next 1KB and expressed in KB. Likewise,
1904 * the Rx FIFO should be large enough to accommodate at least
1905 * one full receive packet and is similarly rounded up and
1906 * expressed in KB.
1907 */
1909 /* upper 16 bits has Tx packet buffer allocation size in KB */
1911 /* lower 16 bits has Rx packet buffer allocation size in KB */
1913 /* the Tx fifo also stores 16 bytes of information about the Tx
1914 * but don't include ethernet FCS because hardware appends it
1915 */
1921 /* software strips receive CRC, so leave room for it */
1926 /* If current Tx allocation is less than the min Tx FIFO size,
1927 * and the min Tx FIFO size is less than the current Rx FIFO
1928 * allocation, take space away from current Rx allocation
1929 */
1934 /* if short on Rx space, Rx wins and must trump Tx
1935 * adjustment
1936 */
1939 }
1941 }
1943 /* flow control settings */
1944 /* The high water mark must be low enough to fit one full frame
1945 * (or the size used for early receive) above it in the Rx FIFO.
1946 * Set it to the lower of:
1947 * - 90% of the Rx FIFO size, or
1948 * - the full Rx FIFO size minus one full frame
1949 */
1959 /* disable receive for all VFs and wait one second */
1966 /* ping all the active vfs to let them know we are going down */
1969 /* disable transmits and receives */
1972 }
1974 /* Allow time for pending master requests to run */
1979 /* need to resetup here after media swap */
1982 }
1987 }
1991 /* Flow control settings reset on hardware reset, so guarantee flow
1992 * control is off when forcing speed.
1993 */
1998 #ifdef CONFIG_IGB_HWMON
1999 /* Re-initialize the thermal sensor on i350 devices. */
2002 /* If present, re-initialize the external thermal sensor
2003 * interface.
2004 */
2007 }
2008 }
2009 #endif
2010 /* Re-establish EEE setting */
2023 }
2024 }
2030 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2033 /* Re-enable PTP, where applicable. */
2037 }
2040 netdev_features_t features)
2041 {
2042 /* Since there is no support for separate Rx/Tx vlan accel
2043 * enable/disable make sure Tx flag is always in same state as Rx.
2044 */
2047 else
2051 }
2054 netdev_features_t features)
2055 {
2069 else
2073 }
2093 #ifdef CONFIG_NET_POLL_CONTROLLER
2095 #endif
2098 };
2100 /**
2101 * igb_set_fw_version - Configure version string for ethtool
2102 * @adapter: adapter struct
2103 **/
2105 {
2121 }
2122 /* fall through */
2124 /* if option is rom valid, display its version too */
2131 /* no option rom */
2142 }
2144 }
2145 }
2147 /**
2148 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2149 *
2150 * @adapter: adapter struct
2151 **/
2153 {
2155 u16 eeprom_data;
2165 }
2173 }
2181 }
2189 }
2192 /* Shouldn't get here */
2196 }
2197 }
2199 /**
2200 * igb_init_i2c - Init I2C interface
2201 * @adapter: pointer to adapter structure
2202 **/
2204 {
2207 /* I2C interface supported on i350 devices */
2211 /* Initialize the i2c bus which is controlled by the registers.
2212 * This bus will use the i2c_algo_bit structue that implements
2213 * the protocol through toggling of the 4 bits in the register.
2214 */
2224 }
2226 /**
2227 * igb_probe - Device Initialization Routine
2228 * @pdev: PCI device information struct
2229 * @ent: entry in igb_pci_tbl
2230 *
2231 * Returns 0 on success, negative on failure
2232 *
2233 * igb_probe initializes an adapter identified by a pci_dev structure.
2234 * The OS initialization, configuring of the adapter private structure,
2235 * and a hardware reset occur.
2236 **/
2238 {
2243 s32 ret_val;
2249 /* Catch broken hardware that put the wrong VF device ID in
2250 * the PCIe SR-IOV capability.
2251 */
2256 }
2272 }
2273 }
2276 IORESOURCE_MEM),
2277 igb_driver_name);
2288 IGB_MAX_TX_QUEUES);
2316 /* PCI config space info */
2323 /* Copy the default MAC, PHY and NVM function pointers */
2327 /* Initialize skew-specific constants */
2332 /* setup the private structure */
2341 /* Copper options */
2346 }
2352 /* features is initialized to 0 in allocation, it might have bits
2353 * set by igb_sw_init so we should use an or instead of an
2354 * assignment.
2355 */
2357 NETIF_F_IP_CSUM |
2358 NETIF_F_IPV6_CSUM |
2359 NETIF_F_TSO |
2360 NETIF_F_TSO6 |
2361 NETIF_F_RXHASH |
2362 NETIF_F_RXCSUM |
2363 NETIF_F_HW_VLAN_CTAG_RX |
2364 NETIF_F_HW_VLAN_CTAG_TX;
2366 /* copy netdev features into list of user selectable features */
2370 /* set this bit last since it cannot be part of hw_features */
2374 NETIF_F_TSO6 |
2375 NETIF_F_IP_CSUM |
2376 NETIF_F_IPV6_CSUM |
2377 NETIF_F_SG;
2384 }
2389 }
2395 /* before reading the NVM, reset the controller to put the device in a
2396 * known good starting state
2397 */
2400 /* make sure the NVM is good , i211/i210 parts can have special NVM
2401 * that doesn't contain a checksum
2402 */
2412 }
2413 }
2420 }
2422 }
2424 /* copy the MAC address out of the NVM */
2434 }
2436 /* get firmware version for ethtool -i */
2439 /* configure RXPBSIZE and TXPBSIZE */
2443 }
2453 /* Initialize link properties that are user-changeable */
2463 /* By default, support wake on port A */
2467 /* Check the NVM for wake support on non-port A ports */
2478 /* now that we have the eeprom settings, apply the special cases where
2479 * the eeprom may be wrong or the board simply won't support wake on
2480 * lan on a particular port
2481 */
2489 /* Wake events only supported on port A for dual fiber
2490 * regardless of eeprom setting
2491 */
2497 /* if quad port adapter, disable WoL on all but port A */
2500 else
2502 /* Reset for multiple quad port adapters */
2507 /* If the device can't wake, don't set software support */
2510 }
2512 /* initialize the wol settings based on the eeprom settings */
2516 /* Some vendors want WoL disabled by default, but still supported */
2521 }
2526 /* reset the hardware with the new settings */
2529 /* Init the I2C interface */
2534 }
2536 /* let the f/w know that the h/w is now under the control of the
2537 * driver.
2538 */
2546 /* carrier off reporting is important to ethtool even BEFORE open */
2549 #ifdef CONFIG_IGB_DCA
2554 }
2556 #endif
2557 #ifdef CONFIG_IGB_HWMON
2558 /* Initialize the thermal sensor on i350 devices. */
2560 u16 ets_word;
2562 /* Read the NVM to determine if this i350 device supports an
2563 * external thermal sensor.
2564 */
2568 else
2575 }
2576 #endif
2577 /* Check if Media Autosense is enabled */
2582 /* do hw tstamp init after resetting */
2586 /* print bus type/speed/width info, not applicable to i354 */
2599 }
2604 E1000_PBANUM_LENGTH);
2607 }
2622 /* Enable EEE for internal copper PHY devices */
2629 }
2633 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2640 }
2641 }
2645 }
2646 }
2650 err_register:
2653 err_eeprom:
2659 err_sw_init:
2662 err_ioremap:
2664 err_alloc_etherdev:
2667 err_pci_reg:
2668 err_dma:
2671 }
2673 #ifdef CONFIG_PCI_IOV
2675 {
2680 /* reclaim resources allocated to VFs */
2682 /* disable iov and allow time for transactions to clear */
2685 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2690 }
2700 /* Re-enable DMA Coalescing flag since IOV is turned off */
2702 }
2705 }
2708 {
2718 }
2732 /* if allocation failed then we do not support SR-IOV */
2739 }
2741 /* only call pci_enable_sriov() if no VFs are allocated already */
2746 }
2752 /* DMA Coalescing is not supported in IOV mode. */
2756 err_out:
2760 out:
2762 }
2764 #endif
2765 /**
2766 * igb_remove_i2c - Cleanup I2C interface
2767 * @adapter: pointer to adapter structure
2768 **/
2770 {
2771 /* free the adapter bus structure */
2773 }
2775 /**
2776 * igb_remove - Device Removal Routine
2777 * @pdev: PCI device information struct
2778 *
2779 * igb_remove is called by the PCI subsystem to alert the driver
2780 * that it should release a PCI device. The could be caused by a
2781 * Hot-Plug event, or because the driver is going to be removed from
2782 * memory.
2783 **/
2785 {
2791 #ifdef CONFIG_IGB_HWMON
2793 #endif
2796 /* The watchdog timer may be rescheduled, so explicitly
2797 * disable watchdog from being rescheduled.
2798 */
2806 #ifdef CONFIG_IGB_DCA
2812 }
2813 #endif
2815 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2816 * would have already happened in close and is redundant.
2817 */
2824 #ifdef CONFIG_PCI_IOV
2826 #endif
2840 }
2842 /**
2843 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2844 * @adapter: board private structure to initialize
2845 *
2846 * This function initializes the vf specific data storage and then attempts to
2847 * allocate the VFs. The reason for ordering it this way is because it is much
2848 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2849 * the memory for the VFs.
2850 **/
2852 {
2853 #ifdef CONFIG_PCI_IOV
2857 /* Virtualization features not supported on i210 family. */
2865 }
2868 {
2870 u32 max_rss_queues;
2872 /* Determine the maximum number of RSS queues supported. */
2882 /* I350 cannot do RSS and SR-IOV at the same time */
2886 }
2887 /* fall through */
2892 }
2893 /* fall through */
2899 }
2903 /* Determine if we need to pair queues. */
2907 /* Device supports enough interrupts without queue pairing. */
2910 /* If VFs are going to be allocated with RSS queues then we
2911 * should pair the queues in order to conserve interrupts due
2912 * to limited supply.
2913 */
2917 /* fall through */
2923 /* If rss_queues > half of max_rss_queues, pair the queues in
2924 * order to conserve interrupts due to limited supply.
2925 */
2929 }
2930 }
2932 /**
2933 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2934 * @adapter: board private structure to initialize
2935 *
2936 * igb_sw_init initializes the Adapter private data structure.
2937 * Fields are initialized based on PCI device information and
2938 * OS network device settings (MTU size).
2939 **/
2941 {
2948 /* set default ring sizes */
2952 /* set default ITR values */
2956 /* set default work limits */
2960 VLAN_HLEN;
2964 #ifdef CONFIG_PCI_IOV
2976 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2980 }
2985 /* Setup and initialize a copy of the hw vlan table array */
2987 GFP_ATOMIC);
2989 /* This call may decrease the number of queues */
2993 }
2997 /* Explicitly disable IRQ since the NIC can be in any state. */
3005 }
3007 /**
3008 * igb_open - Called when a network interface is made active
3009 * @netdev: network interface device structure
3010 *
3011 * Returns 0 on success, negative value on failure
3012 *
3013 * The open entry point is called when a network interface is made
3014 * active by the system (IFF_UP). At this point all resources needed
3015 * for transmit and receive operations are allocated, the interrupt
3016 * handler is registered with the OS, the watchdog timer is started,
3017 * and the stack is notified that the interface is ready.
3018 **/
3020 {
3027 /* disallow open during test */
3031 }
3038 /* allocate transmit descriptors */
3043 /* allocate receive descriptors */
3050 /* before we allocate an interrupt, we must be ready to handle it.
3051 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3052 * as soon as we call pci_request_irq, so we have to setup our
3053 * clean_rx handler before we do so.
3054 */
3061 /* Notify the stack of the actual queue counts. */
3072 /* From here on the code is the same as igb_up() */
3078 /* Clear any pending interrupts. */
3083 /* notify VFs that reset has been completed */
3089 }
3096 /* start the watchdog. */
3102 err_set_queues:
3104 err_req_irq:
3108 err_setup_rx:
3110 err_setup_tx:
3116 }
3119 {
3121 }
3123 /**
3124 * igb_close - Disables a network interface
3125 * @netdev: network interface device structure
3126 *
3127 * Returns 0, this is not allowed to fail
3128 *
3129 * The close entry point is called when an interface is de-activated
3130 * by the OS. The hardware is still under the driver's control, but
3131 * needs to be disabled. A global MAC reset is issued to stop the
3132 * hardware, and all transmit and receive resources are freed.
3133 **/
3135 {
3153 }
3156 {
3158 }
3160 /**
3161 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3162 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3163 *
3164 * Return 0 on success, negative on failure
3165 **/
3167 {
3177 /* round up to nearest 4K */
3191 err:
3196 }
3198 /**
3199 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3200 * (Descriptors) for all queues
3201 * @adapter: board private structure
3202 *
3203 * Return 0 on success, negative on failure
3204 **/
3206 {
3218 }
3219 }
3222 }
3224 /**
3225 * igb_setup_tctl - configure the transmit control registers
3226 * @adapter: Board private structure
3227 **/
3229 {
3231 u32 tctl;
3233 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3236 /* Program the Transmit Control Register */
3244 /* Enable transmits */
3248 }
3250 /**
3251 * igb_configure_tx_ring - Configure transmit ring after Reset
3252 * @adapter: board private structure
3253 * @ring: tx ring to configure
3254 *
3255 * Configure a transmit ring after a reset.
3256 **/
3259 {
3265 /* disable the queue */
3286 }
3288 /**
3289 * igb_configure_tx - Configure transmit Unit after Reset
3290 * @adapter: board private structure
3291 *
3292 * Configure the Tx unit of the MAC after a reset.
3293 **/
3295 {
3300 }
3302 /**
3303 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3304 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3305 *
3306 * Returns 0 on success, negative on failure
3307 **/
3309 {
3319 /* Round up to nearest 4K */
3334 err:
3339 }
3341 /**
3342 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3343 * (Descriptors) for all queues
3344 * @adapter: board private structure
3345 *
3346 * Return 0 on success, negative on failure
3347 **/
3349 {
3361 }
3362 }
3365 }
3367 /**
3368 * igb_setup_mrqc - configure the multiple receive queue control registers
3369 * @adapter: Board private structure
3370 **/
3372 {
3386 /* 82576 supports 2 RSS queues for SR-IOV */
3392 }
3399 }
3402 /* Disable raw packet checksumming so that RSS hash is placed in
3403 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3404 * offloads as they are enabled by default
3405 */
3410 /* Enable Receive Checksum Offload for SCTP */
3413 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3416 /* Generate RSS hash based on packet types, TCP/UDP
3417 * port numbers and/or IPv4/v6 src and dst addresses
3418 */
3420 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3421 E1000_MRQC_RSS_FIELD_IPV6 |
3422 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3423 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3430 /* If VMDq is enabled then we set the appropriate mode for that, else
3431 * we default to RSS so that an RSS hash is calculated per packet even
3432 * if we are only using one queue
3433 */
3436 /* Set the default pool for the PF's first queue */
3440 E1000_VT_CTL_DISABLE_DEF_POOL);
3442 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3444 }
3447 else
3452 }
3456 }
3458 /**
3459 * igb_setup_rctl - configure the receive control registers
3460 * @adapter: Board private structure
3461 **/
3463 {
3465 u32 rctl;
3475 /* enable stripping of CRC. It's unlikely this will break BMC
3476 * redirection as it did with e1000. Newer features require
3477 * that the HW strips the CRC.
3478 */
3481 /* disable store bad packets and clear size bits. */
3484 /* enable LPE to prevent packets larger than max_frame_size */
3487 /* disable queue 0 to prevent tail write w/o re-config */
3490 /* Attention!!! For SR-IOV PF driver operations you must enable
3491 * queue drop for all VF and PF queues to prevent head of line blocking
3492 * if an un-trusted VF does not provide descriptors to hardware.
3493 */
3495 /* set all queue drop enable bits */
3497 }
3499 /* This is useful for sniffing bad packets. */
3501 /* UPE and MPE will be handled by normal PROMISC logic
3502 * in e1000e_set_rx_mode
3503 */
3511 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3512 * and that breaks VLANs.
3513 */
3514 }
3517 }
3521 {
3523 u32 vmolr;
3525 /* if it isn't the PF check to see if VFs are enabled and
3526 * increase the size to support vlan tags
3527 */
3538 }
3540 /**
3541 * igb_rlpml_set - set maximum receive packet size
3542 * @adapter: board private structure
3543 *
3544 * Configure maximum receivable packet size.
3545 **/
3547 {
3554 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3555 * to our max jumbo frame size, in case we need to enable
3556 * jumbo frames on one of the rings later.
3557 * This will not pass over-length frames into the default
3558 * queue because it's gated by the VMOLR.RLPML.
3559 */
3561 }
3564 }
3568 {
3570 u32 vmolr;
3572 /* This register exists only on 82576 and newer so if we are older then
3573 * we should exit and do nothing
3574 */
3581 u32 dvmolr;
3586 }
3589 else
3592 /* clear all bits that might not be set */
3597 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3598 * multicast packets
3599 */
3604 }
3606 /**
3607 * igb_configure_rx_ring - Configure a receive ring after Reset
3608 * @adapter: board private structure
3609 * @ring: receive ring to be configured
3610 *
3611 * Configure the Rx unit of the MAC after a reset.
3612 **/
3615 {
3621 /* disable the queue */
3624 /* Set DMA base address registers */
3631 /* initialize head and tail */
3636 /* set descriptor configuration */
3642 /* Only set Drop Enable if we are supporting multiple queues */
3648 /* set filtering for VMDQ pools */
3655 /* enable receive descriptor fetching */
3658 }
3660 /**
3661 * igb_configure_rx - Configure receive Unit after Reset
3662 * @adapter: board private structure
3663 *
3664 * Configure the Rx unit of the MAC after a reset.
3665 **/
3667 {
3670 /* set UTA to appropriate mode */
3673 /* set the correct pool for the PF default MAC address in entry 0 */
3677 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3678 * the Base and Length of the Rx Descriptor Ring
3679 */
3682 }
3684 /**
3685 * igb_free_tx_resources - Free Tx Resources per Queue
3686 * @tx_ring: Tx descriptor ring for a specific queue
3687 *
3688 * Free all transmit software resources
3689 **/
3691 {
3697 /* if not set, then don't free */
3705 }
3707 /**
3708 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3709 * @adapter: board private structure
3710 *
3711 * Free all transmit software resources
3712 **/
3714 {
3720 }
3724 {
3731 DMA_TO_DEVICE);
3736 DMA_TO_DEVICE);
3737 }
3741 /* buffer_info must be completely set up in the transmit path */
3742 }
3744 /**
3745 * igb_clean_tx_ring - Free Tx Buffers
3746 * @tx_ring: ring to be cleaned
3747 **/
3749 {
3752 u16 i;
3756 /* Free all the Tx ring sk_buffs */
3761 }
3768 /* Zero out the descriptor ring */
3773 }
3775 /**
3776 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3777 * @adapter: board private structure
3778 **/
3780 {
3786 }
3788 /**
3789 * igb_free_rx_resources - Free Rx Resources
3790 * @rx_ring: ring to clean the resources from
3791 *
3792 * Free all receive software resources
3793 **/
3795 {
3801 /* if not set, then don't free */
3809 }
3811 /**
3812 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3813 * @adapter: board private structure
3814 *
3815 * Free all receive software resources
3816 **/
3818 {
3824 }
3826 /**
3827 * igb_clean_rx_ring - Free Rx Buffers per Queue
3828 * @rx_ring: ring to free buffers from
3829 **/
3831 {
3833 u16 i;
3842 /* Free all the Rx ring sk_buffs */
3851 PAGE_SIZE,
3852 DMA_FROM_DEVICE);
3856 }
3861 /* Zero out the descriptor ring */
3867 }
3869 /**
3870 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3871 * @adapter: board private structure
3872 **/
3874 {
3880 }
3882 /**
3883 * igb_set_mac - Change the Ethernet Address of the NIC
3884 * @netdev: network interface device structure
3885 * @p: pointer to an address structure
3886 *
3887 * Returns 0 on success, negative on failure
3888 **/
3890 {
3901 /* set the correct pool for the new PF MAC address in entry 0 */
3906 }
3908 /**
3909 * igb_write_mc_addr_list - write multicast addresses to MTA
3910 * @netdev: network interface device structure
3911 *
3912 * Writes multicast address list to the MTA hash table.
3913 * Returns: -ENOMEM on failure
3914 * 0 on no addresses written
3915 * X on writing X addresses to MTA
3916 **/
3918 {
3926 /* nothing to program, so clear mc list */
3930 }
3936 /* The shared function expects a packed array of only addresses. */
3945 }
3947 /**
3948 * igb_write_uc_addr_list - write unicast addresses to RAR table
3949 * @netdev: network interface device structure
3950 *
3951 * Writes unicast address list to the RAR table.
3952 * Returns: -ENOMEM on failure/insufficient address space
3953 * 0 on no addresses written
3954 * X on writing X addresses to the RAR table
3955 **/
3957 {
3964 /* return ENOMEM indicating insufficient memory for addresses */
3975 rar_entries--,
3976 vfn);
3977 count++;
3978 }
3979 }
3980 /* write the addresses in reverse order to avoid write combining */
3984 }
3988 }
3990 /**
3991 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3992 * @netdev: network interface device structure
3993 *
3994 * The set_rx_mode entry point is called whenever the unicast or multicast
3995 * address lists or the network interface flags are updated. This routine is
3996 * responsible for configuring the hardware for proper unicast, multicast,
3997 * promiscuous mode, and all-multi behavior.
3998 **/
4000 {
4007 /* Check for Promiscuous and All Multicast modes */
4010 /* clear the effected bits */
4014 /* retain VLAN HW filtering if in VT mode */
4024 /* Write addresses to the MTA, if the attempt fails
4025 * then we should just turn on promiscuous mode so
4026 * that we can at least receive multicast traffic
4027 */
4034 }
4035 }
4036 /* Write addresses to available RAR registers, if there is not
4037 * sufficient space to store all the addresses then enable
4038 * unicast promiscuous mode
4039 */
4044 }
4046 }
4049 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4050 * the VMOLR to enable the appropriate modes. Without this workaround
4051 * we will have issues with VLAN tag stripping not being done for frames
4052 * that are only arriving because we are the default pool
4053 */
4061 }
4064 {
4077 }
4080 }
4082 #define IGB_STAGGERED_QUEUE_OFFSET 8
4085 {
4099 }
4100 }
4101 }
4103 /* Need to wait a few seconds after link up to get diagnostic information from
4104 * the phy
4105 */
4107 {
4110 }
4112 /**
4113 * igb_has_link - check shared code for link and determine up/down
4114 * @adapter: pointer to driver private info
4115 **/
4117 {
4121 /* get_link_status is set on LSC (link status) interrupt or
4122 * rx sequence error interrupt. get_link_status will stay
4123 * false until the e1000_check_for_link establishes link
4124 * for copper adapters ONLY
4125 */
4137 }
4147 }
4148 }
4151 }
4154 {
4158 /* check for thermal sensor event on i350 copper only */
4166 }
4169 }
4171 /**
4172 * igb_check_lvmmc - check for malformed packets received
4173 * and indicated in LVMMC register
4174 * @adapter: pointer to adapter
4175 **/
4177 {
4179 u32 lvmmc;
4186 lvmmc);
4187 }
4188 }
4189 }
4191 /**
4192 * igb_watchdog - Timer Call-back
4193 * @data: pointer to adapter cast into an unsigned long
4194 **/
4196 {
4198 /* Do the rest outside of interrupt context */
4200 }
4203 {
4206 watchdog_task);
4210 u32 link;
4212 u32 connsw;
4219 else
4221 }
4223 /* Force link down if we have fiber to swap to */
4229 }
4230 }
4232 /* Perform a reset if the media type changed. */
4237 }
4238 /* Cancel scheduled suspend requests. */
4242 u32 ctrl;
4249 /* Links status message must follow this format */
4261 /* disable EEE if enabled */
4268 }
4270 /* check if SmartSpeed worked */
4275 /* check for thermal sensor event */
4277 E1000_THSTAT_LINK_THROTTLE))
4280 /* adjust timeout factor according to speed/duplex */
4287 /* maybe add some timeout factor ? */
4289 }
4296 /* link state has changed, schedule phy info update */
4300 }
4306 /* check for thermal sensor event */
4308 E1000_THSTAT_PWR_DOWN)) {
4310 }
4312 /* Links status message must follow this format */
4319 /* link state has changed, schedule phy info update */
4324 /* link is down, time to check for alternate media */
4329 /* return immediately */
4331 }
4332 }
4336 /* also check for alternate media here */
4342 /* return immediately */
4344 }
4345 }
4346 }
4355 /* We've lost link, so the controller stops DMA,
4356 * but we've got queued Tx work that's never going
4357 * to get done, so reset controller to flush Tx.
4358 * (Do the reset outside of interrupt context).
4359 */
4363 /* return immediately since reset is imminent */
4365 }
4366 }
4368 /* Force detection of hung controller every watchdog period */
4370 }
4372 /* Cause software interrupt to ensure Rx ring is cleaned */
4381 }
4386 /* Check LVMMC register on i350/i354 only */
4391 /* Reset the timer */
4396 else
4399 }
4400 }
4407 };
4409 /**
4410 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4411 * @q_vector: pointer to q_vector
4412 *
4413 * Stores a new ITR value based on strictly on packet size. This
4414 * algorithm is less sophisticated than that used in igb_update_itr,
4415 * due to the difficulty of synchronizing statistics across multiple
4416 * receive rings. The divisors and thresholds used by this function
4417 * were determined based on theoretical maximum wire speed and testing
4418 * data, in order to minimize response time while increasing bulk
4419 * throughput.
4420 * This functionality is controlled by ethtool's coalescing settings.
4421 * NOTE: This function is called only when operating in a multiqueue
4422 * receive environment.
4423 **/
4425 {
4431 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4432 * ints/sec - ITR timer value of 120 ticks.
4433 */
4437 }
4448 /* if avg_wire_size isn't set no work was done */
4452 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4455 /* Don't starve jumbo frames */
4458 /* Give a little boost to mid-size frames */
4461 else
4464 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4470 set_itr_val:
4474 }
4475 clear_counts:
4480 }
4482 /**
4483 * igb_update_itr - update the dynamic ITR value based on statistics
4484 * @q_vector: pointer to q_vector
4485 * @ring_container: ring info to update the itr for
4486 *
4487 * Stores a new ITR value based on packets and byte
4488 * counts during the last interrupt. The advantage of per interrupt
4489 * computation is faster updates and more accurate ITR for the current
4490 * traffic pattern. Constants in this function were computed
4491 * based on theoretical maximum wire speed and thresholds were set based
4492 * on testing data as well as attempting to minimize response time
4493 * while increasing bulk throughput.
4494 * This functionality is controlled by ethtool's coalescing settings.
4495 * NOTE: These calculations are only valid when operating in a single-
4496 * queue environment.
4497 **/
4500 {
4505 /* no packets, exit with status unchanged */
4511 /* handle TSO and jumbo frames */
4519 /* this if handles the TSO accounting */
4530 }
4538 }
4540 }
4542 /* clear work counters since we have the values we need */
4546 /* write updated itr to ring container */
4548 }
4551 {
4556 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4561 }
4568 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4575 /* counts and packets in update_itr are dependent on these numbers */
4587 }
4589 set_itr_now:
4591 /* this attempts to bias the interrupt rate towards Bulk
4592 * by adding intermediate steps when interrupt rate is
4593 * increasing
4594 */
4599 /* Don't write the value here; it resets the adapter's
4600 * internal timer, and causes us to delay far longer than
4601 * we should between interrupts. Instead, we write the ITR
4602 * value at the beginning of the next interrupt so the timing
4603 * ends up being correct.
4604 */
4607 }
4608 }
4612 {
4618 i++;
4621 /* set bits to identify this as an advanced context descriptor */
4624 /* For 82575, context index must be unique per ring. */
4632 }
4637 {
4653 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4662 IPPROTO_TCP,
4666 IGB_TX_FLAGS_CSUM |
4667 IGB_TX_FLAGS_IPV4;
4674 IGB_TX_FLAGS_CSUM;
4675 }
4677 /* compute header lengths */
4681 /* update gso size and bytecount with header size */
4685 /* MSS L4LEN IDX */
4689 /* VLAN MACLEN IPLEN */
4697 }
4700 {
4727 }
4729 }
4735 E1000_ADVTXD_L4LEN_SHIFT;
4740 E1000_ADVTXD_L4LEN_SHIFT;
4744 E1000_ADVTXD_L4LEN_SHIFT;
4750 l4_hdr);
4751 }
4753 }
4755 /* update TX checksum flag */
4757 }
4763 }
4765 #define IGB_SET_FLAG(_input, _flag, _result) \
4766 ((_flag <= _result) ? \
4767 ((u32)(_input & _flag) * (_result / _flag)) : \
4768 ((u32)(_input & _flag) / (_flag / _result)))
4771 {
4772 /* set type for advanced descriptor with frame checksum insertion */
4774 E1000_ADVTXD_DCMD_DEXT |
4775 E1000_ADVTXD_DCMD_IFCS;
4777 /* set HW vlan bit if vlan is present */
4781 /* set segmentation bits for TSO */
4785 /* set timestamp bit if present */
4789 /* insert frame checksum */
4793 }
4798 {
4801 /* 82575 requires a unique index per ring */
4805 /* insert L4 checksum */
4807 IGB_TX_FLAGS_CSUM,
4810 /* insert IPv4 checksum */
4812 IGB_TX_FLAGS_IPV4,
4816 }
4819 {
4824 /* Herbert's original patch had:
4825 * smp_mb__after_netif_stop_queue();
4826 * but since that doesn't exist yet, just open code it.
4827 */
4830 /* We need to check again in a case another CPU has just
4831 * made room available.
4832 */
4836 /* A reprieve! */
4844 }
4847 {
4851 }
4856 {
4861 dma_addr_t dma;
4882 /* record length, and DMA address */
4892 i++;
4893 tx_desc++;
4897 }
4904 }
4911 i++;
4912 tx_desc++;
4916 }
4926 }
4928 /* write last descriptor with RS and EOP bits */
4934 /* set the timestamp */
4937 /* Force memory writes to complete before letting h/w know there
4938 * are new descriptors to fetch. (Only applicable for weak-ordered
4939 * memory model archs, such as IA-64).
4940 *
4941 * We also need this memory barrier to make certain all of the
4942 * status bits have been updated before next_to_watch is written.
4943 */
4946 /* set next_to_watch value indicating a packet is present */
4949 i++;
4955 /* Make sure there is space in the ring for the next send. */
4961 /* we need this if more than one processor can write to our tail
4962 * at a time, it synchronizes IO on IA64/Altix systems
4963 */
4965 }
4968 dma_error:
4971 /* clear dma mappings for failed tx_buffer_info map */
4979 i--;
4980 }
4983 }
4987 {
4995 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4996 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4997 * + 2 desc gap to keep tail from touching head,
4998 * + 1 desc for context descriptor,
4999 * otherwise try next time
5000 */
5008 }
5011 /* this is a hard error */
5013 }
5015 /* record the location of the first descriptor for this packet */
5033 }
5034 }
5041 }
5043 /* record initial flags and protocol */
5057 out_drop:
5061 }
5065 {
5072 }
5076 {
5082 }
5087 }
5089 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5090 * in order to meet this minimum size requirement.
5091 */
5096 }
5098 /**
5099 * igb_tx_timeout - Respond to a Tx Hang
5100 * @netdev: network interface device structure
5101 **/
5103 {
5107 /* Do the reset outside of interrupt context */
5116 }
5119 {
5126 }
5128 /**
5129 * igb_get_stats64 - Get System Network Statistics
5130 * @netdev: network interface device structure
5131 * @stats: rtnl_link_stats64 pointer
5132 **/
5135 {
5144 }
5146 /**
5147 * igb_change_mtu - Change the Maximum Transfer Unit
5148 * @netdev: network interface device structure
5149 * @new_mtu: new value for maximum frame size
5150 *
5151 * Returns 0 on success, negative on failure
5152 **/
5154 {
5162 }
5164 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5168 }
5170 /* adjust max frame to be at least the size of a standard frame */
5177 /* igb_down has a dependency on max_frame_size */
5189 else
5195 }
5197 /**
5198 * igb_update_stats - Update the board statistics counters
5199 * @adapter: board private structure
5200 **/
5203 {
5212 /* Prevent stats update while adapter is being reset, or if the pci
5213 * connection is down.
5214 */
5233 }
5242 }
5258 }
5263 /* read stats registers */
5320 /* read internal phy specific stats */
5325 /* this stat has invalid values on i210/i211 */
5329 }
5344 /* Fill out the OS statistics structure */
5348 /* Rx Errors */
5350 /* RLEC on some newer hardware can be incorrect so build
5351 * our own version based on RUC and ROC
5352 */
5363 /* Tx Errors */
5370 /* Tx Dropped needs to be maintained elsewhere */
5372 /* Management Stats */
5377 /* OS2BMC Stats */
5384 }
5385 }
5388 {
5392 /* reading ICR causes bit 31 of EICR to be cleared */
5398 /* HW is reporting DMA is out of sync */
5400 /* The DMA Out of Sync is also indication of a spoof event
5401 * in IOV mode. Check the Wrong VM Behavior register to
5402 * see if it is really a spoof event.
5403 */
5405 }
5407 /* Check for a mailbox event */
5413 /* guard against interrupt when we're going down */
5416 }
5422 /* acknowledge the interrupt */
5424 /* retrieve hardware timestamp */
5426 }
5427 }
5432 }
5435 {
5447 else
5452 }
5455 {
5458 /* Write the ITR value calculated from the previous interrupt. */
5464 }
5466 #ifdef CONFIG_IGB_DCA
5470 {
5477 /* We can enable relaxed ordering for reads, but not writes when
5478 * DCA is enabled. This is due to a known issue in some chipsets
5479 * which will cause the DCA tag to be cleared.
5480 */
5482 E1000_DCA_TXCTRL_DATA_RRO_EN |
5483 E1000_DCA_TXCTRL_DESC_DCA_EN;
5486 }
5491 {
5498 /* We can enable relaxed ordering for reads, but not writes when
5499 * DCA is enabled. This is due to a known issue in some chipsets
5500 * which will cause the DCA tag to be cleared.
5501 */
5503 E1000_DCA_RXCTRL_DESC_DCA_EN;
5506 }
5509 {
5523 out_no_update:
5525 }
5528 {
5535 /* Always use CB2 mode, difference is masked in the CB driver. */
5541 }
5542 }
5545 {
5554 /* if already enabled, don't do it again */
5562 }
5563 /* Fall Through since DCA is disabled. */
5566 /* without this a class_device is left
5567 * hanging around in the sysfs model
5568 */
5573 }
5575 }
5578 }
5582 {
5586 __igb_notify_dca);
5589 }
5592 #ifdef CONFIG_PCI_IOV
5594 {
5600 /* By default spoof check is enabled for all VFs */
5604 }
5606 #endif
5608 {
5610 u32 ping;
5618 }
5619 }
5622 {
5628 IGB_VF_FLAG_MULTI_PROMISC);
5636 /* if we have hashes and we are clearing a multicast promisc
5637 * flag we need to write the hashes to the MTA as this step
5638 * was previously skipped
5639 */
5648 }
5649 }
5653 /* there are flags left unprocessed, likely not supported */
5658 }
5662 {
5668 /* salt away the number of multicast addresses assigned
5669 * to this VF for later use to restore when the PF multi cast
5670 * list changes
5671 */
5674 /* only up to 30 hash values supported */
5678 /* store the hashes for later use */
5682 /* Flush and reset the mta with the new values */
5686 }
5689 {
5708 }
5710 }
5711 }
5714 {
5721 /* Find the vlan filter for this id */
5725 /* remove the vf from the pool */
5728 /* if pool is empty then remove entry from vfta */
5734 }
5737 }
5740 }
5743 {
5747 /* The vlvf table only exists on 82576 hardware and newer */
5751 /* we only need to do this if VMDq is enabled */
5755 /* Find the vlan filter for this id */
5761 }
5765 /* Did not find a matching VLAN ID entry that was
5766 * enabled. Search for a free filter entry, i.e.
5767 * one without the enable bit set
5768 */
5773 }
5774 }
5776 /* Found an enabled/available entry */
5779 /* if !enabled we need to set this up in vfta */
5781 /* add VID to filter table */
5784 }
5789 /* do not modify RLPML for PF devices */
5794 u32 size;
5802 }
5805 }
5808 /* remove vf from the pool */
5810 /* if pool is empty then remove entry from vfta */
5814 }
5817 /* do not modify RLPML for PF devices */
5823 u32 size;
5831 }
5832 }
5833 }
5835 }
5838 {
5843 else
5845 }
5849 {
5870 }
5878 }
5879 out:
5881 }
5884 {
5887 u32 reg;
5889 /* Find the vlan filter for this id */
5895 }
5901 }
5904 {
5910 /* If in promiscuous mode we need to make sure the PF also has
5911 * the VLAN filter set.
5912 */
5924 /* Go through all the checks to see if the VLAN filter should
5925 * be wiped completely.
5926 */
5933 /* See if any other pools are set for this VLAN filter
5934 * entry other than the PF.
5935 */
5939 /* If the filter was removed then ensure PF pool bit
5940 * is cleared if the PF only added itself to the pool
5941 * because the PF is in promiscuous mode.
5942 */
5948 }
5950 out:
5952 }
5955 {
5956 /* clear flags - except flag that indicates PF has set the MAC */
5960 /* reset offloads to defaults */
5963 /* reset vlans for device */
5969 else
5972 /* reset multicast table array for vf */
5975 /* Flush and reset the mta with the new values */
5977 }
5980 {
5983 /* clear mac address as we were hotplug removed/added */
5987 /* process remaining reset events */
5989 }
5992 {
5999 /* process all the same items cleared in a function level reset */
6002 /* set vf mac address */
6005 /* enable transmit and receive for vf */
6013 /* reply to reset with ack and vf mac address */
6017 }
6020 {
6021 /* The VF MAC Address is stored in a packed array of bytes
6022 * starting at the second 32 bit word of the msg array
6023 */
6031 }
6034 {
6039 /* if device isn't clear to send it shouldn't be reading either */
6044 }
6045 }
6048 {
6053 s32 retval;
6058 /* if receive failed revoke VF CTS stats and restart init */
6064 }
6066 /* this is a message we already processed, do nothing */
6070 /* until the vf completes a reset it should not be
6071 * allowed to start any configuration.
6072 */
6076 }
6083 }
6090 else
6092 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6093 vf);
6108 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6109 vf);
6110 else
6117 }
6120 out:
6121 /* notify the VF of the results of what it sent us */
6124 else
6128 }
6131 {
6133 u32 vf;
6136 /* process any reset requests */
6140 /* process any messages pending */
6144 /* process any acks */
6147 }
6148 }
6150 /**
6151 * igb_set_uta - Set unicast filter table address
6152 * @adapter: board private structure
6153 *
6154 * The unicast table address is a register array of 32-bit registers.
6155 * The table is meant to be used in a way similar to how the MTA is used
6156 * however due to certain limitations in the hardware it is necessary to
6157 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6158 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6159 **/
6161 {
6165 /* The UTA table only exists on 82576 hardware and newer */
6169 /* we only need to do this if VMDq is enabled */
6175 }
6177 /**
6178 * igb_intr_msi - Interrupt Handler
6179 * @irq: interrupt number
6180 * @data: pointer to a network interface device structure
6181 **/
6183 {
6187 /* read ICR disables interrupts using IAM */
6196 /* HW is reporting DMA is out of sync */
6198 }
6204 }
6210 /* acknowledge the interrupt */
6212 /* retrieve hardware timestamp */
6214 }
6215 }
6220 }
6222 /**
6223 * igb_intr - Legacy Interrupt Handler
6224 * @irq: interrupt number
6225 * @data: pointer to a network interface device structure
6226 **/
6228 {
6232 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6233 * need for the IMC write
6234 */
6237 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6238 * not set, then the adapter didn't send an interrupt
6239 */
6249 /* HW is reporting DMA is out of sync */
6251 }
6255 /* guard against interrupt when we're going down */
6258 }
6264 /* acknowledge the interrupt */
6266 /* retrieve hardware timestamp */
6268 }
6269 }
6274 }
6277 {
6285 else
6287 }
6292 else
6294 }
6295 }
6297 /**
6298 * igb_poll - NAPI Rx polling callback
6299 * @napi: napi polling structure
6300 * @budget: count of how many packets we should handle
6301 **/
6303 {
6306 napi);
6309 #ifdef CONFIG_IGB_DCA
6312 #endif
6319 /* If all work not completed, return budget and keep polling */
6323 /* If not enough Rx work done, exit the polling mode */
6328 }
6330 /**
6331 * igb_clean_tx_irq - Reclaim resources after transmit completes
6332 * @q_vector: pointer to q_vector containing needed info
6333 *
6334 * returns true if ring is completely cleaned
6335 **/
6337 {
6356 /* if next_to_watch is not set then there is no work pending */
6360 /* prevent any other reads prior to eop_desc */
6363 /* if DD is not set pending work has not been completed */
6367 /* clear next_to_watch to prevent false hangs */
6370 /* update the statistics for this packet */
6374 /* free the skb */
6377 /* unmap skb header data */
6381 DMA_TO_DEVICE);
6383 /* clear tx_buffer data */
6387 /* clear last DMA location and unmap remaining buffers */
6389 tx_buffer++;
6390 tx_desc++;
6391 i++;
6396 }
6398 /* unmap any remaining paged data */
6403 DMA_TO_DEVICE);
6405 }
6406 }
6408 /* move us one more past the eop_desc for start of next pkt */
6409 tx_buffer++;
6410 tx_desc++;
6411 i++;
6416 }
6418 /* issue prefetch for next Tx descriptor */
6421 /* update budget accounting */
6422 budget--;
6439 /* Detect a transmit hang in hardware, this serializes the
6440 * check with the clearing of time_stamp and movement of i
6441 */
6448 /* detected Tx unit hang */
6468 jiffies,
6473 /* we are about to reset, no point in enabling stuff */
6475 }
6476 }
6478 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6482 /* Make sure that anybody stopping the queue after this
6483 * sees the new next_to_clean.
6484 */
6495 }
6496 }
6499 }
6501 /**
6502 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6503 * @rx_ring: rx descriptor ring to store buffers on
6504 * @old_buff: donor buffer to have page reused
6505 *
6506 * Synchronizes page for reuse by the adapter
6507 **/
6510 {
6516 /* update, and store next to alloc */
6517 nta++;
6520 /* transfer page from old buffer to new buffer */
6523 /* sync the buffer for use by the device */
6526 IGB_RX_BUFSZ,
6527 DMA_FROM_DEVICE);
6528 }
6533 {
6534 /* avoid re-using remote pages */
6541 #if (PAGE_SIZE < 8192)
6542 /* if we are only owner of page we can reuse it */
6546 /* flip page offset to other buffer */
6549 /* Even if we own the page, we are not allowed to use atomic_set()
6550 * This would break get_page_unless_zero() users.
6551 */
6553 #else
6554 /* move offset up to the next cache line */
6560 /* bump ref count on page before it is given to the stack */
6562 #endif
6565 }
6567 /**
6568 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6569 * @rx_ring: rx descriptor ring to transact packets on
6570 * @rx_buffer: buffer containing page to add
6571 * @rx_desc: descriptor containing length of buffer written by hardware
6572 * @skb: sk_buff to place the data into
6573 *
6574 * This function will add the data contained in rx_buffer->page to the skb.
6575 * This is done either through a direct copy if the data in the buffer is
6576 * less than the skb header size, otherwise it will just attach the page as
6577 * a frag to the skb.
6578 *
6579 * The function will then update the page offset if necessary and return
6580 * true if the buffer can be reused by the adapter.
6581 **/
6586 {
6589 #if (PAGE_SIZE < 8192)
6591 #else
6593 #endif
6602 }
6606 /* we can reuse buffer as-is, just make sure it is local */
6611 /* this page cannot be reused so discard it */
6614 }
6620 }
6625 {
6638 /* prefetch first cache line of first page */
6640 #if L1_CACHE_BYTES < 128
6642 #endif
6644 /* allocate a skb to store the frags */
6649 }
6651 /* we will be copying header into skb->data in
6652 * pskb_may_pull so it is in our interest to prefetch
6653 * it now to avoid a possible cache miss
6654 */
6656 }
6658 /* we are reusing so sync this buffer for CPU use */
6662 IGB_RX_BUFSZ,
6663 DMA_FROM_DEVICE);
6665 /* pull page into skb */
6667 /* hand second half of page back to the ring */
6670 /* we are not reusing the buffer so unmap it */
6673 }
6675 /* clear contents of rx_buffer */
6679 }
6684 {
6687 /* Ignore Checksum bit is set */
6691 /* Rx checksum disabled via ethtool */
6695 /* TCP/UDP checksum error bit is set */
6697 E1000_RXDEXT_STATERR_TCPE |
6698 E1000_RXDEXT_STATERR_IPE)) {
6699 /* work around errata with sctp packets where the TCPE aka
6700 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6701 * packets, (aka let the stack check the crc32c)
6702 */
6708 }
6709 /* let the stack verify checksum errors */
6711 }
6712 /* It must be a TCP or UDP packet with a valid checksum */
6714 E1000_RXD_STAT_UDPCS))
6719 }
6724 {
6728 PKT_HASH_TYPE_L3);
6729 }
6731 /**
6732 * igb_is_non_eop - process handling of non-EOP buffers
6733 * @rx_ring: Rx ring being processed
6734 * @rx_desc: Rx descriptor for current buffer
6735 * @skb: current socket buffer containing buffer in progress
6736 *
6737 * This function updates next to clean. If the buffer is an EOP buffer
6738 * this function exits returning false, otherwise it will place the
6739 * sk_buff in the next buffer to be chained and return true indicating
6740 * that this is in fact a non-EOP buffer.
6741 **/
6744 {
6747 /* fetch, update, and store next to clean */
6757 }
6759 /**
6760 * igb_pull_tail - igb specific version of skb_pull_tail
6761 * @rx_ring: rx descriptor ring packet is being transacted on
6762 * @rx_desc: pointer to the EOP Rx descriptor
6763 * @skb: pointer to current skb being adjusted
6764 *
6765 * This function is an igb specific version of __pskb_pull_tail. The
6766 * main difference between this version and the original function is that
6767 * this function can make several assumptions about the state of things
6768 * that allow for significant optimizations versus the standard function.
6769 * As a result we can do things like drop a frag and maintain an accurate
6770 * truesize for the skb.
6771 */
6775 {
6780 /* it is valid to use page_address instead of kmap since we are
6781 * working with pages allocated out of the lomem pool per
6782 * alloc_page(GFP_ATOMIC)
6783 */
6787 /* retrieve timestamp from buffer */
6790 /* update pointers to remove timestamp header */
6796 /* move va to start of packet data */
6798 }
6800 /* we need the header to contain the greater of either ETH_HLEN or
6801 * 60 bytes if the skb->len is less than 60 for skb_pad.
6802 */
6805 /* align pull length to size of long to optimize memcpy performance */
6808 /* update all of the pointers */
6813 }
6815 /**
6816 * igb_cleanup_headers - Correct corrupted or empty headers
6817 * @rx_ring: rx descriptor ring packet is being transacted on
6818 * @rx_desc: pointer to the EOP Rx descriptor
6819 * @skb: pointer to current skb being fixed
6820 *
6821 * Address the case where we are pulling data in on pages only
6822 * and as such no data is present in the skb header.
6823 *
6824 * In addition if skb is not at least 60 bytes we need to pad it so that
6825 * it is large enough to qualify as a valid Ethernet frame.
6826 *
6827 * Returns true if an error was encountered and skb was freed.
6828 **/
6832 {
6834 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6839 }
6840 }
6842 /* place header in linear portion of buffer */
6846 /* if eth_skb_pad returns an error the skb was freed */
6851 }
6853 /**
6854 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6855 * @rx_ring: rx descriptor ring packet is being transacted on
6856 * @rx_desc: pointer to the EOP Rx descriptor
6857 * @skb: pointer to current skb being populated
6858 *
6859 * This function checks the ring, descriptor, and packet information in
6860 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6861 * other fields within the skb.
6862 **/
6866 {
6879 u16 vid;
6884 else
6888 }
6893 }
6896 {
6905 /* return some buffers to hardware, one at a time is too slow */
6909 }
6916 /* This memory barrier is needed to keep us from reading
6917 * any other fields out of the rx_desc until we know the
6918 * descriptor has been written back
6919 */
6922 /* retrieve a buffer from the ring */
6925 /* exit if we failed to retrieve a buffer */
6929 cleaned_count++;
6931 /* fetch next buffer in frame if non-eop */
6935 /* verify the packet layout is correct */
6939 }
6941 /* probably a little skewed due to removing CRC */
6944 /* populate checksum, timestamp, VLAN, and protocol */
6949 /* reset skb pointer */
6952 /* update budget accounting */
6953 total_packets++;
6954 }
6956 /* place incomplete frames back on ring for completion */
6970 }
6974 {
6976 dma_addr_t dma;
6978 /* since we are recycling buffers we should seldom need to alloc */
6982 /* alloc new page for storage */
6987 }
6989 /* map page for use */
6992 /* if mapping failed free memory back to system since
6993 * there isn't much point in holding memory we can't use
6994 */
7000 }
7007 }
7009 /**
7010 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7011 * @adapter: address of board private structure
7012 **/
7014 {
7019 /* nothing to do */
7031 /* Refresh the desc even if buffer_addrs didn't change
7032 * because each write-back erases this info.
7033 */
7036 rx_desc++;
7037 bi++;
7038 i++;
7043 }
7045 /* clear the hdr_addr for the next_to_use descriptor */
7048 cleaned_count--;
7054 /* record the next descriptor to use */
7057 /* update next to alloc since we have filled the ring */
7060 /* Force memory writes to complete before letting h/w
7061 * know there are new descriptors to fetch. (Only
7062 * applicable for weak-ordered memory model archs,
7063 * such as IA-64).
7064 */
7067 }
7068 }
7070 /**
7071 * igb_mii_ioctl -
7072 * @netdev:
7073 * @ifreq:
7074 * @cmd:
7075 **/
7077 {
7096 }
7098 }
7100 /**
7101 * igb_ioctl -
7102 * @netdev:
7103 * @ifreq:
7104 * @cmd:
7105 **/
7107 {
7119 }
7120 }
7123 {
7127 }
7130 {
7134 }
7137 {
7144 }
7147 {
7154 }
7157 {
7164 /* enable VLAN tag insert/strip */
7169 /* Disable CFI check */
7174 /* disable VLAN tag insert/strip */
7178 }
7181 }
7185 {
7190 /* attempt to add filter to vlvf array */
7193 /* add the filter since PF can receive vlans w/o entry in vlvf */
7199 }
7203 {
7207 s32 err;
7209 /* remove vlan from VLVF table array */
7212 /* if vid was not present in VLVF just remove it from table */
7219 }
7222 {
7223 u16 vid;
7229 }
7232 {
7238 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7239 * for the switch() below to work
7240 */
7244 /* Fiber NIC's only allow 1000 gbps Full duplex
7245 * and 100Mbps Full duplex for 100baseFx sfp
7246 */
7255 }
7256 }
7278 }
7280 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7285 err_inval:
7288 }
7292 {
7298 #ifdef CONFIG_PM
7300 #endif
7309 #ifdef CONFIG_PM
7313 #endif
7323 /* turn on all-multi mode if wake on multicast is enabled */
7328 }
7331 /* advertise wake from D3Cold */
7332 #define E1000_CTRL_ADVD3WUC 0x00100000
7333 /* phy power management enable */
7334 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7338 /* Allow time for pending master requests to run */
7346 }
7351 else
7354 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7355 * would have already happened in close and is redundant.
7356 */
7362 }
7364 #ifdef CONFIG_PM
7365 #ifdef CONFIG_PM_SLEEP
7367 {
7381 }
7384 }
7388 {
7393 u32 err;
7406 }
7415 }
7419 /* let the f/w know that the h/w is now under the control of the
7420 * driver.
7421 */
7432 }
7436 }
7439 {
7448 }
7451 {
7465 }
7468 }
7471 {
7473 }
7477 {
7485 }
7486 }
7488 #ifdef CONFIG_PCI_IOV
7490 {
7499 else
7509 }
7517 }
7520 {
7527 }
7530 {
7540 out:
7542 }
7544 #endif
7546 {
7547 #ifdef CONFIG_PCI_IOV
7550 else
7552 #endif
7554 }
7556 #ifdef CONFIG_NET_POLL_CONTROLLER
7557 /* Polling 'interrupt' - used by things like netconsole to send skbs
7558 * without having to re-enable interrupts. It's not called while
7559 * the interrupt routine is executing.
7560 */
7562 {
7572 else
7575 }
7576 }
7579 /**
7580 * igb_io_error_detected - called when PCI error is detected
7581 * @pdev: Pointer to PCI device
7582 * @state: The current pci connection state
7583 *
7584 * This function is called after a PCI bus error affecting
7585 * this device has been detected.
7586 **/
7588 pci_channel_state_t state)
7589 {
7602 /* Request a slot slot reset. */
7604 }
7606 /**
7607 * igb_io_slot_reset - called after the pci bus has been reset.
7608 * @pdev: Pointer to PCI device
7609 *
7610 * Restart the card from scratch, as if from a cold-boot. Implementation
7611 * resembles the first-half of the igb_resume routine.
7612 **/
7614 {
7618 pci_ers_result_t result;
7636 }
7642 err);
7643 /* non-fatal, continue */
7644 }
7647 }
7649 /**
7650 * igb_io_resume - called when traffic can start flowing again.
7651 * @pdev: Pointer to PCI device
7652 *
7653 * This callback is called when the error recovery driver tells us that
7654 * its OK to resume normal operation. Implementation resembles the
7655 * second-half of the igb_resume routine.
7656 */
7658 {
7666 }
7667 }
7671 /* let the f/w know that the h/w is now under the control of the
7672 * driver.
7673 */
7675 }
7678 u8 qsel)
7679 {
7683 /* HW expects these in little endian so we reverse the byte order
7684 * from network order (big endian) to little endian
7685 */
7690 /* Indicate to hardware the Address is Valid. */
7695 else
7702 }
7706 {
7708 /* VF MAC addresses start at end of receive addresses and moves
7709 * towards the first, as a result a collision should not be possible
7710 */
7718 }
7721 {
7734 }
7736 }
7739 {
7747 }
7748 }
7752 {
7754 u32 bcnrc_val;
7757 /* Calculate the rate factor values to set */
7761 tx_rate;
7765 E1000_RTTBCNRC_RF_INT_MASK);
7769 }
7772 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7773 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7774 */
7777 }
7780 {
7784 /* VF TX rate limit was not set or not supported */
7795 }
7803 actual_link_speed);
7804 }
7805 }
7809 {
7832 }
7836 {
7852 else
7859 }
7863 {
7875 }
7878 {
7880 u32 reg;
7888 /* replication is not supported for 82575 */
7891 /* notify HW that the MAC is adding vlan tags */
7895 /* Fall through */
7897 /* enable replication vlan tag stripping */
7901 /* Fall through */
7903 /* none of the above registers are supported by i350 */
7905 }
7915 }
7916 }
7919 {
7921 u32 dmac_thr;
7922 u16 hwm;
7926 u32 reg;
7928 /* force threshold to 0. */
7931 /* DMA Coalescing high water mark needs to be greater
7932 * than the Rx threshold. Set hwm to PBA - max frame
7933 * size in 16B units, capping it at PBA - 6KB.
7934 */
7944 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7945 * frame size, capping it at PBA - 10KB.
7946 */
7955 /* transition to L0x or L1 if available..*/
7958 /* watchdog timer= +-1000 usec in 32usec intervals */
7961 /* Disable BMC-to-OS Watchdog Enable */
7967 /* no lower threshold to disable
7968 * coalescing(smart fifb)-UTRESH=0
7969 */
7976 /* free space in tx packet buffer to wake from
7977 * DMA coal
7978 */
7982 /* make low power state decision controlled
7983 * by DMA coal
7984 */
7994 }
7995 }
7997 /**
7998 * igb_read_i2c_byte - Reads 8 bit word over I2C
7999 * @hw: pointer to hardware structure
8000 * @byte_offset: byte offset to read
8001 * @dev_addr: device address
8002 * @data: value read
8003 *
8004 * Performs byte read operation over I2C interface at
8005 * a specified device address.
8006 **/
8009 {
8012 s32 status;
8031 }
8032 }
8034 /**
8035 * igb_write_i2c_byte - Writes 8 bit word over I2C
8036 * @hw: pointer to hardware structure
8037 * @byte_offset: byte offset to write
8038 * @dev_addr: device address
8039 * @data: value to write
8040 *
8041 * Performs byte write operation over I2C interface at
8042 * a specified device address.
8043 **/
8046 {
8049 s32 status;
8062 else
8065 }
8068 {
8081 }
8087 }
8088 /* igb_main.c */