?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.14.51
[linux/fpc-iii.git] / drivers / mmc / host / dw_mmc.c
blobde31e20dc56c5f5fe834b5b34e6365f9a4dd3af3
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/sdio.h>
37 #include <linux/bitops.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/of.h>
40 #include <linux/of_gpio.h>
41 #include <linux/mmc/slot-gpio.h>
42
43 #include "dw_mmc.h"
44
45 /* Common flag combinations */
46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
47 SDMMC_INT_HTO | SDMMC_INT_SBE | \
48 SDMMC_INT_EBE | SDMMC_INT_HLE)
49 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
51 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
52 DW_MCI_CMD_ERROR_FLAGS)
53 #define DW_MCI_SEND_STATUS 1
54 #define DW_MCI_RECV_STATUS 2
55 #define DW_MCI_DMA_THRESHOLD 16
56
57 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
58 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
59
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
65 #define DESC_RING_BUF_SZ PAGE_SIZE
66
67 struct idmac_desc_64addr {
68 u32 des0; /* Control Descriptor */
69 #define IDMAC_OWN_CLR64(x) \
70 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
71
72 u32 des1; /* Reserved */
73
74 u32 des2; /*Buffer sizes */
75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
78
79 u32 des3; /* Reserved */
80
81 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
82 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
83
84 u32 des6; /* Lower 32-bits of Next Descriptor Address */
85 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86 };
87
88 struct idmac_desc {
89 __le32 des0; /* Control Descriptor */
90 #define IDMAC_DES0_DIC BIT(1)
91 #define IDMAC_DES0_LD BIT(2)
92 #define IDMAC_DES0_FD BIT(3)
93 #define IDMAC_DES0_CH BIT(4)
94 #define IDMAC_DES0_ER BIT(5)
95 #define IDMAC_DES0_CES BIT(30)
96 #define IDMAC_DES0_OWN BIT(31)
97
98 __le32 des1; /* Buffer sizes */
99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
101
102 __le32 des2; /* buffer 1 physical address */
103
104 __le32 des3; /* buffer 2 physical address */
105 };
106
107 /* Each descriptor can transfer up to 4KB of data in chained mode */
108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
109
110 #if defined(CONFIG_DEBUG_FS)
111 static int dw_mci_req_show(struct seq_file *s, void *v)
112 {
113 struct dw_mci_slot *slot = s->private;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_command *stop;
117 struct mmc_data *data;
118
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot->host->lock);
121 mrq = slot->mrq;
122
123 if (mrq) {
124 cmd = mrq->cmd;
125 data = mrq->data;
126 stop = mrq->stop;
127
128 if (cmd)
129 seq_printf(s,
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd->opcode, cmd->arg, cmd->flags,
132 cmd->resp[0], cmd->resp[1], cmd->resp[2],
133 cmd->resp[2], cmd->error);
134 if (data)
135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136 data->bytes_xfered, data->blocks,
137 data->blksz, data->flags, data->error);
138 if (stop)
139 seq_printf(s,
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop->opcode, stop->arg, stop->flags,
142 stop->resp[0], stop->resp[1], stop->resp[2],
143 stop->resp[2], stop->error);
144 }
145
146 spin_unlock_bh(&slot->host->lock);
147
148 return 0;
149 }
150
151 static int dw_mci_req_open(struct inode *inode, struct file *file)
152 {
153 return single_open(file, dw_mci_req_show, inode->i_private);
154 }
155
156 static const struct file_operations dw_mci_req_fops = {
157 .owner = THIS_MODULE,
158 .open = dw_mci_req_open,
159 .read = seq_read,
160 .llseek = seq_lseek,
161 .release = single_release,
162 };
163
164 static int dw_mci_regs_show(struct seq_file *s, void *v)
165 {
166 struct dw_mci *host = s->private;
167
168 pm_runtime_get_sync(host->dev);
169
170 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
171 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
172 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
173 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
174 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
175 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
176
177 pm_runtime_put_autosuspend(host->dev);
178
179 return 0;
180 }
181
182 static int dw_mci_regs_open(struct inode *inode, struct file *file)
183 {
184 return single_open(file, dw_mci_regs_show, inode->i_private);
185 }
186
187 static const struct file_operations dw_mci_regs_fops = {
188 .owner = THIS_MODULE,
189 .open = dw_mci_regs_open,
190 .read = seq_read,
191 .llseek = seq_lseek,
192 .release = single_release,
193 };
194
195 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
196 {
197 struct mmc_host *mmc = slot->mmc;
198 struct dw_mci *host = slot->host;
199 struct dentry *root;
200 struct dentry *node;
201
202 root = mmc->debugfs_root;
203 if (!root)
204 return;
205
206 node = debugfs_create_file("regs", S_IRUSR, root, host,
207 &dw_mci_regs_fops);
208 if (!node)
209 goto err;
210
211 node = debugfs_create_file("req", S_IRUSR, root, slot,
212 &dw_mci_req_fops);
213 if (!node)
214 goto err;
215
216 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
217 if (!node)
218 goto err;
219
220 node = debugfs_create_x32("pending_events", S_IRUSR, root,
221 (u32 *)&host->pending_events);
222 if (!node)
223 goto err;
224
225 node = debugfs_create_x32("completed_events", S_IRUSR, root,
226 (u32 *)&host->completed_events);
227 if (!node)
228 goto err;
229
230 return;
231
232 err:
233 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
234 }
235 #endif /* defined(CONFIG_DEBUG_FS) */
236
237 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
238 {
239 u32 ctrl;
240
241 ctrl = mci_readl(host, CTRL);
242 ctrl |= reset;
243 mci_writel(host, CTRL, ctrl);
244
245 /* wait till resets clear */
246 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
247 !(ctrl & reset),
248 1, 500 * USEC_PER_MSEC)) {
249 dev_err(host->dev,
250 "Timeout resetting block (ctrl reset %#x)\n",
251 ctrl & reset);
252 return false;
253 }
254
255 return true;
256 }
257
258 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
259 {
260 u32 status;
261
262 /*
263 * Databook says that before issuing a new data transfer command
264 * we need to check to see if the card is busy. Data transfer commands
265 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
266 *
267 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
268 * expected.
269 */
270 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
271 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
272 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
273 status,
274 !(status & SDMMC_STATUS_BUSY),
275 10, 500 * USEC_PER_MSEC))
276 dev_err(host->dev, "Busy; trying anyway\n");
277 }
278 }
279
280 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
281 {
282 struct dw_mci *host = slot->host;
283 unsigned int cmd_status = 0;
284
285 mci_writel(host, CMDARG, arg);
286 wmb(); /* drain writebuffer */
287 dw_mci_wait_while_busy(host, cmd);
288 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
289
290 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
291 !(cmd_status & SDMMC_CMD_START),
292 1, 500 * USEC_PER_MSEC))
293 dev_err(&slot->mmc->class_dev,
294 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
295 cmd, arg, cmd_status);
296 }
297
298 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
299 {
300 struct dw_mci_slot *slot = mmc_priv(mmc);
301 struct dw_mci *host = slot->host;
302 u32 cmdr;
303
304 cmd->error = -EINPROGRESS;
305 cmdr = cmd->opcode;
306
307 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
308 cmd->opcode == MMC_GO_IDLE_STATE ||
309 cmd->opcode == MMC_GO_INACTIVE_STATE ||
310 (cmd->opcode == SD_IO_RW_DIRECT &&
311 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
312 cmdr |= SDMMC_CMD_STOP;
313 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
314 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
315
316 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
317 u32 clk_en_a;
318
319 /* Special bit makes CMD11 not die */
320 cmdr |= SDMMC_CMD_VOLT_SWITCH;
321
322 /* Change state to continue to handle CMD11 weirdness */
323 WARN_ON(slot->host->state != STATE_SENDING_CMD);
324 slot->host->state = STATE_SENDING_CMD11;
325
326 /*
327 * We need to disable low power mode (automatic clock stop)
328 * while doing voltage switch so we don't confuse the card,
329 * since stopping the clock is a specific part of the UHS
330 * voltage change dance.
331 *
332 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
333 * unconditionally turned back on in dw_mci_setup_bus() if it's
334 * ever called with a non-zero clock. That shouldn't happen
335 * until the voltage change is all done.
336 */
337 clk_en_a = mci_readl(host, CLKENA);
338 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
339 mci_writel(host, CLKENA, clk_en_a);
340 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
341 SDMMC_CMD_PRV_DAT_WAIT, 0);
342 }
343
344 if (cmd->flags & MMC_RSP_PRESENT) {
345 /* We expect a response, so set this bit */
346 cmdr |= SDMMC_CMD_RESP_EXP;
347 if (cmd->flags & MMC_RSP_136)
348 cmdr |= SDMMC_CMD_RESP_LONG;
349 }
350
351 if (cmd->flags & MMC_RSP_CRC)
352 cmdr |= SDMMC_CMD_RESP_CRC;
353
354 if (cmd->data) {
355 cmdr |= SDMMC_CMD_DAT_EXP;
356 if (cmd->data->flags & MMC_DATA_WRITE)
357 cmdr |= SDMMC_CMD_DAT_WR;
358 }
359
360 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
361 cmdr |= SDMMC_CMD_USE_HOLD_REG;
362
363 return cmdr;
364 }
365
366 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
367 {
368 struct mmc_command *stop;
369 u32 cmdr;
370
371 if (!cmd->data)
372 return 0;
373
374 stop = &host->stop_abort;
375 cmdr = cmd->opcode;
376 memset(stop, 0, sizeof(struct mmc_command));
377
378 if (cmdr == MMC_READ_SINGLE_BLOCK ||
379 cmdr == MMC_READ_MULTIPLE_BLOCK ||
380 cmdr == MMC_WRITE_BLOCK ||
381 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
382 cmdr == MMC_SEND_TUNING_BLOCK ||
383 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
384 stop->opcode = MMC_STOP_TRANSMISSION;
385 stop->arg = 0;
386 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
387 } else if (cmdr == SD_IO_RW_EXTENDED) {
388 stop->opcode = SD_IO_RW_DIRECT;
389 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
390 ((cmd->arg >> 28) & 0x7);
391 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
392 } else {
393 return 0;
394 }
395
396 cmdr = stop->opcode | SDMMC_CMD_STOP |
397 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
398
399 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
400 cmdr |= SDMMC_CMD_USE_HOLD_REG;
401
402 return cmdr;
403 }
404
405 static inline void dw_mci_set_cto(struct dw_mci *host)
406 {
407 unsigned int cto_clks;
408 unsigned int cto_div;
409 unsigned int cto_ms;
410 unsigned long irqflags;
411
412 cto_clks = mci_readl(host, TMOUT) & 0xff;
413 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
414 if (cto_div == 0)
415 cto_div = 1;
416
417 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
418 host->bus_hz);
419
420 /* add a bit spare time */
421 cto_ms += 10;
422
423 /*
424 * The durations we're working with are fairly short so we have to be
425 * extra careful about synchronization here. Specifically in hardware a
426 * command timeout is _at most_ 5.1 ms, so that means we expect an
427 * interrupt (either command done or timeout) to come rather quickly
428 * after the mci_writel. ...but just in case we have a long interrupt
429 * latency let's add a bit of paranoia.
430 *
431 * In general we'll assume that at least an interrupt will be asserted
432 * in hardware by the time the cto_timer runs. ...and if it hasn't
433 * been asserted in hardware by that time then we'll assume it'll never
434 * come.
435 */
436 spin_lock_irqsave(&host->irq_lock, irqflags);
437 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
438 mod_timer(&host->cto_timer,
439 jiffies + msecs_to_jiffies(cto_ms) + 1);
440 spin_unlock_irqrestore(&host->irq_lock, irqflags);
441 }
442
443 static void dw_mci_start_command(struct dw_mci *host,
444 struct mmc_command *cmd, u32 cmd_flags)
445 {
446 host->cmd = cmd;
447 dev_vdbg(host->dev,
448 "start command: ARGR=0x%08x CMDR=0x%08x\n",
449 cmd->arg, cmd_flags);
450
451 mci_writel(host, CMDARG, cmd->arg);
452 wmb(); /* drain writebuffer */
453 dw_mci_wait_while_busy(host, cmd_flags);
454
455 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
456
457 /* response expected command only */
458 if (cmd_flags & SDMMC_CMD_RESP_EXP)
459 dw_mci_set_cto(host);
460 }
461
462 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
463 {
464 struct mmc_command *stop = &host->stop_abort;
465
466 dw_mci_start_command(host, stop, host->stop_cmdr);
467 }
468
469 /* DMA interface functions */
470 static void dw_mci_stop_dma(struct dw_mci *host)
471 {
472 if (host->using_dma) {
473 host->dma_ops->stop(host);
474 host->dma_ops->cleanup(host);
475 }
476
477 /* Data transfer was stopped by the interrupt handler */
478 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
479 }
480
481 static void dw_mci_dma_cleanup(struct dw_mci *host)
482 {
483 struct mmc_data *data = host->data;
484
485 if (data && data->host_cookie == COOKIE_MAPPED) {
486 dma_unmap_sg(host->dev,
487 data->sg,
488 data->sg_len,
489 mmc_get_dma_dir(data));
490 data->host_cookie = COOKIE_UNMAPPED;
491 }
492 }
493
494 static void dw_mci_idmac_reset(struct dw_mci *host)
495 {
496 u32 bmod = mci_readl(host, BMOD);
497 /* Software reset of DMA */
498 bmod |= SDMMC_IDMAC_SWRESET;
499 mci_writel(host, BMOD, bmod);
500 }
501
502 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
503 {
504 u32 temp;
505
506 /* Disable and reset the IDMAC interface */
507 temp = mci_readl(host, CTRL);
508 temp &= ~SDMMC_CTRL_USE_IDMAC;
509 temp |= SDMMC_CTRL_DMA_RESET;
510 mci_writel(host, CTRL, temp);
511
512 /* Stop the IDMAC running */
513 temp = mci_readl(host, BMOD);
514 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
515 temp |= SDMMC_IDMAC_SWRESET;
516 mci_writel(host, BMOD, temp);
517 }
518
519 static void dw_mci_dmac_complete_dma(void *arg)
520 {
521 struct dw_mci *host = arg;
522 struct mmc_data *data = host->data;
523
524 dev_vdbg(host->dev, "DMA complete\n");
525
526 if ((host->use_dma == TRANS_MODE_EDMAC) &&
527 data && (data->flags & MMC_DATA_READ))
528 /* Invalidate cache after read */
529 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
530 data->sg,
531 data->sg_len,
532 DMA_FROM_DEVICE);
533
534 host->dma_ops->cleanup(host);
535
536 /*
537 * If the card was removed, data will be NULL. No point in trying to
538 * send the stop command or waiting for NBUSY in this case.
539 */
540 if (data) {
541 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
542 tasklet_schedule(&host->tasklet);
543 }
544 }
545
546 static int dw_mci_idmac_init(struct dw_mci *host)
547 {
548 int i;
549
550 if (host->dma_64bit_address == 1) {
551 struct idmac_desc_64addr *p;
552 /* Number of descriptors in the ring buffer */
553 host->ring_size =
554 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
555
556 /* Forward link the descriptor list */
557 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
558 i++, p++) {
559 p->des6 = (host->sg_dma +
560 (sizeof(struct idmac_desc_64addr) *
561 (i + 1))) & 0xffffffff;
562
563 p->des7 = (u64)(host->sg_dma +
564 (sizeof(struct idmac_desc_64addr) *
565 (i + 1))) >> 32;
566 /* Initialize reserved and buffer size fields to "0" */
567 p->des0 = 0;
568 p->des1 = 0;
569 p->des2 = 0;
570 p->des3 = 0;
571 }
572
573 /* Set the last descriptor as the end-of-ring descriptor */
574 p->des6 = host->sg_dma & 0xffffffff;
575 p->des7 = (u64)host->sg_dma >> 32;
576 p->des0 = IDMAC_DES0_ER;
577
578 } else {
579 struct idmac_desc *p;
580 /* Number of descriptors in the ring buffer */
581 host->ring_size =
582 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
583
584 /* Forward link the descriptor list */
585 for (i = 0, p = host->sg_cpu;
586 i < host->ring_size - 1;
587 i++, p++) {
588 p->des3 = cpu_to_le32(host->sg_dma +
589 (sizeof(struct idmac_desc) * (i + 1)));
590 p->des0 = 0;
591 p->des1 = 0;
592 }
593
594 /* Set the last descriptor as the end-of-ring descriptor */
595 p->des3 = cpu_to_le32(host->sg_dma);
596 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
597 }
598
599 dw_mci_idmac_reset(host);
600
601 if (host->dma_64bit_address == 1) {
602 /* Mask out interrupts - get Tx & Rx complete only */
603 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
604 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
605 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
606
607 /* Set the descriptor base address */
608 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
609 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
610
611 } else {
612 /* Mask out interrupts - get Tx & Rx complete only */
613 mci_writel(host, IDSTS, IDMAC_INT_CLR);
614 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
615 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
616
617 /* Set the descriptor base address */
618 mci_writel(host, DBADDR, host->sg_dma);
619 }
620
621 return 0;
622 }
623
624 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
625 struct mmc_data *data,
626 unsigned int sg_len)
627 {
628 unsigned int desc_len;
629 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
630 u32 val;
631 int i;
632
633 desc_first = desc_last = desc = host->sg_cpu;
634
635 for (i = 0; i < sg_len; i++) {
636 unsigned int length = sg_dma_len(&data->sg[i]);
637
638 u64 mem_addr = sg_dma_address(&data->sg[i]);
639
640 for ( ; length ; desc++) {
641 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
642 length : DW_MCI_DESC_DATA_LENGTH;
643
644 length -= desc_len;
645
646 /*
647 * Wait for the former clear OWN bit operation
648 * of IDMAC to make sure that this descriptor
649 * isn't still owned by IDMAC as IDMAC's write
650 * ops and CPU's read ops are asynchronous.
651 */
652 if (readl_poll_timeout_atomic(&desc->des0, val,
653 !(val & IDMAC_DES0_OWN),
654 10, 100 * USEC_PER_MSEC))
655 goto err_own_bit;
656
657 /*
658 * Set the OWN bit and disable interrupts
659 * for this descriptor
660 */
661 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
662 IDMAC_DES0_CH;
663
664 /* Buffer length */
665 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
666
667 /* Physical address to DMA to/from */
668 desc->des4 = mem_addr & 0xffffffff;
669 desc->des5 = mem_addr >> 32;
670
671 /* Update physical address for the next desc */
672 mem_addr += desc_len;
673
674 /* Save pointer to the last descriptor */
675 desc_last = desc;
676 }
677 }
678
679 /* Set first descriptor */
680 desc_first->des0 |= IDMAC_DES0_FD;
681
682 /* Set last descriptor */
683 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
684 desc_last->des0 |= IDMAC_DES0_LD;
685
686 return 0;
687 err_own_bit:
688 /* restore the descriptor chain as it's polluted */
689 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
690 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
691 dw_mci_idmac_init(host);
692 return -EINVAL;
693 }
694
695
696 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
697 struct mmc_data *data,
698 unsigned int sg_len)
699 {
700 unsigned int desc_len;
701 struct idmac_desc *desc_first, *desc_last, *desc;
702 u32 val;
703 int i;
704
705 desc_first = desc_last = desc = host->sg_cpu;
706
707 for (i = 0; i < sg_len; i++) {
708 unsigned int length = sg_dma_len(&data->sg[i]);
709
710 u32 mem_addr = sg_dma_address(&data->sg[i]);
711
712 for ( ; length ; desc++) {
713 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
714 length : DW_MCI_DESC_DATA_LENGTH;
715
716 length -= desc_len;
717
718 /*
719 * Wait for the former clear OWN bit operation
720 * of IDMAC to make sure that this descriptor
721 * isn't still owned by IDMAC as IDMAC's write
722 * ops and CPU's read ops are asynchronous.
723 */
724 if (readl_poll_timeout_atomic(&desc->des0, val,
725 IDMAC_OWN_CLR64(val),
726 10,
727 100 * USEC_PER_MSEC))
728 goto err_own_bit;
729
730 /*
731 * Set the OWN bit and disable interrupts
732 * for this descriptor
733 */
734 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
735 IDMAC_DES0_DIC |
736 IDMAC_DES0_CH);
737
738 /* Buffer length */
739 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
740
741 /* Physical address to DMA to/from */
742 desc->des2 = cpu_to_le32(mem_addr);
743
744 /* Update physical address for the next desc */
745 mem_addr += desc_len;
746
747 /* Save pointer to the last descriptor */
748 desc_last = desc;
749 }
750 }
751
752 /* Set first descriptor */
753 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
754
755 /* Set last descriptor */
756 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
757 IDMAC_DES0_DIC));
758 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
759
760 return 0;
761 err_own_bit:
762 /* restore the descriptor chain as it's polluted */
763 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
764 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
765 dw_mci_idmac_init(host);
766 return -EINVAL;
767 }
768
769 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
770 {
771 u32 temp;
772 int ret;
773
774 if (host->dma_64bit_address == 1)
775 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
776 else
777 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
778
779 if (ret)
780 goto out;
781
782 /* drain writebuffer */
783 wmb();
784
785 /* Make sure to reset DMA in case we did PIO before this */
786 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
787 dw_mci_idmac_reset(host);
788
789 /* Select IDMAC interface */
790 temp = mci_readl(host, CTRL);
791 temp |= SDMMC_CTRL_USE_IDMAC;
792 mci_writel(host, CTRL, temp);
793
794 /* drain writebuffer */
795 wmb();
796
797 /* Enable the IDMAC */
798 temp = mci_readl(host, BMOD);
799 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
800 mci_writel(host, BMOD, temp);
801
802 /* Start it running */
803 mci_writel(host, PLDMND, 1);
804
805 out:
806 return ret;
807 }
808
809 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
810 .init = dw_mci_idmac_init,
811 .start = dw_mci_idmac_start_dma,
812 .stop = dw_mci_idmac_stop_dma,
813 .complete = dw_mci_dmac_complete_dma,
814 .cleanup = dw_mci_dma_cleanup,
815 };
816
817 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
818 {
819 dmaengine_terminate_async(host->dms->ch);
820 }
821
822 static int dw_mci_edmac_start_dma(struct dw_mci *host,
823 unsigned int sg_len)
824 {
825 struct dma_slave_config cfg;
826 struct dma_async_tx_descriptor *desc = NULL;
827 struct scatterlist *sgl = host->data->sg;
828 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
829 u32 sg_elems = host->data->sg_len;
830 u32 fifoth_val;
831 u32 fifo_offset = host->fifo_reg - host->regs;
832 int ret = 0;
833
834 /* Set external dma config: burst size, burst width */
835 cfg.dst_addr = host->phy_regs + fifo_offset;
836 cfg.src_addr = cfg.dst_addr;
837 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
838 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
839
840 /* Match burst msize with external dma config */
841 fifoth_val = mci_readl(host, FIFOTH);
842 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
843 cfg.src_maxburst = cfg.dst_maxburst;
844
845 if (host->data->flags & MMC_DATA_WRITE)
846 cfg.direction = DMA_MEM_TO_DEV;
847 else
848 cfg.direction = DMA_DEV_TO_MEM;
849
850 ret = dmaengine_slave_config(host->dms->ch, &cfg);
851 if (ret) {
852 dev_err(host->dev, "Failed to config edmac.\n");
853 return -EBUSY;
854 }
855
856 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
857 sg_len, cfg.direction,
858 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
859 if (!desc) {
860 dev_err(host->dev, "Can't prepare slave sg.\n");
861 return -EBUSY;
862 }
863
864 /* Set dw_mci_dmac_complete_dma as callback */
865 desc->callback = dw_mci_dmac_complete_dma;
866 desc->callback_param = (void *)host;
867 dmaengine_submit(desc);
868
869 /* Flush cache before write */
870 if (host->data->flags & MMC_DATA_WRITE)
871 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
872 sg_elems, DMA_TO_DEVICE);
873
874 dma_async_issue_pending(host->dms->ch);
875
876 return 0;
877 }
878
879 static int dw_mci_edmac_init(struct dw_mci *host)
880 {
881 /* Request external dma channel */
882 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
883 if (!host->dms)
884 return -ENOMEM;
885
886 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
887 if (!host->dms->ch) {
888 dev_err(host->dev, "Failed to get external DMA channel.\n");
889 kfree(host->dms);
890 host->dms = NULL;
891 return -ENXIO;
892 }
893
894 return 0;
895 }
896
897 static void dw_mci_edmac_exit(struct dw_mci *host)
898 {
899 if (host->dms) {
900 if (host->dms->ch) {
901 dma_release_channel(host->dms->ch);
902 host->dms->ch = NULL;
903 }
904 kfree(host->dms);
905 host->dms = NULL;
906 }
907 }
908
909 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
910 .init = dw_mci_edmac_init,
911 .exit = dw_mci_edmac_exit,
912 .start = dw_mci_edmac_start_dma,
913 .stop = dw_mci_edmac_stop_dma,
914 .complete = dw_mci_dmac_complete_dma,
915 .cleanup = dw_mci_dma_cleanup,
916 };
917
918 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
919 struct mmc_data *data,
920 int cookie)
921 {
922 struct scatterlist *sg;
923 unsigned int i, sg_len;
924
925 if (data->host_cookie == COOKIE_PRE_MAPPED)
926 return data->sg_len;
927
928 /*
929 * We don't do DMA on "complex" transfers, i.e. with
930 * non-word-aligned buffers or lengths. Also, we don't bother
931 * with all the DMA setup overhead for short transfers.
932 */
933 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
934 return -EINVAL;
935
936 if (data->blksz & 3)
937 return -EINVAL;
938
939 for_each_sg(data->sg, sg, data->sg_len, i) {
940 if (sg->offset & 3 || sg->length & 3)
941 return -EINVAL;
942 }
943
944 sg_len = dma_map_sg(host->dev,
945 data->sg,
946 data->sg_len,
947 mmc_get_dma_dir(data));
948 if (sg_len == 0)
949 return -EINVAL;
950
951 data->host_cookie = cookie;
952
953 return sg_len;
954 }
955
956 static void dw_mci_pre_req(struct mmc_host *mmc,
957 struct mmc_request *mrq)
958 {
959 struct dw_mci_slot *slot = mmc_priv(mmc);
960 struct mmc_data *data = mrq->data;
961
962 if (!slot->host->use_dma || !data)
963 return;
964
965 /* This data might be unmapped at this time */
966 data->host_cookie = COOKIE_UNMAPPED;
967
968 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
969 COOKIE_PRE_MAPPED) < 0)
970 data->host_cookie = COOKIE_UNMAPPED;
971 }
972
973 static void dw_mci_post_req(struct mmc_host *mmc,
974 struct mmc_request *mrq,
975 int err)
976 {
977 struct dw_mci_slot *slot = mmc_priv(mmc);
978 struct mmc_data *data = mrq->data;
979
980 if (!slot->host->use_dma || !data)
981 return;
982
983 if (data->host_cookie != COOKIE_UNMAPPED)
984 dma_unmap_sg(slot->host->dev,
985 data->sg,
986 data->sg_len,
987 mmc_get_dma_dir(data));
988 data->host_cookie = COOKIE_UNMAPPED;
989 }
990
991 static int dw_mci_get_cd(struct mmc_host *mmc)
992 {
993 int present;
994 struct dw_mci_slot *slot = mmc_priv(mmc);
995 struct dw_mci *host = slot->host;
996 int gpio_cd = mmc_gpio_get_cd(mmc);
997
998 /* Use platform get_cd function, else try onboard card detect */
999 if (((mmc->caps & MMC_CAP_NEEDS_POLL)
1000 || !mmc_card_is_removable(mmc))) {
1001 present = 1;
1002
1003 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1004 if (mmc->caps & MMC_CAP_NEEDS_POLL) {
1005 dev_info(&mmc->class_dev,
1006 "card is polling.\n");
1007 } else {
1008 dev_info(&mmc->class_dev,
1009 "card is non-removable.\n");
1010 }
1011 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1012 }
1013
1014 return present;
1015 } else if (gpio_cd >= 0)
1016 present = gpio_cd;
1017 else
1018 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1019 == 0 ? 1 : 0;
1020
1021 spin_lock_bh(&host->lock);
1022 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1023 dev_dbg(&mmc->class_dev, "card is present\n");
1024 else if (!present &&
1025 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1026 dev_dbg(&mmc->class_dev, "card is not present\n");
1027 spin_unlock_bh(&host->lock);
1028
1029 return present;
1030 }
1031
1032 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
1033 {
1034 unsigned int blksz = data->blksz;
1035 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
1036 u32 fifo_width = 1 << host->data_shift;
1037 u32 blksz_depth = blksz / fifo_width, fifoth_val;
1038 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
1039 int idx = ARRAY_SIZE(mszs) - 1;
1040
1041 /* pio should ship this scenario */
1042 if (!host->use_dma)
1043 return;
1044
1045 tx_wmark = (host->fifo_depth) / 2;
1046 tx_wmark_invers = host->fifo_depth - tx_wmark;
1047
1048 /*
1049 * MSIZE is '1',
1050 * if blksz is not a multiple of the FIFO width
1051 */
1052 if (blksz % fifo_width)
1053 goto done;
1054
1055 do {
1056 if (!((blksz_depth % mszs[idx]) ||
1057 (tx_wmark_invers % mszs[idx]))) {
1058 msize = idx;
1059 rx_wmark = mszs[idx] - 1;
1060 break;
1061 }
1062 } while (--idx > 0);
1063 /*
1064 * If idx is '0', it won't be tried
1065 * Thus, initial values are uesed
1066 */
1067 done:
1068 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1069 mci_writel(host, FIFOTH, fifoth_val);
1070 }
1071
1072 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1073 {
1074 unsigned int blksz = data->blksz;
1075 u32 blksz_depth, fifo_depth;
1076 u16 thld_size;
1077 u8 enable;
1078
1079 /*
1080 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1081 * in the FIFO region, so we really shouldn't access it).
1082 */
1083 if (host->verid < DW_MMC_240A ||
1084 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1085 return;
1086
1087 /*
1088 * Card write Threshold is introduced since 2.80a
1089 * It's used when HS400 mode is enabled.
1090 */
1091 if (data->flags & MMC_DATA_WRITE &&
1092 !(host->timing != MMC_TIMING_MMC_HS400))
1093 return;
1094
1095 if (data->flags & MMC_DATA_WRITE)
1096 enable = SDMMC_CARD_WR_THR_EN;
1097 else
1098 enable = SDMMC_CARD_RD_THR_EN;
1099
1100 if (host->timing != MMC_TIMING_MMC_HS200 &&
1101 host->timing != MMC_TIMING_UHS_SDR104)
1102 goto disable;
1103
1104 blksz_depth = blksz / (1 << host->data_shift);
1105 fifo_depth = host->fifo_depth;
1106
1107 if (blksz_depth > fifo_depth)
1108 goto disable;
1109
1110 /*
1111 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1112 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1113 * Currently just choose blksz.
1114 */
1115 thld_size = blksz;
1116 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1117 return;
1118
1119 disable:
1120 mci_writel(host, CDTHRCTL, 0);
1121 }
1122
1123 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1124 {
1125 unsigned long irqflags;
1126 int sg_len;
1127 u32 temp;
1128
1129 host->using_dma = 0;
1130
1131 /* If we don't have a channel, we can't do DMA */
1132 if (!host->use_dma)
1133 return -ENODEV;
1134
1135 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1136 if (sg_len < 0) {
1137 host->dma_ops->stop(host);
1138 return sg_len;
1139 }
1140
1141 host->using_dma = 1;
1142
1143 if (host->use_dma == TRANS_MODE_IDMAC)
1144 dev_vdbg(host->dev,
1145 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1146 (unsigned long)host->sg_cpu,
1147 (unsigned long)host->sg_dma,
1148 sg_len);
1149
1150 /*
1151 * Decide the MSIZE and RX/TX Watermark.
1152 * If current block size is same with previous size,
1153 * no need to update fifoth.
1154 */
1155 if (host->prev_blksz != data->blksz)
1156 dw_mci_adjust_fifoth(host, data);
1157
1158 /* Enable the DMA interface */
1159 temp = mci_readl(host, CTRL);
1160 temp |= SDMMC_CTRL_DMA_ENABLE;
1161 mci_writel(host, CTRL, temp);
1162
1163 /* Disable RX/TX IRQs, let DMA handle it */
1164 spin_lock_irqsave(&host->irq_lock, irqflags);
1165 temp = mci_readl(host, INTMASK);
1166 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1167 mci_writel(host, INTMASK, temp);
1168 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1169
1170 if (host->dma_ops->start(host, sg_len)) {
1171 host->dma_ops->stop(host);
1172 /* We can't do DMA, try PIO for this one */
1173 dev_dbg(host->dev,
1174 "%s: fall back to PIO mode for current transfer\n",
1175 __func__);
1176 return -ENODEV;
1177 }
1178
1179 return 0;
1180 }
1181
1182 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1183 {
1184 unsigned long irqflags;
1185 int flags = SG_MITER_ATOMIC;
1186 u32 temp;
1187
1188 data->error = -EINPROGRESS;
1189
1190 WARN_ON(host->data);
1191 host->sg = NULL;
1192 host->data = data;
1193
1194 if (data->flags & MMC_DATA_READ)
1195 host->dir_status = DW_MCI_RECV_STATUS;
1196 else
1197 host->dir_status = DW_MCI_SEND_STATUS;
1198
1199 dw_mci_ctrl_thld(host, data);
1200
1201 if (dw_mci_submit_data_dma(host, data)) {
1202 if (host->data->flags & MMC_DATA_READ)
1203 flags |= SG_MITER_TO_SG;
1204 else
1205 flags |= SG_MITER_FROM_SG;
1206
1207 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1208 host->sg = data->sg;
1209 host->part_buf_start = 0;
1210 host->part_buf_count = 0;
1211
1212 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1213
1214 spin_lock_irqsave(&host->irq_lock, irqflags);
1215 temp = mci_readl(host, INTMASK);
1216 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1217 mci_writel(host, INTMASK, temp);
1218 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1219
1220 temp = mci_readl(host, CTRL);
1221 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1222 mci_writel(host, CTRL, temp);
1223
1224 /*
1225 * Use the initial fifoth_val for PIO mode. If wm_algined
1226 * is set, we set watermark same as data size.
1227 * If next issued data may be transfered by DMA mode,
1228 * prev_blksz should be invalidated.
1229 */
1230 if (host->wm_aligned)
1231 dw_mci_adjust_fifoth(host, data);
1232 else
1233 mci_writel(host, FIFOTH, host->fifoth_val);
1234 host->prev_blksz = 0;
1235 } else {
1236 /*
1237 * Keep the current block size.
1238 * It will be used to decide whether to update
1239 * fifoth register next time.
1240 */
1241 host->prev_blksz = data->blksz;
1242 }
1243 }
1244
1245 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1246 {
1247 struct dw_mci *host = slot->host;
1248 unsigned int clock = slot->clock;
1249 u32 div;
1250 u32 clk_en_a;
1251 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1252
1253 /* We must continue to set bit 28 in CMD until the change is complete */
1254 if (host->state == STATE_WAITING_CMD11_DONE)
1255 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1256
1257 if (!clock) {
1258 mci_writel(host, CLKENA, 0);
1259 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1260 } else if (clock != host->current_speed || force_clkinit) {
1261 div = host->bus_hz / clock;
1262 if (host->bus_hz % clock && host->bus_hz > clock)
1263 /*
1264 * move the + 1 after the divide to prevent
1265 * over-clocking the card.
1266 */
1267 div += 1;
1268
1269 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1270
1271 if ((clock != slot->__clk_old &&
1272 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1273 force_clkinit) {
1274 /* Silent the verbose log if calling from PM context */
1275 if (!force_clkinit)
1276 dev_info(&slot->mmc->class_dev,
1277 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1278 slot->id, host->bus_hz, clock,
1279 div ? ((host->bus_hz / div) >> 1) :
1280 host->bus_hz, div);
1281
1282 /*
1283 * If card is polling, display the message only
1284 * one time at boot time.
1285 */
1286 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1287 slot->mmc->f_min == clock)
1288 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1289 }
1290
1291 /* disable clock */
1292 mci_writel(host, CLKENA, 0);
1293 mci_writel(host, CLKSRC, 0);
1294
1295 /* inform CIU */
1296 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1297
1298 /* set clock to desired speed */
1299 mci_writel(host, CLKDIV, div);
1300
1301 /* inform CIU */
1302 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1303
1304 /* enable clock; only low power if no SDIO */
1305 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1306 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1307 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1308 mci_writel(host, CLKENA, clk_en_a);
1309
1310 /* inform CIU */
1311 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1312
1313 /* keep the last clock value that was requested from core */
1314 slot->__clk_old = clock;
1315 }
1316
1317 host->current_speed = clock;
1318
1319 /* Set the current slot bus width */
1320 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1321 }
1322
1323 static void __dw_mci_start_request(struct dw_mci *host,
1324 struct dw_mci_slot *slot,
1325 struct mmc_command *cmd)
1326 {
1327 struct mmc_request *mrq;
1328 struct mmc_data *data;
1329 u32 cmdflags;
1330
1331 mrq = slot->mrq;
1332
1333 host->mrq = mrq;
1334
1335 host->pending_events = 0;
1336 host->completed_events = 0;
1337 host->cmd_status = 0;
1338 host->data_status = 0;
1339 host->dir_status = 0;
1340
1341 data = cmd->data;
1342 if (data) {
1343 mci_writel(host, TMOUT, 0xFFFFFFFF);
1344 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1345 mci_writel(host, BLKSIZ, data->blksz);
1346 }
1347
1348 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1349
1350 /* this is the first command, send the initialization clock */
1351 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1352 cmdflags |= SDMMC_CMD_INIT;
1353
1354 if (data) {
1355 dw_mci_submit_data(host, data);
1356 wmb(); /* drain writebuffer */
1357 }
1358
1359 dw_mci_start_command(host, cmd, cmdflags);
1360
1361 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1362 unsigned long irqflags;
1363
1364 /*
1365 * Databook says to fail after 2ms w/ no response, but evidence
1366 * shows that sometimes the cmd11 interrupt takes over 130ms.
1367 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1368 * is just about to roll over.
1369 *
1370 * We do this whole thing under spinlock and only if the
1371 * command hasn't already completed (indicating the the irq
1372 * already ran so we don't want the timeout).
1373 */
1374 spin_lock_irqsave(&host->irq_lock, irqflags);
1375 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1376 mod_timer(&host->cmd11_timer,
1377 jiffies + msecs_to_jiffies(500) + 1);
1378 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1379 }
1380
1381 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1382 }
1383
1384 static void dw_mci_start_request(struct dw_mci *host,
1385 struct dw_mci_slot *slot)
1386 {
1387 struct mmc_request *mrq = slot->mrq;
1388 struct mmc_command *cmd;
1389
1390 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1391 __dw_mci_start_request(host, slot, cmd);
1392 }
1393
1394 /* must be called with host->lock held */
1395 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1396 struct mmc_request *mrq)
1397 {
1398 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1399 host->state);
1400
1401 slot->mrq = mrq;
1402
1403 if (host->state == STATE_WAITING_CMD11_DONE) {
1404 dev_warn(&slot->mmc->class_dev,
1405 "Voltage change didn't complete\n");
1406 /*
1407 * this case isn't expected to happen, so we can
1408 * either crash here or just try to continue on
1409 * in the closest possible state
1410 */
1411 host->state = STATE_IDLE;
1412 }
1413
1414 if (host->state == STATE_IDLE) {
1415 host->state = STATE_SENDING_CMD;
1416 dw_mci_start_request(host, slot);
1417 } else {
1418 list_add_tail(&slot->queue_node, &host->queue);
1419 }
1420 }
1421
1422 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1423 {
1424 struct dw_mci_slot *slot = mmc_priv(mmc);
1425 struct dw_mci *host = slot->host;
1426
1427 WARN_ON(slot->mrq);
1428
1429 /*
1430 * The check for card presence and queueing of the request must be
1431 * atomic, otherwise the card could be removed in between and the
1432 * request wouldn't fail until another card was inserted.
1433 */
1434
1435 if (!dw_mci_get_cd(mmc)) {
1436 mrq->cmd->error = -ENOMEDIUM;
1437 mmc_request_done(mmc, mrq);
1438 return;
1439 }
1440
1441 spin_lock_bh(&host->lock);
1442
1443 dw_mci_queue_request(host, slot, mrq);
1444
1445 spin_unlock_bh(&host->lock);
1446 }
1447
1448 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1449 {
1450 struct dw_mci_slot *slot = mmc_priv(mmc);
1451 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1452 u32 regs;
1453 int ret;
1454
1455 switch (ios->bus_width) {
1456 case MMC_BUS_WIDTH_4:
1457 slot->ctype = SDMMC_CTYPE_4BIT;
1458 break;
1459 case MMC_BUS_WIDTH_8:
1460 slot->ctype = SDMMC_CTYPE_8BIT;
1461 break;
1462 default:
1463 /* set default 1 bit mode */
1464 slot->ctype = SDMMC_CTYPE_1BIT;
1465 }
1466
1467 regs = mci_readl(slot->host, UHS_REG);
1468
1469 /* DDR mode set */
1470 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1471 ios->timing == MMC_TIMING_UHS_DDR50 ||
1472 ios->timing == MMC_TIMING_MMC_HS400)
1473 regs |= ((0x1 << slot->id) << 16);
1474 else
1475 regs &= ~((0x1 << slot->id) << 16);
1476
1477 mci_writel(slot->host, UHS_REG, regs);
1478 slot->host->timing = ios->timing;
1479
1480 /*
1481 * Use mirror of ios->clock to prevent race with mmc
1482 * core ios update when finding the minimum.
1483 */
1484 slot->clock = ios->clock;
1485
1486 if (drv_data && drv_data->set_ios)
1487 drv_data->set_ios(slot->host, ios);
1488
1489 switch (ios->power_mode) {
1490 case MMC_POWER_UP:
1491 if (!IS_ERR(mmc->supply.vmmc)) {
1492 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1493 ios->vdd);
1494 if (ret) {
1495 dev_err(slot->host->dev,
1496 "failed to enable vmmc regulator\n");
1497 /*return, if failed turn on vmmc*/
1498 return;
1499 }
1500 }
1501 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1502 regs = mci_readl(slot->host, PWREN);
1503 regs |= (1 << slot->id);
1504 mci_writel(slot->host, PWREN, regs);
1505 break;
1506 case MMC_POWER_ON:
1507 if (!slot->host->vqmmc_enabled) {
1508 if (!IS_ERR(mmc->supply.vqmmc)) {
1509 ret = regulator_enable(mmc->supply.vqmmc);
1510 if (ret < 0)
1511 dev_err(slot->host->dev,
1512 "failed to enable vqmmc\n");
1513 else
1514 slot->host->vqmmc_enabled = true;
1515
1516 } else {
1517 /* Keep track so we don't reset again */
1518 slot->host->vqmmc_enabled = true;
1519 }
1520
1521 /* Reset our state machine after powering on */
1522 dw_mci_ctrl_reset(slot->host,
1523 SDMMC_CTRL_ALL_RESET_FLAGS);
1524 }
1525
1526 /* Adjust clock / bus width after power is up */
1527 dw_mci_setup_bus(slot, false);
1528
1529 break;
1530 case MMC_POWER_OFF:
1531 /* Turn clock off before power goes down */
1532 dw_mci_setup_bus(slot, false);
1533
1534 if (!IS_ERR(mmc->supply.vmmc))
1535 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1536
1537 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1538 regulator_disable(mmc->supply.vqmmc);
1539 slot->host->vqmmc_enabled = false;
1540
1541 regs = mci_readl(slot->host, PWREN);
1542 regs &= ~(1 << slot->id);
1543 mci_writel(slot->host, PWREN, regs);
1544 break;
1545 default:
1546 break;
1547 }
1548
1549 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1550 slot->host->state = STATE_IDLE;
1551 }
1552
1553 static int dw_mci_card_busy(struct mmc_host *mmc)
1554 {
1555 struct dw_mci_slot *slot = mmc_priv(mmc);
1556 u32 status;
1557
1558 /*
1559 * Check the busy bit which is low when DAT[3:0]
1560 * (the data lines) are 0000
1561 */
1562 status = mci_readl(slot->host, STATUS);
1563
1564 return !!(status & SDMMC_STATUS_BUSY);
1565 }
1566
1567 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1568 {
1569 struct dw_mci_slot *slot = mmc_priv(mmc);
1570 struct dw_mci *host = slot->host;
1571 const struct dw_mci_drv_data *drv_data = host->drv_data;
1572 u32 uhs;
1573 u32 v18 = SDMMC_UHS_18V << slot->id;
1574 int ret;
1575
1576 if (drv_data && drv_data->switch_voltage)
1577 return drv_data->switch_voltage(mmc, ios);
1578
1579 /*
1580 * Program the voltage. Note that some instances of dw_mmc may use
1581 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1582 * does no harm but you need to set the regulator directly. Try both.
1583 */
1584 uhs = mci_readl(host, UHS_REG);
1585 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1586 uhs &= ~v18;
1587 else
1588 uhs |= v18;
1589
1590 if (!IS_ERR(mmc->supply.vqmmc)) {
1591 ret = mmc_regulator_set_vqmmc(mmc, ios);
1592
1593 if (ret) {
1594 dev_dbg(&mmc->class_dev,
1595 "Regulator set error %d - %s V\n",
1596 ret, uhs & v18 ? "1.8" : "3.3");
1597 return ret;
1598 }
1599 }
1600 mci_writel(host, UHS_REG, uhs);
1601
1602 return 0;
1603 }
1604
1605 static int dw_mci_get_ro(struct mmc_host *mmc)
1606 {
1607 int read_only;
1608 struct dw_mci_slot *slot = mmc_priv(mmc);
1609 int gpio_ro = mmc_gpio_get_ro(mmc);
1610
1611 /* Use platform get_ro function, else try on board write protect */
1612 if (gpio_ro >= 0)
1613 read_only = gpio_ro;
1614 else
1615 read_only =
1616 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1617
1618 dev_dbg(&mmc->class_dev, "card is %s\n",
1619 read_only ? "read-only" : "read-write");
1620
1621 return read_only;
1622 }
1623
1624 static void dw_mci_hw_reset(struct mmc_host *mmc)
1625 {
1626 struct dw_mci_slot *slot = mmc_priv(mmc);
1627 struct dw_mci *host = slot->host;
1628 int reset;
1629
1630 if (host->use_dma == TRANS_MODE_IDMAC)
1631 dw_mci_idmac_reset(host);
1632
1633 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1634 SDMMC_CTRL_FIFO_RESET))
1635 return;
1636
1637 /*
1638 * According to eMMC spec, card reset procedure:
1639 * tRstW >= 1us: RST_n pulse width
1640 * tRSCA >= 200us: RST_n to Command time
1641 * tRSTH >= 1us: RST_n high period
1642 */
1643 reset = mci_readl(host, RST_N);
1644 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1645 mci_writel(host, RST_N, reset);
1646 usleep_range(1, 2);
1647 reset |= SDMMC_RST_HWACTIVE << slot->id;
1648 mci_writel(host, RST_N, reset);
1649 usleep_range(200, 300);
1650 }
1651
1652 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1653 {
1654 struct dw_mci_slot *slot = mmc_priv(mmc);
1655 struct dw_mci *host = slot->host;
1656
1657 /*
1658 * Low power mode will stop the card clock when idle. According to the
1659 * description of the CLKENA register we should disable low power mode
1660 * for SDIO cards if we need SDIO interrupts to work.
1661 */
1662 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1663 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1664 u32 clk_en_a_old;
1665 u32 clk_en_a;
1666
1667 clk_en_a_old = mci_readl(host, CLKENA);
1668
1669 if (card->type == MMC_TYPE_SDIO ||
1670 card->type == MMC_TYPE_SD_COMBO) {
1671 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1672 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1673 } else {
1674 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1675 clk_en_a = clk_en_a_old | clken_low_pwr;
1676 }
1677
1678 if (clk_en_a != clk_en_a_old) {
1679 mci_writel(host, CLKENA, clk_en_a);
1680 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1681 SDMMC_CMD_PRV_DAT_WAIT, 0);
1682 }
1683 }
1684 }
1685
1686 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1687 {
1688 struct dw_mci *host = slot->host;
1689 unsigned long irqflags;
1690 u32 int_mask;
1691
1692 spin_lock_irqsave(&host->irq_lock, irqflags);
1693
1694 /* Enable/disable Slot Specific SDIO interrupt */
1695 int_mask = mci_readl(host, INTMASK);
1696 if (enb)
1697 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1698 else
1699 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1700 mci_writel(host, INTMASK, int_mask);
1701
1702 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1703 }
1704
1705 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1706 {
1707 struct dw_mci_slot *slot = mmc_priv(mmc);
1708 struct dw_mci *host = slot->host;
1709
1710 __dw_mci_enable_sdio_irq(slot, enb);
1711
1712 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1713 if (enb)
1714 pm_runtime_get_noresume(host->dev);
1715 else
1716 pm_runtime_put_noidle(host->dev);
1717 }
1718
1719 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1720 {
1721 struct dw_mci_slot *slot = mmc_priv(mmc);
1722
1723 __dw_mci_enable_sdio_irq(slot, 1);
1724 }
1725
1726 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1727 {
1728 struct dw_mci_slot *slot = mmc_priv(mmc);
1729 struct dw_mci *host = slot->host;
1730 const struct dw_mci_drv_data *drv_data = host->drv_data;
1731 int err = -EINVAL;
1732
1733 if (drv_data && drv_data->execute_tuning)
1734 err = drv_data->execute_tuning(slot, opcode);
1735 return err;
1736 }
1737
1738 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1739 struct mmc_ios *ios)
1740 {
1741 struct dw_mci_slot *slot = mmc_priv(mmc);
1742 struct dw_mci *host = slot->host;
1743 const struct dw_mci_drv_data *drv_data = host->drv_data;
1744
1745 if (drv_data && drv_data->prepare_hs400_tuning)
1746 return drv_data->prepare_hs400_tuning(host, ios);
1747
1748 return 0;
1749 }
1750
1751 static bool dw_mci_reset(struct dw_mci *host)
1752 {
1753 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1754 bool ret = false;
1755 u32 status = 0;
1756
1757 /*
1758 * Resetting generates a block interrupt, hence setting
1759 * the scatter-gather pointer to NULL.
1760 */
1761 if (host->sg) {
1762 sg_miter_stop(&host->sg_miter);
1763 host->sg = NULL;
1764 }
1765
1766 if (host->use_dma)
1767 flags |= SDMMC_CTRL_DMA_RESET;
1768
1769 if (dw_mci_ctrl_reset(host, flags)) {
1770 /*
1771 * In all cases we clear the RAWINTS
1772 * register to clear any interrupts.
1773 */
1774 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1775
1776 if (!host->use_dma) {
1777 ret = true;
1778 goto ciu_out;
1779 }
1780
1781 /* Wait for dma_req to be cleared */
1782 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1783 status,
1784 !(status & SDMMC_STATUS_DMA_REQ),
1785 1, 500 * USEC_PER_MSEC)) {
1786 dev_err(host->dev,
1787 "%s: Timeout waiting for dma_req to be cleared\n",
1788 __func__);
1789 goto ciu_out;
1790 }
1791
1792 /* when using DMA next we reset the fifo again */
1793 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1794 goto ciu_out;
1795 } else {
1796 /* if the controller reset bit did clear, then set clock regs */
1797 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1798 dev_err(host->dev,
1799 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1800 __func__);
1801 goto ciu_out;
1802 }
1803 }
1804
1805 if (host->use_dma == TRANS_MODE_IDMAC)
1806 /* It is also required that we reinit idmac */
1807 dw_mci_idmac_init(host);
1808
1809 ret = true;
1810
1811 ciu_out:
1812 /* After a CTRL reset we need to have CIU set clock registers */
1813 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1814
1815 return ret;
1816 }
1817
1818 static const struct mmc_host_ops dw_mci_ops = {
1819 .request = dw_mci_request,
1820 .pre_req = dw_mci_pre_req,
1821 .post_req = dw_mci_post_req,
1822 .set_ios = dw_mci_set_ios,
1823 .get_ro = dw_mci_get_ro,
1824 .get_cd = dw_mci_get_cd,
1825 .hw_reset = dw_mci_hw_reset,
1826 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1827 .ack_sdio_irq = dw_mci_ack_sdio_irq,
1828 .execute_tuning = dw_mci_execute_tuning,
1829 .card_busy = dw_mci_card_busy,
1830 .start_signal_voltage_switch = dw_mci_switch_voltage,
1831 .init_card = dw_mci_init_card,
1832 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1833 };
1834
1835 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1836 __releases(&host->lock)
1837 __acquires(&host->lock)
1838 {
1839 struct dw_mci_slot *slot;
1840 struct mmc_host *prev_mmc = host->slot->mmc;
1841
1842 WARN_ON(host->cmd || host->data);
1843
1844 host->slot->mrq = NULL;
1845 host->mrq = NULL;
1846 if (!list_empty(&host->queue)) {
1847 slot = list_entry(host->queue.next,
1848 struct dw_mci_slot, queue_node);
1849 list_del(&slot->queue_node);
1850 dev_vdbg(host->dev, "list not empty: %s is next\n",
1851 mmc_hostname(slot->mmc));
1852 host->state = STATE_SENDING_CMD;
1853 dw_mci_start_request(host, slot);
1854 } else {
1855 dev_vdbg(host->dev, "list empty\n");
1856
1857 if (host->state == STATE_SENDING_CMD11)
1858 host->state = STATE_WAITING_CMD11_DONE;
1859 else
1860 host->state = STATE_IDLE;
1861 }
1862
1863 spin_unlock(&host->lock);
1864 mmc_request_done(prev_mmc, mrq);
1865 spin_lock(&host->lock);
1866 }
1867
1868 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1869 {
1870 u32 status = host->cmd_status;
1871
1872 host->cmd_status = 0;
1873
1874 /* Read the response from the card (up to 16 bytes) */
1875 if (cmd->flags & MMC_RSP_PRESENT) {
1876 if (cmd->flags & MMC_RSP_136) {
1877 cmd->resp[3] = mci_readl(host, RESP0);
1878 cmd->resp[2] = mci_readl(host, RESP1);
1879 cmd->resp[1] = mci_readl(host, RESP2);
1880 cmd->resp[0] = mci_readl(host, RESP3);
1881 } else {
1882 cmd->resp[0] = mci_readl(host, RESP0);
1883 cmd->resp[1] = 0;
1884 cmd->resp[2] = 0;
1885 cmd->resp[3] = 0;
1886 }
1887 }
1888
1889 if (status & SDMMC_INT_RTO)
1890 cmd->error = -ETIMEDOUT;
1891 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1892 cmd->error = -EILSEQ;
1893 else if (status & SDMMC_INT_RESP_ERR)
1894 cmd->error = -EIO;
1895 else
1896 cmd->error = 0;
1897
1898 return cmd->error;
1899 }
1900
1901 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1902 {
1903 u32 status = host->data_status;
1904
1905 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1906 if (status & SDMMC_INT_DRTO) {
1907 data->error = -ETIMEDOUT;
1908 } else if (status & SDMMC_INT_DCRC) {
1909 data->error = -EILSEQ;
1910 } else if (status & SDMMC_INT_EBE) {
1911 if (host->dir_status ==
1912 DW_MCI_SEND_STATUS) {
1913 /*
1914 * No data CRC status was returned.
1915 * The number of bytes transferred
1916 * will be exaggerated in PIO mode.
1917 */
1918 data->bytes_xfered = 0;
1919 data->error = -ETIMEDOUT;
1920 } else if (host->dir_status ==
1921 DW_MCI_RECV_STATUS) {
1922 data->error = -EILSEQ;
1923 }
1924 } else {
1925 /* SDMMC_INT_SBE is included */
1926 data->error = -EILSEQ;
1927 }
1928
1929 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1930
1931 /*
1932 * After an error, there may be data lingering
1933 * in the FIFO
1934 */
1935 dw_mci_reset(host);
1936 } else {
1937 data->bytes_xfered = data->blocks * data->blksz;
1938 data->error = 0;
1939 }
1940
1941 return data->error;
1942 }
1943
1944 static void dw_mci_set_drto(struct dw_mci *host)
1945 {
1946 unsigned int drto_clks;
1947 unsigned int drto_div;
1948 unsigned int drto_ms;
1949
1950 drto_clks = mci_readl(host, TMOUT) >> 8;
1951 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
1952 if (drto_div == 0)
1953 drto_div = 1;
1954
1955 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
1956 host->bus_hz);
1957
1958 /* add a bit spare time */
1959 drto_ms += 10;
1960
1961 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1962 }
1963
1964 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1965 {
1966 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1967 return false;
1968
1969 /*
1970 * Really be certain that the timer has stopped. This is a bit of
1971 * paranoia and could only really happen if we had really bad
1972 * interrupt latency and the interrupt routine and timeout were
1973 * running concurrently so that the del_timer() in the interrupt
1974 * handler couldn't run.
1975 */
1976 WARN_ON(del_timer_sync(&host->cto_timer));
1977 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1978
1979 return true;
1980 }
1981
1982 static void dw_mci_tasklet_func(unsigned long priv)
1983 {
1984 struct dw_mci *host = (struct dw_mci *)priv;
1985 struct mmc_data *data;
1986 struct mmc_command *cmd;
1987 struct mmc_request *mrq;
1988 enum dw_mci_state state;
1989 enum dw_mci_state prev_state;
1990 unsigned int err;
1991
1992 spin_lock(&host->lock);
1993
1994 state = host->state;
1995 data = host->data;
1996 mrq = host->mrq;
1997
1998 do {
1999 prev_state = state;
2000
2001 switch (state) {
2002 case STATE_IDLE:
2003 case STATE_WAITING_CMD11_DONE:
2004 break;
2005
2006 case STATE_SENDING_CMD11:
2007 case STATE_SENDING_CMD:
2008 if (!dw_mci_clear_pending_cmd_complete(host))
2009 break;
2010
2011 cmd = host->cmd;
2012 host->cmd = NULL;
2013 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2014 err = dw_mci_command_complete(host, cmd);
2015 if (cmd == mrq->sbc && !err) {
2016 prev_state = state = STATE_SENDING_CMD;
2017 __dw_mci_start_request(host, host->slot,
2018 mrq->cmd);
2019 goto unlock;
2020 }
2021
2022 if (cmd->data && err) {
2023 /*
2024 * During UHS tuning sequence, sending the stop
2025 * command after the response CRC error would
2026 * throw the system into a confused state
2027 * causing all future tuning phases to report
2028 * failure.
2029 *
2030 * In such case controller will move into a data
2031 * transfer state after a response error or
2032 * response CRC error. Let's let that finish
2033 * before trying to send a stop, so we'll go to
2034 * STATE_SENDING_DATA.
2035 *
2036 * Although letting the data transfer take place
2037 * will waste a bit of time (we already know
2038 * the command was bad), it can't cause any
2039 * errors since it's possible it would have
2040 * taken place anyway if this tasklet got
2041 * delayed. Allowing the transfer to take place
2042 * avoids races and keeps things simple.
2043 */
2044 if ((err != -ETIMEDOUT) &&
2045 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
2046 state = STATE_SENDING_DATA;
2047 continue;
2048 }
2049
2050 dw_mci_stop_dma(host);
2051 send_stop_abort(host, data);
2052 state = STATE_SENDING_STOP;
2053 break;
2054 }
2055
2056 if (!cmd->data || err) {
2057 dw_mci_request_end(host, mrq);
2058 goto unlock;
2059 }
2060
2061 prev_state = state = STATE_SENDING_DATA;
2062 /* fall through */
2063
2064 case STATE_SENDING_DATA:
2065 /*
2066 * We could get a data error and never a transfer
2067 * complete so we'd better check for it here.
2068 *
2069 * Note that we don't really care if we also got a
2070 * transfer complete; stopping the DMA and sending an
2071 * abort won't hurt.
2072 */
2073 if (test_and_clear_bit(EVENT_DATA_ERROR,
2074 &host->pending_events)) {
2075 dw_mci_stop_dma(host);
2076 if (!(host->data_status & (SDMMC_INT_DRTO |
2077 SDMMC_INT_EBE)))
2078 send_stop_abort(host, data);
2079 state = STATE_DATA_ERROR;
2080 break;
2081 }
2082
2083 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2084 &host->pending_events)) {
2085 /*
2086 * If all data-related interrupts don't come
2087 * within the given time in reading data state.
2088 */
2089 if (host->dir_status == DW_MCI_RECV_STATUS)
2090 dw_mci_set_drto(host);
2091 break;
2092 }
2093
2094 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2095
2096 /*
2097 * Handle an EVENT_DATA_ERROR that might have shown up
2098 * before the transfer completed. This might not have
2099 * been caught by the check above because the interrupt
2100 * could have gone off between the previous check and
2101 * the check for transfer complete.
2102 *
2103 * Technically this ought not be needed assuming we
2104 * get a DATA_COMPLETE eventually (we'll notice the
2105 * error and end the request), but it shouldn't hurt.
2106 *
2107 * This has the advantage of sending the stop command.
2108 */
2109 if (test_and_clear_bit(EVENT_DATA_ERROR,
2110 &host->pending_events)) {
2111 dw_mci_stop_dma(host);
2112 if (!(host->data_status & (SDMMC_INT_DRTO |
2113 SDMMC_INT_EBE)))
2114 send_stop_abort(host, data);
2115 state = STATE_DATA_ERROR;
2116 break;
2117 }
2118 prev_state = state = STATE_DATA_BUSY;
2119
2120 /* fall through */
2121
2122 case STATE_DATA_BUSY:
2123 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2124 &host->pending_events)) {
2125 /*
2126 * If data error interrupt comes but data over
2127 * interrupt doesn't come within the given time.
2128 * in reading data state.
2129 */
2130 if (host->dir_status == DW_MCI_RECV_STATUS)
2131 dw_mci_set_drto(host);
2132 break;
2133 }
2134
2135 host->data = NULL;
2136 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2137 err = dw_mci_data_complete(host, data);
2138
2139 if (!err) {
2140 if (!data->stop || mrq->sbc) {
2141 if (mrq->sbc && data->stop)
2142 data->stop->error = 0;
2143 dw_mci_request_end(host, mrq);
2144 goto unlock;
2145 }
2146
2147 /* stop command for open-ended transfer*/
2148 if (data->stop)
2149 send_stop_abort(host, data);
2150 } else {
2151 /*
2152 * If we don't have a command complete now we'll
2153 * never get one since we just reset everything;
2154 * better end the request.
2155 *
2156 * If we do have a command complete we'll fall
2157 * through to the SENDING_STOP command and
2158 * everything will be peachy keen.
2159 */
2160 if (!test_bit(EVENT_CMD_COMPLETE,
2161 &host->pending_events)) {
2162 host->cmd = NULL;
2163 dw_mci_request_end(host, mrq);
2164 goto unlock;
2165 }
2166 }
2167
2168 /*
2169 * If err has non-zero,
2170 * stop-abort command has been already issued.
2171 */
2172 prev_state = state = STATE_SENDING_STOP;
2173
2174 /* fall through */
2175
2176 case STATE_SENDING_STOP:
2177 if (!dw_mci_clear_pending_cmd_complete(host))
2178 break;
2179
2180 /* CMD error in data command */
2181 if (mrq->cmd->error && mrq->data)
2182 dw_mci_reset(host);
2183
2184 host->cmd = NULL;
2185 host->data = NULL;
2186
2187 if (!mrq->sbc && mrq->stop)
2188 dw_mci_command_complete(host, mrq->stop);
2189 else
2190 host->cmd_status = 0;
2191
2192 dw_mci_request_end(host, mrq);
2193 goto unlock;
2194
2195 case STATE_DATA_ERROR:
2196 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2197 &host->pending_events))
2198 break;
2199
2200 state = STATE_DATA_BUSY;
2201 break;
2202 }
2203 } while (state != prev_state);
2204
2205 host->state = state;
2206 unlock:
2207 spin_unlock(&host->lock);
2208
2209 }
2210
2211 /* push final bytes to part_buf, only use during push */
2212 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2213 {
2214 memcpy((void *)&host->part_buf, buf, cnt);
2215 host->part_buf_count = cnt;
2216 }
2217
2218 /* append bytes to part_buf, only use during push */
2219 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2220 {
2221 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2222 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2223 host->part_buf_count += cnt;
2224 return cnt;
2225 }
2226
2227 /* pull first bytes from part_buf, only use during pull */
2228 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2229 {
2230 cnt = min_t(int, cnt, host->part_buf_count);
2231 if (cnt) {
2232 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2233 cnt);
2234 host->part_buf_count -= cnt;
2235 host->part_buf_start += cnt;
2236 }
2237 return cnt;
2238 }
2239
2240 /* pull final bytes from the part_buf, assuming it's just been filled */
2241 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2242 {
2243 memcpy(buf, &host->part_buf, cnt);
2244 host->part_buf_start = cnt;
2245 host->part_buf_count = (1 << host->data_shift) - cnt;
2246 }
2247
2248 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2249 {
2250 struct mmc_data *data = host->data;
2251 int init_cnt = cnt;
2252
2253 /* try and push anything in the part_buf */
2254 if (unlikely(host->part_buf_count)) {
2255 int len = dw_mci_push_part_bytes(host, buf, cnt);
2256
2257 buf += len;
2258 cnt -= len;
2259 if (host->part_buf_count == 2) {
2260 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2261 host->part_buf_count = 0;
2262 }
2263 }
2264 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2265 if (unlikely((unsigned long)buf & 0x1)) {
2266 while (cnt >= 2) {
2267 u16 aligned_buf[64];
2268 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2269 int items = len >> 1;
2270 int i;
2271 /* memcpy from input buffer into aligned buffer */
2272 memcpy(aligned_buf, buf, len);
2273 buf += len;
2274 cnt -= len;
2275 /* push data from aligned buffer into fifo */
2276 for (i = 0; i < items; ++i)
2277 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2278 }
2279 } else
2280 #endif
2281 {
2282 u16 *pdata = buf;
2283
2284 for (; cnt >= 2; cnt -= 2)
2285 mci_fifo_writew(host->fifo_reg, *pdata++);
2286 buf = pdata;
2287 }
2288 /* put anything remaining in the part_buf */
2289 if (cnt) {
2290 dw_mci_set_part_bytes(host, buf, cnt);
2291 /* Push data if we have reached the expected data length */
2292 if ((data->bytes_xfered + init_cnt) ==
2293 (data->blksz * data->blocks))
2294 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2295 }
2296 }
2297
2298 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2299 {
2300 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2301 if (unlikely((unsigned long)buf & 0x1)) {
2302 while (cnt >= 2) {
2303 /* pull data from fifo into aligned buffer */
2304 u16 aligned_buf[64];
2305 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2306 int items = len >> 1;
2307 int i;
2308
2309 for (i = 0; i < items; ++i)
2310 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2311 /* memcpy from aligned buffer into output buffer */
2312 memcpy(buf, aligned_buf, len);
2313 buf += len;
2314 cnt -= len;
2315 }
2316 } else
2317 #endif
2318 {
2319 u16 *pdata = buf;
2320
2321 for (; cnt >= 2; cnt -= 2)
2322 *pdata++ = mci_fifo_readw(host->fifo_reg);
2323 buf = pdata;
2324 }
2325 if (cnt) {
2326 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2327 dw_mci_pull_final_bytes(host, buf, cnt);
2328 }
2329 }
2330
2331 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2332 {
2333 struct mmc_data *data = host->data;
2334 int init_cnt = cnt;
2335
2336 /* try and push anything in the part_buf */
2337 if (unlikely(host->part_buf_count)) {
2338 int len = dw_mci_push_part_bytes(host, buf, cnt);
2339
2340 buf += len;
2341 cnt -= len;
2342 if (host->part_buf_count == 4) {
2343 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2344 host->part_buf_count = 0;
2345 }
2346 }
2347 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2348 if (unlikely((unsigned long)buf & 0x3)) {
2349 while (cnt >= 4) {
2350 u32 aligned_buf[32];
2351 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2352 int items = len >> 2;
2353 int i;
2354 /* memcpy from input buffer into aligned buffer */
2355 memcpy(aligned_buf, buf, len);
2356 buf += len;
2357 cnt -= len;
2358 /* push data from aligned buffer into fifo */
2359 for (i = 0; i < items; ++i)
2360 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2361 }
2362 } else
2363 #endif
2364 {
2365 u32 *pdata = buf;
2366
2367 for (; cnt >= 4; cnt -= 4)
2368 mci_fifo_writel(host->fifo_reg, *pdata++);
2369 buf = pdata;
2370 }
2371 /* put anything remaining in the part_buf */
2372 if (cnt) {
2373 dw_mci_set_part_bytes(host, buf, cnt);
2374 /* Push data if we have reached the expected data length */
2375 if ((data->bytes_xfered + init_cnt) ==
2376 (data->blksz * data->blocks))
2377 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2378 }
2379 }
2380
2381 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2382 {
2383 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2384 if (unlikely((unsigned long)buf & 0x3)) {
2385 while (cnt >= 4) {
2386 /* pull data from fifo into aligned buffer */
2387 u32 aligned_buf[32];
2388 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2389 int items = len >> 2;
2390 int i;
2391
2392 for (i = 0; i < items; ++i)
2393 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2394 /* memcpy from aligned buffer into output buffer */
2395 memcpy(buf, aligned_buf, len);
2396 buf += len;
2397 cnt -= len;
2398 }
2399 } else
2400 #endif
2401 {
2402 u32 *pdata = buf;
2403
2404 for (; cnt >= 4; cnt -= 4)
2405 *pdata++ = mci_fifo_readl(host->fifo_reg);
2406 buf = pdata;
2407 }
2408 if (cnt) {
2409 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2410 dw_mci_pull_final_bytes(host, buf, cnt);
2411 }
2412 }
2413
2414 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2415 {
2416 struct mmc_data *data = host->data;
2417 int init_cnt = cnt;
2418
2419 /* try and push anything in the part_buf */
2420 if (unlikely(host->part_buf_count)) {
2421 int len = dw_mci_push_part_bytes(host, buf, cnt);
2422
2423 buf += len;
2424 cnt -= len;
2425
2426 if (host->part_buf_count == 8) {
2427 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2428 host->part_buf_count = 0;
2429 }
2430 }
2431 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2432 if (unlikely((unsigned long)buf & 0x7)) {
2433 while (cnt >= 8) {
2434 u64 aligned_buf[16];
2435 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2436 int items = len >> 3;
2437 int i;
2438 /* memcpy from input buffer into aligned buffer */
2439 memcpy(aligned_buf, buf, len);
2440 buf += len;
2441 cnt -= len;
2442 /* push data from aligned buffer into fifo */
2443 for (i = 0; i < items; ++i)
2444 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2445 }
2446 } else
2447 #endif
2448 {
2449 u64 *pdata = buf;
2450
2451 for (; cnt >= 8; cnt -= 8)
2452 mci_fifo_writeq(host->fifo_reg, *pdata++);
2453 buf = pdata;
2454 }
2455 /* put anything remaining in the part_buf */
2456 if (cnt) {
2457 dw_mci_set_part_bytes(host, buf, cnt);
2458 /* Push data if we have reached the expected data length */
2459 if ((data->bytes_xfered + init_cnt) ==
2460 (data->blksz * data->blocks))
2461 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2462 }
2463 }
2464
2465 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2466 {
2467 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2468 if (unlikely((unsigned long)buf & 0x7)) {
2469 while (cnt >= 8) {
2470 /* pull data from fifo into aligned buffer */
2471 u64 aligned_buf[16];
2472 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2473 int items = len >> 3;
2474 int i;
2475
2476 for (i = 0; i < items; ++i)
2477 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2478
2479 /* memcpy from aligned buffer into output buffer */
2480 memcpy(buf, aligned_buf, len);
2481 buf += len;
2482 cnt -= len;
2483 }
2484 } else
2485 #endif
2486 {
2487 u64 *pdata = buf;
2488
2489 for (; cnt >= 8; cnt -= 8)
2490 *pdata++ = mci_fifo_readq(host->fifo_reg);
2491 buf = pdata;
2492 }
2493 if (cnt) {
2494 host->part_buf = mci_fifo_readq(host->fifo_reg);
2495 dw_mci_pull_final_bytes(host, buf, cnt);
2496 }
2497 }
2498
2499 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2500 {
2501 int len;
2502
2503 /* get remaining partial bytes */
2504 len = dw_mci_pull_part_bytes(host, buf, cnt);
2505 if (unlikely(len == cnt))
2506 return;
2507 buf += len;
2508 cnt -= len;
2509
2510 /* get the rest of the data */
2511 host->pull_data(host, buf, cnt);
2512 }
2513
2514 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2515 {
2516 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2517 void *buf;
2518 unsigned int offset;
2519 struct mmc_data *data = host->data;
2520 int shift = host->data_shift;
2521 u32 status;
2522 unsigned int len;
2523 unsigned int remain, fcnt;
2524
2525 do {
2526 if (!sg_miter_next(sg_miter))
2527 goto done;
2528
2529 host->sg = sg_miter->piter.sg;
2530 buf = sg_miter->addr;
2531 remain = sg_miter->length;
2532 offset = 0;
2533
2534 do {
2535 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2536 << shift) + host->part_buf_count;
2537 len = min(remain, fcnt);
2538 if (!len)
2539 break;
2540 dw_mci_pull_data(host, (void *)(buf + offset), len);
2541 data->bytes_xfered += len;
2542 offset += len;
2543 remain -= len;
2544 } while (remain);
2545
2546 sg_miter->consumed = offset;
2547 status = mci_readl(host, MINTSTS);
2548 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2549 /* if the RXDR is ready read again */
2550 } while ((status & SDMMC_INT_RXDR) ||
2551 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2552
2553 if (!remain) {
2554 if (!sg_miter_next(sg_miter))
2555 goto done;
2556 sg_miter->consumed = 0;
2557 }
2558 sg_miter_stop(sg_miter);
2559 return;
2560
2561 done:
2562 sg_miter_stop(sg_miter);
2563 host->sg = NULL;
2564 smp_wmb(); /* drain writebuffer */
2565 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2566 }
2567
2568 static void dw_mci_write_data_pio(struct dw_mci *host)
2569 {
2570 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2571 void *buf;
2572 unsigned int offset;
2573 struct mmc_data *data = host->data;
2574 int shift = host->data_shift;
2575 u32 status;
2576 unsigned int len;
2577 unsigned int fifo_depth = host->fifo_depth;
2578 unsigned int remain, fcnt;
2579
2580 do {
2581 if (!sg_miter_next(sg_miter))
2582 goto done;
2583
2584 host->sg = sg_miter->piter.sg;
2585 buf = sg_miter->addr;
2586 remain = sg_miter->length;
2587 offset = 0;
2588
2589 do {
2590 fcnt = ((fifo_depth -
2591 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2592 << shift) - host->part_buf_count;
2593 len = min(remain, fcnt);
2594 if (!len)
2595 break;
2596 host->push_data(host, (void *)(buf + offset), len);
2597 data->bytes_xfered += len;
2598 offset += len;
2599 remain -= len;
2600 } while (remain);
2601
2602 sg_miter->consumed = offset;
2603 status = mci_readl(host, MINTSTS);
2604 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2605 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2606
2607 if (!remain) {
2608 if (!sg_miter_next(sg_miter))
2609 goto done;
2610 sg_miter->consumed = 0;
2611 }
2612 sg_miter_stop(sg_miter);
2613 return;
2614
2615 done:
2616 sg_miter_stop(sg_miter);
2617 host->sg = NULL;
2618 smp_wmb(); /* drain writebuffer */
2619 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2620 }
2621
2622 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2623 {
2624 del_timer(&host->cto_timer);
2625
2626 if (!host->cmd_status)
2627 host->cmd_status = status;
2628
2629 smp_wmb(); /* drain writebuffer */
2630
2631 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2632 tasklet_schedule(&host->tasklet);
2633 }
2634
2635 static void dw_mci_handle_cd(struct dw_mci *host)
2636 {
2637 struct dw_mci_slot *slot = host->slot;
2638
2639 if (slot->mmc->ops->card_event)
2640 slot->mmc->ops->card_event(slot->mmc);
2641 mmc_detect_change(slot->mmc,
2642 msecs_to_jiffies(host->pdata->detect_delay_ms));
2643 }
2644
2645 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2646 {
2647 struct dw_mci *host = dev_id;
2648 u32 pending;
2649 struct dw_mci_slot *slot = host->slot;
2650 unsigned long irqflags;
2651
2652 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2653
2654 if (pending) {
2655 /* Check volt switch first, since it can look like an error */
2656 if ((host->state == STATE_SENDING_CMD11) &&
2657 (pending & SDMMC_INT_VOLT_SWITCH)) {
2658 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2659 pending &= ~SDMMC_INT_VOLT_SWITCH;
2660
2661 /*
2662 * Hold the lock; we know cmd11_timer can't be kicked
2663 * off after the lock is released, so safe to delete.
2664 */
2665 spin_lock_irqsave(&host->irq_lock, irqflags);
2666 dw_mci_cmd_interrupt(host, pending);
2667 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2668
2669 del_timer(&host->cmd11_timer);
2670 }
2671
2672 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2673 spin_lock_irqsave(&host->irq_lock, irqflags);
2674
2675 del_timer(&host->cto_timer);
2676 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2677 host->cmd_status = pending;
2678 smp_wmb(); /* drain writebuffer */
2679 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2680
2681 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2682 }
2683
2684 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2685 /* if there is an error report DATA_ERROR */
2686 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2687 host->data_status = pending;
2688 smp_wmb(); /* drain writebuffer */
2689 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2690 tasklet_schedule(&host->tasklet);
2691 }
2692
2693 if (pending & SDMMC_INT_DATA_OVER) {
2694 del_timer(&host->dto_timer);
2695
2696 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2697 if (!host->data_status)
2698 host->data_status = pending;
2699 smp_wmb(); /* drain writebuffer */
2700 if (host->dir_status == DW_MCI_RECV_STATUS) {
2701 if (host->sg != NULL)
2702 dw_mci_read_data_pio(host, true);
2703 }
2704 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2705 tasklet_schedule(&host->tasklet);
2706 }
2707
2708 if (pending & SDMMC_INT_RXDR) {
2709 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2710 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2711 dw_mci_read_data_pio(host, false);
2712 }
2713
2714 if (pending & SDMMC_INT_TXDR) {
2715 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2716 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2717 dw_mci_write_data_pio(host);
2718 }
2719
2720 if (pending & SDMMC_INT_CMD_DONE) {
2721 spin_lock_irqsave(&host->irq_lock, irqflags);
2722
2723 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2724 dw_mci_cmd_interrupt(host, pending);
2725
2726 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2727 }
2728
2729 if (pending & SDMMC_INT_CD) {
2730 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2731 dw_mci_handle_cd(host);
2732 }
2733
2734 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2735 mci_writel(host, RINTSTS,
2736 SDMMC_INT_SDIO(slot->sdio_id));
2737 __dw_mci_enable_sdio_irq(slot, 0);
2738 sdio_signal_irq(slot->mmc);
2739 }
2740
2741 }
2742
2743 if (host->use_dma != TRANS_MODE_IDMAC)
2744 return IRQ_HANDLED;
2745
2746 /* Handle IDMA interrupts */
2747 if (host->dma_64bit_address == 1) {
2748 pending = mci_readl(host, IDSTS64);
2749 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2750 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2751 SDMMC_IDMAC_INT_RI);
2752 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2753 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2754 host->dma_ops->complete((void *)host);
2755 }
2756 } else {
2757 pending = mci_readl(host, IDSTS);
2758 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2759 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2760 SDMMC_IDMAC_INT_RI);
2761 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2762 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2763 host->dma_ops->complete((void *)host);
2764 }
2765 }
2766
2767 return IRQ_HANDLED;
2768 }
2769
2770 static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
2771 {
2772 struct dw_mci *host = slot->host;
2773 const struct dw_mci_drv_data *drv_data = host->drv_data;
2774 struct mmc_host *mmc = slot->mmc;
2775 int ctrl_id;
2776
2777 if (host->pdata->caps)
2778 mmc->caps = host->pdata->caps;
2779
2780 /*
2781 * Support MMC_CAP_ERASE by default.
2782 * It needs to use trim/discard/erase commands.
2783 */
2784 mmc->caps |= MMC_CAP_ERASE;
2785
2786 if (host->pdata->pm_caps)
2787 mmc->pm_caps = host->pdata->pm_caps;
2788
2789 if (host->dev->of_node) {
2790 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2791 if (ctrl_id < 0)
2792 ctrl_id = 0;
2793 } else {
2794 ctrl_id = to_platform_device(host->dev)->id;
2795 }
2796
2797 if (drv_data && drv_data->caps) {
2798 if (ctrl_id >= drv_data->num_caps) {
2799 dev_err(host->dev, "invalid controller id %d\n",
2800 ctrl_id);
2801 return -EINVAL;
2802 }
2803 mmc->caps |= drv_data->caps[ctrl_id];
2804 }
2805
2806 if (host->pdata->caps2)
2807 mmc->caps2 = host->pdata->caps2;
2808
2809 /* Process SDIO IRQs through the sdio_irq_work. */
2810 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2811 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2812
2813 return 0;
2814 }
2815
2816 static int dw_mci_init_slot(struct dw_mci *host)
2817 {
2818 struct mmc_host *mmc;
2819 struct dw_mci_slot *slot;
2820 int ret;
2821 u32 freq[2];
2822
2823 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2824 if (!mmc)
2825 return -ENOMEM;
2826
2827 slot = mmc_priv(mmc);
2828 slot->id = 0;
2829 slot->sdio_id = host->sdio_id0 + slot->id;
2830 slot->mmc = mmc;
2831 slot->host = host;
2832 host->slot = slot;
2833
2834 mmc->ops = &dw_mci_ops;
2835 if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2836 freq, 2)) {
2837 mmc->f_min = DW_MCI_FREQ_MIN;
2838 mmc->f_max = DW_MCI_FREQ_MAX;
2839 } else {
2840 dev_info(host->dev,
2841 "'clock-freq-min-max' property was deprecated.\n");
2842 mmc->f_min = freq[0];
2843 mmc->f_max = freq[1];
2844 }
2845
2846 /*if there are external regulators, get them*/
2847 ret = mmc_regulator_get_supply(mmc);
2848 if (ret == -EPROBE_DEFER)
2849 goto err_host_allocated;
2850
2851 if (!mmc->ocr_avail)
2852 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2853
2854 ret = mmc_of_parse(mmc);
2855 if (ret)
2856 goto err_host_allocated;
2857
2858 ret = dw_mci_init_slot_caps(slot);
2859 if (ret)
2860 goto err_host_allocated;
2861
2862 /* Useful defaults if platform data is unset. */
2863 if (host->use_dma == TRANS_MODE_IDMAC) {
2864 mmc->max_segs = host->ring_size;
2865 mmc->max_blk_size = 65535;
2866 mmc->max_seg_size = 0x1000;
2867 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2868 mmc->max_blk_count = mmc->max_req_size / 512;
2869 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2870 mmc->max_segs = 64;
2871 mmc->max_blk_size = 65535;
2872 mmc->max_blk_count = 65535;
2873 mmc->max_req_size =
2874 mmc->max_blk_size * mmc->max_blk_count;
2875 mmc->max_seg_size = mmc->max_req_size;
2876 } else {
2877 /* TRANS_MODE_PIO */
2878 mmc->max_segs = 64;
2879 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2880 mmc->max_blk_count = 512;
2881 mmc->max_req_size = mmc->max_blk_size *
2882 mmc->max_blk_count;
2883 mmc->max_seg_size = mmc->max_req_size;
2884 }
2885
2886 dw_mci_get_cd(mmc);
2887
2888 ret = mmc_add_host(mmc);
2889 if (ret)
2890 goto err_host_allocated;
2891
2892 #if defined(CONFIG_DEBUG_FS)
2893 dw_mci_init_debugfs(slot);
2894 #endif
2895
2896 return 0;
2897
2898 err_host_allocated:
2899 mmc_free_host(mmc);
2900 return ret;
2901 }
2902
2903 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2904 {
2905 /* Debugfs stuff is cleaned up by mmc core */
2906 mmc_remove_host(slot->mmc);
2907 slot->host->slot = NULL;
2908 mmc_free_host(slot->mmc);
2909 }
2910
2911 static void dw_mci_init_dma(struct dw_mci *host)
2912 {
2913 int addr_config;
2914 struct device *dev = host->dev;
2915
2916 /*
2917 * Check tansfer mode from HCON[17:16]
2918 * Clear the ambiguous description of dw_mmc databook:
2919 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2920 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2921 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2922 * 2b'11: Non DW DMA Interface -> pio only
2923 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2924 * simpler request/acknowledge handshake mechanism and both of them
2925 * are regarded as external dma master for dw_mmc.
2926 */
2927 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2928 if (host->use_dma == DMA_INTERFACE_IDMA) {
2929 host->use_dma = TRANS_MODE_IDMAC;
2930 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2931 host->use_dma == DMA_INTERFACE_GDMA) {
2932 host->use_dma = TRANS_MODE_EDMAC;
2933 } else {
2934 goto no_dma;
2935 }
2936
2937 /* Determine which DMA interface to use */
2938 if (host->use_dma == TRANS_MODE_IDMAC) {
2939 /*
2940 * Check ADDR_CONFIG bit in HCON to find
2941 * IDMAC address bus width
2942 */
2943 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2944
2945 if (addr_config == 1) {
2946 /* host supports IDMAC in 64-bit address mode */
2947 host->dma_64bit_address = 1;
2948 dev_info(host->dev,
2949 "IDMAC supports 64-bit address mode.\n");
2950 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2951 dma_set_coherent_mask(host->dev,
2952 DMA_BIT_MASK(64));
2953 } else {
2954 /* host supports IDMAC in 32-bit address mode */
2955 host->dma_64bit_address = 0;
2956 dev_info(host->dev,
2957 "IDMAC supports 32-bit address mode.\n");
2958 }
2959
2960 /* Alloc memory for sg translation */
2961 host->sg_cpu = dmam_alloc_coherent(host->dev,
2962 DESC_RING_BUF_SZ,
2963 &host->sg_dma, GFP_KERNEL);
2964 if (!host->sg_cpu) {
2965 dev_err(host->dev,
2966 "%s: could not alloc DMA memory\n",
2967 __func__);
2968 goto no_dma;
2969 }
2970
2971 host->dma_ops = &dw_mci_idmac_ops;
2972 dev_info(host->dev, "Using internal DMA controller.\n");
2973 } else {
2974 /* TRANS_MODE_EDMAC: check dma bindings again */
2975 if ((device_property_read_string_array(dev, "dma-names",
2976 NULL, 0) < 0) ||
2977 !device_property_present(dev, "dmas")) {
2978 goto no_dma;
2979 }
2980 host->dma_ops = &dw_mci_edmac_ops;
2981 dev_info(host->dev, "Using external DMA controller.\n");
2982 }
2983
2984 if (host->dma_ops->init && host->dma_ops->start &&
2985 host->dma_ops->stop && host->dma_ops->cleanup) {
2986 if (host->dma_ops->init(host)) {
2987 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2988 __func__);
2989 goto no_dma;
2990 }
2991 } else {
2992 dev_err(host->dev, "DMA initialization not found.\n");
2993 goto no_dma;
2994 }
2995
2996 return;
2997
2998 no_dma:
2999 dev_info(host->dev, "Using PIO mode.\n");
3000 host->use_dma = TRANS_MODE_PIO;
3001 }
3002
3003 static void dw_mci_cmd11_timer(unsigned long arg)
3004 {
3005 struct dw_mci *host = (struct dw_mci *)arg;
3006
3007 if (host->state != STATE_SENDING_CMD11) {
3008 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
3009 return;
3010 }
3011
3012 host->cmd_status = SDMMC_INT_RTO;
3013 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3014 tasklet_schedule(&host->tasklet);
3015 }
3016
3017 static void dw_mci_cto_timer(unsigned long arg)
3018 {
3019 struct dw_mci *host = (struct dw_mci *)arg;
3020 unsigned long irqflags;
3021 u32 pending;
3022
3023 spin_lock_irqsave(&host->irq_lock, irqflags);
3024
3025 /*
3026 * If somehow we have very bad interrupt latency it's remotely possible
3027 * that the timer could fire while the interrupt is still pending or
3028 * while the interrupt is midway through running. Let's be paranoid
3029 * and detect those two cases. Note that this is paranoia is somewhat
3030 * justified because in this function we don't actually cancel the
3031 * pending command in the controller--we just assume it will never come.
3032 */
3033 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3034 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3035 /* The interrupt should fire; no need to act but we can warn */
3036 dev_warn(host->dev, "Unexpected interrupt latency\n");
3037 goto exit;
3038 }
3039 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3040 /* Presumably interrupt handler couldn't delete the timer */
3041 dev_warn(host->dev, "CTO timeout when already completed\n");
3042 goto exit;
3043 }
3044
3045 /*
3046 * Continued paranoia to make sure we're in the state we expect.
3047 * This paranoia isn't really justified but it seems good to be safe.
3048 */
3049 switch (host->state) {
3050 case STATE_SENDING_CMD11:
3051 case STATE_SENDING_CMD:
3052 case STATE_SENDING_STOP:
3053 /*
3054 * If CMD_DONE interrupt does NOT come in sending command
3055 * state, we should notify the driver to terminate current
3056 * transfer and report a command timeout to the core.
3057 */
3058 host->cmd_status = SDMMC_INT_RTO;
3059 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3060 tasklet_schedule(&host->tasklet);
3061 break;
3062 default:
3063 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3064 host->state);
3065 break;
3066 }
3067
3068 exit:
3069 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3070 }
3071
3072 static void dw_mci_dto_timer(unsigned long arg)
3073 {
3074 struct dw_mci *host = (struct dw_mci *)arg;
3075
3076 switch (host->state) {
3077 case STATE_SENDING_DATA:
3078 case STATE_DATA_BUSY:
3079 /*
3080 * If DTO interrupt does NOT come in sending data state,
3081 * we should notify the driver to terminate current transfer
3082 * and report a data timeout to the core.
3083 */
3084 host->data_status = SDMMC_INT_DRTO;
3085 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3086 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3087 tasklet_schedule(&host->tasklet);
3088 break;
3089 default:
3090 break;
3091 }
3092 }
3093
3094 #ifdef CONFIG_OF
3095 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3096 {
3097 struct dw_mci_board *pdata;
3098 struct device *dev = host->dev;
3099 const struct dw_mci_drv_data *drv_data = host->drv_data;
3100 int ret;
3101 u32 clock_frequency;
3102
3103 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3104 if (!pdata)
3105 return ERR_PTR(-ENOMEM);
3106
3107 /* find reset controller when exist */
3108 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
3109 if (IS_ERR(pdata->rstc)) {
3110 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
3111 return ERR_PTR(-EPROBE_DEFER);
3112 }
3113
3114 /* find out number of slots supported */
3115 if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots))
3116 dev_info(dev, "'num-slots' was deprecated.\n");
3117
3118 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
3119 dev_info(dev,
3120 "fifo-depth property not found, using value of FIFOTH register as default\n");
3121
3122 device_property_read_u32(dev, "card-detect-delay",
3123 &pdata->detect_delay_ms);
3124
3125 device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3126
3127 if (device_property_present(dev, "fifo-watermark-aligned"))
3128 host->wm_aligned = true;
3129
3130 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3131 pdata->bus_hz = clock_frequency;
3132
3133 if (drv_data && drv_data->parse_dt) {
3134 ret = drv_data->parse_dt(host);
3135 if (ret)
3136 return ERR_PTR(ret);
3137 }
3138
3139 return pdata;
3140 }
3141
3142 #else /* CONFIG_OF */
3143 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3144 {
3145 return ERR_PTR(-EINVAL);
3146 }
3147 #endif /* CONFIG_OF */
3148
3149 static void dw_mci_enable_cd(struct dw_mci *host)
3150 {
3151 unsigned long irqflags;
3152 u32 temp;
3153
3154 /*
3155 * No need for CD if all slots have a non-error GPIO
3156 * as well as broken card detection is found.
3157 */
3158 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3159 return;
3160
3161 if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3162 spin_lock_irqsave(&host->irq_lock, irqflags);
3163 temp = mci_readl(host, INTMASK);
3164 temp |= SDMMC_INT_CD;
3165 mci_writel(host, INTMASK, temp);
3166 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3167 }
3168 }
3169
3170 int dw_mci_probe(struct dw_mci *host)
3171 {
3172 const struct dw_mci_drv_data *drv_data = host->drv_data;
3173 int width, i, ret = 0;
3174 u32 fifo_size;
3175
3176 if (!host->pdata) {
3177 host->pdata = dw_mci_parse_dt(host);
3178 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3179 return -EPROBE_DEFER;
3180 } else if (IS_ERR(host->pdata)) {
3181 dev_err(host->dev, "platform data not available\n");
3182 return -EINVAL;
3183 }
3184 }
3185
3186 host->biu_clk = devm_clk_get(host->dev, "biu");
3187 if (IS_ERR(host->biu_clk)) {
3188 dev_dbg(host->dev, "biu clock not available\n");
3189 } else {
3190 ret = clk_prepare_enable(host->biu_clk);
3191 if (ret) {
3192 dev_err(host->dev, "failed to enable biu clock\n");
3193 return ret;
3194 }
3195 }
3196
3197 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3198 if (IS_ERR(host->ciu_clk)) {
3199 dev_dbg(host->dev, "ciu clock not available\n");
3200 host->bus_hz = host->pdata->bus_hz;
3201 } else {
3202 ret = clk_prepare_enable(host->ciu_clk);
3203 if (ret) {
3204 dev_err(host->dev, "failed to enable ciu clock\n");
3205 goto err_clk_biu;
3206 }
3207
3208 if (host->pdata->bus_hz) {
3209 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3210 if (ret)
3211 dev_warn(host->dev,
3212 "Unable to set bus rate to %uHz\n",
3213 host->pdata->bus_hz);
3214 }
3215 host->bus_hz = clk_get_rate(host->ciu_clk);
3216 }
3217
3218 if (!host->bus_hz) {
3219 dev_err(host->dev,
3220 "Platform data must supply bus speed\n");
3221 ret = -ENODEV;
3222 goto err_clk_ciu;
3223 }
3224
3225 if (!IS_ERR(host->pdata->rstc)) {
3226 reset_control_assert(host->pdata->rstc);
3227 usleep_range(10, 50);
3228 reset_control_deassert(host->pdata->rstc);
3229 }
3230
3231 if (drv_data && drv_data->init) {
3232 ret = drv_data->init(host);
3233 if (ret) {
3234 dev_err(host->dev,
3235 "implementation specific init failed\n");
3236 goto err_clk_ciu;
3237 }
3238 }
3239
3240 setup_timer(&host->cmd11_timer,
3241 dw_mci_cmd11_timer, (unsigned long)host);
3242
3243 setup_timer(&host->cto_timer,
3244 dw_mci_cto_timer, (unsigned long)host);
3245
3246 setup_timer(&host->dto_timer,
3247 dw_mci_dto_timer, (unsigned long)host);
3248
3249 spin_lock_init(&host->lock);
3250 spin_lock_init(&host->irq_lock);
3251 INIT_LIST_HEAD(&host->queue);
3252
3253 /*
3254 * Get the host data width - this assumes that HCON has been set with
3255 * the correct values.
3256 */
3257 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3258 if (!i) {
3259 host->push_data = dw_mci_push_data16;
3260 host->pull_data = dw_mci_pull_data16;
3261 width = 16;
3262 host->data_shift = 1;
3263 } else if (i == 2) {
3264 host->push_data = dw_mci_push_data64;
3265 host->pull_data = dw_mci_pull_data64;
3266 width = 64;
3267 host->data_shift = 3;
3268 } else {
3269 /* Check for a reserved value, and warn if it is */
3270 WARN((i != 1),
3271 "HCON reports a reserved host data width!\n"
3272 "Defaulting to 32-bit access.\n");
3273 host->push_data = dw_mci_push_data32;
3274 host->pull_data = dw_mci_pull_data32;
3275 width = 32;
3276 host->data_shift = 2;
3277 }
3278
3279 /* Reset all blocks */
3280 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3281 ret = -ENODEV;
3282 goto err_clk_ciu;
3283 }
3284
3285 host->dma_ops = host->pdata->dma_ops;
3286 dw_mci_init_dma(host);
3287
3288 /* Clear the interrupts for the host controller */
3289 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3290 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3291
3292 /* Put in max timeout */
3293 mci_writel(host, TMOUT, 0xFFFFFFFF);
3294
3295 /*
3296 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3297 * Tx Mark = fifo_size / 2 DMA Size = 8
3298 */
3299 if (!host->pdata->fifo_depth) {
3300 /*
3301 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3302 * have been overwritten by the bootloader, just like we're
3303 * about to do, so if you know the value for your hardware, you
3304 * should put it in the platform data.
3305 */
3306 fifo_size = mci_readl(host, FIFOTH);
3307 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3308 } else {
3309 fifo_size = host->pdata->fifo_depth;
3310 }
3311 host->fifo_depth = fifo_size;
3312 host->fifoth_val =
3313 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3314 mci_writel(host, FIFOTH, host->fifoth_val);
3315
3316 /* disable clock to CIU */
3317 mci_writel(host, CLKENA, 0);
3318 mci_writel(host, CLKSRC, 0);
3319
3320 /*
3321 * In 2.40a spec, Data offset is changed.
3322 * Need to check the version-id and set data-offset for DATA register.
3323 */
3324 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3325 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3326
3327 if (host->data_addr_override)
3328 host->fifo_reg = host->regs + host->data_addr_override;
3329 else if (host->verid < DW_MMC_240A)
3330 host->fifo_reg = host->regs + DATA_OFFSET;
3331 else
3332 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3333
3334 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3335 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3336 host->irq_flags, "dw-mci", host);
3337 if (ret)
3338 goto err_dmaunmap;
3339
3340 /*
3341 * Enable interrupts for command done, data over, data empty,
3342 * receive ready and error such as transmit, receive timeout, crc error
3343 */
3344 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3345 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3346 DW_MCI_ERROR_FLAGS);
3347 /* Enable mci interrupt */
3348 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3349
3350 dev_info(host->dev,
3351 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3352 host->irq, width, fifo_size);
3353
3354 /* We need at least one slot to succeed */
3355 ret = dw_mci_init_slot(host);
3356 if (ret) {
3357 dev_dbg(host->dev, "slot %d init failed\n", i);
3358 goto err_dmaunmap;
3359 }
3360
3361 /* Now that slots are all setup, we can enable card detect */
3362 dw_mci_enable_cd(host);
3363
3364 return 0;
3365
3366 err_dmaunmap:
3367 if (host->use_dma && host->dma_ops->exit)
3368 host->dma_ops->exit(host);
3369
3370 if (!IS_ERR(host->pdata->rstc))
3371 reset_control_assert(host->pdata->rstc);
3372
3373 err_clk_ciu:
3374 clk_disable_unprepare(host->ciu_clk);
3375
3376 err_clk_biu:
3377 clk_disable_unprepare(host->biu_clk);
3378
3379 return ret;
3380 }
3381 EXPORT_SYMBOL(dw_mci_probe);
3382
3383 void dw_mci_remove(struct dw_mci *host)
3384 {
3385 dev_dbg(host->dev, "remove slot\n");
3386 if (host->slot)
3387 dw_mci_cleanup_slot(host->slot);
3388
3389 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3390 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3391
3392 /* disable clock to CIU */
3393 mci_writel(host, CLKENA, 0);
3394 mci_writel(host, CLKSRC, 0);
3395
3396 if (host->use_dma && host->dma_ops->exit)
3397 host->dma_ops->exit(host);
3398
3399 if (!IS_ERR(host->pdata->rstc))
3400 reset_control_assert(host->pdata->rstc);
3401
3402 clk_disable_unprepare(host->ciu_clk);
3403 clk_disable_unprepare(host->biu_clk);
3404 }
3405 EXPORT_SYMBOL(dw_mci_remove);
3406
3407
3408
3409 #ifdef CONFIG_PM
3410 int dw_mci_runtime_suspend(struct device *dev)
3411 {
3412 struct dw_mci *host = dev_get_drvdata(dev);
3413
3414 if (host->use_dma && host->dma_ops->exit)
3415 host->dma_ops->exit(host);
3416
3417 clk_disable_unprepare(host->ciu_clk);
3418
3419 if (host->slot &&
3420 (mmc_can_gpio_cd(host->slot->mmc) ||
3421 !mmc_card_is_removable(host->slot->mmc)))
3422 clk_disable_unprepare(host->biu_clk);
3423
3424 return 0;
3425 }
3426 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3427
3428 int dw_mci_runtime_resume(struct device *dev)
3429 {
3430 int ret = 0;
3431 struct dw_mci *host = dev_get_drvdata(dev);
3432
3433 if (host->slot &&
3434 (mmc_can_gpio_cd(host->slot->mmc) ||
3435 !mmc_card_is_removable(host->slot->mmc))) {
3436 ret = clk_prepare_enable(host->biu_clk);
3437 if (ret)
3438 return ret;
3439 }
3440
3441 ret = clk_prepare_enable(host->ciu_clk);
3442 if (ret)
3443 goto err;
3444
3445 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3446 clk_disable_unprepare(host->ciu_clk);
3447 ret = -ENODEV;
3448 goto err;
3449 }
3450
3451 if (host->use_dma && host->dma_ops->init)
3452 host->dma_ops->init(host);
3453
3454 /*
3455 * Restore the initial value at FIFOTH register
3456 * And Invalidate the prev_blksz with zero
3457 */
3458 mci_writel(host, FIFOTH, host->fifoth_val);
3459 host->prev_blksz = 0;
3460
3461 /* Put in max timeout */
3462 mci_writel(host, TMOUT, 0xFFFFFFFF);
3463
3464 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3465 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3466 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3467 DW_MCI_ERROR_FLAGS);
3468 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3469
3470
3471 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3472 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3473
3474 /* Force setup bus to guarantee available clock output */
3475 dw_mci_setup_bus(host->slot, true);
3476
3477 /* Now that slots are all setup, we can enable card detect */
3478 dw_mci_enable_cd(host);
3479
3480 return 0;
3481
3482 err:
3483 if (host->slot &&
3484 (mmc_can_gpio_cd(host->slot->mmc) ||
3485 !mmc_card_is_removable(host->slot->mmc)))
3486 clk_disable_unprepare(host->biu_clk);
3487
3488 return ret;
3489 }
3490 EXPORT_SYMBOL(dw_mci_runtime_resume);
3491 #endif /* CONFIG_PM */
3492
3493 static int __init dw_mci_init(void)
3494 {
3495 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3496 return 0;
3497 }
3498
3499 static void __exit dw_mci_exit(void)
3500 {
3501 }
3502
3503 module_init(dw_mci_init);
3504 module_exit(dw_mci_exit);
3505
3506 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3507 MODULE_AUTHOR("NXP Semiconductor VietNam");
3508 MODULE_AUTHOR("Imagination Technologies Ltd");
3509 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support