drivers/gpu/drm/imx/imx-tve.c

   1 /*
   2  * i.MX drm driver - Television Encoder (TVEv2)
   3  *
   4  * Copyright (C) 2013 Philipp Zabel, Pengutronix
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/component.h>
  19 #include <linux/module.h>
  20 #include <linux/i2c.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/videodev2.h>
  25 #include <drm/drmP.h>
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_fb_helper.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <video/imx-ipu-v3.h>
  30
  31 #include "imx-drm.h"
  32
  33 #define TVE_COM_CONF_REG        0x00
  34 #define TVE_TVDAC0_CONT_REG     0x28
  35 #define TVE_TVDAC1_CONT_REG     0x2c
  36 #define TVE_TVDAC2_CONT_REG     0x30
  37 #define TVE_CD_CONT_REG         0x34
  38 #define TVE_INT_CONT_REG        0x64
  39 #define TVE_STAT_REG            0x68
  40 #define TVE_TST_MODE_REG        0x6c
  41 #define TVE_MV_CONT_REG         0xdc
  42
  43 /* TVE_COM_CONF_REG */
  44 #define TVE_SYNC_CH_2_EN        BIT(22)
  45 #define TVE_SYNC_CH_1_EN        BIT(21)
  46 #define TVE_SYNC_CH_0_EN        BIT(20)
  47 #define TVE_TV_OUT_MODE_MASK    (0x7 << 12)
  48 #define TVE_TV_OUT_DISABLE      (0x0 << 12)
  49 #define TVE_TV_OUT_CVBS_0       (0x1 << 12)
  50 #define TVE_TV_OUT_CVBS_2       (0x2 << 12)
  51 #define TVE_TV_OUT_CVBS_0_2     (0x3 << 12)
  52 #define TVE_TV_OUT_SVIDEO_0_1   (0x4 << 12)
  53 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2   (0x5 << 12)
  54 #define TVE_TV_OUT_YPBPR        (0x6 << 12)
  55 #define TVE_TV_OUT_RGB          (0x7 << 12)
  56 #define TVE_TV_STAND_MASK       (0xf << 8)
  57 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
  58 #define TVE_P2I_CONV_EN         BIT(7)
  59 #define TVE_INP_VIDEO_FORM      BIT(6)
  60 #define TVE_INP_YCBCR_422       (0x0 << 6)
  61 #define TVE_INP_YCBCR_444       (0x1 << 6)
  62 #define TVE_DATA_SOURCE_MASK    (0x3 << 4)
  63 #define TVE_DATA_SOURCE_BUS1    (0x0 << 4)
  64 #define TVE_DATA_SOURCE_BUS2    (0x1 << 4)
  65 #define TVE_DATA_SOURCE_EXT     (0x2 << 4)
  66 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
  67 #define TVE_IPU_CLK_EN_OFS      3
  68 #define TVE_IPU_CLK_EN          BIT(3)
  69 #define TVE_DAC_SAMP_RATE_OFS   1
  70 #define TVE_DAC_SAMP_RATE_WIDTH 2
  71 #define TVE_DAC_SAMP_RATE_MASK  (0x3 << 1)
  72 #define TVE_DAC_FULL_RATE       (0x0 << 1)
  73 #define TVE_DAC_DIV2_RATE       (0x1 << 1)
  74 #define TVE_DAC_DIV4_RATE       (0x2 << 1)
  75 #define TVE_EN                  BIT(0)
  76
  77 /* TVE_TVDACx_CONT_REG */
  78 #define TVE_TVDAC_GAIN_MASK     (0x3f << 0)
  79
  80 /* TVE_CD_CONT_REG */
  81 #define TVE_CD_CH_2_SM_EN       BIT(22)
  82 #define TVE_CD_CH_1_SM_EN       BIT(21)
  83 #define TVE_CD_CH_0_SM_EN       BIT(20)
  84 #define TVE_CD_CH_2_LM_EN       BIT(18)
  85 #define TVE_CD_CH_1_LM_EN       BIT(17)
  86 #define TVE_CD_CH_0_LM_EN       BIT(16)
  87 #define TVE_CD_CH_2_REF_LVL     BIT(10)
  88 #define TVE_CD_CH_1_REF_LVL     BIT(9)
  89 #define TVE_CD_CH_0_REF_LVL     BIT(8)
  90 #define TVE_CD_EN               BIT(0)
  91
  92 /* TVE_INT_CONT_REG */
  93 #define TVE_FRAME_END_IEN       BIT(13)
  94 #define TVE_CD_MON_END_IEN      BIT(2)
  95 #define TVE_CD_SM_IEN           BIT(1)
  96 #define TVE_CD_LM_IEN           BIT(0)
  97
  98 /* TVE_TST_MODE_REG */
  99 #define TVE_TVDAC_TEST_MODE_MASK        (0x7 << 0)
 100
 101 #define IMX_TVE_DAC_VOLTAGE     2750000
 102
 103 enum {
 104         TVE_MODE_TVOUT,
 105         TVE_MODE_VGA,
 106 };
 107
 108 struct imx_tve {
 109         struct drm_connector connector;
 110         struct drm_encoder encoder;
 111         struct device *dev;
 112         spinlock_t lock;        /* register lock */
 113         bool enabled;
 114         int mode;
 115         int di_hsync_pin;
 116         int di_vsync_pin;
 117
 118         struct regmap *regmap;
 119         struct regulator *dac_reg;
 120         struct i2c_adapter *ddc;
 121         struct clk *clk;
 122         struct clk *di_sel_clk;
 123         struct clk_hw clk_hw_di;
 124         struct clk *di_clk;
 125 };
 126
 127 static inline struct imx_tve *con_to_tve(struct drm_connector *c)
 128 {
 129         return container_of(c, struct imx_tve, connector);
 130 }
 131
 132 static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
 133 {
 134         return container_of(e, struct imx_tve, encoder);
 135 }
 136
 137 static void tve_lock(void *__tve)
 138 __acquires(&tve->lock)
 139 {
 140         struct imx_tve *tve = __tve;
 141
 142         spin_lock(&tve->lock);
 143 }
 144
 145 static void tve_unlock(void *__tve)
 146 __releases(&tve->lock)
 147 {
 148         struct imx_tve *tve = __tve;
 149
 150         spin_unlock(&tve->lock);
 151 }
 152
 153 static void tve_enable(struct imx_tve *tve)
 154 {
 155         if (!tve->enabled) {
 156                 tve->enabled = true;
 157                 clk_prepare_enable(tve->clk);
 158                 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 159                                    TVE_EN, TVE_EN);
 160         }
 161
 162         /* clear interrupt status register */
 163         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
 164
 165         /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
 166         if (tve->mode == TVE_MODE_VGA)
 167                 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
 168         else
 169                 regmap_write(tve->regmap, TVE_INT_CONT_REG,
 170                              TVE_CD_SM_IEN |
 171                              TVE_CD_LM_IEN |
 172                              TVE_CD_MON_END_IEN);
 173 }
 174
 175 static void tve_disable(struct imx_tve *tve)
 176 {
 177         if (tve->enabled) {
 178                 tve->enabled = false;
 179                 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
 180                 clk_disable_unprepare(tve->clk);
 181         }
 182 }
 183
 184 static int tve_setup_tvout(struct imx_tve *tve)
 185 {
 186         return -ENOTSUPP;
 187 }
 188
 189 static int tve_setup_vga(struct imx_tve *tve)
 190 {
 191         unsigned int mask;
 192         unsigned int val;
 193         int ret;
 194
 195         /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
 196         ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
 197                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 198         if (ret)
 199                 return ret;
 200
 201         ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
 202                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 203         if (ret)
 204                 return ret;
 205
 206         ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
 207                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 208         if (ret)
 209                 return ret;
 210
 211         /* set configuration register */
 212         mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
 213         val  = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
 214         mask |= TVE_TV_STAND_MASK       | TVE_P2I_CONV_EN;
 215         val  |= TVE_TV_STAND_HD_1080P30 | 0;
 216         mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
 217         val  |= TVE_TV_OUT_RGB       | TVE_SYNC_CH_0_EN;
 218         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
 219         if (ret)
 220                 return ret;
 221
 222         /* set test mode (as documented) */
 223         return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
 224                                  TVE_TVDAC_TEST_MODE_MASK, 1);
 225 }
 226
 227 static int imx_tve_connector_get_modes(struct drm_connector *connector)
 228 {
 229         struct imx_tve *tve = con_to_tve(connector);
 230         struct edid *edid;
 231         int ret = 0;
 232
 233         if (!tve->ddc)
 234                 return 0;
 235
 236         edid = drm_get_edid(connector, tve->ddc);
 237         if (edid) {
 238                 drm_connector_update_edid_property(connector, edid);
 239                 ret = drm_add_edid_modes(connector, edid);
 240                 kfree(edid);
 241         }
 242
 243         return ret;
 244 }
 245
 246 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
 247                                         struct drm_display_mode *mode)
 248 {
 249         struct imx_tve *tve = con_to_tve(connector);
 250         unsigned long rate;
 251
 252         /* pixel clock with 2x oversampling */
 253         rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
 254         if (rate == mode->clock)
 255                 return MODE_OK;
 256
 257         /* pixel clock without oversampling */
 258         rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
 259         if (rate == mode->clock)
 260                 return MODE_OK;
 261
 262         dev_warn(tve->dev, "ignoring mode %dx%d\n",
 263                  mode->hdisplay, mode->vdisplay);
 264
 265         return MODE_BAD;
 266 }
 267
 268 static struct drm_encoder *imx_tve_connector_best_encoder(
 269                 struct drm_connector *connector)
 270 {
 271         struct imx_tve *tve = con_to_tve(connector);
 272
 273         return &tve->encoder;
 274 }
 275
 276 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
 277                                      struct drm_display_mode *orig_mode,
 278                                      struct drm_display_mode *mode)
 279 {
 280         struct imx_tve *tve = enc_to_tve(encoder);
 281         unsigned long rounded_rate;
 282         unsigned long rate;
 283         int div = 1;
 284         int ret;
 285
 286         /*
 287          * FIXME
 288          * we should try 4k * mode->clock first,
 289          * and enable 4x oversampling for lower resolutions
 290          */
 291         rate = 2000UL * mode->clock;
 292         clk_set_rate(tve->clk, rate);
 293         rounded_rate = clk_get_rate(tve->clk);
 294         if (rounded_rate >= rate)
 295                 div = 2;
 296         clk_set_rate(tve->di_clk, rounded_rate / div);
 297
 298         ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
 299         if (ret < 0) {
 300                 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
 301                         ret);
 302         }
 303
 304         regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 305                            TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
 306
 307         if (tve->mode == TVE_MODE_VGA)
 308                 ret = tve_setup_vga(tve);
 309         else
 310                 ret = tve_setup_tvout(tve);
 311         if (ret)
 312                 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
 313 }
 314
 315 static void imx_tve_encoder_enable(struct drm_encoder *encoder)
 316 {
 317         struct imx_tve *tve = enc_to_tve(encoder);
 318
 319         tve_enable(tve);
 320 }
 321
 322 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
 323 {
 324         struct imx_tve *tve = enc_to_tve(encoder);
 325
 326         tve_disable(tve);
 327 }
 328
 329 static int imx_tve_atomic_check(struct drm_encoder *encoder,
 330                                 struct drm_crtc_state *crtc_state,
 331                                 struct drm_connector_state *conn_state)
 332 {
 333         struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
 334         struct imx_tve *tve = enc_to_tve(encoder);
 335
 336         imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
 337         imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
 338         imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
 339
 340         return 0;
 341 }
 342
 343 static const struct drm_connector_funcs imx_tve_connector_funcs = {
 344         .fill_modes = drm_helper_probe_single_connector_modes,
 345         .destroy = imx_drm_connector_destroy,
 346         .reset = drm_atomic_helper_connector_reset,
 347         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 348         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 349 };
 350
 351 static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
 352         .get_modes = imx_tve_connector_get_modes,
 353         .best_encoder = imx_tve_connector_best_encoder,
 354         .mode_valid = imx_tve_connector_mode_valid,
 355 };
 356
 357 static const struct drm_encoder_funcs imx_tve_encoder_funcs = {
 358         .destroy = imx_drm_encoder_destroy,
 359 };
 360
 361 static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
 362         .mode_set = imx_tve_encoder_mode_set,
 363         .enable = imx_tve_encoder_enable,
 364         .disable = imx_tve_encoder_disable,
 365         .atomic_check = imx_tve_atomic_check,
 366 };
 367
 368 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
 369 {
 370         struct imx_tve *tve = data;
 371         unsigned int val;
 372
 373         regmap_read(tve->regmap, TVE_STAT_REG, &val);
 374
 375         /* clear interrupt status register */
 376         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
 377
 378         return IRQ_HANDLED;
 379 }
 380
 381 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
 382                                             unsigned long parent_rate)
 383 {
 384         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
 385         unsigned int val;
 386         int ret;
 387
 388         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
 389         if (ret < 0)
 390                 return 0;
 391
 392         switch (val & TVE_DAC_SAMP_RATE_MASK) {
 393         case TVE_DAC_DIV4_RATE:
 394                 return parent_rate / 4;
 395         case TVE_DAC_DIV2_RATE:
 396                 return parent_rate / 2;
 397         case TVE_DAC_FULL_RATE:
 398         default:
 399                 return parent_rate;
 400         }
 401
 402         return 0;
 403 }
 404
 405 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
 406                                   unsigned long *prate)
 407 {
 408         unsigned long div;
 409
 410         div = *prate / rate;
 411         if (div >= 4)
 412                 return *prate / 4;
 413         else if (div >= 2)
 414                 return *prate / 2;
 415         return *prate;
 416 }
 417
 418 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
 419                                unsigned long parent_rate)
 420 {
 421         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
 422         unsigned long div;
 423         u32 val;
 424         int ret;
 425
 426         div = parent_rate / rate;
 427         if (div >= 4)
 428                 val = TVE_DAC_DIV4_RATE;
 429         else if (div >= 2)
 430                 val = TVE_DAC_DIV2_RATE;
 431         else
 432                 val = TVE_DAC_FULL_RATE;
 433
 434         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 435                                  TVE_DAC_SAMP_RATE_MASK, val);
 436
 437         if (ret < 0) {
 438                 dev_err(tve->dev, "failed to set divider: %d\n", ret);
 439                 return ret;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static struct clk_ops clk_tve_di_ops = {
 446         .round_rate = clk_tve_di_round_rate,
 447         .set_rate = clk_tve_di_set_rate,
 448         .recalc_rate = clk_tve_di_recalc_rate,
 449 };
 450
 451 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
 452 {
 453         const char *tve_di_parent[1];
 454         struct clk_init_data init = {
 455                 .name = "tve_di",
 456                 .ops = &clk_tve_di_ops,
 457                 .num_parents = 1,
 458                 .flags = 0,
 459         };
 460
 461         tve_di_parent[0] = __clk_get_name(tve->clk);
 462         init.parent_names = (const char **)&tve_di_parent;
 463
 464         tve->clk_hw_di.init = &init;
 465         tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
 466         if (IS_ERR(tve->di_clk)) {
 467                 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
 468                         PTR_ERR(tve->di_clk));
 469                 return PTR_ERR(tve->di_clk);
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
 476 {
 477         int encoder_type;
 478         int ret;
 479
 480         encoder_type = tve->mode == TVE_MODE_VGA ?
 481                                 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
 482
 483         ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
 484         if (ret)
 485                 return ret;
 486
 487         drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
 488         drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
 489                          encoder_type, NULL);
 490
 491         drm_connector_helper_add(&tve->connector,
 492                         &imx_tve_connector_helper_funcs);
 493         drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
 494                            DRM_MODE_CONNECTOR_VGA);
 495
 496         drm_connector_attach_encoder(&tve->connector, &tve->encoder);
 497
 498         return 0;
 499 }
 500
 501 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
 502 {
 503         return (reg % 4 == 0) && (reg <= 0xdc);
 504 }
 505
 506 static struct regmap_config tve_regmap_config = {
 507         .reg_bits = 32,
 508         .val_bits = 32,
 509         .reg_stride = 4,
 510
 511         .readable_reg = imx_tve_readable_reg,
 512
 513         .lock = tve_lock,
 514         .unlock = tve_unlock,
 515
 516         .max_register = 0xdc,
 517 };
 518
 519 static const char * const imx_tve_modes[] = {
 520         [TVE_MODE_TVOUT]  = "tvout",
 521         [TVE_MODE_VGA] = "vga",
 522 };
 523
 524 static const int of_get_tve_mode(struct device_node *np)
 525 {
 526         const char *bm;
 527         int ret, i;
 528
 529         ret = of_property_read_string(np, "fsl,tve-mode", &bm);
 530         if (ret < 0)
 531                 return ret;
 532
 533         for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
 534                 if (!strcasecmp(bm, imx_tve_modes[i]))
 535                         return i;
 536
 537         return -EINVAL;
 538 }
 539
 540 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
 541 {
 542         struct platform_device *pdev = to_platform_device(dev);
 543         struct drm_device *drm = data;
 544         struct device_node *np = dev->of_node;
 545         struct device_node *ddc_node;
 546         struct imx_tve *tve;
 547         struct resource *res;
 548         void __iomem *base;
 549         unsigned int val;
 550         int irq;
 551         int ret;
 552
 553         tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
 554         if (!tve)
 555                 return -ENOMEM;
 556
 557         tve->dev = dev;
 558         spin_lock_init(&tve->lock);
 559
 560         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
 561         if (ddc_node) {
 562                 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
 563                 of_node_put(ddc_node);
 564         }
 565
 566         tve->mode = of_get_tve_mode(np);
 567         if (tve->mode != TVE_MODE_VGA) {
 568                 dev_err(dev, "only VGA mode supported, currently\n");
 569                 return -EINVAL;
 570         }
 571
 572         if (tve->mode == TVE_MODE_VGA) {
 573                 ret = of_property_read_u32(np, "fsl,hsync-pin",
 574                                            &tve->di_hsync_pin);
 575
 576                 if (ret < 0) {
 577                         dev_err(dev, "failed to get hsync pin\n");
 578                         return ret;
 579                 }
 580
 581                 ret = of_property_read_u32(np, "fsl,vsync-pin",
 582                                            &tve->di_vsync_pin);
 583
 584                 if (ret < 0) {
 585                         dev_err(dev, "failed to get vsync pin\n");
 586                         return ret;
 587                 }
 588         }
 589
 590         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 591         base = devm_ioremap_resource(dev, res);
 592         if (IS_ERR(base))
 593                 return PTR_ERR(base);
 594
 595         tve_regmap_config.lock_arg = tve;
 596         tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
 597                                                 &tve_regmap_config);
 598         if (IS_ERR(tve->regmap)) {
 599                 dev_err(dev, "failed to init regmap: %ld\n",
 600                         PTR_ERR(tve->regmap));
 601                 return PTR_ERR(tve->regmap);
 602         }
 603
 604         irq = platform_get_irq(pdev, 0);
 605         if (irq < 0) {
 606                 dev_err(dev, "failed to get irq\n");
 607                 return irq;
 608         }
 609
 610         ret = devm_request_threaded_irq(dev, irq, NULL,
 611                                         imx_tve_irq_handler, IRQF_ONESHOT,
 612                                         "imx-tve", tve);
 613         if (ret < 0) {
 614                 dev_err(dev, "failed to request irq: %d\n", ret);
 615                 return ret;
 616         }
 617
 618         tve->dac_reg = devm_regulator_get(dev, "dac");
 619         if (!IS_ERR(tve->dac_reg)) {
 620                 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
 621                         dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
 622                 ret = regulator_enable(tve->dac_reg);
 623                 if (ret)
 624                         return ret;
 625         }
 626
 627         tve->clk = devm_clk_get(dev, "tve");
 628         if (IS_ERR(tve->clk)) {
 629                 dev_err(dev, "failed to get high speed tve clock: %ld\n",
 630                         PTR_ERR(tve->clk));
 631                 return PTR_ERR(tve->clk);
 632         }
 633
 634         /* this is the IPU DI clock input selector, can be parented to tve_di */
 635         tve->di_sel_clk = devm_clk_get(dev, "di_sel");
 636         if (IS_ERR(tve->di_sel_clk)) {
 637                 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
 638                         PTR_ERR(tve->di_sel_clk));
 639                 return PTR_ERR(tve->di_sel_clk);
 640         }
 641
 642         ret = tve_clk_init(tve, base);
 643         if (ret < 0)
 644                 return ret;
 645
 646         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
 647         if (ret < 0) {
 648                 dev_err(dev, "failed to read configuration register: %d\n",
 649                         ret);
 650                 return ret;
 651         }
 652         if (val != 0x00100000) {
 653                 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
 654                 return -ENODEV;
 655         }
 656
 657         /* disable cable detection for VGA mode */
 658         ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
 659         if (ret)
 660                 return ret;
 661
 662         ret = imx_tve_register(drm, tve);
 663         if (ret)
 664                 return ret;
 665
 666         dev_set_drvdata(dev, tve);
 667
 668         return 0;
 669 }
 670
 671 static void imx_tve_unbind(struct device *dev, struct device *master,
 672         void *data)
 673 {
 674         struct imx_tve *tve = dev_get_drvdata(dev);
 675
 676         if (!IS_ERR(tve->dac_reg))
 677                 regulator_disable(tve->dac_reg);
 678 }
 679
 680 static const struct component_ops imx_tve_ops = {
 681         .bind   = imx_tve_bind,
 682         .unbind = imx_tve_unbind,
 683 };
 684
 685 static int imx_tve_probe(struct platform_device *pdev)
 686 {
 687         return component_add(&pdev->dev, &imx_tve_ops);
 688 }
 689
 690 static int imx_tve_remove(struct platform_device *pdev)
 691 {
 692         component_del(&pdev->dev, &imx_tve_ops);
 693         return 0;
 694 }
 695
 696 static const struct of_device_id imx_tve_dt_ids[] = {
 697         { .compatible = "fsl,imx53-tve", },
 698         { /* sentinel */ }
 699 };
 700 MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
 701
 702 static struct platform_driver imx_tve_driver = {
 703         .probe          = imx_tve_probe,
 704         .remove         = imx_tve_remove,
 705         .driver         = {
 706                 .of_match_table = imx_tve_dt_ids,
 707                 .name   = "imx-tve",
 708         },
 709 };
 710
 711 module_platform_driver(imx_tve_driver);
 712
 713 MODULE_DESCRIPTION("i.MX Television Encoder driver");
 714 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
 715 MODULE_LICENSE("GPL");
 716 MODULE_ALIAS("platform:imx-tve");