drivers/i2c/busses/i2c-altera.c

   1 /*
   2  *  Copyright Intel Corporation (C) 2017.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * Based on the i2c-axxia.c driver.
  17  */
  18 #include <linux/clk.h>
  19 #include <linux/clkdev.h>
  20 #include <linux/err.h>
  21 #include <linux/i2c.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/platform_device.h>
  28
  29 #define ALTR_I2C_TFR_CMD        0x00    /* Transfer Command register */
  30 #define     ALTR_I2C_TFR_CMD_STA        BIT(9)  /* send START before byte */
  31 #define     ALTR_I2C_TFR_CMD_STO        BIT(8)  /* send STOP after byte */
  32 #define     ALTR_I2C_TFR_CMD_RW_D       BIT(0)  /* Direction of transfer */
  33 #define ALTR_I2C_RX_DATA        0x04    /* RX data FIFO register */
  34 #define ALTR_I2C_CTRL           0x08    /* Control register */
  35 #define     ALTR_I2C_CTRL_RXT_SHFT      4       /* RX FIFO Threshold */
  36 #define     ALTR_I2C_CTRL_TCT_SHFT      2       /* TFER CMD FIFO Threshold */
  37 #define     ALTR_I2C_CTRL_BSPEED        BIT(1)  /* Bus Speed (1=Fast) */
  38 #define     ALTR_I2C_CTRL_EN    BIT(0)  /* Enable Core (1=Enable) */
  39 #define ALTR_I2C_ISER           0x0C    /* Interrupt Status Enable register */
  40 #define     ALTR_I2C_ISER_RXOF_EN       BIT(4)  /* Enable RX OVERFLOW IRQ */
  41 #define     ALTR_I2C_ISER_ARB_EN        BIT(3)  /* Enable ARB LOST IRQ */
  42 #define     ALTR_I2C_ISER_NACK_EN       BIT(2)  /* Enable NACK DET IRQ */
  43 #define     ALTR_I2C_ISER_RXRDY_EN      BIT(1)  /* Enable RX Ready IRQ */
  44 #define     ALTR_I2C_ISER_TXRDY_EN      BIT(0)  /* Enable TX Ready IRQ */
  45 #define ALTR_I2C_ISR            0x10    /* Interrupt Status register */
  46 #define     ALTR_I2C_ISR_RXOF           BIT(4)  /* RX OVERFLOW IRQ */
  47 #define     ALTR_I2C_ISR_ARB            BIT(3)  /* ARB LOST IRQ */
  48 #define     ALTR_I2C_ISR_NACK           BIT(2)  /* NACK DET IRQ */
  49 #define     ALTR_I2C_ISR_RXRDY          BIT(1)  /* RX Ready IRQ */
  50 #define     ALTR_I2C_ISR_TXRDY          BIT(0)  /* TX Ready IRQ */
  51 #define ALTR_I2C_STATUS         0x14    /* Status register */
  52 #define     ALTR_I2C_STAT_CORE          BIT(0)  /* Core Status (0=idle) */
  53 #define ALTR_I2C_TC_FIFO_LVL    0x18    /* Transfer FIFO LVL register */
  54 #define ALTR_I2C_RX_FIFO_LVL    0x1C    /* Receive FIFO LVL register */
  55 #define ALTR_I2C_SCL_LOW        0x20    /* SCL low count register */
  56 #define ALTR_I2C_SCL_HIGH       0x24    /* SCL high count register */
  57 #define ALTR_I2C_SDA_HOLD       0x28    /* SDA hold count register */
  58
  59 #define ALTR_I2C_ALL_IRQ        (ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | \
  60                                  ALTR_I2C_ISR_NACK | ALTR_I2C_ISR_RXRDY | \
  61                                  ALTR_I2C_ISR_TXRDY)
  62
  63 #define ALTR_I2C_THRESHOLD      0       /* IRQ Threshold at 1 element */
  64 #define ALTR_I2C_DFLT_FIFO_SZ   4
  65 #define ALTR_I2C_TIMEOUT        100000  /* 100ms */
  66 #define ALTR_I2C_XFER_TIMEOUT   (msecs_to_jiffies(250))
  67
  68 /**
  69  * altr_i2c_dev - I2C device context
  70  * @base: pointer to register struct
  71  * @msg: pointer to current message
  72  * @msg_len: number of bytes transferred in msg
  73  * @msg_err: error code for completed message
  74  * @msg_complete: xfer completion object
  75  * @dev: device reference
  76  * @adapter: core i2c abstraction
  77  * @i2c_clk: clock reference for i2c input clock
  78  * @bus_clk_rate: current i2c bus clock rate
  79  * @buf: ptr to msg buffer for easier use.
  80  * @fifo_size: size of the FIFO passed in.
  81  * @isr_mask: cached copy of local ISR enables.
  82  * @isr_status: cached copy of local ISR status.
  83  * @lock: spinlock for IRQ synchronization.
  84  * @isr_mutex: mutex for IRQ thread.
  85  */
  86 struct altr_i2c_dev {
  87         void __iomem *base;
  88         struct i2c_msg *msg;
  89         size_t msg_len;
  90         int msg_err;
  91         struct completion msg_complete;
  92         struct device *dev;
  93         struct i2c_adapter adapter;
  94         struct clk *i2c_clk;
  95         u32 bus_clk_rate;
  96         u8 *buf;
  97         u32 fifo_size;
  98         u32 isr_mask;
  99         u32 isr_status;
 100         spinlock_t lock;        /* IRQ synchronization */
 101         struct mutex isr_mutex;
 102 };
 103
 104 static void
 105 altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable)
 106 {
 107         unsigned long flags;
 108         u32 int_en;
 109
 110         spin_lock_irqsave(&idev->lock, flags);
 111
 112         int_en = readl(idev->base + ALTR_I2C_ISER);
 113         if (enable)
 114                 idev->isr_mask = int_en | mask;
 115         else
 116                 idev->isr_mask = int_en & ~mask;
 117
 118         writel(idev->isr_mask, idev->base + ALTR_I2C_ISER);
 119
 120         spin_unlock_irqrestore(&idev->lock, flags);
 121 }
 122
 123 static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask)
 124 {
 125         u32 int_en = readl(idev->base + ALTR_I2C_ISR);
 126
 127         writel(int_en | mask, idev->base + ALTR_I2C_ISR);
 128 }
 129
 130 static void altr_i2c_core_disable(struct altr_i2c_dev *idev)
 131 {
 132         u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
 133
 134         writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
 135 }
 136
 137 static void altr_i2c_core_enable(struct altr_i2c_dev *idev)
 138 {
 139         u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
 140
 141         writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
 142 }
 143
 144 static void altr_i2c_reset(struct altr_i2c_dev *idev)
 145 {
 146         altr_i2c_core_disable(idev);
 147         altr_i2c_core_enable(idev);
 148 }
 149
 150 static inline void altr_i2c_stop(struct altr_i2c_dev *idev)
 151 {
 152         writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD);
 153 }
 154
 155 static void altr_i2c_init(struct altr_i2c_dev *idev)
 156 {
 157         u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
 158         u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
 159         u32 tmp = (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_RXT_SHFT) |
 160                   (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_TCT_SHFT);
 161         u32 t_high, t_low;
 162
 163         if (idev->bus_clk_rate <= 100000) {
 164                 tmp &= ~ALTR_I2C_CTRL_BSPEED;
 165                 /* Standard mode SCL 50/50 */
 166                 t_high = divisor * 1 / 2;
 167                 t_low = divisor * 1 / 2;
 168         } else {
 169                 tmp |= ALTR_I2C_CTRL_BSPEED;
 170                 /* Fast mode SCL 33/66 */
 171                 t_high = divisor * 1 / 3;
 172                 t_low = divisor * 2 / 3;
 173         }
 174         writel(tmp, idev->base + ALTR_I2C_CTRL);
 175
 176         dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
 177                 idev->bus_clk_rate, clk_mhz, divisor);
 178
 179         /* Reset controller */
 180         altr_i2c_reset(idev);
 181
 182         /* SCL High Time */
 183         writel(t_high, idev->base + ALTR_I2C_SCL_HIGH);
 184         /* SCL Low Time */
 185         writel(t_low, idev->base + ALTR_I2C_SCL_LOW);
 186         /* SDA Hold Time, 300ns */
 187         writel(3 * clk_mhz / 10, idev->base + ALTR_I2C_SDA_HOLD);
 188
 189         /* Mask all master interrupt bits */
 190         altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
 191 }
 192
 193 /**
 194  * altr_i2c_transfer - On the last byte to be transmitted, send
 195  * a Stop bit on the last byte.
 196  */
 197 static void altr_i2c_transfer(struct altr_i2c_dev *idev, u32 data)
 198 {
 199         /* On the last byte to be transmitted, send STOP */
 200         if (idev->msg_len == 1)
 201                 data |= ALTR_I2C_TFR_CMD_STO;
 202         if (idev->msg_len > 0)
 203                 writel(data, idev->base + ALTR_I2C_TFR_CMD);
 204 }
 205
 206 /**
 207  * altr_i2c_empty_rx_fifo - Fetch data from RX FIFO until end of
 208  * transfer. Send a Stop bit on the last byte.
 209  */
 210 static void altr_i2c_empty_rx_fifo(struct altr_i2c_dev *idev)
 211 {
 212         size_t rx_fifo_avail = readl(idev->base + ALTR_I2C_RX_FIFO_LVL);
 213         int bytes_to_transfer = min(rx_fifo_avail, idev->msg_len);
 214
 215         while (bytes_to_transfer-- > 0) {
 216                 *idev->buf++ = readl(idev->base + ALTR_I2C_RX_DATA);
 217                 idev->msg_len--;
 218                 altr_i2c_transfer(idev, 0);
 219         }
 220 }
 221
 222 /**
 223  * altr_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
 224  * @return: Number of bytes left to transfer.
 225  */
 226 static int altr_i2c_fill_tx_fifo(struct altr_i2c_dev *idev)
 227 {
 228         size_t tx_fifo_avail = idev->fifo_size - readl(idev->base +
 229                                                        ALTR_I2C_TC_FIFO_LVL);
 230         int bytes_to_transfer = min(tx_fifo_avail, idev->msg_len);
 231         int ret = idev->msg_len - bytes_to_transfer;
 232
 233         while (bytes_to_transfer-- > 0) {
 234                 altr_i2c_transfer(idev, *idev->buf++);
 235                 idev->msg_len--;
 236         }
 237
 238         return ret;
 239 }
 240
 241 static irqreturn_t altr_i2c_isr_quick(int irq, void *_dev)
 242 {
 243         struct altr_i2c_dev *idev = _dev;
 244         irqreturn_t ret = IRQ_HANDLED;
 245
 246         /* Read IRQ status but only interested in Enabled IRQs. */
 247         idev->isr_status = readl(idev->base + ALTR_I2C_ISR) & idev->isr_mask;
 248         if (idev->isr_status)
 249                 ret = IRQ_WAKE_THREAD;
 250
 251         return ret;
 252 }
 253
 254 static irqreturn_t altr_i2c_isr(int irq, void *_dev)
 255 {
 256         int ret;
 257         bool read, finish = false;
 258         struct altr_i2c_dev *idev = _dev;
 259         u32 status = idev->isr_status;
 260
 261         mutex_lock(&idev->isr_mutex);
 262         if (!idev->msg) {
 263                 dev_warn(idev->dev, "unexpected interrupt\n");
 264                 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
 265                 goto out;
 266         }
 267         read = (idev->msg->flags & I2C_M_RD) != 0;
 268
 269         /* handle Lost Arbitration */
 270         if (unlikely(status & ALTR_I2C_ISR_ARB)) {
 271                 altr_i2c_int_clear(idev, ALTR_I2C_ISR_ARB);
 272                 idev->msg_err = -EAGAIN;
 273                 finish = true;
 274         } else if (unlikely(status & ALTR_I2C_ISR_NACK)) {
 275                 dev_dbg(idev->dev, "Could not get ACK\n");
 276                 idev->msg_err = -ENXIO;
 277                 altr_i2c_int_clear(idev, ALTR_I2C_ISR_NACK);
 278                 altr_i2c_stop(idev);
 279                 finish = true;
 280         } else if (read && unlikely(status & ALTR_I2C_ISR_RXOF)) {
 281                 /* handle RX FIFO Overflow */
 282                 altr_i2c_empty_rx_fifo(idev);
 283                 altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
 284                 altr_i2c_stop(idev);
 285                 dev_err(idev->dev, "RX FIFO Overflow\n");
 286                 finish = true;
 287         } else if (read && (status & ALTR_I2C_ISR_RXRDY)) {
 288                 /* RX FIFO needs service? */
 289                 altr_i2c_empty_rx_fifo(idev);
 290                 altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
 291                 if (!idev->msg_len)
 292                         finish = true;
 293         } else if (!read && (status & ALTR_I2C_ISR_TXRDY)) {
 294                 /* TX FIFO needs service? */
 295                 altr_i2c_int_clear(idev, ALTR_I2C_ISR_TXRDY);
 296                 if (idev->msg_len > 0)
 297                         altr_i2c_fill_tx_fifo(idev);
 298                 else
 299                         finish = true;
 300         } else {
 301                 dev_warn(idev->dev, "Unexpected interrupt: 0x%x\n", status);
 302                 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
 303         }
 304
 305         if (finish) {
 306                 /* Wait for the Core to finish */
 307                 ret = readl_poll_timeout_atomic(idev->base + ALTR_I2C_STATUS,
 308                                                 status,
 309                                                 !(status & ALTR_I2C_STAT_CORE),
 310                                                 1, ALTR_I2C_TIMEOUT);
 311                 if (ret)
 312                         dev_err(idev->dev, "message timeout\n");
 313                 altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
 314                 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
 315                 complete(&idev->msg_complete);
 316                 dev_dbg(idev->dev, "Message Complete\n");
 317         }
 318 out:
 319         mutex_unlock(&idev->isr_mutex);
 320
 321         return IRQ_HANDLED;
 322 }
 323
 324 static int altr_i2c_xfer_msg(struct altr_i2c_dev *idev, struct i2c_msg *msg)
 325 {
 326         u32 imask = ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | ALTR_I2C_ISR_NACK;
 327         unsigned long time_left;
 328         u32 value;
 329         u8 addr = i2c_8bit_addr_from_msg(msg);
 330
 331         mutex_lock(&idev->isr_mutex);
 332         idev->msg = msg;
 333         idev->msg_len = msg->len;
 334         idev->buf = msg->buf;
 335         idev->msg_err = 0;
 336         reinit_completion(&idev->msg_complete);
 337         altr_i2c_core_enable(idev);
 338
 339         /* Make sure RX FIFO is empty */
 340         do {
 341                 readl(idev->base + ALTR_I2C_RX_DATA);
 342         } while (readl(idev->base + ALTR_I2C_RX_FIFO_LVL));
 343
 344         writel(ALTR_I2C_TFR_CMD_STA | addr, idev->base + ALTR_I2C_TFR_CMD);
 345
 346         if ((msg->flags & I2C_M_RD) != 0) {
 347                 imask |= ALTR_I2C_ISER_RXOF_EN | ALTR_I2C_ISER_RXRDY_EN;
 348                 altr_i2c_int_enable(idev, imask, true);
 349                 /* write the first byte to start the RX */
 350                 altr_i2c_transfer(idev, 0);
 351         } else {
 352                 imask |= ALTR_I2C_ISR_TXRDY;
 353                 altr_i2c_int_enable(idev, imask, true);
 354                 altr_i2c_fill_tx_fifo(idev);
 355         }
 356         mutex_unlock(&idev->isr_mutex);
 357
 358         time_left = wait_for_completion_timeout(&idev->msg_complete,
 359                                                 ALTR_I2C_XFER_TIMEOUT);
 360         altr_i2c_int_enable(idev, imask, false);
 361
 362         value = readl(idev->base + ALTR_I2C_STATUS) & ALTR_I2C_STAT_CORE;
 363         if (value)
 364                 dev_err(idev->dev, "Core Status not IDLE...\n");
 365
 366         if (time_left == 0) {
 367                 idev->msg_err = -ETIMEDOUT;
 368                 dev_dbg(idev->dev, "Transaction timed out.\n");
 369         }
 370
 371         altr_i2c_core_disable(idev);
 372
 373         return idev->msg_err;
 374 }
 375
 376 static int
 377 altr_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 378 {
 379         struct altr_i2c_dev *idev = i2c_get_adapdata(adap);
 380         int i, ret;
 381
 382         for (i = 0; i < num; i++) {
 383                 ret = altr_i2c_xfer_msg(idev, msgs++);
 384                 if (ret)
 385                         return ret;
 386         }
 387         return num;
 388 }
 389
 390 static u32 altr_i2c_func(struct i2c_adapter *adap)
 391 {
 392         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 393 }
 394
 395 static const struct i2c_algorithm altr_i2c_algo = {
 396         .master_xfer = altr_i2c_xfer,
 397         .functionality = altr_i2c_func,
 398 };
 399
 400 static int altr_i2c_probe(struct platform_device *pdev)
 401 {
 402         struct altr_i2c_dev *idev = NULL;
 403         struct resource *res;
 404         int irq, ret;
 405
 406         idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
 407         if (!idev)
 408                 return -ENOMEM;
 409
 410         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 411         idev->base = devm_ioremap_resource(&pdev->dev, res);
 412         if (IS_ERR(idev->base))
 413                 return PTR_ERR(idev->base);
 414
 415         irq = platform_get_irq(pdev, 0);
 416         if (irq < 0) {
 417                 dev_err(&pdev->dev, "missing interrupt resource\n");
 418                 return irq;
 419         }
 420
 421         idev->i2c_clk = devm_clk_get(&pdev->dev, NULL);
 422         if (IS_ERR(idev->i2c_clk)) {
 423                 dev_err(&pdev->dev, "missing clock\n");
 424                 return PTR_ERR(idev->i2c_clk);
 425         }
 426
 427         idev->dev = &pdev->dev;
 428         init_completion(&idev->msg_complete);
 429         spin_lock_init(&idev->lock);
 430         mutex_init(&idev->isr_mutex);
 431
 432         ret = device_property_read_u32(idev->dev, "fifo-size",
 433                                        &idev->fifo_size);
 434         if (ret) {
 435                 dev_err(&pdev->dev, "FIFO size set to default of %d\n",
 436                         ALTR_I2C_DFLT_FIFO_SZ);
 437                 idev->fifo_size = ALTR_I2C_DFLT_FIFO_SZ;
 438         }
 439
 440         ret = device_property_read_u32(idev->dev, "clock-frequency",
 441                                        &idev->bus_clk_rate);
 442         if (ret) {
 443                 dev_err(&pdev->dev, "Default to 100kHz\n");
 444                 idev->bus_clk_rate = 100000;    /* default clock rate */
 445         }
 446
 447         if (idev->bus_clk_rate > 400000) {
 448                 dev_err(&pdev->dev, "invalid clock-frequency %d\n",
 449                         idev->bus_clk_rate);
 450                 return -EINVAL;
 451         }
 452
 453         ret = devm_request_threaded_irq(&pdev->dev, irq, altr_i2c_isr_quick,
 454                                         altr_i2c_isr, IRQF_ONESHOT,
 455                                         pdev->name, idev);
 456         if (ret) {
 457                 dev_err(&pdev->dev, "failed to claim IRQ %d\n", irq);
 458                 return ret;
 459         }
 460
 461         ret = clk_prepare_enable(idev->i2c_clk);
 462         if (ret) {
 463                 dev_err(&pdev->dev, "failed to enable clock\n");
 464                 return ret;
 465         }
 466
 467         altr_i2c_init(idev);
 468
 469         i2c_set_adapdata(&idev->adapter, idev);
 470         strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
 471         idev->adapter.owner = THIS_MODULE;
 472         idev->adapter.algo = &altr_i2c_algo;
 473         idev->adapter.dev.parent = &pdev->dev;
 474         idev->adapter.dev.of_node = pdev->dev.of_node;
 475
 476         platform_set_drvdata(pdev, idev);
 477
 478         ret = i2c_add_adapter(&idev->adapter);
 479         if (ret) {
 480                 clk_disable_unprepare(idev->i2c_clk);
 481                 return ret;
 482         }
 483         dev_info(&pdev->dev, "Altera SoftIP I2C Probe Complete\n");
 484
 485         return 0;
 486 }
 487
 488 static int altr_i2c_remove(struct platform_device *pdev)
 489 {
 490         struct altr_i2c_dev *idev = platform_get_drvdata(pdev);
 491
 492         clk_disable_unprepare(idev->i2c_clk);
 493         i2c_del_adapter(&idev->adapter);
 494
 495         return 0;
 496 }
 497
 498 /* Match table for of_platform binding */
 499 static const struct of_device_id altr_i2c_of_match[] = {
 500         { .compatible = "altr,softip-i2c-v1.0" },
 501         {},
 502 };
 503 MODULE_DEVICE_TABLE(of, altr_i2c_of_match);
 504
 505 static struct platform_driver altr_i2c_driver = {
 506         .probe = altr_i2c_probe,
 507         .remove = altr_i2c_remove,
 508         .driver = {
 509                 .name = "altera-i2c",
 510                 .of_match_table = altr_i2c_of_match,
 511         },
 512 };
 513
 514 module_platform_driver(altr_i2c_driver);
 515
 516 MODULE_DESCRIPTION("Altera Soft IP I2C bus driver");
 517 MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>");
 518 MODULE_LICENSE("GPL v2");