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Linux 4.19.133
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-pxa.c
blobc10ae4778d35050c61a5fb3fef7b69c758e1a6b6
1 /*
2 * i2c_adap_pxa.c
3 *
4 * I2C adapter for the PXA I2C bus access.
5 *
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * History:
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly separated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
21 */
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/init.h>
26 #include <linux/time.h>
27 #include <linux/sched.h>
28 #include <linux/delay.h>
29 #include <linux/errno.h>
30 #include <linux/interrupt.h>
31 #include <linux/i2c-pxa.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <linux/platform_device.h>
35 #include <linux/err.h>
36 #include <linux/clk.h>
37 #include <linux/slab.h>
38 #include <linux/io.h>
39 #include <linux/platform_data/i2c-pxa.h>
40
41 #include <asm/irq.h>
42
43 struct pxa_reg_layout {
44 u32 ibmr;
45 u32 idbr;
46 u32 icr;
47 u32 isr;
48 u32 isar;
49 u32 ilcr;
50 u32 iwcr;
51 u32 fm;
52 u32 hs;
53 };
54
55 enum pxa_i2c_types {
56 REGS_PXA2XX,
57 REGS_PXA3XX,
58 REGS_CE4100,
59 REGS_PXA910,
60 REGS_A3700,
61 };
62
63 #define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */
64 #define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */
65
66 /*
67 * I2C registers definitions
68 */
69 static struct pxa_reg_layout pxa_reg_layout[] = {
70 [REGS_PXA2XX] = {
71 .ibmr = 0x00,
72 .idbr = 0x08,
73 .icr = 0x10,
74 .isr = 0x18,
75 .isar = 0x20,
76 },
77 [REGS_PXA3XX] = {
78 .ibmr = 0x00,
79 .idbr = 0x04,
80 .icr = 0x08,
81 .isr = 0x0c,
82 .isar = 0x10,
83 },
84 [REGS_CE4100] = {
85 .ibmr = 0x14,
86 .idbr = 0x0c,
87 .icr = 0x00,
88 .isr = 0x04,
89 /* no isar register */
90 },
91 [REGS_PXA910] = {
92 .ibmr = 0x00,
93 .idbr = 0x08,
94 .icr = 0x10,
95 .isr = 0x18,
96 .isar = 0x20,
97 .ilcr = 0x28,
98 .iwcr = 0x30,
99 },
100 [REGS_A3700] = {
101 .ibmr = 0x00,
102 .idbr = 0x04,
103 .icr = 0x08,
104 .isr = 0x0c,
105 .isar = 0x10,
106 .fm = ICR_BUSMODE_FM,
107 .hs = ICR_BUSMODE_HS,
108 },
109 };
110
111 static const struct platform_device_id i2c_pxa_id_table[] = {
112 { "pxa2xx-i2c", REGS_PXA2XX },
113 { "pxa3xx-pwri2c", REGS_PXA3XX },
114 { "ce4100-i2c", REGS_CE4100 },
115 { "pxa910-i2c", REGS_PXA910 },
116 { "armada-3700-i2c", REGS_A3700 },
117 { },
118 };
119 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
120
121 /*
122 * I2C bit definitions
123 */
124
125 #define ICR_START (1 << 0) /* start bit */
126 #define ICR_STOP (1 << 1) /* stop bit */
127 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
128 #define ICR_TB (1 << 3) /* transfer byte bit */
129 #define ICR_MA (1 << 4) /* master abort */
130 #define ICR_SCLE (1 << 5) /* master clock enable */
131 #define ICR_IUE (1 << 6) /* unit enable */
132 #define ICR_GCD (1 << 7) /* general call disable */
133 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
134 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
135 #define ICR_BEIE (1 << 10) /* enable bus error ints */
136 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
137 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
138 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
139 #define ICR_UR (1 << 14) /* unit reset */
140 #define ICR_FM (1 << 15) /* fast mode */
141 #define ICR_HS (1 << 16) /* High Speed mode */
142 #define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
143
144 #define ISR_RWM (1 << 0) /* read/write mode */
145 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
146 #define ISR_UB (1 << 2) /* unit busy */
147 #define ISR_IBB (1 << 3) /* bus busy */
148 #define ISR_SSD (1 << 4) /* slave stop detected */
149 #define ISR_ALD (1 << 5) /* arbitration loss detected */
150 #define ISR_ITE (1 << 6) /* tx buffer empty */
151 #define ISR_IRF (1 << 7) /* rx buffer full */
152 #define ISR_GCAD (1 << 8) /* general call address detected */
153 #define ISR_SAD (1 << 9) /* slave address detected */
154 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
155
156 /* bit field shift & mask */
157 #define ILCR_SLV_SHIFT 0
158 #define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
159 #define ILCR_FLV_SHIFT 9
160 #define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
161 #define ILCR_HLVL_SHIFT 18
162 #define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
163 #define ILCR_HLVH_SHIFT 27
164 #define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
165
166 #define IWCR_CNT_SHIFT 0
167 #define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
168 #define IWCR_HS_CNT1_SHIFT 5
169 #define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
170 #define IWCR_HS_CNT2_SHIFT 10
171 #define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
172
173 struct pxa_i2c {
174 spinlock_t lock;
175 wait_queue_head_t wait;
176 struct i2c_msg *msg;
177 unsigned int msg_num;
178 unsigned int msg_idx;
179 unsigned int msg_ptr;
180 unsigned int slave_addr;
181 unsigned int req_slave_addr;
182
183 struct i2c_adapter adap;
184 struct clk *clk;
185 #ifdef CONFIG_I2C_PXA_SLAVE
186 struct i2c_slave_client *slave;
187 #endif
188
189 unsigned int irqlogidx;
190 u32 isrlog[32];
191 u32 icrlog[32];
192
193 void __iomem *reg_base;
194 void __iomem *reg_ibmr;
195 void __iomem *reg_idbr;
196 void __iomem *reg_icr;
197 void __iomem *reg_isr;
198 void __iomem *reg_isar;
199 void __iomem *reg_ilcr;
200 void __iomem *reg_iwcr;
201
202 unsigned long iobase;
203 unsigned long iosize;
204
205 int irq;
206 unsigned int use_pio :1;
207 unsigned int fast_mode :1;
208 unsigned int high_mode:1;
209 unsigned char master_code;
210 unsigned long rate;
211 bool highmode_enter;
212 u32 fm_mask;
213 u32 hs_mask;
214 };
215
216 #define _IBMR(i2c) ((i2c)->reg_ibmr)
217 #define _IDBR(i2c) ((i2c)->reg_idbr)
218 #define _ICR(i2c) ((i2c)->reg_icr)
219 #define _ISR(i2c) ((i2c)->reg_isr)
220 #define _ISAR(i2c) ((i2c)->reg_isar)
221 #define _ILCR(i2c) ((i2c)->reg_ilcr)
222 #define _IWCR(i2c) ((i2c)->reg_iwcr)
223
224 /*
225 * I2C Slave mode address
226 */
227 #define I2C_PXA_SLAVE_ADDR 0x1
228
229 #ifdef DEBUG
230
231 struct bits {
232 u32 mask;
233 const char *set;
234 const char *unset;
235 };
236 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
237
238 static inline void
239 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
240 {
241 printk("%s %08x: ", prefix, val);
242 while (num--) {
243 const char *str = val & bits->mask ? bits->set : bits->unset;
244 if (str)
245 printk("%s ", str);
246 bits++;
247 }
248 }
249
250 static const struct bits isr_bits[] = {
251 PXA_BIT(ISR_RWM, "RX", "TX"),
252 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
253 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
254 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
255 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
256 PXA_BIT(ISR_ALD, "ALD", NULL),
257 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
258 PXA_BIT(ISR_IRF, "RxFull", NULL),
259 PXA_BIT(ISR_GCAD, "GenCall", NULL),
260 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
261 PXA_BIT(ISR_BED, "BusErr", NULL),
262 };
263
264 static void decode_ISR(unsigned int val)
265 {
266 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
267 printk("\n");
268 }
269
270 static const struct bits icr_bits[] = {
271 PXA_BIT(ICR_START, "START", NULL),
272 PXA_BIT(ICR_STOP, "STOP", NULL),
273 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
274 PXA_BIT(ICR_TB, "TB", NULL),
275 PXA_BIT(ICR_MA, "MA", NULL),
276 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
277 PXA_BIT(ICR_IUE, "IUE", "iue"),
278 PXA_BIT(ICR_GCD, "GCD", NULL),
279 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
280 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
281 PXA_BIT(ICR_BEIE, "BEIE", NULL),
282 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
283 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
284 PXA_BIT(ICR_SADIE, "SADIE", NULL),
285 PXA_BIT(ICR_UR, "UR", "ur"),
286 };
287
288 #ifdef CONFIG_I2C_PXA_SLAVE
289 static void decode_ICR(unsigned int val)
290 {
291 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
292 printk("\n");
293 }
294 #endif
295
296 static unsigned int i2c_debug = DEBUG;
297
298 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
299 {
300 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
301 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
302 }
303
304 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
305
306 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
307 {
308 unsigned int i;
309 struct device *dev = &i2c->adap.dev;
310
311 dev_err(dev, "slave_0x%x error: %s\n",
312 i2c->req_slave_addr >> 1, why);
313 dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
314 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
315 dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
316 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
317 readl(_ISR(i2c)));
318 dev_err(dev, "log:");
319 for (i = 0; i < i2c->irqlogidx; i++)
320 pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
321 pr_cont("\n");
322 }
323
324 #else /* ifdef DEBUG */
325
326 #define i2c_debug 0
327
328 #define show_state(i2c) do { } while (0)
329 #define decode_ISR(val) do { } while (0)
330 #define decode_ICR(val) do { } while (0)
331 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
332
333 #endif /* ifdef DEBUG / else */
334
335 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
336 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
337
338 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
339 {
340 return !(readl(_ICR(i2c)) & ICR_SCLE);
341 }
342
343 static void i2c_pxa_abort(struct pxa_i2c *i2c)
344 {
345 int i = 250;
346
347 if (i2c_pxa_is_slavemode(i2c)) {
348 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
349 return;
350 }
351
352 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
353 unsigned long icr = readl(_ICR(i2c));
354
355 icr &= ~ICR_START;
356 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
357
358 writel(icr, _ICR(i2c));
359
360 show_state(i2c);
361
362 mdelay(1);
363 i --;
364 }
365
366 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
367 _ICR(i2c));
368 }
369
370 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
371 {
372 int timeout = DEF_TIMEOUT;
373
374 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
375 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
376 timeout += 4;
377
378 msleep(2);
379 show_state(i2c);
380 }
381
382 if (timeout < 0)
383 show_state(i2c);
384
385 return timeout < 0 ? I2C_RETRY : 0;
386 }
387
388 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
389 {
390 unsigned long timeout = jiffies + HZ*4;
391
392 while (time_before(jiffies, timeout)) {
393 if (i2c_debug > 1)
394 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
395 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
396
397 if (readl(_ISR(i2c)) & ISR_SAD) {
398 if (i2c_debug > 0)
399 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
400 goto out;
401 }
402
403 /* wait for unit and bus being not busy, and we also do a
404 * quick check of the i2c lines themselves to ensure they've
405 * gone high...
406 */
407 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
408 if (i2c_debug > 0)
409 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
410 return 1;
411 }
412
413 msleep(1);
414 }
415
416 if (i2c_debug > 0)
417 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
418 out:
419 return 0;
420 }
421
422 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
423 {
424 if (i2c_debug)
425 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
426
427 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
428 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
429 if (!i2c_pxa_wait_master(i2c)) {
430 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
431 return I2C_RETRY;
432 }
433 }
434
435 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
436 return 0;
437 }
438
439 #ifdef CONFIG_I2C_PXA_SLAVE
440 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
441 {
442 unsigned long timeout = jiffies + HZ*1;
443
444 /* wait for stop */
445
446 show_state(i2c);
447
448 while (time_before(jiffies, timeout)) {
449 if (i2c_debug > 1)
450 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
451 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
452
453 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
454 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
455 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
456 if (i2c_debug > 1)
457 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
458 return 1;
459 }
460
461 msleep(1);
462 }
463
464 if (i2c_debug > 0)
465 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
466 return 0;
467 }
468
469 /*
470 * clear the hold on the bus, and take of anything else
471 * that has been configured
472 */
473 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
474 {
475 show_state(i2c);
476
477 if (errcode < 0) {
478 udelay(100); /* simple delay */
479 } else {
480 /* we need to wait for the stop condition to end */
481
482 /* if we where in stop, then clear... */
483 if (readl(_ICR(i2c)) & ICR_STOP) {
484 udelay(100);
485 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
486 }
487
488 if (!i2c_pxa_wait_slave(i2c)) {
489 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
490 __func__);
491 return;
492 }
493 }
494
495 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
496 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
497
498 if (i2c_debug) {
499 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
500 decode_ICR(readl(_ICR(i2c)));
501 }
502 }
503 #else
504 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
505 #endif
506
507 static void i2c_pxa_reset(struct pxa_i2c *i2c)
508 {
509 pr_debug("Resetting I2C Controller Unit\n");
510
511 /* abort any transfer currently under way */
512 i2c_pxa_abort(i2c);
513
514 /* reset according to 9.8 */
515 writel(ICR_UR, _ICR(i2c));
516 writel(I2C_ISR_INIT, _ISR(i2c));
517 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
518
519 if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
520 writel(i2c->slave_addr, _ISAR(i2c));
521
522 /* set control register values */
523 writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
524 writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
525
526 #ifdef CONFIG_I2C_PXA_SLAVE
527 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
528 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
529 #endif
530
531 i2c_pxa_set_slave(i2c, 0);
532
533 /* enable unit */
534 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
535 udelay(100);
536 }
537
538
539 #ifdef CONFIG_I2C_PXA_SLAVE
540 /*
541 * PXA I2C Slave mode
542 */
543
544 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
545 {
546 if (isr & ISR_BED) {
547 /* what should we do here? */
548 } else {
549 int ret = 0;
550
551 if (i2c->slave != NULL)
552 ret = i2c->slave->read(i2c->slave->data);
553
554 writel(ret, _IDBR(i2c));
555 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
556 }
557 }
558
559 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
560 {
561 unsigned int byte = readl(_IDBR(i2c));
562
563 if (i2c->slave != NULL)
564 i2c->slave->write(i2c->slave->data, byte);
565
566 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
567 }
568
569 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
570 {
571 int timeout;
572
573 if (i2c_debug > 0)
574 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
575 (isr & ISR_RWM) ? 'r' : 't');
576
577 if (i2c->slave != NULL)
578 i2c->slave->event(i2c->slave->data,
579 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
580
581 /*
582 * slave could interrupt in the middle of us generating a
583 * start condition... if this happens, we'd better back off
584 * and stop holding the poor thing up
585 */
586 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
587 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
588
589 timeout = 0x10000;
590
591 while (1) {
592 if ((readl(_IBMR(i2c)) & 2) == 2)
593 break;
594
595 timeout--;
596
597 if (timeout <= 0) {
598 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
599 break;
600 }
601 }
602
603 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
604 }
605
606 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
607 {
608 if (i2c_debug > 2)
609 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
610
611 if (i2c->slave != NULL)
612 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
613
614 if (i2c_debug > 2)
615 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
616
617 /*
618 * If we have a master-mode message waiting,
619 * kick it off now that the slave has completed.
620 */
621 if (i2c->msg)
622 i2c_pxa_master_complete(i2c, I2C_RETRY);
623 }
624 #else
625 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
626 {
627 if (isr & ISR_BED) {
628 /* what should we do here? */
629 } else {
630 writel(0, _IDBR(i2c));
631 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
632 }
633 }
634
635 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
636 {
637 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
638 }
639
640 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
641 {
642 int timeout;
643
644 /*
645 * slave could interrupt in the middle of us generating a
646 * start condition... if this happens, we'd better back off
647 * and stop holding the poor thing up
648 */
649 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
650 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
651
652 timeout = 0x10000;
653
654 while (1) {
655 if ((readl(_IBMR(i2c)) & 2) == 2)
656 break;
657
658 timeout--;
659
660 if (timeout <= 0) {
661 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
662 break;
663 }
664 }
665
666 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
667 }
668
669 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
670 {
671 if (i2c->msg)
672 i2c_pxa_master_complete(i2c, I2C_RETRY);
673 }
674 #endif
675
676 /*
677 * PXA I2C Master mode
678 */
679
680 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
681 {
682 unsigned int addr = (msg->addr & 0x7f) << 1;
683
684 if (msg->flags & I2C_M_RD)
685 addr |= 1;
686
687 return addr;
688 }
689
690 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
691 {
692 u32 icr;
693
694 /*
695 * Step 1: target slave address into IDBR
696 */
697 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
698 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
699
700 /*
701 * Step 2: initiate the write.
702 */
703 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
704 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
705 }
706
707 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
708 {
709 u32 icr;
710
711 /* Clear the START, STOP, ACK, TB and MA flags */
712 icr = readl(_ICR(i2c));
713 icr &= ~(ICR_START | ICR_STOP | ICR_ACKNAK | ICR_TB | ICR_MA);
714 writel(icr, _ICR(i2c));
715 }
716
717 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
718 {
719 /* make timeout the same as for interrupt based functions */
720 long timeout = 2 * DEF_TIMEOUT;
721
722 /*
723 * Wait for the bus to become free.
724 */
725 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
726 udelay(1000);
727 show_state(i2c);
728 }
729
730 if (timeout < 0) {
731 show_state(i2c);
732 dev_err(&i2c->adap.dev,
733 "i2c_pxa: timeout waiting for bus free\n");
734 return I2C_RETRY;
735 }
736
737 /*
738 * Set master mode.
739 */
740 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
741
742 return 0;
743 }
744
745 /*
746 * PXA I2C send master code
747 * 1. Load master code to IDBR and send it.
748 * Note for HS mode, set ICR [GPIOEN].
749 * 2. Wait until win arbitration.
750 */
751 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
752 {
753 u32 icr;
754 long timeout;
755
756 spin_lock_irq(&i2c->lock);
757 i2c->highmode_enter = true;
758 writel(i2c->master_code, _IDBR(i2c));
759
760 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
761 icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
762 writel(icr, _ICR(i2c));
763
764 spin_unlock_irq(&i2c->lock);
765 timeout = wait_event_timeout(i2c->wait,
766 i2c->highmode_enter == false, HZ * 1);
767
768 i2c->highmode_enter = false;
769
770 return (timeout == 0) ? I2C_RETRY : 0;
771 }
772
773 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
774 struct i2c_msg *msg, int num)
775 {
776 unsigned long timeout = 500000; /* 5 seconds */
777 int ret = 0;
778
779 ret = i2c_pxa_pio_set_master(i2c);
780 if (ret)
781 goto out;
782
783 i2c->msg = msg;
784 i2c->msg_num = num;
785 i2c->msg_idx = 0;
786 i2c->msg_ptr = 0;
787 i2c->irqlogidx = 0;
788
789 i2c_pxa_start_message(i2c);
790
791 while (i2c->msg_num > 0 && --timeout) {
792 i2c_pxa_handler(0, i2c);
793 udelay(10);
794 }
795
796 i2c_pxa_stop_message(i2c);
797
798 /*
799 * We place the return code in i2c->msg_idx.
800 */
801 ret = i2c->msg_idx;
802
803 out:
804 if (timeout == 0) {
805 i2c_pxa_scream_blue_murder(i2c, "timeout");
806 ret = I2C_RETRY;
807 }
808
809 return ret;
810 }
811
812 /*
813 * We are protected by the adapter bus mutex.
814 */
815 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
816 {
817 long timeout;
818 int ret;
819
820 /*
821 * Wait for the bus to become free.
822 */
823 ret = i2c_pxa_wait_bus_not_busy(i2c);
824 if (ret) {
825 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
826 goto out;
827 }
828
829 /*
830 * Set master mode.
831 */
832 ret = i2c_pxa_set_master(i2c);
833 if (ret) {
834 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
835 goto out;
836 }
837
838 if (i2c->high_mode) {
839 ret = i2c_pxa_send_mastercode(i2c);
840 if (ret) {
841 dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
842 goto out;
843 }
844 }
845
846 spin_lock_irq(&i2c->lock);
847
848 i2c->msg = msg;
849 i2c->msg_num = num;
850 i2c->msg_idx = 0;
851 i2c->msg_ptr = 0;
852 i2c->irqlogidx = 0;
853
854 i2c_pxa_start_message(i2c);
855
856 spin_unlock_irq(&i2c->lock);
857
858 /*
859 * The rest of the processing occurs in the interrupt handler.
860 */
861 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
862 i2c_pxa_stop_message(i2c);
863
864 /*
865 * We place the return code in i2c->msg_idx.
866 */
867 ret = i2c->msg_idx;
868
869 if (!timeout && i2c->msg_num) {
870 i2c_pxa_scream_blue_murder(i2c, "timeout");
871 ret = I2C_RETRY;
872 }
873
874 out:
875 return ret;
876 }
877
878 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
879 struct i2c_msg msgs[], int num)
880 {
881 struct pxa_i2c *i2c = adap->algo_data;
882 int ret, i;
883
884 /* If the I2C controller is disabled we need to reset it
885 (probably due to a suspend/resume destroying state). We do
886 this here as we can then avoid worrying about resuming the
887 controller before its users. */
888 if (!(readl(_ICR(i2c)) & ICR_IUE))
889 i2c_pxa_reset(i2c);
890
891 for (i = adap->retries; i >= 0; i--) {
892 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
893 if (ret != I2C_RETRY)
894 goto out;
895
896 if (i2c_debug)
897 dev_dbg(&adap->dev, "Retrying transmission\n");
898 udelay(100);
899 }
900 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
901 ret = -EREMOTEIO;
902 out:
903 i2c_pxa_set_slave(i2c, ret);
904 return ret;
905 }
906
907 /*
908 * i2c_pxa_master_complete - complete the message and wake up.
909 */
910 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
911 {
912 i2c->msg_ptr = 0;
913 i2c->msg = NULL;
914 i2c->msg_idx ++;
915 i2c->msg_num = 0;
916 if (ret)
917 i2c->msg_idx = ret;
918 if (!i2c->use_pio)
919 wake_up(&i2c->wait);
920 }
921
922 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
923 {
924 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
925
926 again:
927 /*
928 * If ISR_ALD is set, we lost arbitration.
929 */
930 if (isr & ISR_ALD) {
931 /*
932 * Do we need to do anything here? The PXA docs
933 * are vague about what happens.
934 */
935 i2c_pxa_scream_blue_murder(i2c, "ALD set");
936
937 /*
938 * We ignore this error. We seem to see spurious ALDs
939 * for seemingly no reason. If we handle them as I think
940 * they should, we end up causing an I2C error, which
941 * is painful for some systems.
942 */
943 return; /* ignore */
944 }
945
946 if ((isr & ISR_BED) &&
947 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
948 (isr & ISR_ACKNAK)))) {
949 int ret = BUS_ERROR;
950
951 /*
952 * I2C bus error - either the device NAK'd us, or
953 * something more serious happened. If we were NAK'd
954 * on the initial address phase, we can retry.
955 */
956 if (isr & ISR_ACKNAK) {
957 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
958 ret = I2C_RETRY;
959 else
960 ret = XFER_NAKED;
961 }
962 i2c_pxa_master_complete(i2c, ret);
963 } else if (isr & ISR_RWM) {
964 /*
965 * Read mode. We have just sent the address byte, and
966 * now we must initiate the transfer.
967 */
968 if (i2c->msg_ptr == i2c->msg->len - 1 &&
969 i2c->msg_idx == i2c->msg_num - 1)
970 icr |= ICR_STOP | ICR_ACKNAK;
971
972 icr |= ICR_ALDIE | ICR_TB;
973 } else if (i2c->msg_ptr < i2c->msg->len) {
974 /*
975 * Write mode. Write the next data byte.
976 */
977 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
978
979 icr |= ICR_ALDIE | ICR_TB;
980
981 /*
982 * If this is the last byte of the last message or last byte
983 * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
984 */
985 if ((i2c->msg_ptr == i2c->msg->len) &&
986 ((i2c->msg->flags & I2C_M_STOP) ||
987 (i2c->msg_idx == i2c->msg_num - 1)))
988 icr |= ICR_STOP;
989
990 } else if (i2c->msg_idx < i2c->msg_num - 1) {
991 /*
992 * Next segment of the message.
993 */
994 i2c->msg_ptr = 0;
995 i2c->msg_idx ++;
996 i2c->msg++;
997
998 /*
999 * If we aren't doing a repeated start and address,
1000 * go back and try to send the next byte. Note that
1001 * we do not support switching the R/W direction here.
1002 */
1003 if (i2c->msg->flags & I2C_M_NOSTART)
1004 goto again;
1005
1006 /*
1007 * Write the next address.
1008 */
1009 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
1010 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
1011
1012 /*
1013 * And trigger a repeated start, and send the byte.
1014 */
1015 icr &= ~ICR_ALDIE;
1016 icr |= ICR_START | ICR_TB;
1017 } else {
1018 if (i2c->msg->len == 0) {
1019 /*
1020 * Device probes have a message length of zero
1021 * and need the bus to be reset before it can
1022 * be used again.
1023 */
1024 i2c_pxa_reset(i2c);
1025 }
1026 i2c_pxa_master_complete(i2c, 0);
1027 }
1028
1029 i2c->icrlog[i2c->irqlogidx-1] = icr;
1030
1031 writel(icr, _ICR(i2c));
1032 show_state(i2c);
1033 }
1034
1035 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
1036 {
1037 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
1038
1039 /*
1040 * Read the byte.
1041 */
1042 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
1043
1044 if (i2c->msg_ptr < i2c->msg->len) {
1045 /*
1046 * If this is the last byte of the last
1047 * message, send a STOP.
1048 */
1049 if (i2c->msg_ptr == i2c->msg->len - 1)
1050 icr |= ICR_STOP | ICR_ACKNAK;
1051
1052 icr |= ICR_ALDIE | ICR_TB;
1053 } else {
1054 i2c_pxa_master_complete(i2c, 0);
1055 }
1056
1057 i2c->icrlog[i2c->irqlogidx-1] = icr;
1058
1059 writel(icr, _ICR(i2c));
1060 }
1061
1062 #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
1063 ISR_SAD | ISR_BED)
1064 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
1065 {
1066 struct pxa_i2c *i2c = dev_id;
1067 u32 isr = readl(_ISR(i2c));
1068
1069 if (!(isr & VALID_INT_SOURCE))
1070 return IRQ_NONE;
1071
1072 if (i2c_debug > 2 && 0) {
1073 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1074 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1075 decode_ISR(isr);
1076 }
1077
1078 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1079 i2c->isrlog[i2c->irqlogidx++] = isr;
1080
1081 show_state(i2c);
1082
1083 /*
1084 * Always clear all pending IRQs.
1085 */
1086 writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1087
1088 if (isr & ISR_SAD)
1089 i2c_pxa_slave_start(i2c, isr);
1090 if (isr & ISR_SSD)
1091 i2c_pxa_slave_stop(i2c);
1092
1093 if (i2c_pxa_is_slavemode(i2c)) {
1094 if (isr & ISR_ITE)
1095 i2c_pxa_slave_txempty(i2c, isr);
1096 if (isr & ISR_IRF)
1097 i2c_pxa_slave_rxfull(i2c, isr);
1098 } else if (i2c->msg && (!i2c->highmode_enter)) {
1099 if (isr & ISR_ITE)
1100 i2c_pxa_irq_txempty(i2c, isr);
1101 if (isr & ISR_IRF)
1102 i2c_pxa_irq_rxfull(i2c, isr);
1103 } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1104 i2c->highmode_enter = false;
1105 wake_up(&i2c->wait);
1106 } else {
1107 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1108 }
1109
1110 return IRQ_HANDLED;
1111 }
1112
1113
1114 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
1115 {
1116 struct pxa_i2c *i2c = adap->algo_data;
1117 int ret, i;
1118
1119 for (i = adap->retries; i >= 0; i--) {
1120 ret = i2c_pxa_do_xfer(i2c, msgs, num);
1121 if (ret != I2C_RETRY)
1122 goto out;
1123
1124 if (i2c_debug)
1125 dev_dbg(&adap->dev, "Retrying transmission\n");
1126 udelay(100);
1127 }
1128 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1129 ret = -EREMOTEIO;
1130 out:
1131 i2c_pxa_set_slave(i2c, ret);
1132 return ret;
1133 }
1134
1135 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1136 {
1137 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1138 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1139 }
1140
1141 static const struct i2c_algorithm i2c_pxa_algorithm = {
1142 .master_xfer = i2c_pxa_xfer,
1143 .functionality = i2c_pxa_functionality,
1144 };
1145
1146 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1147 .master_xfer = i2c_pxa_pio_xfer,
1148 .functionality = i2c_pxa_functionality,
1149 };
1150
1151 static const struct of_device_id i2c_pxa_dt_ids[] = {
1152 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
1153 { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
1154 { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
1155 { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
1156 {}
1157 };
1158 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1159
1160 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1161 enum pxa_i2c_types *i2c_types)
1162 {
1163 struct device_node *np = pdev->dev.of_node;
1164 const struct of_device_id *of_id =
1165 of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1166
1167 if (!of_id)
1168 return 1;
1169
1170 /* For device tree we always use the dynamic or alias-assigned ID */
1171 i2c->adap.nr = -1;
1172
1173 if (of_get_property(np, "mrvl,i2c-polling", NULL))
1174 i2c->use_pio = 1;
1175 if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1176 i2c->fast_mode = 1;
1177
1178 *i2c_types = (enum pxa_i2c_types)(of_id->data);
1179
1180 return 0;
1181 }
1182
1183 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1184 struct pxa_i2c *i2c,
1185 enum pxa_i2c_types *i2c_types)
1186 {
1187 struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1188 const struct platform_device_id *id = platform_get_device_id(pdev);
1189
1190 *i2c_types = id->driver_data;
1191 if (plat) {
1192 i2c->use_pio = plat->use_pio;
1193 i2c->fast_mode = plat->fast_mode;
1194 i2c->high_mode = plat->high_mode;
1195 i2c->master_code = plat->master_code;
1196 if (!i2c->master_code)
1197 i2c->master_code = 0xe;
1198 i2c->rate = plat->rate;
1199 }
1200 return 0;
1201 }
1202
1203 static int i2c_pxa_probe(struct platform_device *dev)
1204 {
1205 struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1206 enum pxa_i2c_types i2c_type;
1207 struct pxa_i2c *i2c;
1208 struct resource *res = NULL;
1209 int ret, irq;
1210
1211 i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1212 if (!i2c)
1213 return -ENOMEM;
1214
1215 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1216 i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1217 if (IS_ERR(i2c->reg_base))
1218 return PTR_ERR(i2c->reg_base);
1219
1220 irq = platform_get_irq(dev, 0);
1221 if (irq < 0) {
1222 dev_err(&dev->dev, "no irq resource: %d\n", irq);
1223 return irq;
1224 }
1225
1226 /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1227 i2c->adap.nr = dev->id;
1228
1229 ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1230 if (ret > 0)
1231 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1232 if (ret < 0)
1233 return ret;
1234
1235 i2c->adap.owner = THIS_MODULE;
1236 i2c->adap.retries = 5;
1237
1238 spin_lock_init(&i2c->lock);
1239 init_waitqueue_head(&i2c->wait);
1240
1241 strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1242
1243 i2c->clk = devm_clk_get(&dev->dev, NULL);
1244 if (IS_ERR(i2c->clk)) {
1245 dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1246 return PTR_ERR(i2c->clk);
1247 }
1248
1249 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1250 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1251 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1252 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1253 i2c->fm_mask = pxa_reg_layout[i2c_type].fm ? : ICR_FM;
1254 i2c->hs_mask = pxa_reg_layout[i2c_type].hs ? : ICR_HS;
1255
1256 if (i2c_type != REGS_CE4100)
1257 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1258
1259 if (i2c_type == REGS_PXA910) {
1260 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1261 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1262 }
1263
1264 i2c->iobase = res->start;
1265 i2c->iosize = resource_size(res);
1266
1267 i2c->irq = irq;
1268
1269 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1270 i2c->highmode_enter = false;
1271
1272 if (plat) {
1273 #ifdef CONFIG_I2C_PXA_SLAVE
1274 i2c->slave_addr = plat->slave_addr;
1275 i2c->slave = plat->slave;
1276 #endif
1277 i2c->adap.class = plat->class;
1278 }
1279
1280 if (i2c->high_mode) {
1281 if (i2c->rate) {
1282 clk_set_rate(i2c->clk, i2c->rate);
1283 pr_info("i2c: <%s> set rate to %ld\n",
1284 i2c->adap.name, clk_get_rate(i2c->clk));
1285 } else
1286 pr_warn("i2c: <%s> clock rate not set\n",
1287 i2c->adap.name);
1288 }
1289
1290 clk_prepare_enable(i2c->clk);
1291
1292 if (i2c->use_pio) {
1293 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1294 } else {
1295 i2c->adap.algo = &i2c_pxa_algorithm;
1296 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1297 IRQF_SHARED | IRQF_NO_SUSPEND,
1298 dev_name(&dev->dev), i2c);
1299 if (ret) {
1300 dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1301 goto ereqirq;
1302 }
1303 }
1304
1305 i2c_pxa_reset(i2c);
1306
1307 i2c->adap.algo_data = i2c;
1308 i2c->adap.dev.parent = &dev->dev;
1309 #ifdef CONFIG_OF
1310 i2c->adap.dev.of_node = dev->dev.of_node;
1311 #endif
1312
1313 ret = i2c_add_numbered_adapter(&i2c->adap);
1314 if (ret < 0)
1315 goto ereqirq;
1316
1317 platform_set_drvdata(dev, i2c);
1318
1319 #ifdef CONFIG_I2C_PXA_SLAVE
1320 dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1321 i2c->slave_addr);
1322 #else
1323 dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1324 #endif
1325 return 0;
1326
1327 ereqirq:
1328 clk_disable_unprepare(i2c->clk);
1329 return ret;
1330 }
1331
1332 static int i2c_pxa_remove(struct platform_device *dev)
1333 {
1334 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1335
1336 i2c_del_adapter(&i2c->adap);
1337
1338 clk_disable_unprepare(i2c->clk);
1339
1340 return 0;
1341 }
1342
1343 #ifdef CONFIG_PM
1344 static int i2c_pxa_suspend_noirq(struct device *dev)
1345 {
1346 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1347
1348 clk_disable(i2c->clk);
1349
1350 return 0;
1351 }
1352
1353 static int i2c_pxa_resume_noirq(struct device *dev)
1354 {
1355 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1356
1357 clk_enable(i2c->clk);
1358 i2c_pxa_reset(i2c);
1359
1360 return 0;
1361 }
1362
1363 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1364 .suspend_noirq = i2c_pxa_suspend_noirq,
1365 .resume_noirq = i2c_pxa_resume_noirq,
1366 };
1367
1368 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1369 #else
1370 #define I2C_PXA_DEV_PM_OPS NULL
1371 #endif
1372
1373 static struct platform_driver i2c_pxa_driver = {
1374 .probe = i2c_pxa_probe,
1375 .remove = i2c_pxa_remove,
1376 .driver = {
1377 .name = "pxa2xx-i2c",
1378 .pm = I2C_PXA_DEV_PM_OPS,
1379 .of_match_table = i2c_pxa_dt_ids,
1380 },
1381 .id_table = i2c_pxa_id_table,
1382 };
1383
1384 static int __init i2c_adap_pxa_init(void)
1385 {
1386 return platform_driver_register(&i2c_pxa_driver);
1387 }
1388
1389 static void __exit i2c_adap_pxa_exit(void)
1390 {
1391 platform_driver_unregister(&i2c_pxa_driver);
1392 }
1393
1394 MODULE_LICENSE("GPL");
1395 MODULE_ALIAS("platform:pxa2xx-i2c");
1396
1397 subsys_initcall(i2c_adap_pxa_init);
1398 module_exit(i2c_adap_pxa_exit);
Linux with added FPC-III support