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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / dsa / mt7530.c
blob616afd81536af6806dede73b53101f14aef3fceb
1 /*
2 * Mediatek MT7530 DSA Switch driver
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14 #include <linux/etherdevice.h>
15 #include <linux/if_bridge.h>
16 #include <linux/iopoll.h>
17 #include <linux/mdio.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/netdevice.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_net.h>
24 #include <linux/of_platform.h>
25 #include <linux/phy.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/reset.h>
29 #include <linux/gpio/consumer.h>
30 #include <net/dsa.h>
31
32 #include "mt7530.h"
33
34 /* String, offset, and register size in bytes if different from 4 bytes */
35 static const struct mt7530_mib_desc mt7530_mib[] = {
36 MIB_DESC(1, 0x00, "TxDrop"),
37 MIB_DESC(1, 0x04, "TxCrcErr"),
38 MIB_DESC(1, 0x08, "TxUnicast"),
39 MIB_DESC(1, 0x0c, "TxMulticast"),
40 MIB_DESC(1, 0x10, "TxBroadcast"),
41 MIB_DESC(1, 0x14, "TxCollision"),
42 MIB_DESC(1, 0x18, "TxSingleCollision"),
43 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
44 MIB_DESC(1, 0x20, "TxDeferred"),
45 MIB_DESC(1, 0x24, "TxLateCollision"),
46 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
47 MIB_DESC(1, 0x2c, "TxPause"),
48 MIB_DESC(1, 0x30, "TxPktSz64"),
49 MIB_DESC(1, 0x34, "TxPktSz65To127"),
50 MIB_DESC(1, 0x38, "TxPktSz128To255"),
51 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
52 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
53 MIB_DESC(1, 0x44, "Tx1024ToMax"),
54 MIB_DESC(2, 0x48, "TxBytes"),
55 MIB_DESC(1, 0x60, "RxDrop"),
56 MIB_DESC(1, 0x64, "RxFiltering"),
57 MIB_DESC(1, 0x6c, "RxMulticast"),
58 MIB_DESC(1, 0x70, "RxBroadcast"),
59 MIB_DESC(1, 0x74, "RxAlignErr"),
60 MIB_DESC(1, 0x78, "RxCrcErr"),
61 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
62 MIB_DESC(1, 0x80, "RxFragErr"),
63 MIB_DESC(1, 0x84, "RxOverSzErr"),
64 MIB_DESC(1, 0x88, "RxJabberErr"),
65 MIB_DESC(1, 0x8c, "RxPause"),
66 MIB_DESC(1, 0x90, "RxPktSz64"),
67 MIB_DESC(1, 0x94, "RxPktSz65To127"),
68 MIB_DESC(1, 0x98, "RxPktSz128To255"),
69 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
70 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
71 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
72 MIB_DESC(2, 0xa8, "RxBytes"),
73 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
74 MIB_DESC(1, 0xb4, "RxIngressDrop"),
75 MIB_DESC(1, 0xb8, "RxArlDrop"),
76 };
77
78 static int
79 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val)
80 {
81 int ret;
82
83 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val);
84 if (ret < 0)
85 dev_err(priv->dev,
86 "failed to priv write register\n");
87 return ret;
88 }
89
90 static u32
91 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg)
92 {
93 int ret;
94 u32 val;
95
96 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val);
97 if (ret < 0) {
98 dev_err(priv->dev,
99 "failed to priv read register\n");
100 return ret;
101 }
102
103 return val;
104 }
105
106 static void
107 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg,
108 u32 mask, u32 set)
109 {
110 u32 val;
111
112 val = mt7623_trgmii_read(priv, reg);
113 val &= ~mask;
114 val |= set;
115 mt7623_trgmii_write(priv, reg, val);
116 }
117
118 static void
119 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val)
120 {
121 mt7623_trgmii_rmw(priv, reg, 0, val);
122 }
123
124 static void
125 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val)
126 {
127 mt7623_trgmii_rmw(priv, reg, val, 0);
128 }
129
130 static int
131 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
132 {
133 struct mii_bus *bus = priv->bus;
134 int value, ret;
135
136 /* Write the desired MMD Devad */
137 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
138 if (ret < 0)
139 goto err;
140
141 /* Write the desired MMD register address */
142 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
143 if (ret < 0)
144 goto err;
145
146 /* Select the Function : DATA with no post increment */
147 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
148 if (ret < 0)
149 goto err;
150
151 /* Read the content of the MMD's selected register */
152 value = bus->read(bus, 0, MII_MMD_DATA);
153
154 return value;
155 err:
156 dev_err(&bus->dev, "failed to read mmd register\n");
157
158 return ret;
159 }
160
161 static int
162 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
163 int devad, u32 data)
164 {
165 struct mii_bus *bus = priv->bus;
166 int ret;
167
168 /* Write the desired MMD Devad */
169 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
170 if (ret < 0)
171 goto err;
172
173 /* Write the desired MMD register address */
174 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
175 if (ret < 0)
176 goto err;
177
178 /* Select the Function : DATA with no post increment */
179 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
180 if (ret < 0)
181 goto err;
182
183 /* Write the data into MMD's selected register */
184 ret = bus->write(bus, 0, MII_MMD_DATA, data);
185 err:
186 if (ret < 0)
187 dev_err(&bus->dev,
188 "failed to write mmd register\n");
189 return ret;
190 }
191
192 static void
193 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
194 {
195 struct mii_bus *bus = priv->bus;
196
197 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
198
199 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
200
201 mutex_unlock(&bus->mdio_lock);
202 }
203
204 static void
205 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
206 {
207 struct mii_bus *bus = priv->bus;
208 u32 val;
209
210 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
211
212 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
213 val &= ~mask;
214 val |= set;
215 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
216
217 mutex_unlock(&bus->mdio_lock);
218 }
219
220 static void
221 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
222 {
223 core_rmw(priv, reg, 0, val);
224 }
225
226 static void
227 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
228 {
229 core_rmw(priv, reg, val, 0);
230 }
231
232 static int
233 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
234 {
235 struct mii_bus *bus = priv->bus;
236 u16 page, r, lo, hi;
237 int ret;
238
239 page = (reg >> 6) & 0x3ff;
240 r = (reg >> 2) & 0xf;
241 lo = val & 0xffff;
242 hi = val >> 16;
243
244 /* MT7530 uses 31 as the pseudo port */
245 ret = bus->write(bus, 0x1f, 0x1f, page);
246 if (ret < 0)
247 goto err;
248
249 ret = bus->write(bus, 0x1f, r, lo);
250 if (ret < 0)
251 goto err;
252
253 ret = bus->write(bus, 0x1f, 0x10, hi);
254 err:
255 if (ret < 0)
256 dev_err(&bus->dev,
257 "failed to write mt7530 register\n");
258 return ret;
259 }
260
261 static u32
262 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
263 {
264 struct mii_bus *bus = priv->bus;
265 u16 page, r, lo, hi;
266 int ret;
267
268 page = (reg >> 6) & 0x3ff;
269 r = (reg >> 2) & 0xf;
270
271 /* MT7530 uses 31 as the pseudo port */
272 ret = bus->write(bus, 0x1f, 0x1f, page);
273 if (ret < 0) {
274 dev_err(&bus->dev,
275 "failed to read mt7530 register\n");
276 return ret;
277 }
278
279 lo = bus->read(bus, 0x1f, r);
280 hi = bus->read(bus, 0x1f, 0x10);
281
282 return (hi << 16) | (lo & 0xffff);
283 }
284
285 static void
286 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
287 {
288 struct mii_bus *bus = priv->bus;
289
290 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
291
292 mt7530_mii_write(priv, reg, val);
293
294 mutex_unlock(&bus->mdio_lock);
295 }
296
297 static u32
298 _mt7530_read(struct mt7530_dummy_poll *p)
299 {
300 struct mii_bus *bus = p->priv->bus;
301 u32 val;
302
303 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
304
305 val = mt7530_mii_read(p->priv, p->reg);
306
307 mutex_unlock(&bus->mdio_lock);
308
309 return val;
310 }
311
312 static u32
313 mt7530_read(struct mt7530_priv *priv, u32 reg)
314 {
315 struct mt7530_dummy_poll p;
316
317 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
318 return _mt7530_read(&p);
319 }
320
321 static void
322 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
323 u32 mask, u32 set)
324 {
325 struct mii_bus *bus = priv->bus;
326 u32 val;
327
328 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
329
330 val = mt7530_mii_read(priv, reg);
331 val &= ~mask;
332 val |= set;
333 mt7530_mii_write(priv, reg, val);
334
335 mutex_unlock(&bus->mdio_lock);
336 }
337
338 static void
339 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
340 {
341 mt7530_rmw(priv, reg, 0, val);
342 }
343
344 static void
345 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
346 {
347 mt7530_rmw(priv, reg, val, 0);
348 }
349
350 static int
351 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
352 {
353 u32 val;
354 int ret;
355 struct mt7530_dummy_poll p;
356
357 /* Set the command operating upon the MAC address entries */
358 val = ATC_BUSY | ATC_MAT(0) | cmd;
359 mt7530_write(priv, MT7530_ATC, val);
360
361 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
362 ret = readx_poll_timeout(_mt7530_read, &p, val,
363 !(val & ATC_BUSY), 20, 20000);
364 if (ret < 0) {
365 dev_err(priv->dev, "reset timeout\n");
366 return ret;
367 }
368
369 /* Additional sanity for read command if the specified
370 * entry is invalid
371 */
372 val = mt7530_read(priv, MT7530_ATC);
373 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
374 return -EINVAL;
375
376 if (rsp)
377 *rsp = val;
378
379 return 0;
380 }
381
382 static void
383 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
384 {
385 u32 reg[3];
386 int i;
387
388 /* Read from ARL table into an array */
389 for (i = 0; i < 3; i++) {
390 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
391
392 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
393 __func__, __LINE__, i, reg[i]);
394 }
395
396 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
397 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
398 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
399 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
400 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
401 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
402 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
403 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
404 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
405 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
406 }
407
408 static void
409 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
410 u8 port_mask, const u8 *mac,
411 u8 aging, u8 type)
412 {
413 u32 reg[3] = { 0 };
414 int i;
415
416 reg[1] |= vid & CVID_MASK;
417 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
418 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
419 /* STATIC_ENT indicate that entry is static wouldn't
420 * be aged out and STATIC_EMP specified as erasing an
421 * entry
422 */
423 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
424 reg[1] |= mac[5] << MAC_BYTE_5;
425 reg[1] |= mac[4] << MAC_BYTE_4;
426 reg[0] |= mac[3] << MAC_BYTE_3;
427 reg[0] |= mac[2] << MAC_BYTE_2;
428 reg[0] |= mac[1] << MAC_BYTE_1;
429 reg[0] |= mac[0] << MAC_BYTE_0;
430
431 /* Write array into the ARL table */
432 for (i = 0; i < 3; i++)
433 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
434 }
435
436 static int
437 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
438 {
439 struct mt7530_priv *priv = ds->priv;
440 u32 ncpo1, ssc_delta, trgint, i;
441
442 switch (mode) {
443 case PHY_INTERFACE_MODE_RGMII:
444 trgint = 0;
445 ncpo1 = 0x0c80;
446 ssc_delta = 0x87;
447 break;
448 case PHY_INTERFACE_MODE_TRGMII:
449 trgint = 1;
450 ncpo1 = 0x1400;
451 ssc_delta = 0x57;
452 break;
453 default:
454 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
455 return -EINVAL;
456 }
457
458 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
459 P6_INTF_MODE(trgint));
460
461 /* Lower Tx Driving for TRGMII path */
462 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
463 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
464 TD_DM_DRVP(8) | TD_DM_DRVN(8));
465
466 /* Setup core clock for MT7530 */
467 if (!trgint) {
468 /* Disable MT7530 core clock */
469 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
470
471 /* Disable PLL, since phy_device has not yet been created
472 * provided for phy_[read,write]_mmd_indirect is called, we
473 * provide our own core_write_mmd_indirect to complete this
474 * function.
475 */
476 core_write_mmd_indirect(priv,
477 CORE_GSWPLL_GRP1,
478 MDIO_MMD_VEND2,
479 0);
480
481 /* Set core clock into 500Mhz */
482 core_write(priv, CORE_GSWPLL_GRP2,
483 RG_GSWPLL_POSDIV_500M(1) |
484 RG_GSWPLL_FBKDIV_500M(25));
485
486 /* Enable PLL */
487 core_write(priv, CORE_GSWPLL_GRP1,
488 RG_GSWPLL_EN_PRE |
489 RG_GSWPLL_POSDIV_200M(2) |
490 RG_GSWPLL_FBKDIV_200M(32));
491
492 /* Enable MT7530 core clock */
493 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
494 }
495
496 /* Setup the MT7530 TRGMII Tx Clock */
497 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
498 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
499 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
500 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
501 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
502 core_write(priv, CORE_PLL_GROUP4,
503 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
504 RG_SYSPLL_BIAS_LPF_EN);
505 core_write(priv, CORE_PLL_GROUP2,
506 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
507 RG_SYSPLL_POSDIV(1));
508 core_write(priv, CORE_PLL_GROUP7,
509 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
510 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
511 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
512 REG_GSWCK_EN | REG_TRGMIICK_EN);
513
514 if (!trgint)
515 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
516 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
517 RD_TAP_MASK, RD_TAP(16));
518 else
519 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
520
521 return 0;
522 }
523
524 static int
525 mt7623_pad_clk_setup(struct dsa_switch *ds)
526 {
527 struct mt7530_priv *priv = ds->priv;
528 int i;
529
530 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
531 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i),
532 TD_DM_DRVP(8) | TD_DM_DRVN(8));
533
534 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL);
535 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST);
536
537 return 0;
538 }
539
540 static void
541 mt7530_mib_reset(struct dsa_switch *ds)
542 {
543 struct mt7530_priv *priv = ds->priv;
544
545 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
546 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
547 }
548
549 static void
550 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable)
551 {
552 u32 mask = PMCR_TX_EN | PMCR_RX_EN | PMCR_FORCE_LNK;
553
554 if (enable)
555 mt7530_set(priv, MT7530_PMCR_P(port), mask);
556 else
557 mt7530_clear(priv, MT7530_PMCR_P(port), mask);
558 }
559
560 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
561 {
562 struct mt7530_priv *priv = ds->priv;
563
564 return mdiobus_read_nested(priv->bus, port, regnum);
565 }
566
567 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
568 u16 val)
569 {
570 struct mt7530_priv *priv = ds->priv;
571
572 return mdiobus_write_nested(priv->bus, port, regnum, val);
573 }
574
575 static void
576 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
577 uint8_t *data)
578 {
579 int i;
580
581 if (stringset != ETH_SS_STATS)
582 return;
583
584 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
585 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
586 ETH_GSTRING_LEN);
587 }
588
589 static void
590 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
591 uint64_t *data)
592 {
593 struct mt7530_priv *priv = ds->priv;
594 const struct mt7530_mib_desc *mib;
595 u32 reg, i;
596 u64 hi;
597
598 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
599 mib = &mt7530_mib[i];
600 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
601
602 data[i] = mt7530_read(priv, reg);
603 if (mib->size == 2) {
604 hi = mt7530_read(priv, reg + 4);
605 data[i] |= hi << 32;
606 }
607 }
608 }
609
610 static int
611 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
612 {
613 if (sset != ETH_SS_STATS)
614 return 0;
615
616 return ARRAY_SIZE(mt7530_mib);
617 }
618
619 static void mt7530_adjust_link(struct dsa_switch *ds, int port,
620 struct phy_device *phydev)
621 {
622 struct mt7530_priv *priv = ds->priv;
623
624 if (phy_is_pseudo_fixed_link(phydev)) {
625 dev_dbg(priv->dev, "phy-mode for master device = %x\n",
626 phydev->interface);
627
628 /* Setup TX circuit incluing relevant PAD and driving */
629 mt7530_pad_clk_setup(ds, phydev->interface);
630
631 /* Setup RX circuit, relevant PAD and driving on the host
632 * which must be placed after the setup on the device side is
633 * all finished.
634 */
635 mt7623_pad_clk_setup(ds);
636 } else {
637 u16 lcl_adv = 0, rmt_adv = 0;
638 u8 flowctrl;
639 u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
640
641 switch (phydev->speed) {
642 case SPEED_1000:
643 mcr |= PMCR_FORCE_SPEED_1000;
644 break;
645 case SPEED_100:
646 mcr |= PMCR_FORCE_SPEED_100;
647 break;
648 };
649
650 if (phydev->link)
651 mcr |= PMCR_FORCE_LNK;
652
653 if (phydev->duplex) {
654 mcr |= PMCR_FORCE_FDX;
655
656 if (phydev->pause)
657 rmt_adv = LPA_PAUSE_CAP;
658 if (phydev->asym_pause)
659 rmt_adv |= LPA_PAUSE_ASYM;
660
661 if (phydev->advertising & ADVERTISED_Pause)
662 lcl_adv |= ADVERTISE_PAUSE_CAP;
663 if (phydev->advertising & ADVERTISED_Asym_Pause)
664 lcl_adv |= ADVERTISE_PAUSE_ASYM;
665
666 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
667
668 if (flowctrl & FLOW_CTRL_TX)
669 mcr |= PMCR_TX_FC_EN;
670 if (flowctrl & FLOW_CTRL_RX)
671 mcr |= PMCR_RX_FC_EN;
672 }
673 mt7530_write(priv, MT7530_PMCR_P(port), mcr);
674 }
675 }
676
677 static int
678 mt7530_cpu_port_enable(struct mt7530_priv *priv,
679 int port)
680 {
681 /* Enable Mediatek header mode on the cpu port */
682 mt7530_write(priv, MT7530_PVC_P(port),
683 PORT_SPEC_TAG);
684
685 /* Setup the MAC by default for the cpu port */
686 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
687
688 /* Unknown multicast frame forwarding to the cpu port */
689 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
690
691 /* CPU port gets connected to all user ports of
692 * the switch
693 */
694 mt7530_write(priv, MT7530_PCR_P(port),
695 PCR_MATRIX(dsa_user_ports(priv->ds)));
696
697 return 0;
698 }
699
700 static int
701 mt7530_port_enable(struct dsa_switch *ds, int port,
702 struct phy_device *phy)
703 {
704 struct mt7530_priv *priv = ds->priv;
705
706 mutex_lock(&priv->reg_mutex);
707
708 /* Setup the MAC for the user port */
709 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK);
710
711 /* Allow the user port gets connected to the cpu port and also
712 * restore the port matrix if the port is the member of a certain
713 * bridge.
714 */
715 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
716 priv->ports[port].enable = true;
717 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
718 priv->ports[port].pm);
719 mt7530_port_set_status(priv, port, 1);
720
721 mutex_unlock(&priv->reg_mutex);
722
723 return 0;
724 }
725
726 static void
727 mt7530_port_disable(struct dsa_switch *ds, int port,
728 struct phy_device *phy)
729 {
730 struct mt7530_priv *priv = ds->priv;
731
732 mutex_lock(&priv->reg_mutex);
733
734 /* Clear up all port matrix which could be restored in the next
735 * enablement for the port.
736 */
737 priv->ports[port].enable = false;
738 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
739 PCR_MATRIX_CLR);
740 mt7530_port_set_status(priv, port, 0);
741
742 mutex_unlock(&priv->reg_mutex);
743 }
744
745 static void
746 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
747 {
748 struct mt7530_priv *priv = ds->priv;
749 u32 stp_state;
750
751 switch (state) {
752 case BR_STATE_DISABLED:
753 stp_state = MT7530_STP_DISABLED;
754 break;
755 case BR_STATE_BLOCKING:
756 stp_state = MT7530_STP_BLOCKING;
757 break;
758 case BR_STATE_LISTENING:
759 stp_state = MT7530_STP_LISTENING;
760 break;
761 case BR_STATE_LEARNING:
762 stp_state = MT7530_STP_LEARNING;
763 break;
764 case BR_STATE_FORWARDING:
765 default:
766 stp_state = MT7530_STP_FORWARDING;
767 break;
768 }
769
770 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
771 }
772
773 static int
774 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
775 struct net_device *bridge)
776 {
777 struct mt7530_priv *priv = ds->priv;
778 u32 port_bitmap = BIT(MT7530_CPU_PORT);
779 int i;
780
781 mutex_lock(&priv->reg_mutex);
782
783 for (i = 0; i < MT7530_NUM_PORTS; i++) {
784 /* Add this port to the port matrix of the other ports in the
785 * same bridge. If the port is disabled, port matrix is kept
786 * and not being setup until the port becomes enabled.
787 */
788 if (dsa_is_user_port(ds, i) && i != port) {
789 if (dsa_to_port(ds, i)->bridge_dev != bridge)
790 continue;
791 if (priv->ports[i].enable)
792 mt7530_set(priv, MT7530_PCR_P(i),
793 PCR_MATRIX(BIT(port)));
794 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
795
796 port_bitmap |= BIT(i);
797 }
798 }
799
800 /* Add the all other ports to this port matrix. */
801 if (priv->ports[port].enable)
802 mt7530_rmw(priv, MT7530_PCR_P(port),
803 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
804 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
805
806 mutex_unlock(&priv->reg_mutex);
807
808 return 0;
809 }
810
811 static void
812 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
813 {
814 struct mt7530_priv *priv = ds->priv;
815 bool all_user_ports_removed = true;
816 int i;
817
818 /* When a port is removed from the bridge, the port would be set up
819 * back to the default as is at initial boot which is a VLAN-unaware
820 * port.
821 */
822 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
823 MT7530_PORT_MATRIX_MODE);
824 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
825 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
826 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
827
828 priv->ports[port].vlan_filtering = false;
829
830 for (i = 0; i < MT7530_NUM_PORTS; i++) {
831 if (dsa_is_user_port(ds, i) &&
832 priv->ports[i].vlan_filtering) {
833 all_user_ports_removed = false;
834 break;
835 }
836 }
837
838 /* CPU port also does the same thing until all user ports belonging to
839 * the CPU port get out of VLAN filtering mode.
840 */
841 if (all_user_ports_removed) {
842 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
843 PCR_MATRIX(dsa_user_ports(priv->ds)));
844 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
845 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
846 }
847 }
848
849 static void
850 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
851 {
852 struct mt7530_priv *priv = ds->priv;
853
854 /* The real fabric path would be decided on the membership in the
855 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
856 * means potential VLAN can be consisting of certain subset of all
857 * ports.
858 */
859 mt7530_rmw(priv, MT7530_PCR_P(port),
860 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
861
862 /* Trapped into security mode allows packet forwarding through VLAN
863 * table lookup. CPU port is set to fallback mode to let untagged
864 * frames pass through.
865 */
866 if (dsa_is_cpu_port(ds, port))
867 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
868 MT7530_PORT_FALLBACK_MODE);
869 else
870 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
871 MT7530_PORT_SECURITY_MODE);
872
873 /* Set the port as a user port which is to be able to recognize VID
874 * from incoming packets before fetching entry within the VLAN table.
875 */
876 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
877 VLAN_ATTR(MT7530_VLAN_USER) |
878 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
879 }
880
881 static void
882 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
883 struct net_device *bridge)
884 {
885 struct mt7530_priv *priv = ds->priv;
886 int i;
887
888 mutex_lock(&priv->reg_mutex);
889
890 for (i = 0; i < MT7530_NUM_PORTS; i++) {
891 /* Remove this port from the port matrix of the other ports
892 * in the same bridge. If the port is disabled, port matrix
893 * is kept and not being setup until the port becomes enabled.
894 * And the other port's port matrix cannot be broken when the
895 * other port is still a VLAN-aware port.
896 */
897 if (!priv->ports[i].vlan_filtering &&
898 dsa_is_user_port(ds, i) && i != port) {
899 if (dsa_to_port(ds, i)->bridge_dev != bridge)
900 continue;
901 if (priv->ports[i].enable)
902 mt7530_clear(priv, MT7530_PCR_P(i),
903 PCR_MATRIX(BIT(port)));
904 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
905 }
906 }
907
908 /* Set the cpu port to be the only one in the port matrix of
909 * this port.
910 */
911 if (priv->ports[port].enable)
912 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
913 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
914 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
915
916 mt7530_port_set_vlan_unaware(ds, port);
917
918 mutex_unlock(&priv->reg_mutex);
919 }
920
921 static int
922 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
923 const unsigned char *addr, u16 vid)
924 {
925 struct mt7530_priv *priv = ds->priv;
926 int ret;
927 u8 port_mask = BIT(port);
928
929 mutex_lock(&priv->reg_mutex);
930 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
931 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
932 mutex_unlock(&priv->reg_mutex);
933
934 return ret;
935 }
936
937 static int
938 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
939 const unsigned char *addr, u16 vid)
940 {
941 struct mt7530_priv *priv = ds->priv;
942 int ret;
943 u8 port_mask = BIT(port);
944
945 mutex_lock(&priv->reg_mutex);
946 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
947 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
948 mutex_unlock(&priv->reg_mutex);
949
950 return ret;
951 }
952
953 static int
954 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
955 dsa_fdb_dump_cb_t *cb, void *data)
956 {
957 struct mt7530_priv *priv = ds->priv;
958 struct mt7530_fdb _fdb = { 0 };
959 int cnt = MT7530_NUM_FDB_RECORDS;
960 int ret = 0;
961 u32 rsp = 0;
962
963 mutex_lock(&priv->reg_mutex);
964
965 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
966 if (ret < 0)
967 goto err;
968
969 do {
970 if (rsp & ATC_SRCH_HIT) {
971 mt7530_fdb_read(priv, &_fdb);
972 if (_fdb.port_mask & BIT(port)) {
973 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
974 data);
975 if (ret < 0)
976 break;
977 }
978 }
979 } while (--cnt &&
980 !(rsp & ATC_SRCH_END) &&
981 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
982 err:
983 mutex_unlock(&priv->reg_mutex);
984
985 return 0;
986 }
987
988 static int
989 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
990 {
991 struct mt7530_dummy_poll p;
992 u32 val;
993 int ret;
994
995 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
996 mt7530_write(priv, MT7530_VTCR, val);
997
998 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
999 ret = readx_poll_timeout(_mt7530_read, &p, val,
1000 !(val & VTCR_BUSY), 20, 20000);
1001 if (ret < 0) {
1002 dev_err(priv->dev, "poll timeout\n");
1003 return ret;
1004 }
1005
1006 val = mt7530_read(priv, MT7530_VTCR);
1007 if (val & VTCR_INVALID) {
1008 dev_err(priv->dev, "read VTCR invalid\n");
1009 return -EINVAL;
1010 }
1011
1012 return 0;
1013 }
1014
1015 static int
1016 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
1017 bool vlan_filtering)
1018 {
1019 struct mt7530_priv *priv = ds->priv;
1020
1021 priv->ports[port].vlan_filtering = vlan_filtering;
1022
1023 if (vlan_filtering) {
1024 /* The port is being kept as VLAN-unaware port when bridge is
1025 * set up with vlan_filtering not being set, Otherwise, the
1026 * port and the corresponding CPU port is required the setup
1027 * for becoming a VLAN-aware port.
1028 */
1029 mt7530_port_set_vlan_aware(ds, port);
1030 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
1031 }
1032
1033 return 0;
1034 }
1035
1036 static int
1037 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
1038 const struct switchdev_obj_port_vlan *vlan)
1039 {
1040 /* nothing needed */
1041
1042 return 0;
1043 }
1044
1045 static void
1046 mt7530_hw_vlan_add(struct mt7530_priv *priv,
1047 struct mt7530_hw_vlan_entry *entry)
1048 {
1049 u8 new_members;
1050 u32 val;
1051
1052 new_members = entry->old_members | BIT(entry->port) |
1053 BIT(MT7530_CPU_PORT);
1054
1055 /* Validate the entry with independent learning, create egress tag per
1056 * VLAN and joining the port as one of the port members.
1057 */
1058 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1059 mt7530_write(priv, MT7530_VAWD1, val);
1060
1061 /* Decide whether adding tag or not for those outgoing packets from the
1062 * port inside the VLAN.
1063 */
1064 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1065 MT7530_VLAN_EGRESS_TAG;
1066 mt7530_rmw(priv, MT7530_VAWD2,
1067 ETAG_CTRL_P_MASK(entry->port),
1068 ETAG_CTRL_P(entry->port, val));
1069
1070 /* CPU port is always taken as a tagged port for serving more than one
1071 * VLANs across and also being applied with egress type stack mode for
1072 * that VLAN tags would be appended after hardware special tag used as
1073 * DSA tag.
1074 */
1075 mt7530_rmw(priv, MT7530_VAWD2,
1076 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1077 ETAG_CTRL_P(MT7530_CPU_PORT,
1078 MT7530_VLAN_EGRESS_STACK));
1079 }
1080
1081 static void
1082 mt7530_hw_vlan_del(struct mt7530_priv *priv,
1083 struct mt7530_hw_vlan_entry *entry)
1084 {
1085 u8 new_members;
1086 u32 val;
1087
1088 new_members = entry->old_members & ~BIT(entry->port);
1089
1090 val = mt7530_read(priv, MT7530_VAWD1);
1091 if (!(val & VLAN_VALID)) {
1092 dev_err(priv->dev,
1093 "Cannot be deleted due to invalid entry\n");
1094 return;
1095 }
1096
1097 /* If certain member apart from CPU port is still alive in the VLAN,
1098 * the entry would be kept valid. Otherwise, the entry is got to be
1099 * disabled.
1100 */
1101 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1102 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1103 VLAN_VALID;
1104 mt7530_write(priv, MT7530_VAWD1, val);
1105 } else {
1106 mt7530_write(priv, MT7530_VAWD1, 0);
1107 mt7530_write(priv, MT7530_VAWD2, 0);
1108 }
1109 }
1110
1111 static void
1112 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1113 struct mt7530_hw_vlan_entry *entry,
1114 mt7530_vlan_op vlan_op)
1115 {
1116 u32 val;
1117
1118 /* Fetch entry */
1119 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1120
1121 val = mt7530_read(priv, MT7530_VAWD1);
1122
1123 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1124
1125 /* Manipulate entry */
1126 vlan_op(priv, entry);
1127
1128 /* Flush result to hardware */
1129 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1130 }
1131
1132 static void
1133 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1134 const struct switchdev_obj_port_vlan *vlan)
1135 {
1136 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1137 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1138 struct mt7530_hw_vlan_entry new_entry;
1139 struct mt7530_priv *priv = ds->priv;
1140 u16 vid;
1141
1142 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1143 * being set.
1144 */
1145 if (!priv->ports[port].vlan_filtering)
1146 return;
1147
1148 mutex_lock(&priv->reg_mutex);
1149
1150 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1151 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1152 mt7530_hw_vlan_update(priv, vid, &new_entry,
1153 mt7530_hw_vlan_add);
1154 }
1155
1156 if (pvid) {
1157 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1158 G0_PORT_VID(vlan->vid_end));
1159 priv->ports[port].pvid = vlan->vid_end;
1160 }
1161
1162 mutex_unlock(&priv->reg_mutex);
1163 }
1164
1165 static int
1166 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1167 const struct switchdev_obj_port_vlan *vlan)
1168 {
1169 struct mt7530_hw_vlan_entry target_entry;
1170 struct mt7530_priv *priv = ds->priv;
1171 u16 vid, pvid;
1172
1173 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1174 * being set.
1175 */
1176 if (!priv->ports[port].vlan_filtering)
1177 return 0;
1178
1179 mutex_lock(&priv->reg_mutex);
1180
1181 pvid = priv->ports[port].pvid;
1182 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1183 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1184 mt7530_hw_vlan_update(priv, vid, &target_entry,
1185 mt7530_hw_vlan_del);
1186
1187 /* PVID is being restored to the default whenever the PVID port
1188 * is being removed from the VLAN.
1189 */
1190 if (pvid == vid)
1191 pvid = G0_PORT_VID_DEF;
1192 }
1193
1194 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1195 priv->ports[port].pvid = pvid;
1196
1197 mutex_unlock(&priv->reg_mutex);
1198
1199 return 0;
1200 }
1201
1202 static enum dsa_tag_protocol
1203 mtk_get_tag_protocol(struct dsa_switch *ds, int port)
1204 {
1205 struct mt7530_priv *priv = ds->priv;
1206
1207 if (port != MT7530_CPU_PORT) {
1208 dev_warn(priv->dev,
1209 "port not matched with tagging CPU port\n");
1210 return DSA_TAG_PROTO_NONE;
1211 } else {
1212 return DSA_TAG_PROTO_MTK;
1213 }
1214 }
1215
1216 static int
1217 mt7530_setup(struct dsa_switch *ds)
1218 {
1219 struct mt7530_priv *priv = ds->priv;
1220 int ret, i;
1221 u32 id, val;
1222 struct device_node *dn;
1223 struct mt7530_dummy_poll p;
1224
1225 /* The parent node of master netdev which holds the common system
1226 * controller also is the container for two GMACs nodes representing
1227 * as two netdev instances.
1228 */
1229 dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent;
1230 priv->ethernet = syscon_node_to_regmap(dn);
1231 if (IS_ERR(priv->ethernet))
1232 return PTR_ERR(priv->ethernet);
1233
1234 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1235 ret = regulator_enable(priv->core_pwr);
1236 if (ret < 0) {
1237 dev_err(priv->dev,
1238 "Failed to enable core power: %d\n", ret);
1239 return ret;
1240 }
1241
1242 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1243 ret = regulator_enable(priv->io_pwr);
1244 if (ret < 0) {
1245 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1246 ret);
1247 return ret;
1248 }
1249
1250 /* Reset whole chip through gpio pin or memory-mapped registers for
1251 * different type of hardware
1252 */
1253 if (priv->mcm) {
1254 reset_control_assert(priv->rstc);
1255 usleep_range(1000, 1100);
1256 reset_control_deassert(priv->rstc);
1257 } else {
1258 gpiod_set_value_cansleep(priv->reset, 0);
1259 usleep_range(1000, 1100);
1260 gpiod_set_value_cansleep(priv->reset, 1);
1261 }
1262
1263 /* Waiting for MT7530 got to stable */
1264 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1265 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1266 20, 1000000);
1267 if (ret < 0) {
1268 dev_err(priv->dev, "reset timeout\n");
1269 return ret;
1270 }
1271
1272 id = mt7530_read(priv, MT7530_CREV);
1273 id >>= CHIP_NAME_SHIFT;
1274 if (id != MT7530_ID) {
1275 dev_err(priv->dev, "chip %x can't be supported\n", id);
1276 return -ENODEV;
1277 }
1278
1279 /* Reset the switch through internal reset */
1280 mt7530_write(priv, MT7530_SYS_CTRL,
1281 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1282 SYS_CTRL_REG_RST);
1283
1284 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1285 val = mt7530_read(priv, MT7530_MHWTRAP);
1286 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1287 val |= MHWTRAP_MANUAL;
1288 mt7530_write(priv, MT7530_MHWTRAP, val);
1289
1290 /* Enable and reset MIB counters */
1291 mt7530_mib_reset(ds);
1292
1293 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1294 /* Disable forwarding by default on all ports */
1295 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1296 PCR_MATRIX_CLR);
1297
1298 if (dsa_is_cpu_port(ds, i))
1299 mt7530_cpu_port_enable(priv, i);
1300 else
1301 mt7530_port_disable(ds, i, NULL);
1302
1303 /* Enable consistent egress tag */
1304 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1305 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1306 }
1307
1308 /* Flush the FDB table */
1309 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1310 if (ret < 0)
1311 return ret;
1312
1313 return 0;
1314 }
1315
1316 static const struct dsa_switch_ops mt7530_switch_ops = {
1317 .get_tag_protocol = mtk_get_tag_protocol,
1318 .setup = mt7530_setup,
1319 .get_strings = mt7530_get_strings,
1320 .phy_read = mt7530_phy_read,
1321 .phy_write = mt7530_phy_write,
1322 .get_ethtool_stats = mt7530_get_ethtool_stats,
1323 .get_sset_count = mt7530_get_sset_count,
1324 .adjust_link = mt7530_adjust_link,
1325 .port_enable = mt7530_port_enable,
1326 .port_disable = mt7530_port_disable,
1327 .port_stp_state_set = mt7530_stp_state_set,
1328 .port_bridge_join = mt7530_port_bridge_join,
1329 .port_bridge_leave = mt7530_port_bridge_leave,
1330 .port_fdb_add = mt7530_port_fdb_add,
1331 .port_fdb_del = mt7530_port_fdb_del,
1332 .port_fdb_dump = mt7530_port_fdb_dump,
1333 .port_vlan_filtering = mt7530_port_vlan_filtering,
1334 .port_vlan_prepare = mt7530_port_vlan_prepare,
1335 .port_vlan_add = mt7530_port_vlan_add,
1336 .port_vlan_del = mt7530_port_vlan_del,
1337 };
1338
1339 static int
1340 mt7530_probe(struct mdio_device *mdiodev)
1341 {
1342 struct mt7530_priv *priv;
1343 struct device_node *dn;
1344
1345 dn = mdiodev->dev.of_node;
1346
1347 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1348 if (!priv)
1349 return -ENOMEM;
1350
1351 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
1352 if (!priv->ds)
1353 return -ENOMEM;
1354
1355 /* Use medatek,mcm property to distinguish hardware type that would
1356 * casues a little bit differences on power-on sequence.
1357 */
1358 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1359 if (priv->mcm) {
1360 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1361
1362 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1363 if (IS_ERR(priv->rstc)) {
1364 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1365 return PTR_ERR(priv->rstc);
1366 }
1367 }
1368
1369 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1370 if (IS_ERR(priv->core_pwr))
1371 return PTR_ERR(priv->core_pwr);
1372
1373 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1374 if (IS_ERR(priv->io_pwr))
1375 return PTR_ERR(priv->io_pwr);
1376
1377 /* Not MCM that indicates switch works as the remote standalone
1378 * integrated circuit so the GPIO pin would be used to complete
1379 * the reset, otherwise memory-mapped register accessing used
1380 * through syscon provides in the case of MCM.
1381 */
1382 if (!priv->mcm) {
1383 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1384 GPIOD_OUT_LOW);
1385 if (IS_ERR(priv->reset)) {
1386 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1387 return PTR_ERR(priv->reset);
1388 }
1389 }
1390
1391 priv->bus = mdiodev->bus;
1392 priv->dev = &mdiodev->dev;
1393 priv->ds->priv = priv;
1394 priv->ds->ops = &mt7530_switch_ops;
1395 mutex_init(&priv->reg_mutex);
1396 dev_set_drvdata(&mdiodev->dev, priv);
1397
1398 return dsa_register_switch(priv->ds);
1399 }
1400
1401 static void
1402 mt7530_remove(struct mdio_device *mdiodev)
1403 {
1404 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1405 int ret = 0;
1406
1407 ret = regulator_disable(priv->core_pwr);
1408 if (ret < 0)
1409 dev_err(priv->dev,
1410 "Failed to disable core power: %d\n", ret);
1411
1412 ret = regulator_disable(priv->io_pwr);
1413 if (ret < 0)
1414 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1415 ret);
1416
1417 dsa_unregister_switch(priv->ds);
1418 mutex_destroy(&priv->reg_mutex);
1419 }
1420
1421 static const struct of_device_id mt7530_of_match[] = {
1422 { .compatible = "mediatek,mt7530" },
1423 { /* sentinel */ },
1424 };
1425 MODULE_DEVICE_TABLE(of, mt7530_of_match);
1426
1427 static struct mdio_driver mt7530_mdio_driver = {
1428 .probe = mt7530_probe,
1429 .remove = mt7530_remove,
1430 .mdiodrv.driver = {
1431 .name = "mt7530",
1432 .of_match_table = mt7530_of_match,
1433 },
1434 };
1435
1436 mdio_module_driver(mt7530_mdio_driver);
1437
1438 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1439 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1440 MODULE_LICENSE("GPL");
Linux with added FPC-III support