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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_sriov.c
blobab60f4f9cc246f08cbd7b8700e50dc2393114048
1 /* bnx2x_sriov.c: QLogic Everest network driver.
2 *
3 * Copyright 2009-2013 Broadcom Corporation
4 * Copyright 2014 QLogic Corporation
5 * All rights reserved
6 *
7 * Unless you and QLogic execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2, available
10 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
11 *
12 * Notwithstanding the above, under no circumstances may you combine this
13 * software in any way with any other QLogic software provided under a
14 * license other than the GPL, without QLogic's express prior written
15 * consent.
16 *
17 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
18 * Written by: Shmulik Ravid
19 * Ariel Elior <ariel.elior@qlogic.com>
20 *
21 */
22 #include "bnx2x.h"
23 #include "bnx2x_init.h"
24 #include "bnx2x_cmn.h"
25 #include "bnx2x_sp.h"
26 #include <linux/crc32.h>
27 #include <linux/if_vlan.h>
28
29 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx,
30 struct bnx2x_virtf **vf,
31 struct pf_vf_bulletin_content **bulletin,
32 bool test_queue);
33
34 /* General service functions */
35 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
36 u16 pf_id)
37 {
38 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
39 pf_id);
40 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
41 pf_id);
42 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
43 pf_id);
44 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
45 pf_id);
46 }
47
48 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
49 u8 enable)
50 {
51 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
52 enable);
53 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
54 enable);
55 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
56 enable);
57 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
58 enable);
59 }
60
61 int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid)
62 {
63 int idx;
64
65 for_each_vf(bp, idx)
66 if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid)
67 break;
68 return idx;
69 }
70
71 static
72 struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid)
73 {
74 u16 idx = (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid);
75 return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL;
76 }
77
78 static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf,
79 u8 igu_sb_id, u8 segment, u16 index, u8 op,
80 u8 update)
81 {
82 /* acking a VF sb through the PF - use the GRC */
83 u32 ctl;
84 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
85 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
86 u32 func_encode = vf->abs_vfid;
87 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id;
88 struct igu_regular cmd_data = {0};
89
90 cmd_data.sb_id_and_flags =
91 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
92 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
93 (update << IGU_REGULAR_BUPDATE_SHIFT) |
94 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
95
96 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
97 func_encode << IGU_CTRL_REG_FID_SHIFT |
98 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
99
100 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
101 cmd_data.sb_id_and_flags, igu_addr_data);
102 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags);
103 mmiowb();
104 barrier();
105
106 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
107 ctl, igu_addr_ctl);
108 REG_WR(bp, igu_addr_ctl, ctl);
109 mmiowb();
110 barrier();
111 }
112
113 static bool bnx2x_validate_vf_sp_objs(struct bnx2x *bp,
114 struct bnx2x_virtf *vf,
115 bool print_err)
116 {
117 if (!bnx2x_leading_vfq(vf, sp_initialized)) {
118 if (print_err)
119 BNX2X_ERR("Slowpath objects not yet initialized!\n");
120 else
121 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n");
122 return false;
123 }
124 return true;
125 }
126
127 /* VFOP operations states */
128 void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf,
129 struct bnx2x_queue_init_params *init_params,
130 struct bnx2x_queue_setup_params *setup_params,
131 u16 q_idx, u16 sb_idx)
132 {
133 DP(BNX2X_MSG_IOV,
134 "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d",
135 vf->abs_vfid,
136 q_idx,
137 sb_idx,
138 init_params->tx.sb_cq_index,
139 init_params->tx.hc_rate,
140 setup_params->flags,
141 setup_params->txq_params.traffic_type);
142 }
143
144 void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf,
145 struct bnx2x_queue_init_params *init_params,
146 struct bnx2x_queue_setup_params *setup_params,
147 u16 q_idx, u16 sb_idx)
148 {
149 struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params;
150
151 DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n"
152 "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n",
153 vf->abs_vfid,
154 q_idx,
155 sb_idx,
156 init_params->rx.sb_cq_index,
157 init_params->rx.hc_rate,
158 setup_params->gen_params.mtu,
159 rxq_params->buf_sz,
160 rxq_params->sge_buf_sz,
161 rxq_params->max_sges_pkt,
162 rxq_params->tpa_agg_sz,
163 setup_params->flags,
164 rxq_params->drop_flags,
165 rxq_params->cache_line_log);
166 }
167
168 void bnx2x_vfop_qctor_prep(struct bnx2x *bp,
169 struct bnx2x_virtf *vf,
170 struct bnx2x_vf_queue *q,
171 struct bnx2x_vf_queue_construct_params *p,
172 unsigned long q_type)
173 {
174 struct bnx2x_queue_init_params *init_p = &p->qstate.params.init;
175 struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup;
176
177 /* INIT */
178
179 /* Enable host coalescing in the transition to INIT state */
180 if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags))
181 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags);
182
183 if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags))
184 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags);
185
186 /* FW SB ID */
187 init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
188 init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
189
190 /* context */
191 init_p->cxts[0] = q->cxt;
192
193 /* SETUP */
194
195 /* Setup-op general parameters */
196 setup_p->gen_params.spcl_id = vf->sp_cl_id;
197 setup_p->gen_params.stat_id = vfq_stat_id(vf, q);
198 setup_p->gen_params.fp_hsi = vf->fp_hsi;
199
200 /* Setup-op flags:
201 * collect statistics, zero statistics, local-switching, security,
202 * OV for Flex10, RSS and MCAST for leading
203 */
204 if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags))
205 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags);
206
207 /* for VFs, enable tx switching, bd coherency, and mac address
208 * anti-spoofing
209 */
210 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags);
211 __set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags);
212 __set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags);
213
214 /* Setup-op rx parameters */
215 if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) {
216 struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params;
217
218 rxq_p->cl_qzone_id = vfq_qzone_id(vf, q);
219 rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx);
220 rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid);
221
222 if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags))
223 rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES;
224 }
225
226 /* Setup-op tx parameters */
227 if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) {
228 setup_p->txq_params.tss_leading_cl_id = vf->leading_rss;
229 setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
230 }
231 }
232
233 static int bnx2x_vf_queue_create(struct bnx2x *bp,
234 struct bnx2x_virtf *vf, int qid,
235 struct bnx2x_vf_queue_construct_params *qctor)
236 {
237 struct bnx2x_queue_state_params *q_params;
238 int rc = 0;
239
240 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
241
242 /* Prepare ramrod information */
243 q_params = &qctor->qstate;
244 q_params->q_obj = &bnx2x_vfq(vf, qid, sp_obj);
245 set_bit(RAMROD_COMP_WAIT, &q_params->ramrod_flags);
246
247 if (bnx2x_get_q_logical_state(bp, q_params->q_obj) ==
248 BNX2X_Q_LOGICAL_STATE_ACTIVE) {
249 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n");
250 goto out;
251 }
252
253 /* Run Queue 'construction' ramrods */
254 q_params->cmd = BNX2X_Q_CMD_INIT;
255 rc = bnx2x_queue_state_change(bp, q_params);
256 if (rc)
257 goto out;
258
259 memcpy(&q_params->params.setup, &qctor->prep_qsetup,
260 sizeof(struct bnx2x_queue_setup_params));
261 q_params->cmd = BNX2X_Q_CMD_SETUP;
262 rc = bnx2x_queue_state_change(bp, q_params);
263 if (rc)
264 goto out;
265
266 /* enable interrupts */
267 bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, bnx2x_vfq(vf, qid, sb_idx)),
268 USTORM_ID, 0, IGU_INT_ENABLE, 0);
269 out:
270 return rc;
271 }
272
273 static int bnx2x_vf_queue_destroy(struct bnx2x *bp, struct bnx2x_virtf *vf,
274 int qid)
275 {
276 enum bnx2x_queue_cmd cmds[] = {BNX2X_Q_CMD_HALT,
277 BNX2X_Q_CMD_TERMINATE,
278 BNX2X_Q_CMD_CFC_DEL};
279 struct bnx2x_queue_state_params q_params;
280 int rc, i;
281
282 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
283
284 /* Prepare ramrod information */
285 memset(&q_params, 0, sizeof(struct bnx2x_queue_state_params));
286 q_params.q_obj = &bnx2x_vfq(vf, qid, sp_obj);
287 set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
288
289 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) ==
290 BNX2X_Q_LOGICAL_STATE_STOPPED) {
291 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n");
292 goto out;
293 }
294
295 /* Run Queue 'destruction' ramrods */
296 for (i = 0; i < ARRAY_SIZE(cmds); i++) {
297 q_params.cmd = cmds[i];
298 rc = bnx2x_queue_state_change(bp, &q_params);
299 if (rc) {
300 BNX2X_ERR("Failed to run Queue command %d\n", cmds[i]);
301 return rc;
302 }
303 }
304 out:
305 /* Clean Context */
306 if (bnx2x_vfq(vf, qid, cxt)) {
307 bnx2x_vfq(vf, qid, cxt)->ustorm_ag_context.cdu_usage = 0;
308 bnx2x_vfq(vf, qid, cxt)->xstorm_ag_context.cdu_reserved = 0;
309 }
310
311 return 0;
312 }
313
314 static void
315 bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid)
316 {
317 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
318 if (vf) {
319 /* the first igu entry belonging to VFs of this PF */
320 if (!BP_VFDB(bp)->first_vf_igu_entry)
321 BP_VFDB(bp)->first_vf_igu_entry = igu_sb_id;
322
323 /* the first igu entry belonging to this VF */
324 if (!vf_sb_count(vf))
325 vf->igu_base_id = igu_sb_id;
326
327 ++vf_sb_count(vf);
328 ++vf->sb_count;
329 }
330 BP_VFDB(bp)->vf_sbs_pool++;
331 }
332
333 static inline void bnx2x_vf_vlan_credit(struct bnx2x *bp,
334 struct bnx2x_vlan_mac_obj *obj,
335 atomic_t *counter)
336 {
337 struct list_head *pos;
338 int read_lock;
339 int cnt = 0;
340
341 read_lock = bnx2x_vlan_mac_h_read_lock(bp, obj);
342 if (read_lock)
343 DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n");
344
345 list_for_each(pos, &obj->head)
346 cnt++;
347
348 if (!read_lock)
349 bnx2x_vlan_mac_h_read_unlock(bp, obj);
350
351 atomic_set(counter, cnt);
352 }
353
354 static int bnx2x_vf_vlan_mac_clear(struct bnx2x *bp, struct bnx2x_virtf *vf,
355 int qid, bool drv_only, int type)
356 {
357 struct bnx2x_vlan_mac_ramrod_params ramrod;
358 int rc;
359
360 DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid,
361 (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" :
362 (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs");
363
364 /* Prepare ramrod params */
365 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params));
366 if (type == BNX2X_VF_FILTER_VLAN_MAC) {
367 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
368 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj);
369 } else if (type == BNX2X_VF_FILTER_MAC) {
370 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
371 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj);
372 } else {
373 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
374 }
375 ramrod.user_req.cmd = BNX2X_VLAN_MAC_DEL;
376
377 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags);
378 if (drv_only)
379 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags);
380 else
381 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags);
382
383 /* Start deleting */
384 rc = ramrod.vlan_mac_obj->delete_all(bp,
385 ramrod.vlan_mac_obj,
386 &ramrod.user_req.vlan_mac_flags,
387 &ramrod.ramrod_flags);
388 if (rc) {
389 BNX2X_ERR("Failed to delete all %s\n",
390 (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" :
391 (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs");
392 return rc;
393 }
394
395 return 0;
396 }
397
398 static int bnx2x_vf_mac_vlan_config(struct bnx2x *bp,
399 struct bnx2x_virtf *vf, int qid,
400 struct bnx2x_vf_mac_vlan_filter *filter,
401 bool drv_only)
402 {
403 struct bnx2x_vlan_mac_ramrod_params ramrod;
404 int rc;
405
406 DP(BNX2X_MSG_IOV, "vf[%d] - %s a %s filter\n",
407 vf->abs_vfid, filter->add ? "Adding" : "Deleting",
408 (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MAC" :
409 (filter->type == BNX2X_VF_FILTER_MAC) ? "MAC" : "VLAN");
410
411 /* Prepare ramrod params */
412 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params));
413 if (filter->type == BNX2X_VF_FILTER_VLAN_MAC) {
414 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj);
415 ramrod.user_req.u.vlan.vlan = filter->vid;
416 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN);
417 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
418 } else if (filter->type == BNX2X_VF_FILTER_VLAN) {
419 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
420 ramrod.user_req.u.vlan.vlan = filter->vid;
421 } else {
422 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
423 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj);
424 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN);
425 }
426 ramrod.user_req.cmd = filter->add ? BNX2X_VLAN_MAC_ADD :
427 BNX2X_VLAN_MAC_DEL;
428
429 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags);
430 if (drv_only)
431 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags);
432 else
433 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags);
434
435 /* Add/Remove the filter */
436 rc = bnx2x_config_vlan_mac(bp, &ramrod);
437 if (rc == -EEXIST)
438 return 0;
439 if (rc) {
440 BNX2X_ERR("Failed to %s %s\n",
441 filter->add ? "add" : "delete",
442 (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ?
443 "VLAN-MAC" :
444 (filter->type == BNX2X_VF_FILTER_MAC) ?
445 "MAC" : "VLAN");
446 return rc;
447 }
448
449 filter->applied = true;
450
451 return 0;
452 }
453
454 int bnx2x_vf_mac_vlan_config_list(struct bnx2x *bp, struct bnx2x_virtf *vf,
455 struct bnx2x_vf_mac_vlan_filters *filters,
456 int qid, bool drv_only)
457 {
458 int rc = 0, i;
459
460 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
461
462 if (!bnx2x_validate_vf_sp_objs(bp, vf, true))
463 return -EINVAL;
464
465 /* Prepare ramrod params */
466 for (i = 0; i < filters->count; i++) {
467 rc = bnx2x_vf_mac_vlan_config(bp, vf, qid,
468 &filters->filters[i], drv_only);
469 if (rc)
470 break;
471 }
472
473 /* Rollback if needed */
474 if (i != filters->count) {
475 BNX2X_ERR("Managed only %d/%d filters - rolling back\n",
476 i, filters->count);
477 while (--i >= 0) {
478 if (!filters->filters[i].applied)
479 continue;
480 filters->filters[i].add = !filters->filters[i].add;
481 bnx2x_vf_mac_vlan_config(bp, vf, qid,
482 &filters->filters[i],
483 drv_only);
484 }
485 }
486
487 /* It's our responsibility to free the filters */
488 kfree(filters);
489
490 return rc;
491 }
492
493 int bnx2x_vf_queue_setup(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid,
494 struct bnx2x_vf_queue_construct_params *qctor)
495 {
496 int rc;
497
498 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
499
500 rc = bnx2x_vf_queue_create(bp, vf, qid, qctor);
501 if (rc)
502 goto op_err;
503
504 /* Schedule the configuration of any pending vlan filters */
505 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_HYPERVISOR_VLAN,
506 BNX2X_MSG_IOV);
507 return 0;
508 op_err:
509 BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc);
510 return rc;
511 }
512
513 static int bnx2x_vf_queue_flr(struct bnx2x *bp, struct bnx2x_virtf *vf,
514 int qid)
515 {
516 int rc;
517
518 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
519
520 /* If needed, clean the filtering data base */
521 if ((qid == LEADING_IDX) &&
522 bnx2x_validate_vf_sp_objs(bp, vf, false)) {
523 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true,
524 BNX2X_VF_FILTER_VLAN_MAC);
525 if (rc)
526 goto op_err;
527 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true,
528 BNX2X_VF_FILTER_VLAN);
529 if (rc)
530 goto op_err;
531 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true,
532 BNX2X_VF_FILTER_MAC);
533 if (rc)
534 goto op_err;
535 }
536
537 /* Terminate queue */
538 if (bnx2x_vfq(vf, qid, sp_obj).state != BNX2X_Q_STATE_RESET) {
539 struct bnx2x_queue_state_params qstate;
540
541 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params));
542 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj);
543 qstate.q_obj->state = BNX2X_Q_STATE_STOPPED;
544 qstate.cmd = BNX2X_Q_CMD_TERMINATE;
545 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags);
546 rc = bnx2x_queue_state_change(bp, &qstate);
547 if (rc)
548 goto op_err;
549 }
550
551 return 0;
552 op_err:
553 BNX2X_ERR("vf[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc);
554 return rc;
555 }
556
557 int bnx2x_vf_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf,
558 bnx2x_mac_addr_t *mcasts, int mc_num, bool drv_only)
559 {
560 struct bnx2x_mcast_list_elem *mc = NULL;
561 struct bnx2x_mcast_ramrod_params mcast;
562 int rc, i;
563
564 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
565
566 /* Prepare Multicast command */
567 memset(&mcast, 0, sizeof(struct bnx2x_mcast_ramrod_params));
568 mcast.mcast_obj = &vf->mcast_obj;
569 if (drv_only)
570 set_bit(RAMROD_DRV_CLR_ONLY, &mcast.ramrod_flags);
571 else
572 set_bit(RAMROD_COMP_WAIT, &mcast.ramrod_flags);
573 if (mc_num) {
574 mc = kcalloc(mc_num, sizeof(struct bnx2x_mcast_list_elem),
575 GFP_KERNEL);
576 if (!mc) {
577 BNX2X_ERR("Cannot Configure multicasts due to lack of memory\n");
578 return -ENOMEM;
579 }
580 }
581
582 if (mc_num) {
583 INIT_LIST_HEAD(&mcast.mcast_list);
584 for (i = 0; i < mc_num; i++) {
585 mc[i].mac = mcasts[i];
586 list_add_tail(&mc[i].link,
587 &mcast.mcast_list);
588 }
589
590 /* add new mcasts */
591 mcast.mcast_list_len = mc_num;
592 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_SET);
593 if (rc)
594 BNX2X_ERR("Failed to set multicasts\n");
595 } else {
596 /* clear existing mcasts */
597 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_DEL);
598 if (rc)
599 BNX2X_ERR("Failed to remove multicasts\n");
600 }
601
602 kfree(mc);
603
604 return rc;
605 }
606
607 static void bnx2x_vf_prep_rx_mode(struct bnx2x *bp, u8 qid,
608 struct bnx2x_rx_mode_ramrod_params *ramrod,
609 struct bnx2x_virtf *vf,
610 unsigned long accept_flags)
611 {
612 struct bnx2x_vf_queue *vfq = vfq_get(vf, qid);
613
614 memset(ramrod, 0, sizeof(*ramrod));
615 ramrod->cid = vfq->cid;
616 ramrod->cl_id = vfq_cl_id(vf, vfq);
617 ramrod->rx_mode_obj = &bp->rx_mode_obj;
618 ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid);
619 ramrod->rx_accept_flags = accept_flags;
620 ramrod->tx_accept_flags = accept_flags;
621 ramrod->pstate = &vf->filter_state;
622 ramrod->state = BNX2X_FILTER_RX_MODE_PENDING;
623
624 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state);
625 set_bit(RAMROD_RX, &ramrod->ramrod_flags);
626 set_bit(RAMROD_TX, &ramrod->ramrod_flags);
627
628 ramrod->rdata = bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2);
629 ramrod->rdata_mapping = bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2);
630 }
631
632 int bnx2x_vf_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf,
633 int qid, unsigned long accept_flags)
634 {
635 struct bnx2x_rx_mode_ramrod_params ramrod;
636
637 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
638
639 bnx2x_vf_prep_rx_mode(bp, qid, &ramrod, vf, accept_flags);
640 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags);
641 vfq_get(vf, qid)->accept_flags = ramrod.rx_accept_flags;
642 return bnx2x_config_rx_mode(bp, &ramrod);
643 }
644
645 int bnx2x_vf_queue_teardown(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid)
646 {
647 int rc;
648
649 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
650
651 /* Remove all classification configuration for leading queue */
652 if (qid == LEADING_IDX) {
653 rc = bnx2x_vf_rxmode(bp, vf, qid, 0);
654 if (rc)
655 goto op_err;
656
657 /* Remove filtering if feasible */
658 if (bnx2x_validate_vf_sp_objs(bp, vf, true)) {
659 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid,
660 false,
661 BNX2X_VF_FILTER_VLAN_MAC);
662 if (rc)
663 goto op_err;
664 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid,
665 false,
666 BNX2X_VF_FILTER_VLAN);
667 if (rc)
668 goto op_err;
669 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid,
670 false,
671 BNX2X_VF_FILTER_MAC);
672 if (rc)
673 goto op_err;
674 rc = bnx2x_vf_mcast(bp, vf, NULL, 0, false);
675 if (rc)
676 goto op_err;
677 }
678 }
679
680 /* Destroy queue */
681 rc = bnx2x_vf_queue_destroy(bp, vf, qid);
682 if (rc)
683 goto op_err;
684 return rc;
685 op_err:
686 BNX2X_ERR("vf[%d:%d] error: rc %d\n",
687 vf->abs_vfid, qid, rc);
688 return rc;
689 }
690
691 /* VF enable primitives
692 * when pretend is required the caller is responsible
693 * for calling pretend prior to calling these routines
694 */
695
696 /* internal vf enable - until vf is enabled internally all transactions
697 * are blocked. This routine should always be called last with pretend.
698 */
699 static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable)
700 {
701 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0);
702 }
703
704 /* clears vf error in all semi blocks */
705 static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid)
706 {
707 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid);
708 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid);
709 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid);
710 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid);
711 }
712
713 static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid)
714 {
715 u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5;
716 u32 was_err_reg = 0;
717
718 switch (was_err_group) {
719 case 0:
720 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR;
721 break;
722 case 1:
723 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR;
724 break;
725 case 2:
726 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR;
727 break;
728 case 3:
729 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR;
730 break;
731 }
732 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f));
733 }
734
735 static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf)
736 {
737 int i;
738 u32 val;
739
740 /* Set VF masks and configuration - pretend */
741 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
742
743 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
744 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
745 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
746 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
747 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
748 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
749
750 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
751 val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN);
752 val &= ~IGU_VF_CONF_PARENT_MASK;
753 val |= (BP_ABS_FUNC(bp) >> 1) << IGU_VF_CONF_PARENT_SHIFT;
754 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);
755
756 DP(BNX2X_MSG_IOV,
757 "value in IGU_REG_VF_CONFIGURATION of vf %d after write is 0x%08x\n",
758 vf->abs_vfid, val);
759
760 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
761
762 /* iterate over all queues, clear sb consumer */
763 for (i = 0; i < vf_sb_count(vf); i++) {
764 u8 igu_sb_id = vf_igu_sb(vf, i);
765
766 /* zero prod memory */
767 REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0);
768
769 /* clear sb state machine */
770 bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id,
771 false /* VF */);
772
773 /* disable + update */
774 bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0,
775 IGU_INT_DISABLE, 1);
776 }
777 }
778
779 void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid)
780 {
781 /* set the VF-PF association in the FW */
782 storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp));
783 storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1);
784
785 /* clear vf errors*/
786 bnx2x_vf_semi_clear_err(bp, abs_vfid);
787 bnx2x_vf_pglue_clear_err(bp, abs_vfid);
788
789 /* internal vf-enable - pretend */
790 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid));
791 DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid);
792 bnx2x_vf_enable_internal(bp, true);
793 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
794 }
795
796 static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf)
797 {
798 /* Reset vf in IGU interrupts are still disabled */
799 bnx2x_vf_igu_reset(bp, vf);
800
801 /* pretend to enable the vf with the PBF */
802 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
803 REG_WR(bp, PBF_REG_DISABLE_VF, 0);
804 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
805 }
806
807 static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid)
808 {
809 struct pci_dev *dev;
810 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
811
812 if (!vf)
813 return false;
814
815 dev = pci_get_domain_bus_and_slot(vf->domain, vf->bus, vf->devfn);
816 if (dev)
817 return bnx2x_is_pcie_pending(dev);
818 return false;
819 }
820
821 int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid)
822 {
823 /* Verify no pending pci transactions */
824 if (bnx2x_vf_is_pcie_pending(bp, abs_vfid))
825 BNX2X_ERR("PCIE Transactions still pending\n");
826
827 return 0;
828 }
829
830 /* must be called after the number of PF queues and the number of VFs are
831 * both known
832 */
833 static void
834 bnx2x_iov_static_resc(struct bnx2x *bp, struct bnx2x_virtf *vf)
835 {
836 struct vf_pf_resc_request *resc = &vf->alloc_resc;
837
838 /* will be set only during VF-ACQUIRE */
839 resc->num_rxqs = 0;
840 resc->num_txqs = 0;
841
842 resc->num_mac_filters = VF_MAC_CREDIT_CNT;
843 resc->num_vlan_filters = VF_VLAN_CREDIT_CNT;
844
845 /* no real limitation */
846 resc->num_mc_filters = 0;
847
848 /* num_sbs already set */
849 resc->num_sbs = vf->sb_count;
850 }
851
852 /* FLR routines: */
853 static void bnx2x_vf_free_resc(struct bnx2x *bp, struct bnx2x_virtf *vf)
854 {
855 /* reset the state variables */
856 bnx2x_iov_static_resc(bp, vf);
857 vf->state = VF_FREE;
858 }
859
860 static void bnx2x_vf_flr_clnup_hw(struct bnx2x *bp, struct bnx2x_virtf *vf)
861 {
862 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
863
864 /* DQ usage counter */
865 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
866 bnx2x_flr_clnup_poll_hw_counter(bp, DORQ_REG_VF_USAGE_CNT,
867 "DQ VF usage counter timed out",
868 poll_cnt);
869 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
870
871 /* FW cleanup command - poll for the results */
872 if (bnx2x_send_final_clnup(bp, (u8)FW_VF_HANDLE(vf->abs_vfid),
873 poll_cnt))
874 BNX2X_ERR("VF[%d] Final cleanup timed-out\n", vf->abs_vfid);
875
876 /* verify TX hw is flushed */
877 bnx2x_tx_hw_flushed(bp, poll_cnt);
878 }
879
880 static void bnx2x_vf_flr(struct bnx2x *bp, struct bnx2x_virtf *vf)
881 {
882 int rc, i;
883
884 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
885
886 /* the cleanup operations are valid if and only if the VF
887 * was first acquired.
888 */
889 for (i = 0; i < vf_rxq_count(vf); i++) {
890 rc = bnx2x_vf_queue_flr(bp, vf, i);
891 if (rc)
892 goto out;
893 }
894
895 /* remove multicasts */
896 bnx2x_vf_mcast(bp, vf, NULL, 0, true);
897
898 /* dispatch final cleanup and wait for HW queues to flush */
899 bnx2x_vf_flr_clnup_hw(bp, vf);
900
901 /* release VF resources */
902 bnx2x_vf_free_resc(bp, vf);
903
904 vf->malicious = false;
905
906 /* re-open the mailbox */
907 bnx2x_vf_enable_mbx(bp, vf->abs_vfid);
908 return;
909 out:
910 BNX2X_ERR("vf[%d:%d] failed flr: rc %d\n",
911 vf->abs_vfid, i, rc);
912 }
913
914 static void bnx2x_vf_flr_clnup(struct bnx2x *bp)
915 {
916 struct bnx2x_virtf *vf;
917 int i;
918
919 for (i = 0; i < BNX2X_NR_VIRTFN(bp); i++) {
920 /* VF should be RESET & in FLR cleanup states */
921 if (bnx2x_vf(bp, i, state) != VF_RESET ||
922 !bnx2x_vf(bp, i, flr_clnup_stage))
923 continue;
924
925 DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n",
926 i, BNX2X_NR_VIRTFN(bp));
927
928 vf = BP_VF(bp, i);
929
930 /* lock the vf pf channel */
931 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR);
932
933 /* invoke the VF FLR SM */
934 bnx2x_vf_flr(bp, vf);
935
936 /* mark the VF to be ACKED and continue */
937 vf->flr_clnup_stage = false;
938 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR);
939 }
940
941 /* Acknowledge the handled VFs.
942 * we are acknowledge all the vfs which an flr was requested for, even
943 * if amongst them there are such that we never opened, since the mcp
944 * will interrupt us immediately again if we only ack some of the bits,
945 * resulting in an endless loop. This can happen for example in KVM
946 * where an 'all ones' flr request is sometimes given by hyper visor
947 */
948 DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n",
949 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]);
950 for (i = 0; i < FLRD_VFS_DWORDS; i++)
951 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i],
952 bp->vfdb->flrd_vfs[i]);
953
954 bnx2x_fw_command(bp, DRV_MSG_CODE_VF_DISABLED_DONE, 0);
955
956 /* clear the acked bits - better yet if the MCP implemented
957 * write to clear semantics
958 */
959 for (i = 0; i < FLRD_VFS_DWORDS; i++)
960 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 0);
961 }
962
963 void bnx2x_vf_handle_flr_event(struct bnx2x *bp)
964 {
965 int i;
966
967 /* Read FLR'd VFs */
968 for (i = 0; i < FLRD_VFS_DWORDS; i++)
969 bp->vfdb->flrd_vfs[i] = SHMEM2_RD(bp, mcp_vf_disabled[i]);
970
971 DP(BNX2X_MSG_MCP,
972 "DRV_STATUS_VF_DISABLED received for vfs 0x%x 0x%x\n",
973 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]);
974
975 for_each_vf(bp, i) {
976 struct bnx2x_virtf *vf = BP_VF(bp, i);
977 u32 reset = 0;
978
979 if (vf->abs_vfid < 32)
980 reset = bp->vfdb->flrd_vfs[0] & (1 << vf->abs_vfid);
981 else
982 reset = bp->vfdb->flrd_vfs[1] &
983 (1 << (vf->abs_vfid - 32));
984
985 if (reset) {
986 /* set as reset and ready for cleanup */
987 vf->state = VF_RESET;
988 vf->flr_clnup_stage = true;
989
990 DP(BNX2X_MSG_IOV,
991 "Initiating Final cleanup for VF %d\n",
992 vf->abs_vfid);
993 }
994 }
995
996 /* do the FLR cleanup for all marked VFs*/
997 bnx2x_vf_flr_clnup(bp);
998 }
999
1000 /* IOV global initialization routines */
1001 void bnx2x_iov_init_dq(struct bnx2x *bp)
1002 {
1003 if (!IS_SRIOV(bp))
1004 return;
1005
1006 /* Set the DQ such that the CID reflect the abs_vfid */
1007 REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0);
1008 REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS));
1009
1010 /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to
1011 * the PF L2 queues
1012 */
1013 REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID);
1014
1015 /* The VF window size is the log2 of the max number of CIDs per VF */
1016 REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND);
1017
1018 /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match
1019 * the Pf doorbell size although the 2 are independent.
1020 */
1021 REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3);
1022
1023 /* No security checks for now -
1024 * configure single rule (out of 16) mask = 0x1, value = 0x0,
1025 * CID range 0 - 0x1ffff
1026 */
1027 REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1);
1028 REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0);
1029 REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);
1030 REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);
1031
1032 /* set the VF doorbell threshold. This threshold represents the amount
1033 * of doorbells allowed in the main DORQ fifo for a specific VF.
1034 */
1035 REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64);
1036 }
1037
1038 void bnx2x_iov_init_dmae(struct bnx2x *bp)
1039 {
1040 if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV))
1041 REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0);
1042 }
1043
1044 static int bnx2x_vf_domain(struct bnx2x *bp, int vfid)
1045 {
1046 struct pci_dev *dev = bp->pdev;
1047
1048 return pci_domain_nr(dev->bus);
1049 }
1050
1051 static int bnx2x_vf_bus(struct bnx2x *bp, int vfid)
1052 {
1053 struct pci_dev *dev = bp->pdev;
1054 struct bnx2x_sriov *iov = &bp->vfdb->sriov;
1055
1056 return dev->bus->number + ((dev->devfn + iov->offset +
1057 iov->stride * vfid) >> 8);
1058 }
1059
1060 static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid)
1061 {
1062 struct pci_dev *dev = bp->pdev;
1063 struct bnx2x_sriov *iov = &bp->vfdb->sriov;
1064
1065 return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff;
1066 }
1067
1068 static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf)
1069 {
1070 int i, n;
1071 struct pci_dev *dev = bp->pdev;
1072 struct bnx2x_sriov *iov = &bp->vfdb->sriov;
1073
1074 for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) {
1075 u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i);
1076 u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i);
1077
1078 size /= iov->total;
1079 vf->bars[n].bar = start + size * vf->abs_vfid;
1080 vf->bars[n].size = size;
1081 }
1082 }
1083
1084 static int
1085 bnx2x_get_vf_igu_cam_info(struct bnx2x *bp)
1086 {
1087 int sb_id;
1088 u32 val;
1089 u8 fid, current_pf = 0;
1090
1091 /* IGU in normal mode - read CAM */
1092 for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) {
1093 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4);
1094 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
1095 continue;
1096 fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID);
1097 if (fid & IGU_FID_ENCODE_IS_PF)
1098 current_pf = fid & IGU_FID_PF_NUM_MASK;
1099 else if (current_pf == BP_FUNC(bp))
1100 bnx2x_vf_set_igu_info(bp, sb_id,
1101 (fid & IGU_FID_VF_NUM_MASK));
1102 DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n",
1103 ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"),
1104 ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) :
1105 (fid & IGU_FID_VF_NUM_MASK)), sb_id,
1106 GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR));
1107 }
1108 DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool);
1109 return BP_VFDB(bp)->vf_sbs_pool;
1110 }
1111
1112 static void __bnx2x_iov_free_vfdb(struct bnx2x *bp)
1113 {
1114 if (bp->vfdb) {
1115 kfree(bp->vfdb->vfqs);
1116 kfree(bp->vfdb->vfs);
1117 kfree(bp->vfdb);
1118 }
1119 bp->vfdb = NULL;
1120 }
1121
1122 static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov)
1123 {
1124 int pos;
1125 struct pci_dev *dev = bp->pdev;
1126
1127 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
1128 if (!pos) {
1129 BNX2X_ERR("failed to find SRIOV capability in device\n");
1130 return -ENODEV;
1131 }
1132
1133 iov->pos = pos;
1134 DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos);
1135 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl);
1136 pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total);
1137 pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial);
1138 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
1139 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
1140 pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
1141 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
1142 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
1143
1144 return 0;
1145 }
1146
1147 static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov)
1148 {
1149 u32 val;
1150
1151 /* read the SRIOV capability structure
1152 * The fields can be read via configuration read or
1153 * directly from the device (starting at offset PCICFG_OFFSET)
1154 */
1155 if (bnx2x_sriov_pci_cfg_info(bp, iov))
1156 return -ENODEV;
1157
1158 /* get the number of SRIOV bars */
1159 iov->nres = 0;
1160
1161 /* read the first_vfid */
1162 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF);
1163 iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK)
1164 * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp));
1165
1166 DP(BNX2X_MSG_IOV,
1167 "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n",
1168 BP_FUNC(bp),
1169 iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total,
1170 iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz);
1171
1172 return 0;
1173 }
1174
1175 /* must be called after PF bars are mapped */
1176 int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param,
1177 int num_vfs_param)
1178 {
1179 int err, i;
1180 struct bnx2x_sriov *iov;
1181 struct pci_dev *dev = bp->pdev;
1182
1183 bp->vfdb = NULL;
1184
1185 /* verify is pf */
1186 if (IS_VF(bp))
1187 return 0;
1188
1189 /* verify sriov capability is present in configuration space */
1190 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV))
1191 return 0;
1192
1193 /* verify chip revision */
1194 if (CHIP_IS_E1x(bp))
1195 return 0;
1196
1197 /* check if SRIOV support is turned off */
1198 if (!num_vfs_param)
1199 return 0;
1200
1201 /* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */
1202 if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) {
1203 BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n",
1204 BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID);
1205 return 0;
1206 }
1207
1208 /* SRIOV can be enabled only with MSIX */
1209 if (int_mode_param == BNX2X_INT_MODE_MSI ||
1210 int_mode_param == BNX2X_INT_MODE_INTX) {
1211 BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n");
1212 return 0;
1213 }
1214
1215 err = -EIO;
1216 /* verify ari is enabled */
1217 if (!pci_ari_enabled(bp->pdev->bus)) {
1218 BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n");
1219 return 0;
1220 }
1221
1222 /* verify igu is in normal mode */
1223 if (CHIP_INT_MODE_IS_BC(bp)) {
1224 BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n");
1225 return 0;
1226 }
1227
1228 /* allocate the vfs database */
1229 bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL);
1230 if (!bp->vfdb) {
1231 BNX2X_ERR("failed to allocate vf database\n");
1232 err = -ENOMEM;
1233 goto failed;
1234 }
1235
1236 /* get the sriov info - Linux already collected all the pertinent
1237 * information, however the sriov structure is for the private use
1238 * of the pci module. Also we want this information regardless
1239 * of the hyper-visor.
1240 */
1241 iov = &(bp->vfdb->sriov);
1242 err = bnx2x_sriov_info(bp, iov);
1243 if (err)
1244 goto failed;
1245
1246 /* SR-IOV capability was enabled but there are no VFs*/
1247 if (iov->total == 0)
1248 goto failed;
1249
1250 iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param);
1251
1252 DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n",
1253 num_vfs_param, iov->nr_virtfn);
1254
1255 /* allocate the vf array */
1256 bp->vfdb->vfs = kcalloc(BNX2X_NR_VIRTFN(bp),
1257 sizeof(struct bnx2x_virtf),
1258 GFP_KERNEL);
1259 if (!bp->vfdb->vfs) {
1260 BNX2X_ERR("failed to allocate vf array\n");
1261 err = -ENOMEM;
1262 goto failed;
1263 }
1264
1265 /* Initial VF init - index and abs_vfid - nr_virtfn must be set */
1266 for_each_vf(bp, i) {
1267 bnx2x_vf(bp, i, index) = i;
1268 bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i;
1269 bnx2x_vf(bp, i, state) = VF_FREE;
1270 mutex_init(&bnx2x_vf(bp, i, op_mutex));
1271 bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE;
1272 }
1273
1274 /* re-read the IGU CAM for VFs - index and abs_vfid must be set */
1275 if (!bnx2x_get_vf_igu_cam_info(bp)) {
1276 BNX2X_ERR("No entries in IGU CAM for vfs\n");
1277 err = -EINVAL;
1278 goto failed;
1279 }
1280
1281 /* allocate the queue arrays for all VFs */
1282 bp->vfdb->vfqs = kcalloc(BNX2X_MAX_NUM_VF_QUEUES,
1283 sizeof(struct bnx2x_vf_queue),
1284 GFP_KERNEL);
1285
1286 if (!bp->vfdb->vfqs) {
1287 BNX2X_ERR("failed to allocate vf queue array\n");
1288 err = -ENOMEM;
1289 goto failed;
1290 }
1291
1292 /* Prepare the VFs event synchronization mechanism */
1293 mutex_init(&bp->vfdb->event_mutex);
1294
1295 mutex_init(&bp->vfdb->bulletin_mutex);
1296
1297 if (SHMEM2_HAS(bp, sriov_switch_mode))
1298 SHMEM2_WR(bp, sriov_switch_mode, SRIOV_SWITCH_MODE_VEB);
1299
1300 return 0;
1301 failed:
1302 DP(BNX2X_MSG_IOV, "Failed err=%d\n", err);
1303 __bnx2x_iov_free_vfdb(bp);
1304 return err;
1305 }
1306
1307 void bnx2x_iov_remove_one(struct bnx2x *bp)
1308 {
1309 int vf_idx;
1310
1311 /* if SRIOV is not enabled there's nothing to do */
1312 if (!IS_SRIOV(bp))
1313 return;
1314
1315 bnx2x_disable_sriov(bp);
1316
1317 /* disable access to all VFs */
1318 for (vf_idx = 0; vf_idx < bp->vfdb->sriov.total; vf_idx++) {
1319 bnx2x_pretend_func(bp,
1320 HW_VF_HANDLE(bp,
1321 bp->vfdb->sriov.first_vf_in_pf +
1322 vf_idx));
1323 DP(BNX2X_MSG_IOV, "disabling internal access for vf %d\n",
1324 bp->vfdb->sriov.first_vf_in_pf + vf_idx);
1325 bnx2x_vf_enable_internal(bp, 0);
1326 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1327 }
1328
1329 /* free vf database */
1330 __bnx2x_iov_free_vfdb(bp);
1331 }
1332
1333 void bnx2x_iov_free_mem(struct bnx2x *bp)
1334 {
1335 int i;
1336
1337 if (!IS_SRIOV(bp))
1338 return;
1339
1340 /* free vfs hw contexts */
1341 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
1342 struct hw_dma *cxt = &bp->vfdb->context[i];
1343 BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size);
1344 }
1345
1346 BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr,
1347 BP_VFDB(bp)->sp_dma.mapping,
1348 BP_VFDB(bp)->sp_dma.size);
1349
1350 BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr,
1351 BP_VF_MBX_DMA(bp)->mapping,
1352 BP_VF_MBX_DMA(bp)->size);
1353
1354 BNX2X_PCI_FREE(BP_VF_BULLETIN_DMA(bp)->addr,
1355 BP_VF_BULLETIN_DMA(bp)->mapping,
1356 BP_VF_BULLETIN_DMA(bp)->size);
1357 }
1358
1359 int bnx2x_iov_alloc_mem(struct bnx2x *bp)
1360 {
1361 size_t tot_size;
1362 int i, rc = 0;
1363
1364 if (!IS_SRIOV(bp))
1365 return rc;
1366
1367 /* allocate vfs hw contexts */
1368 tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) *
1369 BNX2X_CIDS_PER_VF * sizeof(union cdu_context);
1370
1371 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
1372 struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i);
1373 cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ);
1374
1375 if (cxt->size) {
1376 cxt->addr = BNX2X_PCI_ALLOC(&cxt->mapping, cxt->size);
1377 if (!cxt->addr)
1378 goto alloc_mem_err;
1379 } else {
1380 cxt->addr = NULL;
1381 cxt->mapping = 0;
1382 }
1383 tot_size -= cxt->size;
1384 }
1385
1386 /* allocate vfs ramrods dma memory - client_init and set_mac */
1387 tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp);
1388 BP_VFDB(bp)->sp_dma.addr = BNX2X_PCI_ALLOC(&BP_VFDB(bp)->sp_dma.mapping,
1389 tot_size);
1390 if (!BP_VFDB(bp)->sp_dma.addr)
1391 goto alloc_mem_err;
1392 BP_VFDB(bp)->sp_dma.size = tot_size;
1393
1394 /* allocate mailboxes */
1395 tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE;
1396 BP_VF_MBX_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_MBX_DMA(bp)->mapping,
1397 tot_size);
1398 if (!BP_VF_MBX_DMA(bp)->addr)
1399 goto alloc_mem_err;
1400
1401 BP_VF_MBX_DMA(bp)->size = tot_size;
1402
1403 /* allocate local bulletin boards */
1404 tot_size = BNX2X_NR_VIRTFN(bp) * BULLETIN_CONTENT_SIZE;
1405 BP_VF_BULLETIN_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_BULLETIN_DMA(bp)->mapping,
1406 tot_size);
1407 if (!BP_VF_BULLETIN_DMA(bp)->addr)
1408 goto alloc_mem_err;
1409
1410 BP_VF_BULLETIN_DMA(bp)->size = tot_size;
1411
1412 return 0;
1413
1414 alloc_mem_err:
1415 return -ENOMEM;
1416 }
1417
1418 static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf,
1419 struct bnx2x_vf_queue *q)
1420 {
1421 u8 cl_id = vfq_cl_id(vf, q);
1422 u8 func_id = FW_VF_HANDLE(vf->abs_vfid);
1423 unsigned long q_type = 0;
1424
1425 set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
1426 set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
1427
1428 /* Queue State object */
1429 bnx2x_init_queue_obj(bp, &q->sp_obj,
1430 cl_id, &q->cid, 1, func_id,
1431 bnx2x_vf_sp(bp, vf, q_data),
1432 bnx2x_vf_sp_map(bp, vf, q_data),
1433 q_type);
1434
1435 /* sp indication is set only when vlan/mac/etc. are initialized */
1436 q->sp_initialized = false;
1437
1438 DP(BNX2X_MSG_IOV,
1439 "initialized vf %d's queue object. func id set to %d. cid set to 0x%x\n",
1440 vf->abs_vfid, q->sp_obj.func_id, q->cid);
1441 }
1442
1443 static int bnx2x_max_speed_cap(struct bnx2x *bp)
1444 {
1445 u32 supported = bp->port.supported[bnx2x_get_link_cfg_idx(bp)];
1446
1447 if (supported &
1448 (SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full))
1449 return 20000;
1450
1451 return 10000; /* assume lowest supported speed is 10G */
1452 }
1453
1454 int bnx2x_iov_link_update_vf(struct bnx2x *bp, int idx)
1455 {
1456 struct bnx2x_link_report_data *state = &bp->last_reported_link;
1457 struct pf_vf_bulletin_content *bulletin;
1458 struct bnx2x_virtf *vf;
1459 bool update = true;
1460 int rc = 0;
1461
1462 /* sanity and init */
1463 rc = bnx2x_vf_op_prep(bp, idx, &vf, &bulletin, false);
1464 if (rc)
1465 return rc;
1466
1467 mutex_lock(&bp->vfdb->bulletin_mutex);
1468
1469 if (vf->link_cfg == IFLA_VF_LINK_STATE_AUTO) {
1470 bulletin->valid_bitmap |= 1 << LINK_VALID;
1471
1472 bulletin->link_speed = state->line_speed;
1473 bulletin->link_flags = 0;
1474 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1475 &state->link_report_flags))
1476 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN;
1477 if (test_bit(BNX2X_LINK_REPORT_FD,
1478 &state->link_report_flags))
1479 bulletin->link_flags |= VFPF_LINK_REPORT_FULL_DUPLEX;
1480 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1481 &state->link_report_flags))
1482 bulletin->link_flags |= VFPF_LINK_REPORT_RX_FC_ON;
1483 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1484 &state->link_report_flags))
1485 bulletin->link_flags |= VFPF_LINK_REPORT_TX_FC_ON;
1486 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_DISABLE &&
1487 !(bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) {
1488 bulletin->valid_bitmap |= 1 << LINK_VALID;
1489 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN;
1490 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_ENABLE &&
1491 (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) {
1492 bulletin->valid_bitmap |= 1 << LINK_VALID;
1493 bulletin->link_speed = bnx2x_max_speed_cap(bp);
1494 bulletin->link_flags &= ~VFPF_LINK_REPORT_LINK_DOWN;
1495 } else {
1496 update = false;
1497 }
1498
1499 if (update) {
1500 DP(NETIF_MSG_LINK | BNX2X_MSG_IOV,
1501 "vf %d mode %u speed %d flags %x\n", idx,
1502 vf->link_cfg, bulletin->link_speed, bulletin->link_flags);
1503
1504 /* Post update on VF's bulletin board */
1505 rc = bnx2x_post_vf_bulletin(bp, idx);
1506 if (rc) {
1507 BNX2X_ERR("failed to update VF[%d] bulletin\n", idx);
1508 goto out;
1509 }
1510 }
1511
1512 out:
1513 mutex_unlock(&bp->vfdb->bulletin_mutex);
1514 return rc;
1515 }
1516
1517 int bnx2x_set_vf_link_state(struct net_device *dev, int idx, int link_state)
1518 {
1519 struct bnx2x *bp = netdev_priv(dev);
1520 struct bnx2x_virtf *vf = BP_VF(bp, idx);
1521
1522 if (!vf)
1523 return -EINVAL;
1524
1525 if (vf->link_cfg == link_state)
1526 return 0; /* nothing todo */
1527
1528 vf->link_cfg = link_state;
1529
1530 return bnx2x_iov_link_update_vf(bp, idx);
1531 }
1532
1533 void bnx2x_iov_link_update(struct bnx2x *bp)
1534 {
1535 int vfid;
1536
1537 if (!IS_SRIOV(bp))
1538 return;
1539
1540 for_each_vf(bp, vfid)
1541 bnx2x_iov_link_update_vf(bp, vfid);
1542 }
1543
1544 /* called by bnx2x_nic_load */
1545 int bnx2x_iov_nic_init(struct bnx2x *bp)
1546 {
1547 int vfid;
1548
1549 if (!IS_SRIOV(bp)) {
1550 DP(BNX2X_MSG_IOV, "vfdb was not allocated\n");
1551 return 0;
1552 }
1553
1554 DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn);
1555
1556 /* let FLR complete ... */
1557 msleep(100);
1558
1559 /* initialize vf database */
1560 for_each_vf(bp, vfid) {
1561 struct bnx2x_virtf *vf = BP_VF(bp, vfid);
1562
1563 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) *
1564 BNX2X_CIDS_PER_VF;
1565
1566 union cdu_context *base_cxt = (union cdu_context *)
1567 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr +
1568 (base_vf_cid & (ILT_PAGE_CIDS-1));
1569
1570 DP(BNX2X_MSG_IOV,
1571 "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n",
1572 vf->abs_vfid, vf_sb_count(vf), base_vf_cid,
1573 BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt);
1574
1575 /* init statically provisioned resources */
1576 bnx2x_iov_static_resc(bp, vf);
1577
1578 /* queues are initialized during VF-ACQUIRE */
1579 vf->filter_state = 0;
1580 vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id);
1581
1582 bnx2x_init_credit_pool(&vf->vf_vlans_pool, 0,
1583 vf_vlan_rules_cnt(vf));
1584 bnx2x_init_credit_pool(&vf->vf_macs_pool, 0,
1585 vf_mac_rules_cnt(vf));
1586
1587 /* init mcast object - This object will be re-initialized
1588 * during VF-ACQUIRE with the proper cl_id and cid.
1589 * It needs to be initialized here so that it can be safely
1590 * handled by a subsequent FLR flow.
1591 */
1592 bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF,
1593 0xFF, 0xFF, 0xFF,
1594 bnx2x_vf_sp(bp, vf, mcast_rdata),
1595 bnx2x_vf_sp_map(bp, vf, mcast_rdata),
1596 BNX2X_FILTER_MCAST_PENDING,
1597 &vf->filter_state,
1598 BNX2X_OBJ_TYPE_RX_TX);
1599
1600 /* set the mailbox message addresses */
1601 BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *)
1602 (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid *
1603 MBX_MSG_ALIGNED_SIZE);
1604
1605 BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping +
1606 vfid * MBX_MSG_ALIGNED_SIZE;
1607
1608 /* Enable vf mailbox */
1609 bnx2x_vf_enable_mbx(bp, vf->abs_vfid);
1610 }
1611
1612 /* Final VF init */
1613 for_each_vf(bp, vfid) {
1614 struct bnx2x_virtf *vf = BP_VF(bp, vfid);
1615
1616 /* fill in the BDF and bars */
1617 vf->domain = bnx2x_vf_domain(bp, vfid);
1618 vf->bus = bnx2x_vf_bus(bp, vfid);
1619 vf->devfn = bnx2x_vf_devfn(bp, vfid);
1620 bnx2x_vf_set_bars(bp, vf);
1621
1622 DP(BNX2X_MSG_IOV,
1623 "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n",
1624 vf->abs_vfid, vf->bus, vf->devfn,
1625 (unsigned)vf->bars[0].bar, vf->bars[0].size,
1626 (unsigned)vf->bars[1].bar, vf->bars[1].size,
1627 (unsigned)vf->bars[2].bar, vf->bars[2].size);
1628 }
1629
1630 return 0;
1631 }
1632
1633 /* called by bnx2x_chip_cleanup */
1634 int bnx2x_iov_chip_cleanup(struct bnx2x *bp)
1635 {
1636 int i;
1637
1638 if (!IS_SRIOV(bp))
1639 return 0;
1640
1641 /* release all the VFs */
1642 for_each_vf(bp, i)
1643 bnx2x_vf_release(bp, BP_VF(bp, i));
1644
1645 return 0;
1646 }
1647
1648 /* called by bnx2x_init_hw_func, returns the next ilt line */
1649 int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line)
1650 {
1651 int i;
1652 struct bnx2x_ilt *ilt = BP_ILT(bp);
1653
1654 if (!IS_SRIOV(bp))
1655 return line;
1656
1657 /* set vfs ilt lines */
1658 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
1659 struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i);
1660
1661 ilt->lines[line+i].page = hw_cxt->addr;
1662 ilt->lines[line+i].page_mapping = hw_cxt->mapping;
1663 ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */
1664 }
1665 return line + i;
1666 }
1667
1668 static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid)
1669 {
1670 return ((cid >= BNX2X_FIRST_VF_CID) &&
1671 ((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS));
1672 }
1673
1674 static
1675 void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp,
1676 struct bnx2x_vf_queue *vfq,
1677 union event_ring_elem *elem)
1678 {
1679 unsigned long ramrod_flags = 0;
1680 int rc = 0;
1681 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
1682
1683 /* Always push next commands out, don't wait here */
1684 set_bit(RAMROD_CONT, &ramrod_flags);
1685
1686 switch (echo >> BNX2X_SWCID_SHIFT) {
1687 case BNX2X_FILTER_MAC_PENDING:
1688 rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem,
1689 &ramrod_flags);
1690 break;
1691 case BNX2X_FILTER_VLAN_PENDING:
1692 rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem,
1693 &ramrod_flags);
1694 break;
1695 default:
1696 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
1697 return;
1698 }
1699 if (rc < 0)
1700 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
1701 else if (rc > 0)
1702 DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n");
1703 }
1704
1705 static
1706 void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp,
1707 struct bnx2x_virtf *vf)
1708 {
1709 struct bnx2x_mcast_ramrod_params rparam = {NULL};
1710 int rc;
1711
1712 rparam.mcast_obj = &vf->mcast_obj;
1713 vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw);
1714
1715 /* If there are pending mcast commands - send them */
1716 if (vf->mcast_obj.check_pending(&vf->mcast_obj)) {
1717 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
1718 if (rc < 0)
1719 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
1720 rc);
1721 }
1722 }
1723
1724 static
1725 void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp,
1726 struct bnx2x_virtf *vf)
1727 {
1728 smp_mb__before_atomic();
1729 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state);
1730 smp_mb__after_atomic();
1731 }
1732
1733 static void bnx2x_vf_handle_rss_update_eqe(struct bnx2x *bp,
1734 struct bnx2x_virtf *vf)
1735 {
1736 vf->rss_conf_obj.raw.clear_pending(&vf->rss_conf_obj.raw);
1737 }
1738
1739 int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem)
1740 {
1741 struct bnx2x_virtf *vf;
1742 int qidx = 0, abs_vfid;
1743 u8 opcode;
1744 u16 cid = 0xffff;
1745
1746 if (!IS_SRIOV(bp))
1747 return 1;
1748
1749 /* first get the cid - the only events we handle here are cfc-delete
1750 * and set-mac completion
1751 */
1752 opcode = elem->message.opcode;
1753
1754 switch (opcode) {
1755 case EVENT_RING_OPCODE_CFC_DEL:
1756 cid = SW_CID(elem->message.data.cfc_del_event.cid);
1757 DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid);
1758 break;
1759 case EVENT_RING_OPCODE_CLASSIFICATION_RULES:
1760 case EVENT_RING_OPCODE_MULTICAST_RULES:
1761 case EVENT_RING_OPCODE_FILTERS_RULES:
1762 case EVENT_RING_OPCODE_RSS_UPDATE_RULES:
1763 cid = SW_CID(elem->message.data.eth_event.echo);
1764 DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid);
1765 break;
1766 case EVENT_RING_OPCODE_VF_FLR:
1767 abs_vfid = elem->message.data.vf_flr_event.vf_id;
1768 DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n",
1769 abs_vfid);
1770 goto get_vf;
1771 case EVENT_RING_OPCODE_MALICIOUS_VF:
1772 abs_vfid = elem->message.data.malicious_vf_event.vf_id;
1773 BNX2X_ERR("Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n",
1774 abs_vfid,
1775 elem->message.data.malicious_vf_event.err_id);
1776 goto get_vf;
1777 default:
1778 return 1;
1779 }
1780
1781 /* check if the cid is the VF range */
1782 if (!bnx2x_iov_is_vf_cid(bp, cid)) {
1783 DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid);
1784 return 1;
1785 }
1786
1787 /* extract vf and rxq index from vf_cid - relies on the following:
1788 * 1. vfid on cid reflects the true abs_vfid
1789 * 2. The max number of VFs (per path) is 64
1790 */
1791 qidx = cid & ((1 << BNX2X_VF_CID_WND)-1);
1792 abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1);
1793 get_vf:
1794 vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
1795
1796 if (!vf) {
1797 BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n",
1798 cid, abs_vfid);
1799 return 0;
1800 }
1801
1802 switch (opcode) {
1803 case EVENT_RING_OPCODE_CFC_DEL:
1804 DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n",
1805 vf->abs_vfid, qidx);
1806 vfq_get(vf, qidx)->sp_obj.complete_cmd(bp,
1807 &vfq_get(vf,
1808 qidx)->sp_obj,
1809 BNX2X_Q_CMD_CFC_DEL);
1810 break;
1811 case EVENT_RING_OPCODE_CLASSIFICATION_RULES:
1812 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n",
1813 vf->abs_vfid, qidx);
1814 bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem);
1815 break;
1816 case EVENT_RING_OPCODE_MULTICAST_RULES:
1817 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n",
1818 vf->abs_vfid, qidx);
1819 bnx2x_vf_handle_mcast_eqe(bp, vf);
1820 break;
1821 case EVENT_RING_OPCODE_FILTERS_RULES:
1822 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n",
1823 vf->abs_vfid, qidx);
1824 bnx2x_vf_handle_filters_eqe(bp, vf);
1825 break;
1826 case EVENT_RING_OPCODE_RSS_UPDATE_RULES:
1827 DP(BNX2X_MSG_IOV, "got VF [%d:%d] RSS update ramrod\n",
1828 vf->abs_vfid, qidx);
1829 bnx2x_vf_handle_rss_update_eqe(bp, vf);
1830 /* fall through */
1831 case EVENT_RING_OPCODE_VF_FLR:
1832 /* Do nothing for now */
1833 return 0;
1834 case EVENT_RING_OPCODE_MALICIOUS_VF:
1835 vf->malicious = true;
1836 return 0;
1837 }
1838
1839 return 0;
1840 }
1841
1842 static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid)
1843 {
1844 /* extract the vf from vf_cid - relies on the following:
1845 * 1. vfid on cid reflects the true abs_vfid
1846 * 2. The max number of VFs (per path) is 64
1847 */
1848 int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1);
1849 return bnx2x_vf_by_abs_fid(bp, abs_vfid);
1850 }
1851
1852 void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid,
1853 struct bnx2x_queue_sp_obj **q_obj)
1854 {
1855 struct bnx2x_virtf *vf;
1856
1857 if (!IS_SRIOV(bp))
1858 return;
1859
1860 vf = bnx2x_vf_by_cid(bp, vf_cid);
1861
1862 if (vf) {
1863 /* extract queue index from vf_cid - relies on the following:
1864 * 1. vfid on cid reflects the true abs_vfid
1865 * 2. The max number of VFs (per path) is 64
1866 */
1867 int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1);
1868 *q_obj = &bnx2x_vfq(vf, q_index, sp_obj);
1869 } else {
1870 BNX2X_ERR("No vf matching cid %d\n", vf_cid);
1871 }
1872 }
1873
1874 void bnx2x_iov_adjust_stats_req(struct bnx2x *bp)
1875 {
1876 int i;
1877 int first_queue_query_index, num_queues_req;
1878 dma_addr_t cur_data_offset;
1879 struct stats_query_entry *cur_query_entry;
1880 u8 stats_count = 0;
1881 bool is_fcoe = false;
1882
1883 if (!IS_SRIOV(bp))
1884 return;
1885
1886 if (!NO_FCOE(bp))
1887 is_fcoe = true;
1888
1889 /* fcoe adds one global request and one queue request */
1890 num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe;
1891 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX -
1892 (is_fcoe ? 0 : 1);
1893
1894 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1895 "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n",
1896 BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index,
1897 first_queue_query_index + num_queues_req);
1898
1899 cur_data_offset = bp->fw_stats_data_mapping +
1900 offsetof(struct bnx2x_fw_stats_data, queue_stats) +
1901 num_queues_req * sizeof(struct per_queue_stats);
1902
1903 cur_query_entry = &bp->fw_stats_req->
1904 query[first_queue_query_index + num_queues_req];
1905
1906 for_each_vf(bp, i) {
1907 int j;
1908 struct bnx2x_virtf *vf = BP_VF(bp, i);
1909
1910 if (vf->state != VF_ENABLED) {
1911 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1912 "vf %d not enabled so no stats for it\n",
1913 vf->abs_vfid);
1914 continue;
1915 }
1916
1917 if (vf->malicious) {
1918 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1919 "vf %d malicious so no stats for it\n",
1920 vf->abs_vfid);
1921 continue;
1922 }
1923
1924 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1925 "add addresses for vf %d\n", vf->abs_vfid);
1926 for_each_vfq(vf, j) {
1927 struct bnx2x_vf_queue *rxq = vfq_get(vf, j);
1928
1929 dma_addr_t q_stats_addr =
1930 vf->fw_stat_map + j * vf->stats_stride;
1931
1932 /* collect stats fro active queues only */
1933 if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) ==
1934 BNX2X_Q_LOGICAL_STATE_STOPPED)
1935 continue;
1936
1937 /* create stats query entry for this queue */
1938 cur_query_entry->kind = STATS_TYPE_QUEUE;
1939 cur_query_entry->index = vfq_stat_id(vf, rxq);
1940 cur_query_entry->funcID =
1941 cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid));
1942 cur_query_entry->address.hi =
1943 cpu_to_le32(U64_HI(q_stats_addr));
1944 cur_query_entry->address.lo =
1945 cpu_to_le32(U64_LO(q_stats_addr));
1946 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1947 "added address %x %x for vf %d queue %d client %d\n",
1948 cur_query_entry->address.hi,
1949 cur_query_entry->address.lo,
1950 cur_query_entry->funcID,
1951 j, cur_query_entry->index);
1952 cur_query_entry++;
1953 cur_data_offset += sizeof(struct per_queue_stats);
1954 stats_count++;
1955
1956 /* all stats are coalesced to the leading queue */
1957 if (vf->cfg_flags & VF_CFG_STATS_COALESCE)
1958 break;
1959 }
1960 }
1961 bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count;
1962 }
1963
1964 /* VF API helpers */
1965 static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid,
1966 u8 enable)
1967 {
1968 u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4;
1969 u32 val = enable ? (abs_vfid | (1 << 6)) : 0;
1970
1971 REG_WR(bp, reg, val);
1972 }
1973
1974 static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf)
1975 {
1976 int i;
1977
1978 for_each_vfq(vf, i)
1979 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid,
1980 vfq_qzone_id(vf, vfq_get(vf, i)), false);
1981 }
1982
1983 static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf)
1984 {
1985 u32 val;
1986
1987 /* clear the VF configuration - pretend */
1988 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
1989 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
1990 val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN |
1991 IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK);
1992 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);
1993 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1994 }
1995
1996 u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf)
1997 {
1998 return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF),
1999 BNX2X_VF_MAX_QUEUES);
2000 }
2001
2002 static
2003 int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf,
2004 struct vf_pf_resc_request *req_resc)
2005 {
2006 u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf);
2007 u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf);
2008
2009 return ((req_resc->num_rxqs <= rxq_cnt) &&
2010 (req_resc->num_txqs <= txq_cnt) &&
2011 (req_resc->num_sbs <= vf_sb_count(vf)) &&
2012 (req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) &&
2013 (req_resc->num_vlan_filters <= vf_vlan_rules_cnt(vf)));
2014 }
2015
2016 /* CORE VF API */
2017 int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf,
2018 struct vf_pf_resc_request *resc)
2019 {
2020 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) *
2021 BNX2X_CIDS_PER_VF;
2022
2023 union cdu_context *base_cxt = (union cdu_context *)
2024 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr +
2025 (base_vf_cid & (ILT_PAGE_CIDS-1));
2026 int i;
2027
2028 /* if state is 'acquired' the VF was not released or FLR'd, in
2029 * this case the returned resources match the acquired already
2030 * acquired resources. Verify that the requested numbers do
2031 * not exceed the already acquired numbers.
2032 */
2033 if (vf->state == VF_ACQUIRED) {
2034 DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n",
2035 vf->abs_vfid);
2036
2037 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) {
2038 BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n",
2039 vf->abs_vfid);
2040 return -EINVAL;
2041 }
2042 return 0;
2043 }
2044
2045 /* Otherwise vf state must be 'free' or 'reset' */
2046 if (vf->state != VF_FREE && vf->state != VF_RESET) {
2047 BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n",
2048 vf->abs_vfid, vf->state);
2049 return -EINVAL;
2050 }
2051
2052 /* static allocation:
2053 * the global maximum number are fixed per VF. Fail the request if
2054 * requested number exceed these globals
2055 */
2056 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) {
2057 DP(BNX2X_MSG_IOV,
2058 "cannot fulfill vf resource request. Placing maximal available values in response\n");
2059 /* set the max resource in the vf */
2060 return -ENOMEM;
2061 }
2062
2063 /* Set resources counters - 0 request means max available */
2064 vf_sb_count(vf) = resc->num_sbs;
2065 vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf);
2066 vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf);
2067
2068 DP(BNX2X_MSG_IOV,
2069 "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n",
2070 vf_sb_count(vf), vf_rxq_count(vf),
2071 vf_txq_count(vf), vf_mac_rules_cnt(vf),
2072 vf_vlan_rules_cnt(vf));
2073
2074 /* Initialize the queues */
2075 if (!vf->vfqs) {
2076 DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n");
2077 return -EINVAL;
2078 }
2079
2080 for_each_vfq(vf, i) {
2081 struct bnx2x_vf_queue *q = vfq_get(vf, i);
2082
2083 if (!q) {
2084 BNX2X_ERR("q number %d was not allocated\n", i);
2085 return -EINVAL;
2086 }
2087
2088 q->index = i;
2089 q->cxt = &((base_cxt + i)->eth);
2090 q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i;
2091
2092 DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n",
2093 vf->abs_vfid, i, q->index, q->cid, q->cxt);
2094
2095 /* init SP objects */
2096 bnx2x_vfq_init(bp, vf, q);
2097 }
2098 vf->state = VF_ACQUIRED;
2099 return 0;
2100 }
2101
2102 int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map)
2103 {
2104 struct bnx2x_func_init_params func_init = {0};
2105 int i;
2106
2107 /* the sb resources are initialized at this point, do the
2108 * FW/HW initializations
2109 */
2110 for_each_vf_sb(vf, i)
2111 bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true,
2112 vf_igu_sb(vf, i), vf_igu_sb(vf, i));
2113
2114 /* Sanity checks */
2115 if (vf->state != VF_ACQUIRED) {
2116 DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n",
2117 vf->abs_vfid, vf->state);
2118 return -EINVAL;
2119 }
2120
2121 /* let FLR complete ... */
2122 msleep(100);
2123
2124 /* FLR cleanup epilogue */
2125 if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid))
2126 return -EBUSY;
2127
2128 /* reset IGU VF statistics: MSIX */
2129 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0);
2130
2131 /* function setup */
2132 func_init.pf_id = BP_FUNC(bp);
2133 func_init.func_id = FW_VF_HANDLE(vf->abs_vfid);
2134 bnx2x_func_init(bp, &func_init);
2135
2136 /* Enable the vf */
2137 bnx2x_vf_enable_access(bp, vf->abs_vfid);
2138 bnx2x_vf_enable_traffic(bp, vf);
2139
2140 /* queue protection table */
2141 for_each_vfq(vf, i)
2142 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid,
2143 vfq_qzone_id(vf, vfq_get(vf, i)), true);
2144
2145 vf->state = VF_ENABLED;
2146
2147 /* update vf bulletin board */
2148 bnx2x_post_vf_bulletin(bp, vf->index);
2149
2150 return 0;
2151 }
2152
2153 struct set_vf_state_cookie {
2154 struct bnx2x_virtf *vf;
2155 u8 state;
2156 };
2157
2158 static void bnx2x_set_vf_state(void *cookie)
2159 {
2160 struct set_vf_state_cookie *p = (struct set_vf_state_cookie *)cookie;
2161
2162 p->vf->state = p->state;
2163 }
2164
2165 int bnx2x_vf_close(struct bnx2x *bp, struct bnx2x_virtf *vf)
2166 {
2167 int rc = 0, i;
2168
2169 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
2170
2171 /* Close all queues */
2172 for (i = 0; i < vf_rxq_count(vf); i++) {
2173 rc = bnx2x_vf_queue_teardown(bp, vf, i);
2174 if (rc)
2175 goto op_err;
2176 }
2177
2178 /* disable the interrupts */
2179 DP(BNX2X_MSG_IOV, "disabling igu\n");
2180 bnx2x_vf_igu_disable(bp, vf);
2181
2182 /* disable the VF */
2183 DP(BNX2X_MSG_IOV, "clearing qtbl\n");
2184 bnx2x_vf_clr_qtbl(bp, vf);
2185
2186 /* need to make sure there are no outstanding stats ramrods which may
2187 * cause the device to access the VF's stats buffer which it will free
2188 * as soon as we return from the close flow.
2189 */
2190 {
2191 struct set_vf_state_cookie cookie;
2192
2193 cookie.vf = vf;
2194 cookie.state = VF_ACQUIRED;
2195 rc = bnx2x_stats_safe_exec(bp, bnx2x_set_vf_state, &cookie);
2196 if (rc)
2197 goto op_err;
2198 }
2199
2200 DP(BNX2X_MSG_IOV, "set state to acquired\n");
2201
2202 return 0;
2203 op_err:
2204 BNX2X_ERR("vf[%d] CLOSE error: rc %d\n", vf->abs_vfid, rc);
2205 return rc;
2206 }
2207
2208 /* VF release can be called either: 1. The VF was acquired but
2209 * not enabled 2. the vf was enabled or in the process of being
2210 * enabled
2211 */
2212 int bnx2x_vf_free(struct bnx2x *bp, struct bnx2x_virtf *vf)
2213 {
2214 int rc;
2215
2216 DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid,
2217 vf->state == VF_FREE ? "Free" :
2218 vf->state == VF_ACQUIRED ? "Acquired" :
2219 vf->state == VF_ENABLED ? "Enabled" :
2220 vf->state == VF_RESET ? "Reset" :
2221 "Unknown");
2222
2223 switch (vf->state) {
2224 case VF_ENABLED:
2225 rc = bnx2x_vf_close(bp, vf);
2226 if (rc)
2227 goto op_err;
2228 /* Fallthrough to release resources */
2229 case VF_ACQUIRED:
2230 DP(BNX2X_MSG_IOV, "about to free resources\n");
2231 bnx2x_vf_free_resc(bp, vf);
2232 break;
2233
2234 case VF_FREE:
2235 case VF_RESET:
2236 default:
2237 break;
2238 }
2239 return 0;
2240 op_err:
2241 BNX2X_ERR("VF[%d] RELEASE error: rc %d\n", vf->abs_vfid, rc);
2242 return rc;
2243 }
2244
2245 int bnx2x_vf_rss_update(struct bnx2x *bp, struct bnx2x_virtf *vf,
2246 struct bnx2x_config_rss_params *rss)
2247 {
2248 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
2249 set_bit(RAMROD_COMP_WAIT, &rss->ramrod_flags);
2250 return bnx2x_config_rss(bp, rss);
2251 }
2252
2253 int bnx2x_vf_tpa_update(struct bnx2x *bp, struct bnx2x_virtf *vf,
2254 struct vfpf_tpa_tlv *tlv,
2255 struct bnx2x_queue_update_tpa_params *params)
2256 {
2257 aligned_u64 *sge_addr = tlv->tpa_client_info.sge_addr;
2258 struct bnx2x_queue_state_params qstate;
2259 int qid, rc = 0;
2260
2261 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
2262
2263 /* Set ramrod params */
2264 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params));
2265 memcpy(&qstate.params.update_tpa, params,
2266 sizeof(struct bnx2x_queue_update_tpa_params));
2267 qstate.cmd = BNX2X_Q_CMD_UPDATE_TPA;
2268 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags);
2269
2270 for (qid = 0; qid < vf_rxq_count(vf); qid++) {
2271 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj);
2272 qstate.params.update_tpa.sge_map = sge_addr[qid];
2273 DP(BNX2X_MSG_IOV, "sge_addr[%d:%d] %08x:%08x\n",
2274 vf->abs_vfid, qid, U64_HI(sge_addr[qid]),
2275 U64_LO(sge_addr[qid]));
2276 rc = bnx2x_queue_state_change(bp, &qstate);
2277 if (rc) {
2278 BNX2X_ERR("Failed to configure sge_addr %08x:%08x for [%d:%d]\n",
2279 U64_HI(sge_addr[qid]), U64_LO(sge_addr[qid]),
2280 vf->abs_vfid, qid);
2281 return rc;
2282 }
2283 }
2284
2285 return rc;
2286 }
2287
2288 /* VF release ~ VF close + VF release-resources
2289 * Release is the ultimate SW shutdown and is called whenever an
2290 * irrecoverable error is encountered.
2291 */
2292 int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf)
2293 {
2294 int rc;
2295
2296 DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid);
2297 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF);
2298
2299 rc = bnx2x_vf_free(bp, vf);
2300 if (rc)
2301 WARN(rc,
2302 "VF[%d] Failed to allocate resources for release op- rc=%d\n",
2303 vf->abs_vfid, rc);
2304 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF);
2305 return rc;
2306 }
2307
2308 void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
2309 enum channel_tlvs tlv)
2310 {
2311 /* we don't lock the channel for unsupported tlvs */
2312 if (!bnx2x_tlv_supported(tlv)) {
2313 BNX2X_ERR("attempting to lock with unsupported tlv. Aborting\n");
2314 return;
2315 }
2316
2317 /* lock the channel */
2318 mutex_lock(&vf->op_mutex);
2319
2320 /* record the locking op */
2321 vf->op_current = tlv;
2322
2323 /* log the lock */
2324 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n",
2325 vf->abs_vfid, tlv);
2326 }
2327
2328 void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
2329 enum channel_tlvs expected_tlv)
2330 {
2331 enum channel_tlvs current_tlv;
2332
2333 if (!vf) {
2334 BNX2X_ERR("VF was %p\n", vf);
2335 return;
2336 }
2337
2338 current_tlv = vf->op_current;
2339
2340 /* we don't unlock the channel for unsupported tlvs */
2341 if (!bnx2x_tlv_supported(expected_tlv))
2342 return;
2343
2344 WARN(expected_tlv != vf->op_current,
2345 "lock mismatch: expected %d found %d", expected_tlv,
2346 vf->op_current);
2347
2348 /* record the locking op */
2349 vf->op_current = CHANNEL_TLV_NONE;
2350
2351 /* lock the channel */
2352 mutex_unlock(&vf->op_mutex);
2353
2354 /* log the unlock */
2355 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n",
2356 vf->abs_vfid, current_tlv);
2357 }
2358
2359 static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable)
2360 {
2361 struct bnx2x_queue_state_params q_params;
2362 u32 prev_flags;
2363 int i, rc;
2364
2365 /* Verify changes are needed and record current Tx switching state */
2366 prev_flags = bp->flags;
2367 if (enable)
2368 bp->flags |= TX_SWITCHING;
2369 else
2370 bp->flags &= ~TX_SWITCHING;
2371 if (prev_flags == bp->flags)
2372 return 0;
2373
2374 /* Verify state enables the sending of queue ramrods */
2375 if ((bp->state != BNX2X_STATE_OPEN) ||
2376 (bnx2x_get_q_logical_state(bp,
2377 &bnx2x_sp_obj(bp, &bp->fp[0]).q_obj) !=
2378 BNX2X_Q_LOGICAL_STATE_ACTIVE))
2379 return 0;
2380
2381 /* send q. update ramrod to configure Tx switching */
2382 memset(&q_params, 0, sizeof(q_params));
2383 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
2384 q_params.cmd = BNX2X_Q_CMD_UPDATE;
2385 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
2386 &q_params.params.update.update_flags);
2387 if (enable)
2388 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING,
2389 &q_params.params.update.update_flags);
2390 else
2391 __clear_bit(BNX2X_Q_UPDATE_TX_SWITCHING,
2392 &q_params.params.update.update_flags);
2393
2394 /* send the ramrod on all the queues of the PF */
2395 for_each_eth_queue(bp, i) {
2396 struct bnx2x_fastpath *fp = &bp->fp[i];
2397 int tx_idx;
2398
2399 /* Set the appropriate Queue object */
2400 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
2401
2402 for (tx_idx = FIRST_TX_COS_INDEX;
2403 tx_idx < fp->max_cos; tx_idx++) {
2404 q_params.params.update.cid_index = tx_idx;
2405
2406 /* Update the Queue state */
2407 rc = bnx2x_queue_state_change(bp, &q_params);
2408 if (rc) {
2409 BNX2X_ERR("Failed to configure Tx switching\n");
2410 return rc;
2411 }
2412 }
2413 }
2414
2415 DP(BNX2X_MSG_IOV, "%s Tx Switching\n", enable ? "Enabled" : "Disabled");
2416 return 0;
2417 }
2418
2419 int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param)
2420 {
2421 struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev));
2422
2423 if (!IS_SRIOV(bp)) {
2424 BNX2X_ERR("failed to configure SR-IOV since vfdb was not allocated. Check dmesg for errors in probe stage\n");
2425 return -EINVAL;
2426 }
2427
2428 DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n",
2429 num_vfs_param, BNX2X_NR_VIRTFN(bp));
2430
2431 /* HW channel is only operational when PF is up */
2432 if (bp->state != BNX2X_STATE_OPEN) {
2433 BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n");
2434 return -EINVAL;
2435 }
2436
2437 /* we are always bound by the total_vfs in the configuration space */
2438 if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) {
2439 BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n",
2440 num_vfs_param, BNX2X_NR_VIRTFN(bp));
2441 num_vfs_param = BNX2X_NR_VIRTFN(bp);
2442 }
2443
2444 bp->requested_nr_virtfn = num_vfs_param;
2445 if (num_vfs_param == 0) {
2446 bnx2x_set_pf_tx_switching(bp, false);
2447 bnx2x_disable_sriov(bp);
2448 return 0;
2449 } else {
2450 return bnx2x_enable_sriov(bp);
2451 }
2452 }
2453
2454 #define IGU_ENTRY_SIZE 4
2455
2456 int bnx2x_enable_sriov(struct bnx2x *bp)
2457 {
2458 int rc = 0, req_vfs = bp->requested_nr_virtfn;
2459 int vf_idx, sb_idx, vfq_idx, qcount, first_vf;
2460 u32 igu_entry, address;
2461 u16 num_vf_queues;
2462
2463 if (req_vfs == 0)
2464 return 0;
2465
2466 first_vf = bp->vfdb->sriov.first_vf_in_pf;
2467
2468 /* statically distribute vf sb pool between VFs */
2469 num_vf_queues = min_t(u16, BNX2X_VF_MAX_QUEUES,
2470 BP_VFDB(bp)->vf_sbs_pool / req_vfs);
2471
2472 /* zero previous values learned from igu cam */
2473 for (vf_idx = 0; vf_idx < req_vfs; vf_idx++) {
2474 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
2475
2476 vf->sb_count = 0;
2477 vf_sb_count(BP_VF(bp, vf_idx)) = 0;
2478 }
2479 bp->vfdb->vf_sbs_pool = 0;
2480
2481 /* prepare IGU cam */
2482 sb_idx = BP_VFDB(bp)->first_vf_igu_entry;
2483 address = IGU_REG_MAPPING_MEMORY + sb_idx * IGU_ENTRY_SIZE;
2484 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) {
2485 for (vfq_idx = 0; vfq_idx < num_vf_queues; vfq_idx++) {
2486 igu_entry = vf_idx << IGU_REG_MAPPING_MEMORY_FID_SHIFT |
2487 vfq_idx << IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT |
2488 IGU_REG_MAPPING_MEMORY_VALID;
2489 DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n",
2490 sb_idx, vf_idx);
2491 REG_WR(bp, address, igu_entry);
2492 sb_idx++;
2493 address += IGU_ENTRY_SIZE;
2494 }
2495 }
2496
2497 /* Reinitialize vf database according to igu cam */
2498 bnx2x_get_vf_igu_cam_info(bp);
2499
2500 DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n",
2501 BP_VFDB(bp)->vf_sbs_pool, num_vf_queues);
2502
2503 qcount = 0;
2504 for_each_vf(bp, vf_idx) {
2505 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
2506
2507 /* set local queue arrays */
2508 vf->vfqs = &bp->vfdb->vfqs[qcount];
2509 qcount += vf_sb_count(vf);
2510 bnx2x_iov_static_resc(bp, vf);
2511 }
2512
2513 /* prepare msix vectors in VF configuration space - the value in the
2514 * PCI configuration space should be the index of the last entry,
2515 * namely one less than the actual size of the table
2516 */
2517 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) {
2518 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx));
2519 REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL,
2520 num_vf_queues - 1);
2521 DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n",
2522 vf_idx, num_vf_queues - 1);
2523 }
2524 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
2525
2526 /* enable sriov. This will probe all the VFs, and consequentially cause
2527 * the "acquire" messages to appear on the VF PF channel.
2528 */
2529 DP(BNX2X_MSG_IOV, "about to call enable sriov\n");
2530 bnx2x_disable_sriov(bp);
2531
2532 rc = bnx2x_set_pf_tx_switching(bp, true);
2533 if (rc)
2534 return rc;
2535
2536 rc = pci_enable_sriov(bp->pdev, req_vfs);
2537 if (rc) {
2538 BNX2X_ERR("pci_enable_sriov failed with %d\n", rc);
2539 return rc;
2540 }
2541 DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs);
2542 return req_vfs;
2543 }
2544
2545 void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp)
2546 {
2547 int vfidx;
2548 struct pf_vf_bulletin_content *bulletin;
2549
2550 DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n");
2551 for_each_vf(bp, vfidx) {
2552 bulletin = BP_VF_BULLETIN(bp, vfidx);
2553 if (bulletin->valid_bitmap & (1 << VLAN_VALID))
2554 bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0,
2555 htons(ETH_P_8021Q));
2556 }
2557 }
2558
2559 void bnx2x_disable_sriov(struct bnx2x *bp)
2560 {
2561 if (pci_vfs_assigned(bp->pdev)) {
2562 DP(BNX2X_MSG_IOV,
2563 "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2564 return;
2565 }
2566
2567 pci_disable_sriov(bp->pdev);
2568 }
2569
2570 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx,
2571 struct bnx2x_virtf **vf,
2572 struct pf_vf_bulletin_content **bulletin,
2573 bool test_queue)
2574 {
2575 if (bp->state != BNX2X_STATE_OPEN) {
2576 BNX2X_ERR("PF is down - can't utilize iov-related functionality\n");
2577 return -EINVAL;
2578 }
2579
2580 if (!IS_SRIOV(bp)) {
2581 BNX2X_ERR("sriov is disabled - can't utilize iov-related functionality\n");
2582 return -EINVAL;
2583 }
2584
2585 if (vfidx >= BNX2X_NR_VIRTFN(bp)) {
2586 BNX2X_ERR("VF is uninitialized - can't utilize iov-related functionality. vfidx was %d BNX2X_NR_VIRTFN was %d\n",
2587 vfidx, BNX2X_NR_VIRTFN(bp));
2588 return -EINVAL;
2589 }
2590
2591 /* init members */
2592 *vf = BP_VF(bp, vfidx);
2593 *bulletin = BP_VF_BULLETIN(bp, vfidx);
2594
2595 if (!*vf) {
2596 BNX2X_ERR("Unable to get VF structure for vfidx %d\n", vfidx);
2597 return -EINVAL;
2598 }
2599
2600 if (test_queue && !(*vf)->vfqs) {
2601 BNX2X_ERR("vfqs struct is null. Was this invoked before dynamically enabling SR-IOV? vfidx was %d\n",
2602 vfidx);
2603 return -EINVAL;
2604 }
2605
2606 if (!*bulletin) {
2607 BNX2X_ERR("Bulletin Board struct is null for vfidx %d\n",
2608 vfidx);
2609 return -EINVAL;
2610 }
2611
2612 return 0;
2613 }
2614
2615 int bnx2x_get_vf_config(struct net_device *dev, int vfidx,
2616 struct ifla_vf_info *ivi)
2617 {
2618 struct bnx2x *bp = netdev_priv(dev);
2619 struct bnx2x_virtf *vf = NULL;
2620 struct pf_vf_bulletin_content *bulletin = NULL;
2621 struct bnx2x_vlan_mac_obj *mac_obj;
2622 struct bnx2x_vlan_mac_obj *vlan_obj;
2623 int rc;
2624
2625 /* sanity and init */
2626 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true);
2627 if (rc)
2628 return rc;
2629
2630 mac_obj = &bnx2x_leading_vfq(vf, mac_obj);
2631 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj);
2632 if (!mac_obj || !vlan_obj) {
2633 BNX2X_ERR("VF partially initialized\n");
2634 return -EINVAL;
2635 }
2636
2637 ivi->vf = vfidx;
2638 ivi->qos = 0;
2639 ivi->max_tx_rate = 10000; /* always 10G. TBA take from link struct */
2640 ivi->min_tx_rate = 0;
2641 ivi->spoofchk = 1; /*always enabled */
2642 if (vf->state == VF_ENABLED) {
2643 /* mac and vlan are in vlan_mac objects */
2644 if (bnx2x_validate_vf_sp_objs(bp, vf, false)) {
2645 mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac,
2646 0, ETH_ALEN);
2647 vlan_obj->get_n_elements(bp, vlan_obj, 1,
2648 (u8 *)&ivi->vlan, 0,
2649 VLAN_HLEN);
2650 }
2651 } else {
2652 mutex_lock(&bp->vfdb->bulletin_mutex);
2653 /* mac */
2654 if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID))
2655 /* mac configured by ndo so its in bulletin board */
2656 memcpy(&ivi->mac, bulletin->mac, ETH_ALEN);
2657 else
2658 /* function has not been loaded yet. Show mac as 0s */
2659 eth_zero_addr(ivi->mac);
2660
2661 /* vlan */
2662 if (bulletin->valid_bitmap & (1 << VLAN_VALID))
2663 /* vlan configured by ndo so its in bulletin board */
2664 memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN);
2665 else
2666 /* function has not been loaded yet. Show vlans as 0s */
2667 memset(&ivi->vlan, 0, VLAN_HLEN);
2668
2669 mutex_unlock(&bp->vfdb->bulletin_mutex);
2670 }
2671
2672 return 0;
2673 }
2674
2675 /* New mac for VF. Consider these cases:
2676 * 1. VF hasn't been acquired yet - save the mac in local bulletin board and
2677 * supply at acquire.
2678 * 2. VF has already been acquired but has not yet initialized - store in local
2679 * bulletin board. mac will be posted on VF bulletin board after VF init. VF
2680 * will configure this mac when it is ready.
2681 * 3. VF has already initialized but has not yet setup a queue - post the new
2682 * mac on VF's bulletin board right now. VF will configure this mac when it
2683 * is ready.
2684 * 4. VF has already set a queue - delete any macs already configured for this
2685 * queue and manually config the new mac.
2686 * In any event, once this function has been called refuse any attempts by the
2687 * VF to configure any mac for itself except for this mac. In case of a race
2688 * where the VF fails to see the new post on its bulletin board before sending a
2689 * mac configuration request, the PF will simply fail the request and VF can try
2690 * again after consulting its bulletin board.
2691 */
2692 int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac)
2693 {
2694 struct bnx2x *bp = netdev_priv(dev);
2695 int rc, q_logical_state;
2696 struct bnx2x_virtf *vf = NULL;
2697 struct pf_vf_bulletin_content *bulletin = NULL;
2698
2699 if (!is_valid_ether_addr(mac)) {
2700 BNX2X_ERR("mac address invalid\n");
2701 return -EINVAL;
2702 }
2703
2704 /* sanity and init */
2705 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true);
2706 if (rc)
2707 return rc;
2708
2709 mutex_lock(&bp->vfdb->bulletin_mutex);
2710
2711 /* update PF's copy of the VF's bulletin. Will no longer accept mac
2712 * configuration requests from vf unless match this mac
2713 */
2714 bulletin->valid_bitmap |= 1 << MAC_ADDR_VALID;
2715 memcpy(bulletin->mac, mac, ETH_ALEN);
2716
2717 /* Post update on VF's bulletin board */
2718 rc = bnx2x_post_vf_bulletin(bp, vfidx);
2719
2720 /* release lock before checking return code */
2721 mutex_unlock(&bp->vfdb->bulletin_mutex);
2722
2723 if (rc) {
2724 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx);
2725 return rc;
2726 }
2727
2728 q_logical_state =
2729 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj));
2730 if (vf->state == VF_ENABLED &&
2731 q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) {
2732 /* configure the mac in device on this vf's queue */
2733 unsigned long ramrod_flags = 0;
2734 struct bnx2x_vlan_mac_obj *mac_obj;
2735
2736 /* User should be able to see failure reason in system logs */
2737 if (!bnx2x_validate_vf_sp_objs(bp, vf, true))
2738 return -EINVAL;
2739
2740 /* must lock vfpf channel to protect against vf flows */
2741 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC);
2742
2743 /* remove existing eth macs */
2744 mac_obj = &bnx2x_leading_vfq(vf, mac_obj);
2745 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true);
2746 if (rc) {
2747 BNX2X_ERR("failed to delete eth macs\n");
2748 rc = -EINVAL;
2749 goto out;
2750 }
2751
2752 /* remove existing uc list macs */
2753 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true);
2754 if (rc) {
2755 BNX2X_ERR("failed to delete uc_list macs\n");
2756 rc = -EINVAL;
2757 goto out;
2758 }
2759
2760 /* configure the new mac to device */
2761 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2762 bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true,
2763 BNX2X_ETH_MAC, &ramrod_flags);
2764
2765 out:
2766 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC);
2767 }
2768
2769 return rc;
2770 }
2771
2772 static void bnx2x_set_vf_vlan_acceptance(struct bnx2x *bp,
2773 struct bnx2x_virtf *vf, bool accept)
2774 {
2775 struct bnx2x_rx_mode_ramrod_params rx_ramrod;
2776 unsigned long accept_flags;
2777
2778 /* need to remove/add the VF's accept_any_vlan bit */
2779 accept_flags = bnx2x_leading_vfq(vf, accept_flags);
2780 if (accept)
2781 set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
2782 else
2783 clear_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
2784
2785 bnx2x_vf_prep_rx_mode(bp, LEADING_IDX, &rx_ramrod, vf,
2786 accept_flags);
2787 bnx2x_leading_vfq(vf, accept_flags) = accept_flags;
2788 bnx2x_config_rx_mode(bp, &rx_ramrod);
2789 }
2790
2791 static int bnx2x_set_vf_vlan_filter(struct bnx2x *bp, struct bnx2x_virtf *vf,
2792 u16 vlan, bool add)
2793 {
2794 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
2795 unsigned long ramrod_flags = 0;
2796 int rc = 0;
2797
2798 /* configure the new vlan to device */
2799 memset(&ramrod_param, 0, sizeof(ramrod_param));
2800 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2801 ramrod_param.vlan_mac_obj = &bnx2x_leading_vfq(vf, vlan_obj);
2802 ramrod_param.ramrod_flags = ramrod_flags;
2803 ramrod_param.user_req.u.vlan.vlan = vlan;
2804 ramrod_param.user_req.cmd = add ? BNX2X_VLAN_MAC_ADD
2805 : BNX2X_VLAN_MAC_DEL;
2806 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
2807 if (rc) {
2808 BNX2X_ERR("failed to configure vlan\n");
2809 return -EINVAL;
2810 }
2811
2812 return 0;
2813 }
2814
2815 int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos,
2816 __be16 vlan_proto)
2817 {
2818 struct pf_vf_bulletin_content *bulletin = NULL;
2819 struct bnx2x *bp = netdev_priv(dev);
2820 struct bnx2x_vlan_mac_obj *vlan_obj;
2821 unsigned long vlan_mac_flags = 0;
2822 unsigned long ramrod_flags = 0;
2823 struct bnx2x_virtf *vf = NULL;
2824 int i, rc;
2825
2826 if (vlan > 4095) {
2827 BNX2X_ERR("illegal vlan value %d\n", vlan);
2828 return -EINVAL;
2829 }
2830
2831 if (vlan_proto != htons(ETH_P_8021Q))
2832 return -EPROTONOSUPPORT;
2833
2834 DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n",
2835 vfidx, vlan, 0);
2836
2837 /* sanity and init */
2838 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true);
2839 if (rc)
2840 return rc;
2841
2842 /* update PF's copy of the VF's bulletin. No point in posting the vlan
2843 * to the VF since it doesn't have anything to do with it. But it useful
2844 * to store it here in case the VF is not up yet and we can only
2845 * configure the vlan later when it does. Treat vlan id 0 as remove the
2846 * Host tag.
2847 */
2848 mutex_lock(&bp->vfdb->bulletin_mutex);
2849
2850 if (vlan > 0)
2851 bulletin->valid_bitmap |= 1 << VLAN_VALID;
2852 else
2853 bulletin->valid_bitmap &= ~(1 << VLAN_VALID);
2854 bulletin->vlan = vlan;
2855
2856 /* Post update on VF's bulletin board */
2857 rc = bnx2x_post_vf_bulletin(bp, vfidx);
2858 if (rc)
2859 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx);
2860 mutex_unlock(&bp->vfdb->bulletin_mutex);
2861
2862 /* is vf initialized and queue set up? */
2863 if (vf->state != VF_ENABLED ||
2864 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)) !=
2865 BNX2X_Q_LOGICAL_STATE_ACTIVE)
2866 return rc;
2867
2868 /* User should be able to see error in system logs */
2869 if (!bnx2x_validate_vf_sp_objs(bp, vf, true))
2870 return -EINVAL;
2871
2872 /* must lock vfpf channel to protect against vf flows */
2873 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN);
2874
2875 /* remove existing vlans */
2876 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2877 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj);
2878 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags,
2879 &ramrod_flags);
2880 if (rc) {
2881 BNX2X_ERR("failed to delete vlans\n");
2882 rc = -EINVAL;
2883 goto out;
2884 }
2885
2886 /* clear accept_any_vlan when HV forces vlan, otherwise
2887 * according to VF capabilities
2888 */
2889 if (vlan || !(vf->cfg_flags & VF_CFG_VLAN_FILTER))
2890 bnx2x_set_vf_vlan_acceptance(bp, vf, !vlan);
2891
2892 rc = bnx2x_set_vf_vlan_filter(bp, vf, vlan, true);
2893 if (rc)
2894 goto out;
2895
2896 /* send queue update ramrods to configure default vlan and
2897 * silent vlan removal
2898 */
2899 for_each_vfq(vf, i) {
2900 struct bnx2x_queue_state_params q_params = {NULL};
2901 struct bnx2x_queue_update_params *update_params;
2902
2903 q_params.q_obj = &bnx2x_vfq(vf, i, sp_obj);
2904
2905 /* validate the Q is UP */
2906 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) !=
2907 BNX2X_Q_LOGICAL_STATE_ACTIVE)
2908 continue;
2909
2910 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
2911 q_params.cmd = BNX2X_Q_CMD_UPDATE;
2912 update_params = &q_params.params.update;
2913 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
2914 &update_params->update_flags);
2915 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
2916 &update_params->update_flags);
2917 if (vlan == 0) {
2918 /* if vlan is 0 then we want to leave the VF traffic
2919 * untagged, and leave the incoming traffic untouched
2920 * (i.e. do not remove any vlan tags).
2921 */
2922 __clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN,
2923 &update_params->update_flags);
2924 __clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
2925 &update_params->update_flags);
2926 } else {
2927 /* configure default vlan to vf queue and set silent
2928 * vlan removal (the vf remains unaware of this vlan).
2929 */
2930 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN,
2931 &update_params->update_flags);
2932 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
2933 &update_params->update_flags);
2934 update_params->def_vlan = vlan;
2935 update_params->silent_removal_value =
2936 vlan & VLAN_VID_MASK;
2937 update_params->silent_removal_mask = VLAN_VID_MASK;
2938 }
2939
2940 /* Update the Queue state */
2941 rc = bnx2x_queue_state_change(bp, &q_params);
2942 if (rc) {
2943 BNX2X_ERR("Failed to configure default VLAN queue %d\n",
2944 i);
2945 goto out;
2946 }
2947 }
2948 out:
2949 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN);
2950
2951 if (rc)
2952 DP(BNX2X_MSG_IOV,
2953 "updated VF[%d] vlan configuration (vlan = %d)\n",
2954 vfidx, vlan);
2955
2956 return rc;
2957 }
2958
2959 /* crc is the first field in the bulletin board. Compute the crc over the
2960 * entire bulletin board excluding the crc field itself. Use the length field
2961 * as the Bulletin Board was posted by a PF with possibly a different version
2962 * from the vf which will sample it. Therefore, the length is computed by the
2963 * PF and then used blindly by the VF.
2964 */
2965 u32 bnx2x_crc_vf_bulletin(struct pf_vf_bulletin_content *bulletin)
2966 {
2967 return crc32(BULLETIN_CRC_SEED,
2968 ((u8 *)bulletin) + sizeof(bulletin->crc),
2969 bulletin->length - sizeof(bulletin->crc));
2970 }
2971
2972 /* Check for new posts on the bulletin board */
2973 enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp)
2974 {
2975 struct pf_vf_bulletin_content *bulletin;
2976 int attempts;
2977
2978 /* sampling structure in mid post may result with corrupted data
2979 * validate crc to ensure coherency.
2980 */
2981 for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) {
2982 u32 crc;
2983
2984 /* sample the bulletin board */
2985 memcpy(&bp->shadow_bulletin, bp->pf2vf_bulletin,
2986 sizeof(union pf_vf_bulletin));
2987
2988 crc = bnx2x_crc_vf_bulletin(&bp->shadow_bulletin.content);
2989
2990 if (bp->shadow_bulletin.content.crc == crc)
2991 break;
2992
2993 BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n",
2994 bp->shadow_bulletin.content.crc, crc);
2995 }
2996
2997 if (attempts >= BULLETIN_ATTEMPTS) {
2998 BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n",
2999 attempts);
3000 return PFVF_BULLETIN_CRC_ERR;
3001 }
3002 bulletin = &bp->shadow_bulletin.content;
3003
3004 /* bulletin board hasn't changed since last sample */
3005 if (bp->old_bulletin.version == bulletin->version)
3006 return PFVF_BULLETIN_UNCHANGED;
3007
3008 /* the mac address in bulletin board is valid and is new */
3009 if (bulletin->valid_bitmap & 1 << MAC_ADDR_VALID &&
3010 !ether_addr_equal(bulletin->mac, bp->old_bulletin.mac)) {
3011 /* update new mac to net device */
3012 memcpy(bp->dev->dev_addr, bulletin->mac, ETH_ALEN);
3013 }
3014
3015 if (bulletin->valid_bitmap & (1 << LINK_VALID)) {
3016 DP(BNX2X_MSG_IOV, "link update speed %d flags %x\n",
3017 bulletin->link_speed, bulletin->link_flags);
3018
3019 bp->vf_link_vars.line_speed = bulletin->link_speed;
3020 bp->vf_link_vars.link_report_flags = 0;
3021 /* Link is down */
3022 if (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)
3023 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
3024 &bp->vf_link_vars.link_report_flags);
3025 /* Full DUPLEX */
3026 if (bulletin->link_flags & VFPF_LINK_REPORT_FULL_DUPLEX)
3027 __set_bit(BNX2X_LINK_REPORT_FD,
3028 &bp->vf_link_vars.link_report_flags);
3029 /* Rx Flow Control is ON */
3030 if (bulletin->link_flags & VFPF_LINK_REPORT_RX_FC_ON)
3031 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON,
3032 &bp->vf_link_vars.link_report_flags);
3033 /* Tx Flow Control is ON */
3034 if (bulletin->link_flags & VFPF_LINK_REPORT_TX_FC_ON)
3035 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON,
3036 &bp->vf_link_vars.link_report_flags);
3037 __bnx2x_link_report(bp);
3038 }
3039
3040 /* copy new bulletin board to bp */
3041 memcpy(&bp->old_bulletin, bulletin,
3042 sizeof(struct pf_vf_bulletin_content));
3043
3044 return PFVF_BULLETIN_UPDATED;
3045 }
3046
3047 void bnx2x_timer_sriov(struct bnx2x *bp)
3048 {
3049 bnx2x_sample_bulletin(bp);
3050
3051 /* if channel is down we need to self destruct */
3052 if (bp->old_bulletin.valid_bitmap & 1 << CHANNEL_DOWN)
3053 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
3054 BNX2X_MSG_IOV);
3055 }
3056
3057 void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp)
3058 {
3059 /* vf doorbells are embedded within the regview */
3060 return bp->regview + PXP_VF_ADDR_DB_START;
3061 }
3062
3063 void bnx2x_vf_pci_dealloc(struct bnx2x *bp)
3064 {
3065 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping,
3066 sizeof(struct bnx2x_vf_mbx_msg));
3067 BNX2X_PCI_FREE(bp->pf2vf_bulletin, bp->pf2vf_bulletin_mapping,
3068 sizeof(union pf_vf_bulletin));
3069 }
3070
3071 int bnx2x_vf_pci_alloc(struct bnx2x *bp)
3072 {
3073 mutex_init(&bp->vf2pf_mutex);
3074
3075 /* allocate vf2pf mailbox for vf to pf channel */
3076 bp->vf2pf_mbox = BNX2X_PCI_ALLOC(&bp->vf2pf_mbox_mapping,
3077 sizeof(struct bnx2x_vf_mbx_msg));
3078 if (!bp->vf2pf_mbox)
3079 goto alloc_mem_err;
3080
3081 /* allocate pf 2 vf bulletin board */
3082 bp->pf2vf_bulletin = BNX2X_PCI_ALLOC(&bp->pf2vf_bulletin_mapping,
3083 sizeof(union pf_vf_bulletin));
3084 if (!bp->pf2vf_bulletin)
3085 goto alloc_mem_err;
3086
3087 bnx2x_vf_bulletin_finalize(&bp->pf2vf_bulletin->content, true);
3088
3089 return 0;
3090
3091 alloc_mem_err:
3092 bnx2x_vf_pci_dealloc(bp);
3093 return -ENOMEM;
3094 }
3095
3096 void bnx2x_iov_channel_down(struct bnx2x *bp)
3097 {
3098 int vf_idx;
3099 struct pf_vf_bulletin_content *bulletin;
3100
3101 if (!IS_SRIOV(bp))
3102 return;
3103
3104 for_each_vf(bp, vf_idx) {
3105 /* locate this VFs bulletin board and update the channel down
3106 * bit
3107 */
3108 bulletin = BP_VF_BULLETIN(bp, vf_idx);
3109 bulletin->valid_bitmap |= 1 << CHANNEL_DOWN;
3110
3111 /* update vf bulletin board */
3112 bnx2x_post_vf_bulletin(bp, vf_idx);
3113 }
3114 }
3115
3116 void bnx2x_iov_task(struct work_struct *work)
3117 {
3118 struct bnx2x *bp = container_of(work, struct bnx2x, iov_task.work);
3119
3120 if (!netif_running(bp->dev))
3121 return;
3122
3123 if (test_and_clear_bit(BNX2X_IOV_HANDLE_FLR,
3124 &bp->iov_task_state))
3125 bnx2x_vf_handle_flr_event(bp);
3126
3127 if (test_and_clear_bit(BNX2X_IOV_HANDLE_VF_MSG,
3128 &bp->iov_task_state))
3129 bnx2x_vf_mbx(bp);
3130 }
3131
3132 void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag)
3133 {
3134 smp_mb__before_atomic();
3135 set_bit(flag, &bp->iov_task_state);
3136 smp_mb__after_atomic();
3137 DP(BNX2X_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag);
3138 queue_delayed_work(bnx2x_iov_wq, &bp->iov_task, 0);
3139 }
Linux with added FPC-III support