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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / broadcom / bnxt / bnxt_hsi.h
blob971ace5d0d4a4a77eb75ed672106e7ca6a5ccbc3
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 *
10 * DO NOT MODIFY!!! This file is automatically generated.
11 */
12
13 #ifndef _BNXT_HSI_H_
14 #define _BNXT_HSI_H_
15
16 /* hwrm_cmd_hdr (size:128b/16B) */
17 struct hwrm_cmd_hdr {
18 __le16 req_type;
19 __le16 cmpl_ring;
20 __le16 seq_id;
21 __le16 target_id;
22 __le64 resp_addr;
23 };
24
25 /* hwrm_resp_hdr (size:64b/8B) */
26 struct hwrm_resp_hdr {
27 __le16 error_code;
28 __le16 req_type;
29 __le16 seq_id;
30 __le16 resp_len;
31 };
32
33 #define CMD_DISCR_TLV_ENCAP 0x8000UL
34 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
35
36
37 #define TLV_TYPE_HWRM_REQUEST 0x1UL
38 #define TLV_TYPE_HWRM_RESPONSE 0x2UL
39 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
40 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL
41 #define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL
42 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
43 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
44 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
45 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL
46 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL
47 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
48 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
49
50
51 /* tlv (size:64b/8B) */
52 struct tlv {
53 __le16 cmd_discr;
54 u8 reserved_8b;
55 u8 flags;
56 #define TLV_FLAGS_MORE 0x1UL
57 #define TLV_FLAGS_MORE_LAST 0x0UL
58 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL
59 #define TLV_FLAGS_REQUIRED 0x2UL
60 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
61 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
62 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
63 __le16 tlv_type;
64 __le16 length;
65 };
66
67 /* input (size:128b/16B) */
68 struct input {
69 __le16 req_type;
70 __le16 cmpl_ring;
71 __le16 seq_id;
72 __le16 target_id;
73 __le64 resp_addr;
74 };
75
76 /* output (size:64b/8B) */
77 struct output {
78 __le16 error_code;
79 __le16 req_type;
80 __le16 seq_id;
81 __le16 resp_len;
82 };
83
84 /* hwrm_short_input (size:128b/16B) */
85 struct hwrm_short_input {
86 __le16 req_type;
87 __le16 signature;
88 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
89 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
90 __le16 unused_0;
91 __le16 size;
92 __le64 req_addr;
93 };
94
95 /* cmd_nums (size:64b/8B) */
96 struct cmd_nums {
97 __le16 req_type;
98 #define HWRM_VER_GET 0x0UL
99 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
100 #define HWRM_FUNC_BUF_UNRGTR 0xeUL
101 #define HWRM_FUNC_VF_CFG 0xfUL
102 #define HWRM_RESERVED1 0x10UL
103 #define HWRM_FUNC_RESET 0x11UL
104 #define HWRM_FUNC_GETFID 0x12UL
105 #define HWRM_FUNC_VF_ALLOC 0x13UL
106 #define HWRM_FUNC_VF_FREE 0x14UL
107 #define HWRM_FUNC_QCAPS 0x15UL
108 #define HWRM_FUNC_QCFG 0x16UL
109 #define HWRM_FUNC_CFG 0x17UL
110 #define HWRM_FUNC_QSTATS 0x18UL
111 #define HWRM_FUNC_CLR_STATS 0x19UL
112 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL
113 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL
114 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL
115 #define HWRM_FUNC_DRV_RGTR 0x1dUL
116 #define HWRM_FUNC_DRV_QVER 0x1eUL
117 #define HWRM_FUNC_BUF_RGTR 0x1fUL
118 #define HWRM_PORT_PHY_CFG 0x20UL
119 #define HWRM_PORT_MAC_CFG 0x21UL
120 #define HWRM_PORT_TS_QUERY 0x22UL
121 #define HWRM_PORT_QSTATS 0x23UL
122 #define HWRM_PORT_LPBK_QSTATS 0x24UL
123 #define HWRM_PORT_CLR_STATS 0x25UL
124 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL
125 #define HWRM_PORT_PHY_QCFG 0x27UL
126 #define HWRM_PORT_MAC_QCFG 0x28UL
127 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL
128 #define HWRM_PORT_PHY_QCAPS 0x2aUL
129 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL
130 #define HWRM_PORT_PHY_I2C_READ 0x2cUL
131 #define HWRM_PORT_LED_CFG 0x2dUL
132 #define HWRM_PORT_LED_QCFG 0x2eUL
133 #define HWRM_PORT_LED_QCAPS 0x2fUL
134 #define HWRM_QUEUE_QPORTCFG 0x30UL
135 #define HWRM_QUEUE_QCFG 0x31UL
136 #define HWRM_QUEUE_CFG 0x32UL
137 #define HWRM_FUNC_VLAN_CFG 0x33UL
138 #define HWRM_FUNC_VLAN_QCFG 0x34UL
139 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL
140 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL
141 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL
142 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL
143 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL
144 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL
145 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL
146 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL
147 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL
148 #define HWRM_VNIC_ALLOC 0x40UL
149 #define HWRM_VNIC_FREE 0x41UL
150 #define HWRM_VNIC_CFG 0x42UL
151 #define HWRM_VNIC_QCFG 0x43UL
152 #define HWRM_VNIC_TPA_CFG 0x44UL
153 #define HWRM_VNIC_TPA_QCFG 0x45UL
154 #define HWRM_VNIC_RSS_CFG 0x46UL
155 #define HWRM_VNIC_RSS_QCFG 0x47UL
156 #define HWRM_VNIC_PLCMODES_CFG 0x48UL
157 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL
158 #define HWRM_VNIC_QCAPS 0x4aUL
159 #define HWRM_RING_ALLOC 0x50UL
160 #define HWRM_RING_FREE 0x51UL
161 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
162 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
163 #define HWRM_RING_AGGINT_QCAPS 0x54UL
164 #define HWRM_RING_RESET 0x5eUL
165 #define HWRM_RING_GRP_ALLOC 0x60UL
166 #define HWRM_RING_GRP_FREE 0x61UL
167 #define HWRM_RESERVED5 0x64UL
168 #define HWRM_RESERVED6 0x65UL
169 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL
170 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL
171 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
172 #define HWRM_CFA_L2_FILTER_FREE 0x91UL
173 #define HWRM_CFA_L2_FILTER_CFG 0x92UL
174 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL
175 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL
176 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL
177 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL
178 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL
179 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL
180 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL
181 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL
182 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL
183 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL
184 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL
185 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL
186 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
187 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
188 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
189 #define HWRM_STAT_CTX_ALLOC 0xb0UL
190 #define HWRM_STAT_CTX_FREE 0xb1UL
191 #define HWRM_STAT_CTX_QUERY 0xb2UL
192 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL
193 #define HWRM_PORT_QSTATS_EXT 0xb4UL
194 #define HWRM_FW_RESET 0xc0UL
195 #define HWRM_FW_QSTATUS 0xc1UL
196 #define HWRM_FW_HEALTH_CHECK 0xc2UL
197 #define HWRM_FW_SYNC 0xc3UL
198 #define HWRM_FW_SET_TIME 0xc8UL
199 #define HWRM_FW_GET_TIME 0xc9UL
200 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
201 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL
202 #define HWRM_FW_IPC_MAILBOX 0xccUL
203 #define HWRM_EXEC_FWD_RESP 0xd0UL
204 #define HWRM_REJECT_FWD_RESP 0xd1UL
205 #define HWRM_FWD_RESP 0xd2UL
206 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
207 #define HWRM_OEM_CMD 0xd4UL
208 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL
209 #define HWRM_WOL_FILTER_ALLOC 0xf0UL
210 #define HWRM_WOL_FILTER_FREE 0xf1UL
211 #define HWRM_WOL_FILTER_QCFG 0xf2UL
212 #define HWRM_WOL_REASON_QCFG 0xf3UL
213 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
214 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
215 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
216 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
217 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
218 #define HWRM_CFA_VFR_ALLOC 0xfdUL
219 #define HWRM_CFA_VFR_FREE 0xfeUL
220 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
221 #define HWRM_CFA_VF_PAIR_FREE 0x101UL
222 #define HWRM_CFA_VF_PAIR_INFO 0x102UL
223 #define HWRM_CFA_FLOW_ALLOC 0x103UL
224 #define HWRM_CFA_FLOW_FREE 0x104UL
225 #define HWRM_CFA_FLOW_FLUSH 0x105UL
226 #define HWRM_CFA_FLOW_STATS 0x106UL
227 #define HWRM_CFA_FLOW_INFO 0x107UL
228 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL
229 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL
230 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL
231 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL
232 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL
233 #define HWRM_CFA_PAIR_ALLOC 0x10dUL
234 #define HWRM_CFA_PAIR_FREE 0x10eUL
235 #define HWRM_CFA_PAIR_INFO 0x10fUL
236 #define HWRM_FW_IPC_MSG 0x110UL
237 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
238 #define HWRM_ENGINE_CKV_HELLO 0x12dUL
239 #define HWRM_ENGINE_CKV_STATUS 0x12eUL
240 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
241 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
242 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL
243 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL
244 #define HWRM_ENGINE_CKV_FLUSH 0x133UL
245 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL
246 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
247 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
248 #define HWRM_ENGINE_QG_QUERY 0x13dUL
249 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
250 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL
251 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL
252 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL
253 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL
254 #define HWRM_ENGINE_QG_METER_BIND 0x143UL
255 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL
256 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL
257 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL
258 #define HWRM_ENGINE_SG_QUERY 0x147UL
259 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL
260 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL
261 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL
262 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL
263 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL
264 #define HWRM_ENGINE_STATS_CONFIG 0x155UL
265 #define HWRM_ENGINE_STATS_CLEAR 0x156UL
266 #define HWRM_ENGINE_STATS_QUERY 0x157UL
267 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL
268 #define HWRM_ENGINE_RQ_FREE 0x15fUL
269 #define HWRM_ENGINE_CQ_ALLOC 0x160UL
270 #define HWRM_ENGINE_CQ_FREE 0x161UL
271 #define HWRM_ENGINE_NQ_ALLOC 0x162UL
272 #define HWRM_ENGINE_NQ_FREE 0x163UL
273 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
274 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
275 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
276 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
277 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL
278 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL
279 #define HWRM_FUNC_VF_BW_CFG 0x195UL
280 #define HWRM_FUNC_VF_BW_QCFG 0x196UL
281 #define HWRM_SELFTEST_QLIST 0x200UL
282 #define HWRM_SELFTEST_EXEC 0x201UL
283 #define HWRM_SELFTEST_IRQ 0x202UL
284 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL
285 #define HWRM_PCIE_QSTATS 0x204UL
286 #define HWRM_DBG_READ_DIRECT 0xff10UL
287 #define HWRM_DBG_READ_INDIRECT 0xff11UL
288 #define HWRM_DBG_WRITE_DIRECT 0xff12UL
289 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL
290 #define HWRM_DBG_DUMP 0xff14UL
291 #define HWRM_DBG_ERASE_NVM 0xff15UL
292 #define HWRM_DBG_CFG 0xff16UL
293 #define HWRM_DBG_COREDUMP_LIST 0xff17UL
294 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL
295 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
296 #define HWRM_DBG_FW_CLI 0xff1aUL
297 #define HWRM_DBG_I2C_CMD 0xff1bUL
298 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
299 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL
300 #define HWRM_NVM_FLUSH 0xfff0UL
301 #define HWRM_NVM_GET_VARIABLE 0xfff1UL
302 #define HWRM_NVM_SET_VARIABLE 0xfff2UL
303 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL
304 #define HWRM_NVM_MODIFY 0xfff4UL
305 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL
306 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL
307 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL
308 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL
309 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL
310 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL
311 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL
312 #define HWRM_NVM_RAW_DUMP 0xfffcUL
313 #define HWRM_NVM_READ 0xfffdUL
314 #define HWRM_NVM_WRITE 0xfffeUL
315 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL
316 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
317 __le16 unused_0[3];
318 };
319
320 /* ret_codes (size:64b/8B) */
321 struct ret_codes {
322 __le16 error_code;
323 #define HWRM_ERR_CODE_SUCCESS 0x0UL
324 #define HWRM_ERR_CODE_FAIL 0x1UL
325 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
326 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
327 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
328 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
329 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
330 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
331 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
332 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
333 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
334 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
335 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
336 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
337 __le16 unused_0[3];
338 };
339
340 /* hwrm_err_output (size:128b/16B) */
341 struct hwrm_err_output {
342 __le16 error_code;
343 __le16 req_type;
344 __le16 seq_id;
345 __le16 resp_len;
346 __le32 opaque_0;
347 __le16 opaque_1;
348 u8 cmd_err;
349 u8 valid;
350 };
351 #define HWRM_NA_SIGNATURE ((__le32)(-1))
352 #define HWRM_MAX_REQ_LEN 128
353 #define HWRM_MAX_RESP_LEN 280
354 #define HW_HASH_INDEX_SIZE 0x80
355 #define HW_HASH_KEY_SIZE 40
356 #define HWRM_RESP_VALID_KEY 1
357 #define HWRM_VERSION_MAJOR 1
358 #define HWRM_VERSION_MINOR 9
359 #define HWRM_VERSION_UPDATE 2
360 #define HWRM_VERSION_RSVD 25
361 #define HWRM_VERSION_STR "1.9.2.25"
362
363 /* hwrm_ver_get_input (size:192b/24B) */
364 struct hwrm_ver_get_input {
365 __le16 req_type;
366 __le16 cmpl_ring;
367 __le16 seq_id;
368 __le16 target_id;
369 __le64 resp_addr;
370 u8 hwrm_intf_maj;
371 u8 hwrm_intf_min;
372 u8 hwrm_intf_upd;
373 u8 unused_0[5];
374 };
375
376 /* hwrm_ver_get_output (size:1408b/176B) */
377 struct hwrm_ver_get_output {
378 __le16 error_code;
379 __le16 req_type;
380 __le16 seq_id;
381 __le16 resp_len;
382 u8 hwrm_intf_maj_8b;
383 u8 hwrm_intf_min_8b;
384 u8 hwrm_intf_upd_8b;
385 u8 hwrm_intf_rsvd_8b;
386 u8 hwrm_fw_maj_8b;
387 u8 hwrm_fw_min_8b;
388 u8 hwrm_fw_bld_8b;
389 u8 hwrm_fw_rsvd_8b;
390 u8 mgmt_fw_maj_8b;
391 u8 mgmt_fw_min_8b;
392 u8 mgmt_fw_bld_8b;
393 u8 mgmt_fw_rsvd_8b;
394 u8 netctrl_fw_maj_8b;
395 u8 netctrl_fw_min_8b;
396 u8 netctrl_fw_bld_8b;
397 u8 netctrl_fw_rsvd_8b;
398 __le32 dev_caps_cfg;
399 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
400 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
401 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
402 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
403 u8 roce_fw_maj_8b;
404 u8 roce_fw_min_8b;
405 u8 roce_fw_bld_8b;
406 u8 roce_fw_rsvd_8b;
407 char hwrm_fw_name[16];
408 char mgmt_fw_name[16];
409 char netctrl_fw_name[16];
410 u8 reserved2[16];
411 char roce_fw_name[16];
412 __le16 chip_num;
413 u8 chip_rev;
414 u8 chip_metal;
415 u8 chip_bond_id;
416 u8 chip_platform_type;
417 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL
418 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL
419 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
420 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
421 __le16 max_req_win_len;
422 __le16 max_resp_len;
423 __le16 def_req_timeout;
424 u8 flags;
425 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL
426 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL
427 u8 unused_0[2];
428 u8 always_1;
429 __le16 hwrm_intf_major;
430 __le16 hwrm_intf_minor;
431 __le16 hwrm_intf_build;
432 __le16 hwrm_intf_patch;
433 __le16 hwrm_fw_major;
434 __le16 hwrm_fw_minor;
435 __le16 hwrm_fw_build;
436 __le16 hwrm_fw_patch;
437 __le16 mgmt_fw_major;
438 __le16 mgmt_fw_minor;
439 __le16 mgmt_fw_build;
440 __le16 mgmt_fw_patch;
441 __le16 netctrl_fw_major;
442 __le16 netctrl_fw_minor;
443 __le16 netctrl_fw_build;
444 __le16 netctrl_fw_patch;
445 __le16 roce_fw_major;
446 __le16 roce_fw_minor;
447 __le16 roce_fw_build;
448 __le16 roce_fw_patch;
449 __le16 max_ext_req_len;
450 u8 unused_1[5];
451 u8 valid;
452 };
453
454 /* eject_cmpl (size:128b/16B) */
455 struct eject_cmpl {
456 __le16 type;
457 #define EJECT_CMPL_TYPE_MASK 0x3fUL
458 #define EJECT_CMPL_TYPE_SFT 0
459 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
460 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
461 __le16 len;
462 __le32 opaque;
463 __le32 v;
464 #define EJECT_CMPL_V 0x1UL
465 __le32 unused_2;
466 };
467
468 /* hwrm_cmpl (size:128b/16B) */
469 struct hwrm_cmpl {
470 __le16 type;
471 #define CMPL_TYPE_MASK 0x3fUL
472 #define CMPL_TYPE_SFT 0
473 #define CMPL_TYPE_HWRM_DONE 0x20UL
474 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE
475 __le16 sequence_id;
476 __le32 unused_1;
477 __le32 v;
478 #define CMPL_V 0x1UL
479 __le32 unused_3;
480 };
481
482 /* hwrm_fwd_req_cmpl (size:128b/16B) */
483 struct hwrm_fwd_req_cmpl {
484 __le16 req_len_type;
485 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL
486 #define FWD_REQ_CMPL_TYPE_SFT 0
487 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL
488 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
489 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
490 #define FWD_REQ_CMPL_REQ_LEN_SFT 6
491 __le16 source_id;
492 __le32 unused0;
493 __le32 req_buf_addr_v[2];
494 #define FWD_REQ_CMPL_V 0x1UL
495 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
496 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
497 };
498
499 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
500 struct hwrm_fwd_resp_cmpl {
501 __le16 type;
502 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL
503 #define FWD_RESP_CMPL_TYPE_SFT 0
504 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL
505 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
506 __le16 source_id;
507 __le16 resp_len;
508 __le16 unused_1;
509 __le32 resp_buf_addr_v[2];
510 #define FWD_RESP_CMPL_V 0x1UL
511 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
512 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
513 };
514
515 /* hwrm_async_event_cmpl (size:128b/16B) */
516 struct hwrm_async_event_cmpl {
517 __le16 type;
518 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
519 #define ASYNC_EVENT_CMPL_TYPE_SFT 0
520 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
521 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
522 __le16 event_id;
523 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
524 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL
525 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
526 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
527 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
528 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
529 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
530 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
531 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
532 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
533 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
534 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
535 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL
536 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL
537 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
538 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
539 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
540 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
541 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
542 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
543 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
544 __le32 event_data2;
545 u8 opaque_v;
546 #define ASYNC_EVENT_CMPL_V 0x1UL
547 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
548 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
549 u8 timestamp_lo;
550 __le16 timestamp_hi;
551 __le32 event_data1;
552 };
553
554 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
555 struct hwrm_async_event_cmpl_link_status_change {
556 __le16 type;
557 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
558 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
559 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
560 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
561 __le16 event_id;
562 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
563 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
564 __le32 event_data2;
565 u8 opaque_v;
566 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
567 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
568 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
569 u8 timestamp_lo;
570 __le16 timestamp_hi;
571 __le32 event_data1;
572 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
573 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL
574 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL
575 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
576 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
577 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
578 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
579 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
580 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL
581 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20
582 };
583
584 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
585 struct hwrm_async_event_cmpl_port_conn_not_allowed {
586 __le16 type;
587 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
588 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
589 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
590 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
591 __le16 event_id;
592 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
593 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
594 __le32 event_data2;
595 u8 opaque_v;
596 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
597 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
598 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
599 u8 timestamp_lo;
600 __le16 timestamp_hi;
601 __le32 event_data1;
602 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
603 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
604 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
605 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
606 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
607 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
608 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
609 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
610 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
611 };
612
613 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
614 struct hwrm_async_event_cmpl_link_speed_cfg_change {
615 __le16 type;
616 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
617 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
618 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
619 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
620 __le16 event_id;
621 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
622 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
623 __le32 event_data2;
624 u8 opaque_v;
625 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
626 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
627 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
628 u8 timestamp_lo;
629 __le16 timestamp_hi;
630 __le32 event_data1;
631 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
632 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
633 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
634 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
635 };
636
637 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
638 struct hwrm_async_event_cmpl_vf_cfg_change {
639 __le16 type;
640 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
641 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
642 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
643 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
644 __le16 event_id;
645 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
646 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
647 __le32 event_data2;
648 u8 opaque_v;
649 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
650 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
651 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
652 u8 timestamp_lo;
653 __le16 timestamp_hi;
654 __le32 event_data1;
655 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
656 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
657 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
658 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
659 };
660
661 /* hwrm_func_reset_input (size:192b/24B) */
662 struct hwrm_func_reset_input {
663 __le16 req_type;
664 __le16 cmpl_ring;
665 __le16 seq_id;
666 __le16 target_id;
667 __le64 resp_addr;
668 __le32 enables;
669 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
670 __le16 vf_id;
671 u8 func_reset_level;
672 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL
673 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
674 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
675 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL
676 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
677 u8 unused_0;
678 };
679
680 /* hwrm_func_reset_output (size:128b/16B) */
681 struct hwrm_func_reset_output {
682 __le16 error_code;
683 __le16 req_type;
684 __le16 seq_id;
685 __le16 resp_len;
686 u8 unused_0[7];
687 u8 valid;
688 };
689
690 /* hwrm_func_getfid_input (size:192b/24B) */
691 struct hwrm_func_getfid_input {
692 __le16 req_type;
693 __le16 cmpl_ring;
694 __le16 seq_id;
695 __le16 target_id;
696 __le64 resp_addr;
697 __le32 enables;
698 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
699 __le16 pci_id;
700 u8 unused_0[2];
701 };
702
703 /* hwrm_func_getfid_output (size:128b/16B) */
704 struct hwrm_func_getfid_output {
705 __le16 error_code;
706 __le16 req_type;
707 __le16 seq_id;
708 __le16 resp_len;
709 __le16 fid;
710 u8 unused_0[5];
711 u8 valid;
712 };
713
714 /* hwrm_func_vf_alloc_input (size:192b/24B) */
715 struct hwrm_func_vf_alloc_input {
716 __le16 req_type;
717 __le16 cmpl_ring;
718 __le16 seq_id;
719 __le16 target_id;
720 __le64 resp_addr;
721 __le32 enables;
722 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
723 __le16 first_vf_id;
724 __le16 num_vfs;
725 };
726
727 /* hwrm_func_vf_alloc_output (size:128b/16B) */
728 struct hwrm_func_vf_alloc_output {
729 __le16 error_code;
730 __le16 req_type;
731 __le16 seq_id;
732 __le16 resp_len;
733 __le16 first_vf_id;
734 u8 unused_0[5];
735 u8 valid;
736 };
737
738 /* hwrm_func_vf_free_input (size:192b/24B) */
739 struct hwrm_func_vf_free_input {
740 __le16 req_type;
741 __le16 cmpl_ring;
742 __le16 seq_id;
743 __le16 target_id;
744 __le64 resp_addr;
745 __le32 enables;
746 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
747 __le16 first_vf_id;
748 __le16 num_vfs;
749 };
750
751 /* hwrm_func_vf_free_output (size:128b/16B) */
752 struct hwrm_func_vf_free_output {
753 __le16 error_code;
754 __le16 req_type;
755 __le16 seq_id;
756 __le16 resp_len;
757 u8 unused_0[7];
758 u8 valid;
759 };
760
761 /* hwrm_func_vf_cfg_input (size:448b/56B) */
762 struct hwrm_func_vf_cfg_input {
763 __le16 req_type;
764 __le16 cmpl_ring;
765 __le16 seq_id;
766 __le16 target_id;
767 __le64 resp_addr;
768 __le32 enables;
769 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
770 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
771 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
772 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
773 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL
774 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL
775 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL
776 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL
777 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL
778 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL
779 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL
780 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL
781 __le16 mtu;
782 __le16 guest_vlan;
783 __le16 async_event_cr;
784 u8 dflt_mac_addr[6];
785 __le32 flags;
786 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL
787 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL
788 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL
789 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL
790 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL
791 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL
792 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL
793 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL
794 __le16 num_rsscos_ctxs;
795 __le16 num_cmpl_rings;
796 __le16 num_tx_rings;
797 __le16 num_rx_rings;
798 __le16 num_l2_ctxs;
799 __le16 num_vnics;
800 __le16 num_stat_ctxs;
801 __le16 num_hw_ring_grps;
802 u8 unused_0[4];
803 };
804
805 /* hwrm_func_vf_cfg_output (size:128b/16B) */
806 struct hwrm_func_vf_cfg_output {
807 __le16 error_code;
808 __le16 req_type;
809 __le16 seq_id;
810 __le16 resp_len;
811 u8 unused_0[7];
812 u8 valid;
813 };
814
815 /* hwrm_func_qcaps_input (size:192b/24B) */
816 struct hwrm_func_qcaps_input {
817 __le16 req_type;
818 __le16 cmpl_ring;
819 __le16 seq_id;
820 __le16 target_id;
821 __le64 resp_addr;
822 __le16 fid;
823 u8 unused_0[6];
824 };
825
826 /* hwrm_func_qcaps_output (size:640b/80B) */
827 struct hwrm_func_qcaps_output {
828 __le16 error_code;
829 __le16 req_type;
830 __le16 seq_id;
831 __le16 resp_len;
832 __le16 fid;
833 __le16 port_id;
834 __le32 flags;
835 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
836 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
837 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
838 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
839 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
840 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
841 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
842 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
843 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
844 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
845 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
846 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
847 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
848 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
849 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
850 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
851 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
852 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
853 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
854 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
855 u8 mac_address[6];
856 __le16 max_rsscos_ctx;
857 __le16 max_cmpl_rings;
858 __le16 max_tx_rings;
859 __le16 max_rx_rings;
860 __le16 max_l2_ctxs;
861 __le16 max_vnics;
862 __le16 first_vf_id;
863 __le16 max_vfs;
864 __le16 max_stat_ctx;
865 __le32 max_encap_records;
866 __le32 max_decap_records;
867 __le32 max_tx_em_flows;
868 __le32 max_tx_wm_flows;
869 __le32 max_rx_em_flows;
870 __le32 max_rx_wm_flows;
871 __le32 max_mcast_filters;
872 __le32 max_flow_id;
873 __le32 max_hw_ring_grps;
874 __le16 max_sp_tx_rings;
875 u8 unused_0;
876 u8 valid;
877 };
878
879 /* hwrm_func_qcfg_input (size:192b/24B) */
880 struct hwrm_func_qcfg_input {
881 __le16 req_type;
882 __le16 cmpl_ring;
883 __le16 seq_id;
884 __le16 target_id;
885 __le64 resp_addr;
886 __le16 fid;
887 u8 unused_0[6];
888 };
889
890 /* hwrm_func_qcfg_output (size:640b/80B) */
891 struct hwrm_func_qcfg_output {
892 __le16 error_code;
893 __le16 req_type;
894 __le16 seq_id;
895 __le16 resp_len;
896 __le16 fid;
897 __le16 port_id;
898 __le16 vlan;
899 __le16 flags;
900 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL
901 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL
902 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL
903 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
904 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
905 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
906 u8 mac_address[6];
907 __le16 pci_id;
908 __le16 alloc_rsscos_ctx;
909 __le16 alloc_cmpl_rings;
910 __le16 alloc_tx_rings;
911 __le16 alloc_rx_rings;
912 __le16 alloc_l2_ctx;
913 __le16 alloc_vnics;
914 __le16 mtu;
915 __le16 mru;
916 __le16 stat_ctx_id;
917 u8 port_partition_type;
918 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL
919 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL
920 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
921 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
922 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
923 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
924 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
925 u8 port_pf_cnt;
926 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
927 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
928 __le16 dflt_vnic_id;
929 __le16 max_mtu_configured;
930 __le32 min_bw;
931 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL
932 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0
933 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL
934 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28)
935 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28)
936 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
937 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
938 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29
939 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
940 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
941 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
942 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
943 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
944 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
945 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
946 __le32 max_bw;
947 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL
948 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0
949 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL
950 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28)
951 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28)
952 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
953 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
954 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29
955 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
956 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
957 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
958 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
959 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
960 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
961 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
962 u8 evb_mode;
963 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
964 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL
965 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL
966 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA
967 u8 options;
968 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
969 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0
970 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
971 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
972 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
973 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
974 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2
975 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
976 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
977 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
978 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
979 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL
980 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4
981 __le16 alloc_vfs;
982 __le32 alloc_mcast_filters;
983 __le32 alloc_hw_ring_grps;
984 __le16 alloc_sp_tx_rings;
985 __le16 alloc_stat_ctx;
986 __le16 alloc_msix;
987 u8 unused_2[5];
988 u8 valid;
989 };
990
991 /* hwrm_func_cfg_input (size:704b/88B) */
992 struct hwrm_func_cfg_input {
993 __le16 req_type;
994 __le16 cmpl_ring;
995 __le16 seq_id;
996 __le16 target_id;
997 __le64 resp_addr;
998 __le16 fid;
999 __le16 num_msix;
1000 __le32 flags;
1001 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL
1002 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL
1003 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL
1004 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2
1005 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL
1006 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL
1007 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL
1008 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL
1009 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL
1010 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL
1011 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL
1012 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL
1013 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL
1014 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
1015 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
1016 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
1017 __le32 enables;
1018 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
1019 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
1020 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
1021 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
1022 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
1023 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
1024 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
1025 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
1026 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
1027 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
1028 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
1029 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
1030 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
1031 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
1032 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
1033 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
1034 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
1035 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
1036 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
1037 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
1038 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
1039 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
1040 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
1041 __le16 mtu;
1042 __le16 mru;
1043 __le16 num_rsscos_ctxs;
1044 __le16 num_cmpl_rings;
1045 __le16 num_tx_rings;
1046 __le16 num_rx_rings;
1047 __le16 num_l2_ctxs;
1048 __le16 num_vnics;
1049 __le16 num_stat_ctxs;
1050 __le16 num_hw_ring_grps;
1051 u8 dflt_mac_addr[6];
1052 __le16 dflt_vlan;
1053 __be32 dflt_ip_addr[4];
1054 __le32 min_bw;
1055 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1056 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0
1057 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL
1058 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28)
1059 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28)
1060 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
1061 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1062 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29
1063 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1064 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1065 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1066 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1067 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1068 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1069 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
1070 __le32 max_bw;
1071 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1072 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0
1073 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL
1074 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
1075 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
1076 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
1077 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1078 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
1079 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1080 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1081 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1082 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1083 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1084 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1085 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
1086 __le16 async_event_cr;
1087 u8 vlan_antispoof_mode;
1088 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL
1089 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL
1090 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL
1091 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
1092 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
1093 u8 allowed_vlan_pris;
1094 u8 evb_mode;
1095 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
1096 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL
1097 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL
1098 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA
1099 u8 options;
1100 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1101 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0
1102 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1103 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1104 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
1105 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1106 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2
1107 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1108 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1109 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1110 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
1111 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL
1112 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4
1113 __le16 num_mcast_filters;
1114 };
1115
1116 /* hwrm_func_cfg_output (size:128b/16B) */
1117 struct hwrm_func_cfg_output {
1118 __le16 error_code;
1119 __le16 req_type;
1120 __le16 seq_id;
1121 __le16 resp_len;
1122 u8 unused_0[7];
1123 u8 valid;
1124 };
1125
1126 /* hwrm_func_qstats_input (size:192b/24B) */
1127 struct hwrm_func_qstats_input {
1128 __le16 req_type;
1129 __le16 cmpl_ring;
1130 __le16 seq_id;
1131 __le16 target_id;
1132 __le64 resp_addr;
1133 __le16 fid;
1134 u8 unused_0[6];
1135 };
1136
1137 /* hwrm_func_qstats_output (size:1408b/176B) */
1138 struct hwrm_func_qstats_output {
1139 __le16 error_code;
1140 __le16 req_type;
1141 __le16 seq_id;
1142 __le16 resp_len;
1143 __le64 tx_ucast_pkts;
1144 __le64 tx_mcast_pkts;
1145 __le64 tx_bcast_pkts;
1146 __le64 tx_discard_pkts;
1147 __le64 tx_drop_pkts;
1148 __le64 tx_ucast_bytes;
1149 __le64 tx_mcast_bytes;
1150 __le64 tx_bcast_bytes;
1151 __le64 rx_ucast_pkts;
1152 __le64 rx_mcast_pkts;
1153 __le64 rx_bcast_pkts;
1154 __le64 rx_discard_pkts;
1155 __le64 rx_drop_pkts;
1156 __le64 rx_ucast_bytes;
1157 __le64 rx_mcast_bytes;
1158 __le64 rx_bcast_bytes;
1159 __le64 rx_agg_pkts;
1160 __le64 rx_agg_bytes;
1161 __le64 rx_agg_events;
1162 __le64 rx_agg_aborts;
1163 u8 unused_0[7];
1164 u8 valid;
1165 };
1166
1167 /* hwrm_func_clr_stats_input (size:192b/24B) */
1168 struct hwrm_func_clr_stats_input {
1169 __le16 req_type;
1170 __le16 cmpl_ring;
1171 __le16 seq_id;
1172 __le16 target_id;
1173 __le64 resp_addr;
1174 __le16 fid;
1175 u8 unused_0[6];
1176 };
1177
1178 /* hwrm_func_clr_stats_output (size:128b/16B) */
1179 struct hwrm_func_clr_stats_output {
1180 __le16 error_code;
1181 __le16 req_type;
1182 __le16 seq_id;
1183 __le16 resp_len;
1184 u8 unused_0[7];
1185 u8 valid;
1186 };
1187
1188 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
1189 struct hwrm_func_vf_resc_free_input {
1190 __le16 req_type;
1191 __le16 cmpl_ring;
1192 __le16 seq_id;
1193 __le16 target_id;
1194 __le64 resp_addr;
1195 __le16 vf_id;
1196 u8 unused_0[6];
1197 };
1198
1199 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
1200 struct hwrm_func_vf_resc_free_output {
1201 __le16 error_code;
1202 __le16 req_type;
1203 __le16 seq_id;
1204 __le16 resp_len;
1205 u8 unused_0[7];
1206 u8 valid;
1207 };
1208
1209 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
1210 struct hwrm_func_drv_rgtr_input {
1211 __le16 req_type;
1212 __le16 cmpl_ring;
1213 __le16 seq_id;
1214 __le16 target_id;
1215 __le64 resp_addr;
1216 __le32 flags;
1217 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1218 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1219 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
1220 __le32 enables;
1221 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1222 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
1223 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
1224 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
1225 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
1226 __le16 os_type;
1227 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL
1228 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
1229 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL
1230 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL
1231 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL
1232 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL
1233 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL
1234 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL
1235 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL
1236 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
1237 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL
1238 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
1239 u8 ver_maj_8b;
1240 u8 ver_min_8b;
1241 u8 ver_upd_8b;
1242 u8 unused_0[3];
1243 __le32 timestamp;
1244 u8 unused_1[4];
1245 __le32 vf_req_fwd[8];
1246 __le32 async_event_fwd[8];
1247 __le16 ver_maj;
1248 __le16 ver_min;
1249 __le16 ver_upd;
1250 __le16 ver_patch;
1251 };
1252
1253 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
1254 struct hwrm_func_drv_rgtr_output {
1255 __le16 error_code;
1256 __le16 req_type;
1257 __le16 seq_id;
1258 __le16 resp_len;
1259 __le32 flags;
1260 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL
1261 u8 unused_0[3];
1262 u8 valid;
1263 };
1264
1265 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
1266 struct hwrm_func_drv_unrgtr_input {
1267 __le16 req_type;
1268 __le16 cmpl_ring;
1269 __le16 seq_id;
1270 __le16 target_id;
1271 __le64 resp_addr;
1272 __le32 flags;
1273 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
1274 u8 unused_0[4];
1275 };
1276
1277 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
1278 struct hwrm_func_drv_unrgtr_output {
1279 __le16 error_code;
1280 __le16 req_type;
1281 __le16 seq_id;
1282 __le16 resp_len;
1283 u8 unused_0[7];
1284 u8 valid;
1285 };
1286
1287 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
1288 struct hwrm_func_buf_rgtr_input {
1289 __le16 req_type;
1290 __le16 cmpl_ring;
1291 __le16 seq_id;
1292 __le16 target_id;
1293 __le64 resp_addr;
1294 __le32 enables;
1295 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
1296 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
1297 __le16 vf_id;
1298 __le16 req_buf_num_pages;
1299 __le16 req_buf_page_size;
1300 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
1301 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL
1302 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL
1303 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
1304 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL
1305 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL
1306 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL
1307 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
1308 __le16 req_buf_len;
1309 __le16 resp_buf_len;
1310 u8 unused_0[2];
1311 __le64 req_buf_page_addr0;
1312 __le64 req_buf_page_addr1;
1313 __le64 req_buf_page_addr2;
1314 __le64 req_buf_page_addr3;
1315 __le64 req_buf_page_addr4;
1316 __le64 req_buf_page_addr5;
1317 __le64 req_buf_page_addr6;
1318 __le64 req_buf_page_addr7;
1319 __le64 req_buf_page_addr8;
1320 __le64 req_buf_page_addr9;
1321 __le64 error_buf_addr;
1322 __le64 resp_buf_addr;
1323 };
1324
1325 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
1326 struct hwrm_func_buf_rgtr_output {
1327 __le16 error_code;
1328 __le16 req_type;
1329 __le16 seq_id;
1330 __le16 resp_len;
1331 u8 unused_0[7];
1332 u8 valid;
1333 };
1334
1335 /* hwrm_func_drv_qver_input (size:192b/24B) */
1336 struct hwrm_func_drv_qver_input {
1337 __le16 req_type;
1338 __le16 cmpl_ring;
1339 __le16 seq_id;
1340 __le16 target_id;
1341 __le64 resp_addr;
1342 __le32 reserved;
1343 __le16 fid;
1344 u8 unused_0[2];
1345 };
1346
1347 /* hwrm_func_drv_qver_output (size:256b/32B) */
1348 struct hwrm_func_drv_qver_output {
1349 __le16 error_code;
1350 __le16 req_type;
1351 __le16 seq_id;
1352 __le16 resp_len;
1353 __le16 os_type;
1354 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL
1355 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL
1356 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL
1357 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL
1358 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL
1359 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL
1360 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL
1361 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL
1362 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL
1363 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
1364 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL
1365 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
1366 u8 ver_maj_8b;
1367 u8 ver_min_8b;
1368 u8 ver_upd_8b;
1369 u8 unused_0[3];
1370 __le16 ver_maj;
1371 __le16 ver_min;
1372 __le16 ver_upd;
1373 __le16 ver_patch;
1374 u8 unused_1[7];
1375 u8 valid;
1376 };
1377
1378 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
1379 struct hwrm_func_resource_qcaps_input {
1380 __le16 req_type;
1381 __le16 cmpl_ring;
1382 __le16 seq_id;
1383 __le16 target_id;
1384 __le64 resp_addr;
1385 __le16 fid;
1386 u8 unused_0[6];
1387 };
1388
1389 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
1390 struct hwrm_func_resource_qcaps_output {
1391 __le16 error_code;
1392 __le16 req_type;
1393 __le16 seq_id;
1394 __le16 resp_len;
1395 __le16 max_vfs;
1396 __le16 max_msix;
1397 __le16 vf_reservation_strategy;
1398 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL
1399 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL
1400 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
1401 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
1402 __le16 min_rsscos_ctx;
1403 __le16 max_rsscos_ctx;
1404 __le16 min_cmpl_rings;
1405 __le16 max_cmpl_rings;
1406 __le16 min_tx_rings;
1407 __le16 max_tx_rings;
1408 __le16 min_rx_rings;
1409 __le16 max_rx_rings;
1410 __le16 min_l2_ctxs;
1411 __le16 max_l2_ctxs;
1412 __le16 min_vnics;
1413 __le16 max_vnics;
1414 __le16 min_stat_ctx;
1415 __le16 max_stat_ctx;
1416 __le16 min_hw_ring_grps;
1417 __le16 max_hw_ring_grps;
1418 __le16 max_tx_scheduler_inputs;
1419 u8 unused_0[7];
1420 u8 valid;
1421 };
1422
1423 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
1424 struct hwrm_func_vf_resource_cfg_input {
1425 __le16 req_type;
1426 __le16 cmpl_ring;
1427 __le16 seq_id;
1428 __le16 target_id;
1429 __le64 resp_addr;
1430 __le16 vf_id;
1431 __le16 max_msix;
1432 __le16 min_rsscos_ctx;
1433 __le16 max_rsscos_ctx;
1434 __le16 min_cmpl_rings;
1435 __le16 max_cmpl_rings;
1436 __le16 min_tx_rings;
1437 __le16 max_tx_rings;
1438 __le16 min_rx_rings;
1439 __le16 max_rx_rings;
1440 __le16 min_l2_ctxs;
1441 __le16 max_l2_ctxs;
1442 __le16 min_vnics;
1443 __le16 max_vnics;
1444 __le16 min_stat_ctx;
1445 __le16 max_stat_ctx;
1446 __le16 min_hw_ring_grps;
1447 __le16 max_hw_ring_grps;
1448 u8 unused_0[4];
1449 };
1450
1451 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
1452 struct hwrm_func_vf_resource_cfg_output {
1453 __le16 error_code;
1454 __le16 req_type;
1455 __le16 seq_id;
1456 __le16 resp_len;
1457 __le16 reserved_rsscos_ctx;
1458 __le16 reserved_cmpl_rings;
1459 __le16 reserved_tx_rings;
1460 __le16 reserved_rx_rings;
1461 __le16 reserved_l2_ctxs;
1462 __le16 reserved_vnics;
1463 __le16 reserved_stat_ctx;
1464 __le16 reserved_hw_ring_grps;
1465 u8 unused_0[7];
1466 u8 valid;
1467 };
1468
1469 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
1470 struct hwrm_func_backing_store_qcaps_input {
1471 __le16 req_type;
1472 __le16 cmpl_ring;
1473 __le16 seq_id;
1474 __le16 target_id;
1475 __le64 resp_addr;
1476 };
1477
1478 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
1479 struct hwrm_func_backing_store_qcaps_output {
1480 __le16 error_code;
1481 __le16 req_type;
1482 __le16 seq_id;
1483 __le16 resp_len;
1484 __le32 qp_max_entries;
1485 __le16 qp_min_qp1_entries;
1486 __le16 qp_max_l2_entries;
1487 __le16 qp_entry_size;
1488 __le16 srq_max_l2_entries;
1489 __le32 srq_max_entries;
1490 __le16 srq_entry_size;
1491 __le16 cq_max_l2_entries;
1492 __le32 cq_max_entries;
1493 __le16 cq_entry_size;
1494 __le16 vnic_max_vnic_entries;
1495 __le16 vnic_max_ring_table_entries;
1496 __le16 vnic_entry_size;
1497 __le32 stat_max_entries;
1498 __le16 stat_entry_size;
1499 __le16 tqm_entry_size;
1500 __le32 tqm_min_entries_per_ring;
1501 __le32 tqm_max_entries_per_ring;
1502 __le32 mrav_max_entries;
1503 __le16 mrav_entry_size;
1504 __le16 tim_entry_size;
1505 __le32 tim_max_entries;
1506 u8 unused_0[3];
1507 u8 valid;
1508 };
1509
1510 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
1511 struct hwrm_func_backing_store_cfg_input {
1512 __le16 req_type;
1513 __le16 cmpl_ring;
1514 __le16 seq_id;
1515 __le16 target_id;
1516 __le64 resp_addr;
1517 __le32 flags;
1518 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
1519 __le32 enables;
1520 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL
1521 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL
1522 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL
1523 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL
1524 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL
1525 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL
1526 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL
1527 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL
1528 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL
1529 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL
1530 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL
1531 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL
1532 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL
1533 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL
1534 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL
1535 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL
1536 u8 qpc_pg_size_qpc_lvl;
1537 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL
1538 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0
1539 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL
1540 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL
1541 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL
1542 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
1543 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL
1544 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4
1545 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4)
1546 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4)
1547 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4)
1548 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4)
1549 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4)
1550 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4)
1551 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
1552 u8 srq_pg_size_srq_lvl;
1553 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL
1554 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0
1555 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL
1556 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL
1557 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL
1558 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
1559 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL
1560 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4
1561 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
1562 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
1563 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
1564 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
1565 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
1566 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
1567 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
1568 u8 cq_pg_size_cq_lvl;
1569 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL
1570 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0
1571 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL
1572 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL
1573 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL
1574 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
1575 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL
1576 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4
1577 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4)
1578 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4)
1579 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4)
1580 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4)
1581 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4)
1582 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4)
1583 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
1584 u8 vnic_pg_size_vnic_lvl;
1585 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL
1586 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0
1587 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL
1588 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL
1589 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL
1590 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
1591 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL
1592 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4
1593 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
1594 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
1595 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
1596 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
1597 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
1598 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
1599 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
1600 u8 stat_pg_size_stat_lvl;
1601 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL
1602 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0
1603 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL
1604 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL
1605 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL
1606 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
1607 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL
1608 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4
1609 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4)
1610 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4)
1611 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4)
1612 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4)
1613 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4)
1614 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4)
1615 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
1616 u8 tqm_sp_pg_size_tqm_sp_lvl;
1617 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL
1618 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0
1619 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL
1620 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL
1621 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL
1622 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
1623 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL
1624 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4
1625 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
1626 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
1627 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
1628 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
1629 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
1630 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
1631 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
1632 u8 tqm_ring0_pg_size_tqm_ring0_lvl;
1633 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL
1634 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0
1635 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL
1636 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL
1637 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL
1638 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
1639 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL
1640 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4
1641 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
1642 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
1643 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
1644 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
1645 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
1646 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
1647 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
1648 u8 tqm_ring1_pg_size_tqm_ring1_lvl;
1649 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL
1650 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0
1651 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL
1652 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL
1653 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL
1654 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
1655 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL
1656 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4
1657 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
1658 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
1659 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
1660 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
1661 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
1662 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
1663 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
1664 u8 tqm_ring2_pg_size_tqm_ring2_lvl;
1665 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL
1666 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0
1667 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL
1668 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL
1669 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL
1670 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
1671 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL
1672 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4
1673 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
1674 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
1675 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
1676 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
1677 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
1678 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
1679 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
1680 u8 tqm_ring3_pg_size_tqm_ring3_lvl;
1681 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL
1682 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0
1683 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL
1684 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL
1685 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL
1686 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
1687 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL
1688 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4
1689 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
1690 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
1691 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
1692 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
1693 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
1694 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
1695 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
1696 u8 tqm_ring4_pg_size_tqm_ring4_lvl;
1697 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL
1698 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0
1699 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL
1700 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL
1701 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL
1702 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
1703 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL
1704 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4
1705 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
1706 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
1707 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
1708 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
1709 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
1710 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
1711 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
1712 u8 tqm_ring5_pg_size_tqm_ring5_lvl;
1713 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL
1714 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0
1715 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL
1716 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL
1717 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL
1718 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
1719 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL
1720 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4
1721 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
1722 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
1723 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
1724 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
1725 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
1726 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
1727 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
1728 u8 tqm_ring6_pg_size_tqm_ring6_lvl;
1729 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL
1730 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0
1731 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL
1732 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL
1733 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL
1734 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
1735 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL
1736 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4
1737 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
1738 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
1739 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
1740 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
1741 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
1742 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
1743 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
1744 u8 tqm_ring7_pg_size_tqm_ring7_lvl;
1745 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL
1746 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0
1747 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL
1748 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL
1749 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL
1750 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
1751 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL
1752 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4
1753 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
1754 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
1755 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
1756 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
1757 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
1758 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
1759 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
1760 u8 mrav_pg_size_mrav_lvl;
1761 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL
1762 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0
1763 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL
1764 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL
1765 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL
1766 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
1767 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL
1768 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4
1769 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
1770 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
1771 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
1772 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
1773 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
1774 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
1775 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
1776 u8 tim_pg_size_tim_lvl;
1777 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL
1778 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0
1779 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL
1780 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL
1781 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL
1782 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
1783 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL
1784 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4
1785 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4)
1786 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4)
1787 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4)
1788 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4)
1789 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4)
1790 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4)
1791 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
1792 __le64 qpc_page_dir;
1793 __le64 srq_page_dir;
1794 __le64 cq_page_dir;
1795 __le64 vnic_page_dir;
1796 __le64 stat_page_dir;
1797 __le64 tqm_sp_page_dir;
1798 __le64 tqm_ring0_page_dir;
1799 __le64 tqm_ring1_page_dir;
1800 __le64 tqm_ring2_page_dir;
1801 __le64 tqm_ring3_page_dir;
1802 __le64 tqm_ring4_page_dir;
1803 __le64 tqm_ring5_page_dir;
1804 __le64 tqm_ring6_page_dir;
1805 __le64 tqm_ring7_page_dir;
1806 __le64 mrav_page_dir;
1807 __le64 tim_page_dir;
1808 __le32 qp_num_entries;
1809 __le32 srq_num_entries;
1810 __le32 cq_num_entries;
1811 __le32 stat_num_entries;
1812 __le32 tqm_sp_num_entries;
1813 __le32 tqm_ring0_num_entries;
1814 __le32 tqm_ring1_num_entries;
1815 __le32 tqm_ring2_num_entries;
1816 __le32 tqm_ring3_num_entries;
1817 __le32 tqm_ring4_num_entries;
1818 __le32 tqm_ring5_num_entries;
1819 __le32 tqm_ring6_num_entries;
1820 __le32 tqm_ring7_num_entries;
1821 __le32 mrav_num_entries;
1822 __le32 tim_num_entries;
1823 __le16 qp_num_qp1_entries;
1824 __le16 qp_num_l2_entries;
1825 __le16 qp_entry_size;
1826 __le16 srq_num_l2_entries;
1827 __le16 srq_entry_size;
1828 __le16 cq_num_l2_entries;
1829 __le16 cq_entry_size;
1830 __le16 vnic_num_vnic_entries;
1831 __le16 vnic_num_ring_table_entries;
1832 __le16 vnic_entry_size;
1833 __le16 stat_entry_size;
1834 __le16 tqm_entry_size;
1835 __le16 mrav_entry_size;
1836 __le16 tim_entry_size;
1837 };
1838
1839 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
1840 struct hwrm_func_backing_store_cfg_output {
1841 __le16 error_code;
1842 __le16 req_type;
1843 __le16 seq_id;
1844 __le16 resp_len;
1845 u8 unused_0[7];
1846 u8 valid;
1847 };
1848
1849 /* hwrm_func_drv_if_change_input (size:192b/24B) */
1850 struct hwrm_func_drv_if_change_input {
1851 __le16 req_type;
1852 __le16 cmpl_ring;
1853 __le16 seq_id;
1854 __le16 target_id;
1855 __le64 resp_addr;
1856 __le32 flags;
1857 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL
1858 __le32 unused;
1859 };
1860
1861 /* hwrm_func_drv_if_change_output (size:128b/16B) */
1862 struct hwrm_func_drv_if_change_output {
1863 __le16 error_code;
1864 __le16 req_type;
1865 __le16 seq_id;
1866 __le16 resp_len;
1867 __le32 flags;
1868 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
1869 u8 unused_0[3];
1870 u8 valid;
1871 };
1872
1873 /* hwrm_port_phy_cfg_input (size:448b/56B) */
1874 struct hwrm_port_phy_cfg_input {
1875 __le16 req_type;
1876 __le16 cmpl_ring;
1877 __le16 seq_id;
1878 __le16 target_id;
1879 __le64 resp_addr;
1880 __le32 flags;
1881 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
1882 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
1883 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
1884 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
1885 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
1886 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
1887 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
1888 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
1889 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
1890 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
1891 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
1892 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
1893 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
1894 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
1895 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
1896 __le32 enables;
1897 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
1898 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
1899 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
1900 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
1901 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
1902 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
1903 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
1904 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
1905 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
1906 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
1907 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
1908 __le16 port_id;
1909 __le16 force_link_speed;
1910 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
1911 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
1912 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL
1913 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
1914 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
1915 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL
1916 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
1917 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
1918 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
1919 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
1920 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL
1921 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
1922 u8 auto_mode;
1923 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL
1924 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL
1925 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL
1926 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
1927 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
1928 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
1929 u8 auto_duplex;
1930 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
1931 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
1932 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
1933 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
1934 u8 auto_pause;
1935 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
1936 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
1937 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
1938 u8 unused_0;
1939 __le16 auto_link_speed;
1940 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
1941 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL
1942 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL
1943 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
1944 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL
1945 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL
1946 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL
1947 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL
1948 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL
1949 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
1950 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL
1951 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
1952 __le16 auto_link_speed_mask;
1953 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
1954 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
1955 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
1956 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
1957 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
1958 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
1959 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
1960 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
1961 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
1962 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
1963 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
1964 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
1965 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
1966 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
1967 u8 wirespeed;
1968 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
1969 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
1970 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
1971 u8 lpbk;
1972 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL
1973 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL
1974 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL
1975 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
1976 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL
1977 u8 force_pause;
1978 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
1979 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
1980 u8 unused_1;
1981 __le32 preemphasis;
1982 __le16 eee_link_speed_mask;
1983 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
1984 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
1985 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
1986 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
1987 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
1988 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
1989 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
1990 u8 unused_2[2];
1991 __le32 tx_lpi_timer;
1992 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
1993 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
1994 __le32 unused_3;
1995 };
1996
1997 /* hwrm_port_phy_cfg_output (size:128b/16B) */
1998 struct hwrm_port_phy_cfg_output {
1999 __le16 error_code;
2000 __le16 req_type;
2001 __le16 seq_id;
2002 __le16 resp_len;
2003 u8 unused_0[7];
2004 u8 valid;
2005 };
2006
2007 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
2008 struct hwrm_port_phy_cfg_cmd_err {
2009 u8 code;
2010 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
2011 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
2012 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL
2013 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY
2014 u8 unused_0[7];
2015 };
2016
2017 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
2018 struct hwrm_port_phy_qcfg_input {
2019 __le16 req_type;
2020 __le16 cmpl_ring;
2021 __le16 seq_id;
2022 __le16 target_id;
2023 __le64 resp_addr;
2024 __le16 port_id;
2025 u8 unused_0[6];
2026 };
2027
2028 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
2029 struct hwrm_port_phy_qcfg_output {
2030 __le16 error_code;
2031 __le16 req_type;
2032 __le16 seq_id;
2033 __le16 resp_len;
2034 u8 link;
2035 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
2036 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
2037 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
2038 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
2039 u8 unused_0;
2040 __le16 link_speed;
2041 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
2042 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
2043 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
2044 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
2045 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
2046 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
2047 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
2048 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
2049 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
2050 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
2051 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
2052 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
2053 u8 duplex_cfg;
2054 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
2055 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
2056 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
2057 u8 pause;
2058 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
2059 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
2060 __le16 support_speeds;
2061 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
2062 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
2063 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
2064 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
2065 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
2066 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
2067 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
2068 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
2069 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
2070 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
2071 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
2072 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
2073 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
2074 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
2075 __le16 force_link_speed;
2076 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
2077 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL
2078 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL
2079 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
2080 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL
2081 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL
2082 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL
2083 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL
2084 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL
2085 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
2086 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL
2087 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
2088 u8 auto_mode;
2089 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL
2090 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL
2091 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL
2092 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
2093 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL
2094 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
2095 u8 auto_pause;
2096 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
2097 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
2098 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
2099 __le16 auto_link_speed;
2100 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
2101 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL
2102 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL
2103 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
2104 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL
2105 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL
2106 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL
2107 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL
2108 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL
2109 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
2110 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL
2111 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
2112 __le16 auto_link_speed_mask;
2113 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
2114 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
2115 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
2116 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
2117 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
2118 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
2119 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
2120 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
2121 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
2122 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
2123 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
2124 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
2125 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
2126 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
2127 u8 wirespeed;
2128 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
2129 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
2130 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
2131 u8 lpbk;
2132 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL
2133 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL
2134 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL
2135 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
2136 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
2137 u8 force_pause;
2138 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
2139 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
2140 u8 module_status;
2141 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL
2142 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL
2143 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL
2144 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL
2145 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL
2146 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
2147 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
2148 __le32 preemphasis;
2149 u8 phy_maj;
2150 u8 phy_min;
2151 u8 phy_bld;
2152 u8 phy_type;
2153 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL
2154 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL
2155 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL
2156 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL
2157 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL
2158 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL
2159 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL
2160 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL
2161 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL
2162 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL
2163 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL
2164 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL
2165 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL
2166 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL
2167 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL
2168 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL
2169 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL
2170 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL
2171 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL
2172 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL
2173 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL
2174 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL
2175 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL
2176 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL
2177 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
2178 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
2179 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
2180 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
2181 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX
2182 u8 media_type;
2183 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
2184 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
2185 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
2186 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
2187 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
2188 u8 xcvr_pkg_type;
2189 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
2190 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
2191 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
2192 u8 eee_config_phy_addr;
2193 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
2194 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
2195 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
2196 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
2197 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
2198 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
2199 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
2200 u8 parallel_detect;
2201 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
2202 __le16 link_partner_adv_speeds;
2203 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
2204 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
2205 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
2206 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
2207 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
2208 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
2209 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
2210 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
2211 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
2212 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
2213 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
2214 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
2215 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
2216 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
2217 u8 link_partner_adv_auto_mode;
2218 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL
2219 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL
2220 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL
2221 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
2222 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL
2223 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
2224 u8 link_partner_adv_pause;
2225 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
2226 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
2227 __le16 adv_eee_link_speed_mask;
2228 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
2229 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
2230 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
2231 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
2232 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
2233 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
2234 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
2235 __le16 link_partner_adv_eee_link_speed_mask;
2236 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
2237 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
2238 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
2239 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
2240 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
2241 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
2242 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
2243 __le32 xcvr_identifier_type_tx_lpi_timer;
2244 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
2245 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
2246 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
2247 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
2248 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
2249 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
2250 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
2251 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
2252 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
2253 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
2254 __le16 fec_cfg;
2255 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
2256 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
2257 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
2258 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
2259 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
2260 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
2261 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
2262 u8 duplex_state;
2263 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
2264 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
2265 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
2266 u8 option_flags;
2267 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
2268 char phy_vendor_name[16];
2269 char phy_vendor_partnumber[16];
2270 u8 unused_2[7];
2271 u8 valid;
2272 };
2273
2274 /* hwrm_port_mac_cfg_input (size:320b/40B) */
2275 struct hwrm_port_mac_cfg_input {
2276 __le16 req_type;
2277 __le16 cmpl_ring;
2278 __le16 seq_id;
2279 __le16 target_id;
2280 __le64 resp_addr;
2281 __le32 flags;
2282 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
2283 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL
2284 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
2285 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
2286 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
2287 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
2288 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
2289 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
2290 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL
2291 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL
2292 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL
2293 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL
2294 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL
2295 __le32 enables;
2296 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
2297 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
2298 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL
2299 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
2300 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
2301 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
2302 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
2303 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
2304 __le16 port_id;
2305 u8 ipg;
2306 u8 lpbk;
2307 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
2308 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL
2309 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
2310 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE
2311 u8 vlan_pri2cos_map_pri;
2312 u8 reserved1;
2313 u8 tunnel_pri2cos_map_pri;
2314 u8 dscp2pri_map_pri;
2315 __le16 rx_ts_capture_ptp_msg_type;
2316 __le16 tx_ts_capture_ptp_msg_type;
2317 u8 cos_field_cfg;
2318 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL
2319 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
2320 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
2321 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
2322 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
2323 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
2324 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
2325 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
2326 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
2327 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
2328 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
2329 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
2330 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
2331 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
2332 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
2333 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
2334 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
2335 u8 unused_0[3];
2336 };
2337
2338 /* hwrm_port_mac_cfg_output (size:128b/16B) */
2339 struct hwrm_port_mac_cfg_output {
2340 __le16 error_code;
2341 __le16 req_type;
2342 __le16 seq_id;
2343 __le16 resp_len;
2344 __le16 mru;
2345 __le16 mtu;
2346 u8 ipg;
2347 u8 lpbk;
2348 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL
2349 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL
2350 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
2351 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE
2352 u8 unused_0;
2353 u8 valid;
2354 };
2355
2356 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
2357 struct hwrm_port_mac_ptp_qcfg_input {
2358 __le16 req_type;
2359 __le16 cmpl_ring;
2360 __le16 seq_id;
2361 __le16 target_id;
2362 __le64 resp_addr;
2363 __le16 port_id;
2364 u8 unused_0[6];
2365 };
2366
2367 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
2368 struct hwrm_port_mac_ptp_qcfg_output {
2369 __le16 error_code;
2370 __le16 req_type;
2371 __le16 seq_id;
2372 __le16 resp_len;
2373 u8 flags;
2374 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
2375 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL
2376 u8 unused_0[3];
2377 __le32 rx_ts_reg_off_lower;
2378 __le32 rx_ts_reg_off_upper;
2379 __le32 rx_ts_reg_off_seq_id;
2380 __le32 rx_ts_reg_off_src_id_0;
2381 __le32 rx_ts_reg_off_src_id_1;
2382 __le32 rx_ts_reg_off_src_id_2;
2383 __le32 rx_ts_reg_off_domain_id;
2384 __le32 rx_ts_reg_off_fifo;
2385 __le32 rx_ts_reg_off_fifo_adv;
2386 __le32 rx_ts_reg_off_granularity;
2387 __le32 tx_ts_reg_off_lower;
2388 __le32 tx_ts_reg_off_upper;
2389 __le32 tx_ts_reg_off_seq_id;
2390 __le32 tx_ts_reg_off_fifo;
2391 __le32 tx_ts_reg_off_granularity;
2392 u8 unused_1[7];
2393 u8 valid;
2394 };
2395
2396 /* tx_port_stats (size:3264b/408B) */
2397 struct tx_port_stats {
2398 __le64 tx_64b_frames;
2399 __le64 tx_65b_127b_frames;
2400 __le64 tx_128b_255b_frames;
2401 __le64 tx_256b_511b_frames;
2402 __le64 tx_512b_1023b_frames;
2403 __le64 tx_1024b_1518b_frames;
2404 __le64 tx_good_vlan_frames;
2405 __le64 tx_1519b_2047b_frames;
2406 __le64 tx_2048b_4095b_frames;
2407 __le64 tx_4096b_9216b_frames;
2408 __le64 tx_9217b_16383b_frames;
2409 __le64 tx_good_frames;
2410 __le64 tx_total_frames;
2411 __le64 tx_ucast_frames;
2412 __le64 tx_mcast_frames;
2413 __le64 tx_bcast_frames;
2414 __le64 tx_pause_frames;
2415 __le64 tx_pfc_frames;
2416 __le64 tx_jabber_frames;
2417 __le64 tx_fcs_err_frames;
2418 __le64 tx_control_frames;
2419 __le64 tx_oversz_frames;
2420 __le64 tx_single_dfrl_frames;
2421 __le64 tx_multi_dfrl_frames;
2422 __le64 tx_single_coll_frames;
2423 __le64 tx_multi_coll_frames;
2424 __le64 tx_late_coll_frames;
2425 __le64 tx_excessive_coll_frames;
2426 __le64 tx_frag_frames;
2427 __le64 tx_err;
2428 __le64 tx_tagged_frames;
2429 __le64 tx_dbl_tagged_frames;
2430 __le64 tx_runt_frames;
2431 __le64 tx_fifo_underruns;
2432 __le64 tx_pfc_ena_frames_pri0;
2433 __le64 tx_pfc_ena_frames_pri1;
2434 __le64 tx_pfc_ena_frames_pri2;
2435 __le64 tx_pfc_ena_frames_pri3;
2436 __le64 tx_pfc_ena_frames_pri4;
2437 __le64 tx_pfc_ena_frames_pri5;
2438 __le64 tx_pfc_ena_frames_pri6;
2439 __le64 tx_pfc_ena_frames_pri7;
2440 __le64 tx_eee_lpi_events;
2441 __le64 tx_eee_lpi_duration;
2442 __le64 tx_llfc_logical_msgs;
2443 __le64 tx_hcfc_msgs;
2444 __le64 tx_total_collisions;
2445 __le64 tx_bytes;
2446 __le64 tx_xthol_frames;
2447 __le64 tx_stat_discard;
2448 __le64 tx_stat_error;
2449 };
2450
2451 /* rx_port_stats (size:4224b/528B) */
2452 struct rx_port_stats {
2453 __le64 rx_64b_frames;
2454 __le64 rx_65b_127b_frames;
2455 __le64 rx_128b_255b_frames;
2456 __le64 rx_256b_511b_frames;
2457 __le64 rx_512b_1023b_frames;
2458 __le64 rx_1024b_1518b_frames;
2459 __le64 rx_good_vlan_frames;
2460 __le64 rx_1519b_2047b_frames;
2461 __le64 rx_2048b_4095b_frames;
2462 __le64 rx_4096b_9216b_frames;
2463 __le64 rx_9217b_16383b_frames;
2464 __le64 rx_total_frames;
2465 __le64 rx_ucast_frames;
2466 __le64 rx_mcast_frames;
2467 __le64 rx_bcast_frames;
2468 __le64 rx_fcs_err_frames;
2469 __le64 rx_ctrl_frames;
2470 __le64 rx_pause_frames;
2471 __le64 rx_pfc_frames;
2472 __le64 rx_unsupported_opcode_frames;
2473 __le64 rx_unsupported_da_pausepfc_frames;
2474 __le64 rx_wrong_sa_frames;
2475 __le64 rx_align_err_frames;
2476 __le64 rx_oor_len_frames;
2477 __le64 rx_code_err_frames;
2478 __le64 rx_false_carrier_frames;
2479 __le64 rx_ovrsz_frames;
2480 __le64 rx_jbr_frames;
2481 __le64 rx_mtu_err_frames;
2482 __le64 rx_match_crc_frames;
2483 __le64 rx_promiscuous_frames;
2484 __le64 rx_tagged_frames;
2485 __le64 rx_double_tagged_frames;
2486 __le64 rx_trunc_frames;
2487 __le64 rx_good_frames;
2488 __le64 rx_pfc_xon2xoff_frames_pri0;
2489 __le64 rx_pfc_xon2xoff_frames_pri1;
2490 __le64 rx_pfc_xon2xoff_frames_pri2;
2491 __le64 rx_pfc_xon2xoff_frames_pri3;
2492 __le64 rx_pfc_xon2xoff_frames_pri4;
2493 __le64 rx_pfc_xon2xoff_frames_pri5;
2494 __le64 rx_pfc_xon2xoff_frames_pri6;
2495 __le64 rx_pfc_xon2xoff_frames_pri7;
2496 __le64 rx_pfc_ena_frames_pri0;
2497 __le64 rx_pfc_ena_frames_pri1;
2498 __le64 rx_pfc_ena_frames_pri2;
2499 __le64 rx_pfc_ena_frames_pri3;
2500 __le64 rx_pfc_ena_frames_pri4;
2501 __le64 rx_pfc_ena_frames_pri5;
2502 __le64 rx_pfc_ena_frames_pri6;
2503 __le64 rx_pfc_ena_frames_pri7;
2504 __le64 rx_sch_crc_err_frames;
2505 __le64 rx_undrsz_frames;
2506 __le64 rx_frag_frames;
2507 __le64 rx_eee_lpi_events;
2508 __le64 rx_eee_lpi_duration;
2509 __le64 rx_llfc_physical_msgs;
2510 __le64 rx_llfc_logical_msgs;
2511 __le64 rx_llfc_msgs_with_crc_err;
2512 __le64 rx_hcfc_msgs;
2513 __le64 rx_hcfc_msgs_with_crc_err;
2514 __le64 rx_bytes;
2515 __le64 rx_runt_bytes;
2516 __le64 rx_runt_frames;
2517 __le64 rx_stat_discard;
2518 __le64 rx_stat_err;
2519 };
2520
2521 /* hwrm_port_qstats_input (size:320b/40B) */
2522 struct hwrm_port_qstats_input {
2523 __le16 req_type;
2524 __le16 cmpl_ring;
2525 __le16 seq_id;
2526 __le16 target_id;
2527 __le64 resp_addr;
2528 __le16 port_id;
2529 u8 unused_0[6];
2530 __le64 tx_stat_host_addr;
2531 __le64 rx_stat_host_addr;
2532 };
2533
2534 /* hwrm_port_qstats_output (size:128b/16B) */
2535 struct hwrm_port_qstats_output {
2536 __le16 error_code;
2537 __le16 req_type;
2538 __le16 seq_id;
2539 __le16 resp_len;
2540 __le16 tx_stat_size;
2541 __le16 rx_stat_size;
2542 u8 unused_0[3];
2543 u8 valid;
2544 };
2545
2546 /* tx_port_stats_ext (size:2048b/256B) */
2547 struct tx_port_stats_ext {
2548 __le64 tx_bytes_cos0;
2549 __le64 tx_bytes_cos1;
2550 __le64 tx_bytes_cos2;
2551 __le64 tx_bytes_cos3;
2552 __le64 tx_bytes_cos4;
2553 __le64 tx_bytes_cos5;
2554 __le64 tx_bytes_cos6;
2555 __le64 tx_bytes_cos7;
2556 __le64 tx_packets_cos0;
2557 __le64 tx_packets_cos1;
2558 __le64 tx_packets_cos2;
2559 __le64 tx_packets_cos3;
2560 __le64 tx_packets_cos4;
2561 __le64 tx_packets_cos5;
2562 __le64 tx_packets_cos6;
2563 __le64 tx_packets_cos7;
2564 __le64 pfc_pri0_tx_duration_us;
2565 __le64 pfc_pri0_tx_transitions;
2566 __le64 pfc_pri1_tx_duration_us;
2567 __le64 pfc_pri1_tx_transitions;
2568 __le64 pfc_pri2_tx_duration_us;
2569 __le64 pfc_pri2_tx_transitions;
2570 __le64 pfc_pri3_tx_duration_us;
2571 __le64 pfc_pri3_tx_transitions;
2572 __le64 pfc_pri4_tx_duration_us;
2573 __le64 pfc_pri4_tx_transitions;
2574 __le64 pfc_pri5_tx_duration_us;
2575 __le64 pfc_pri5_tx_transitions;
2576 __le64 pfc_pri6_tx_duration_us;
2577 __le64 pfc_pri6_tx_transitions;
2578 __le64 pfc_pri7_tx_duration_us;
2579 __le64 pfc_pri7_tx_transitions;
2580 };
2581
2582 /* rx_port_stats_ext (size:2368b/296B) */
2583 struct rx_port_stats_ext {
2584 __le64 link_down_events;
2585 __le64 continuous_pause_events;
2586 __le64 resume_pause_events;
2587 __le64 continuous_roce_pause_events;
2588 __le64 resume_roce_pause_events;
2589 __le64 rx_bytes_cos0;
2590 __le64 rx_bytes_cos1;
2591 __le64 rx_bytes_cos2;
2592 __le64 rx_bytes_cos3;
2593 __le64 rx_bytes_cos4;
2594 __le64 rx_bytes_cos5;
2595 __le64 rx_bytes_cos6;
2596 __le64 rx_bytes_cos7;
2597 __le64 rx_packets_cos0;
2598 __le64 rx_packets_cos1;
2599 __le64 rx_packets_cos2;
2600 __le64 rx_packets_cos3;
2601 __le64 rx_packets_cos4;
2602 __le64 rx_packets_cos5;
2603 __le64 rx_packets_cos6;
2604 __le64 rx_packets_cos7;
2605 __le64 pfc_pri0_rx_duration_us;
2606 __le64 pfc_pri0_rx_transitions;
2607 __le64 pfc_pri1_rx_duration_us;
2608 __le64 pfc_pri1_rx_transitions;
2609 __le64 pfc_pri2_rx_duration_us;
2610 __le64 pfc_pri2_rx_transitions;
2611 __le64 pfc_pri3_rx_duration_us;
2612 __le64 pfc_pri3_rx_transitions;
2613 __le64 pfc_pri4_rx_duration_us;
2614 __le64 pfc_pri4_rx_transitions;
2615 __le64 pfc_pri5_rx_duration_us;
2616 __le64 pfc_pri5_rx_transitions;
2617 __le64 pfc_pri6_rx_duration_us;
2618 __le64 pfc_pri6_rx_transitions;
2619 __le64 pfc_pri7_rx_duration_us;
2620 __le64 pfc_pri7_rx_transitions;
2621 };
2622
2623 /* hwrm_port_qstats_ext_input (size:320b/40B) */
2624 struct hwrm_port_qstats_ext_input {
2625 __le16 req_type;
2626 __le16 cmpl_ring;
2627 __le16 seq_id;
2628 __le16 target_id;
2629 __le64 resp_addr;
2630 __le16 port_id;
2631 __le16 tx_stat_size;
2632 __le16 rx_stat_size;
2633 u8 unused_0[2];
2634 __le64 tx_stat_host_addr;
2635 __le64 rx_stat_host_addr;
2636 };
2637
2638 /* hwrm_port_qstats_ext_output (size:128b/16B) */
2639 struct hwrm_port_qstats_ext_output {
2640 __le16 error_code;
2641 __le16 req_type;
2642 __le16 seq_id;
2643 __le16 resp_len;
2644 __le16 tx_stat_size;
2645 __le16 rx_stat_size;
2646 __le16 total_active_cos_queues;
2647 u8 unused_0;
2648 u8 valid;
2649 };
2650
2651 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
2652 struct hwrm_port_lpbk_qstats_input {
2653 __le16 req_type;
2654 __le16 cmpl_ring;
2655 __le16 seq_id;
2656 __le16 target_id;
2657 __le64 resp_addr;
2658 };
2659
2660 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
2661 struct hwrm_port_lpbk_qstats_output {
2662 __le16 error_code;
2663 __le16 req_type;
2664 __le16 seq_id;
2665 __le16 resp_len;
2666 __le64 lpbk_ucast_frames;
2667 __le64 lpbk_mcast_frames;
2668 __le64 lpbk_bcast_frames;
2669 __le64 lpbk_ucast_bytes;
2670 __le64 lpbk_mcast_bytes;
2671 __le64 lpbk_bcast_bytes;
2672 __le64 tx_stat_discard;
2673 __le64 tx_stat_error;
2674 __le64 rx_stat_discard;
2675 __le64 rx_stat_error;
2676 u8 unused_0[7];
2677 u8 valid;
2678 };
2679
2680 /* hwrm_port_clr_stats_input (size:192b/24B) */
2681 struct hwrm_port_clr_stats_input {
2682 __le16 req_type;
2683 __le16 cmpl_ring;
2684 __le16 seq_id;
2685 __le16 target_id;
2686 __le64 resp_addr;
2687 __le16 port_id;
2688 u8 unused_0[6];
2689 };
2690
2691 /* hwrm_port_clr_stats_output (size:128b/16B) */
2692 struct hwrm_port_clr_stats_output {
2693 __le16 error_code;
2694 __le16 req_type;
2695 __le16 seq_id;
2696 __le16 resp_len;
2697 u8 unused_0[7];
2698 u8 valid;
2699 };
2700
2701 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
2702 struct hwrm_port_lpbk_clr_stats_input {
2703 __le16 req_type;
2704 __le16 cmpl_ring;
2705 __le16 seq_id;
2706 __le16 target_id;
2707 __le64 resp_addr;
2708 };
2709
2710 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
2711 struct hwrm_port_lpbk_clr_stats_output {
2712 __le16 error_code;
2713 __le16 req_type;
2714 __le16 seq_id;
2715 __le16 resp_len;
2716 u8 unused_0[7];
2717 u8 valid;
2718 };
2719
2720 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
2721 struct hwrm_port_phy_qcaps_input {
2722 __le16 req_type;
2723 __le16 cmpl_ring;
2724 __le16 seq_id;
2725 __le16 target_id;
2726 __le64 resp_addr;
2727 __le16 port_id;
2728 u8 unused_0[6];
2729 };
2730
2731 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
2732 struct hwrm_port_phy_qcaps_output {
2733 __le16 error_code;
2734 __le16 req_type;
2735 __le16 seq_id;
2736 __le16 resp_len;
2737 u8 flags;
2738 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
2739 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL
2740 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfcUL
2741 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 2
2742 u8 port_cnt;
2743 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
2744 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
2745 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL
2746 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL
2747 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL
2748 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4
2749 __le16 supported_speeds_force_mode;
2750 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
2751 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
2752 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
2753 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
2754 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
2755 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
2756 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
2757 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
2758 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
2759 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
2760 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
2761 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
2762 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
2763 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
2764 __le16 supported_speeds_auto_mode;
2765 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
2766 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
2767 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
2768 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
2769 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
2770 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
2771 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
2772 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
2773 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
2774 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
2775 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
2776 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
2777 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
2778 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
2779 __le16 supported_speeds_eee_mode;
2780 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
2781 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
2782 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
2783 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL
2784 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
2785 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
2786 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
2787 __le32 tx_lpi_timer_low;
2788 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
2789 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
2790 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL
2791 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24
2792 __le32 valid_tx_lpi_timer_high;
2793 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
2794 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
2795 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL
2796 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24
2797 };
2798
2799 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
2800 struct hwrm_port_phy_i2c_read_input {
2801 __le16 req_type;
2802 __le16 cmpl_ring;
2803 __le16 seq_id;
2804 __le16 target_id;
2805 __le64 resp_addr;
2806 __le32 flags;
2807 __le32 enables;
2808 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL
2809 __le16 port_id;
2810 u8 i2c_slave_addr;
2811 u8 unused_0;
2812 __le16 page_number;
2813 __le16 page_offset;
2814 u8 data_length;
2815 u8 unused_1[7];
2816 };
2817
2818 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
2819 struct hwrm_port_phy_i2c_read_output {
2820 __le16 error_code;
2821 __le16 req_type;
2822 __le16 seq_id;
2823 __le16 resp_len;
2824 __le32 data[16];
2825 u8 unused_0[7];
2826 u8 valid;
2827 };
2828
2829 /* hwrm_port_led_cfg_input (size:512b/64B) */
2830 struct hwrm_port_led_cfg_input {
2831 __le16 req_type;
2832 __le16 cmpl_ring;
2833 __le16 seq_id;
2834 __le16 target_id;
2835 __le64 resp_addr;
2836 __le32 enables;
2837 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL
2838 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL
2839 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL
2840 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL
2841 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL
2842 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL
2843 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL
2844 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL
2845 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL
2846 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL
2847 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL
2848 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL
2849 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL
2850 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL
2851 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL
2852 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL
2853 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL
2854 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL
2855 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL
2856 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL
2857 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL
2858 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL
2859 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL
2860 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL
2861 __le16 port_id;
2862 u8 num_leds;
2863 u8 rsvd;
2864 u8 led0_id;
2865 u8 led0_state;
2866 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL
2867 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL
2868 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL
2869 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL
2870 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
2871 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
2872 u8 led0_color;
2873 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL
2874 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL
2875 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL
2876 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
2877 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
2878 u8 unused_0;
2879 __le16 led0_blink_on;
2880 __le16 led0_blink_off;
2881 u8 led0_group_id;
2882 u8 rsvd0;
2883 u8 led1_id;
2884 u8 led1_state;
2885 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL
2886 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL
2887 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL
2888 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL
2889 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
2890 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
2891 u8 led1_color;
2892 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL
2893 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL
2894 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL
2895 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
2896 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
2897 u8 unused_1;
2898 __le16 led1_blink_on;
2899 __le16 led1_blink_off;
2900 u8 led1_group_id;
2901 u8 rsvd1;
2902 u8 led2_id;
2903 u8 led2_state;
2904 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL
2905 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL
2906 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL
2907 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL
2908 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
2909 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
2910 u8 led2_color;
2911 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL
2912 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL
2913 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL
2914 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
2915 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
2916 u8 unused_2;
2917 __le16 led2_blink_on;
2918 __le16 led2_blink_off;
2919 u8 led2_group_id;
2920 u8 rsvd2;
2921 u8 led3_id;
2922 u8 led3_state;
2923 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL
2924 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL
2925 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL
2926 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL
2927 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
2928 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
2929 u8 led3_color;
2930 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL
2931 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL
2932 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL
2933 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
2934 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
2935 u8 unused_3;
2936 __le16 led3_blink_on;
2937 __le16 led3_blink_off;
2938 u8 led3_group_id;
2939 u8 rsvd3;
2940 };
2941
2942 /* hwrm_port_led_cfg_output (size:128b/16B) */
2943 struct hwrm_port_led_cfg_output {
2944 __le16 error_code;
2945 __le16 req_type;
2946 __le16 seq_id;
2947 __le16 resp_len;
2948 u8 unused_0[7];
2949 u8 valid;
2950 };
2951
2952 /* hwrm_port_led_qcfg_input (size:192b/24B) */
2953 struct hwrm_port_led_qcfg_input {
2954 __le16 req_type;
2955 __le16 cmpl_ring;
2956 __le16 seq_id;
2957 __le16 target_id;
2958 __le64 resp_addr;
2959 __le16 port_id;
2960 u8 unused_0[6];
2961 };
2962
2963 /* hwrm_port_led_qcfg_output (size:448b/56B) */
2964 struct hwrm_port_led_qcfg_output {
2965 __le16 error_code;
2966 __le16 req_type;
2967 __le16 seq_id;
2968 __le16 resp_len;
2969 u8 num_leds;
2970 u8 led0_id;
2971 u8 led0_type;
2972 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL
2973 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
2974 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL
2975 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
2976 u8 led0_state;
2977 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL
2978 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL
2979 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL
2980 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL
2981 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
2982 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
2983 u8 led0_color;
2984 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL
2985 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL
2986 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL
2987 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
2988 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
2989 u8 unused_0;
2990 __le16 led0_blink_on;
2991 __le16 led0_blink_off;
2992 u8 led0_group_id;
2993 u8 led1_id;
2994 u8 led1_type;
2995 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL
2996 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
2997 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL
2998 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
2999 u8 led1_state;
3000 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL
3001 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL
3002 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL
3003 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL
3004 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
3005 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
3006 u8 led1_color;
3007 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL
3008 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL
3009 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL
3010 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
3011 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
3012 u8 unused_1;
3013 __le16 led1_blink_on;
3014 __le16 led1_blink_off;
3015 u8 led1_group_id;
3016 u8 led2_id;
3017 u8 led2_type;
3018 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL
3019 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
3020 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL
3021 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
3022 u8 led2_state;
3023 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL
3024 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL
3025 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL
3026 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL
3027 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
3028 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
3029 u8 led2_color;
3030 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL
3031 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL
3032 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL
3033 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
3034 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
3035 u8 unused_2;
3036 __le16 led2_blink_on;
3037 __le16 led2_blink_off;
3038 u8 led2_group_id;
3039 u8 led3_id;
3040 u8 led3_type;
3041 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL
3042 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
3043 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL
3044 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
3045 u8 led3_state;
3046 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL
3047 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL
3048 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL
3049 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL
3050 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
3051 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
3052 u8 led3_color;
3053 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL
3054 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL
3055 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL
3056 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
3057 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
3058 u8 unused_3;
3059 __le16 led3_blink_on;
3060 __le16 led3_blink_off;
3061 u8 led3_group_id;
3062 u8 unused_4[6];
3063 u8 valid;
3064 };
3065
3066 /* hwrm_port_led_qcaps_input (size:192b/24B) */
3067 struct hwrm_port_led_qcaps_input {
3068 __le16 req_type;
3069 __le16 cmpl_ring;
3070 __le16 seq_id;
3071 __le16 target_id;
3072 __le64 resp_addr;
3073 __le16 port_id;
3074 u8 unused_0[6];
3075 };
3076
3077 /* hwrm_port_led_qcaps_output (size:384b/48B) */
3078 struct hwrm_port_led_qcaps_output {
3079 __le16 error_code;
3080 __le16 req_type;
3081 __le16 seq_id;
3082 __le16 resp_len;
3083 u8 num_leds;
3084 u8 unused[3];
3085 u8 led0_id;
3086 u8 led0_type;
3087 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL
3088 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
3089 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL
3090 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
3091 u8 led0_group_id;
3092 u8 unused_0;
3093 __le16 led0_state_caps;
3094 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL
3095 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL
3096 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL
3097 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3098 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3099 __le16 led0_color_caps;
3100 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL
3101 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3102 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3103 u8 led1_id;
3104 u8 led1_type;
3105 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL
3106 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
3107 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL
3108 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
3109 u8 led1_group_id;
3110 u8 unused_1;
3111 __le16 led1_state_caps;
3112 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL
3113 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL
3114 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL
3115 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3116 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3117 __le16 led1_color_caps;
3118 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL
3119 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3120 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3121 u8 led2_id;
3122 u8 led2_type;
3123 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL
3124 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
3125 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL
3126 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
3127 u8 led2_group_id;
3128 u8 unused_2;
3129 __le16 led2_state_caps;
3130 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL
3131 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL
3132 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL
3133 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3134 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3135 __le16 led2_color_caps;
3136 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL
3137 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3138 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3139 u8 led3_id;
3140 u8 led3_type;
3141 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL
3142 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
3143 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL
3144 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
3145 u8 led3_group_id;
3146 u8 unused_3;
3147 __le16 led3_state_caps;
3148 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL
3149 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL
3150 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL
3151 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3152 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3153 __le16 led3_color_caps;
3154 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL
3155 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3156 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3157 u8 unused_4[3];
3158 u8 valid;
3159 };
3160
3161 /* hwrm_queue_qportcfg_input (size:192b/24B) */
3162 struct hwrm_queue_qportcfg_input {
3163 __le16 req_type;
3164 __le16 cmpl_ring;
3165 __le16 seq_id;
3166 __le16 target_id;
3167 __le64 resp_addr;
3168 __le32 flags;
3169 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
3170 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL
3171 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL
3172 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
3173 __le16 port_id;
3174 u8 drv_qmap_cap;
3175 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL
3176 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL
3177 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED
3178 u8 unused_0;
3179 };
3180
3181 /* hwrm_queue_qportcfg_output (size:256b/32B) */
3182 struct hwrm_queue_qportcfg_output {
3183 __le16 error_code;
3184 __le16 req_type;
3185 __le16 seq_id;
3186 __le16 resp_len;
3187 u8 max_configurable_queues;
3188 u8 max_configurable_lossless_queues;
3189 u8 queue_cfg_allowed;
3190 u8 queue_cfg_info;
3191 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
3192 u8 queue_pfcenable_cfg_allowed;
3193 u8 queue_pri2cos_cfg_allowed;
3194 u8 queue_cos2bw_cfg_allowed;
3195 u8 queue_id0;
3196 u8 queue_id0_service_profile;
3197 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL
3198 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL
3199 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3200 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3201 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3202 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL
3203 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
3204 u8 queue_id1;
3205 u8 queue_id1_service_profile;
3206 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL
3207 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL
3208 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3209 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3210 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3211 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL
3212 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
3213 u8 queue_id2;
3214 u8 queue_id2_service_profile;
3215 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL
3216 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL
3217 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3218 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3219 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3220 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL
3221 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
3222 u8 queue_id3;
3223 u8 queue_id3_service_profile;
3224 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL
3225 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL
3226 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3227 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3228 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3229 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL
3230 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
3231 u8 queue_id4;
3232 u8 queue_id4_service_profile;
3233 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL
3234 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL
3235 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3236 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3237 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3238 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL
3239 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
3240 u8 queue_id5;
3241 u8 queue_id5_service_profile;
3242 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL
3243 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL
3244 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3245 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3246 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3247 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL
3248 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
3249 u8 queue_id6;
3250 u8 queue_id6_service_profile;
3251 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL
3252 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL
3253 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3254 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3255 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3256 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL
3257 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
3258 u8 queue_id7;
3259 u8 queue_id7_service_profile;
3260 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL
3261 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL
3262 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3263 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3264 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3265 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL
3266 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
3267 u8 valid;
3268 };
3269
3270 /* hwrm_queue_cfg_input (size:320b/40B) */
3271 struct hwrm_queue_cfg_input {
3272 __le16 req_type;
3273 __le16 cmpl_ring;
3274 __le16 seq_id;
3275 __le16 target_id;
3276 __le64 resp_addr;
3277 __le32 flags;
3278 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
3279 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0
3280 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL
3281 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL
3282 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
3283 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
3284 __le32 enables;
3285 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
3286 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
3287 __le32 queue_id;
3288 __le32 dflt_len;
3289 u8 service_profile;
3290 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL
3291 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
3292 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL
3293 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
3294 u8 unused_0[7];
3295 };
3296
3297 /* hwrm_queue_cfg_output (size:128b/16B) */
3298 struct hwrm_queue_cfg_output {
3299 __le16 error_code;
3300 __le16 req_type;
3301 __le16 seq_id;
3302 __le16 resp_len;
3303 u8 unused_0[7];
3304 u8 valid;
3305 };
3306
3307 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
3308 struct hwrm_queue_pfcenable_qcfg_input {
3309 __le16 req_type;
3310 __le16 cmpl_ring;
3311 __le16 seq_id;
3312 __le16 target_id;
3313 __le64 resp_addr;
3314 __le16 port_id;
3315 u8 unused_0[6];
3316 };
3317
3318 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
3319 struct hwrm_queue_pfcenable_qcfg_output {
3320 __le16 error_code;
3321 __le16 req_type;
3322 __le16 seq_id;
3323 __le16 resp_len;
3324 __le32 flags;
3325 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL
3326 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL
3327 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL
3328 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL
3329 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL
3330 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL
3331 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL
3332 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL
3333 u8 unused_0[3];
3334 u8 valid;
3335 };
3336
3337 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
3338 struct hwrm_queue_pfcenable_cfg_input {
3339 __le16 req_type;
3340 __le16 cmpl_ring;
3341 __le16 seq_id;
3342 __le16 target_id;
3343 __le64 resp_addr;
3344 __le32 flags;
3345 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
3346 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
3347 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
3348 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
3349 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
3350 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
3351 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
3352 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
3353 __le16 port_id;
3354 u8 unused_0[2];
3355 };
3356
3357 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
3358 struct hwrm_queue_pfcenable_cfg_output {
3359 __le16 error_code;
3360 __le16 req_type;
3361 __le16 seq_id;
3362 __le16 resp_len;
3363 u8 unused_0[7];
3364 u8 valid;
3365 };
3366
3367 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
3368 struct hwrm_queue_pri2cos_qcfg_input {
3369 __le16 req_type;
3370 __le16 cmpl_ring;
3371 __le16 seq_id;
3372 __le16 target_id;
3373 __le64 resp_addr;
3374 __le32 flags;
3375 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL
3376 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL
3377 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL
3378 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
3379 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL
3380 u8 port_id;
3381 u8 unused_0[3];
3382 };
3383
3384 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
3385 struct hwrm_queue_pri2cos_qcfg_output {
3386 __le16 error_code;
3387 __le16 req_type;
3388 __le16 seq_id;
3389 __le16 resp_len;
3390 u8 pri0_cos_queue_id;
3391 u8 pri1_cos_queue_id;
3392 u8 pri2_cos_queue_id;
3393 u8 pri3_cos_queue_id;
3394 u8 pri4_cos_queue_id;
3395 u8 pri5_cos_queue_id;
3396 u8 pri6_cos_queue_id;
3397 u8 pri7_cos_queue_id;
3398 u8 queue_cfg_info;
3399 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
3400 u8 unused_0[6];
3401 u8 valid;
3402 };
3403
3404 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
3405 struct hwrm_queue_pri2cos_cfg_input {
3406 __le16 req_type;
3407 __le16 cmpl_ring;
3408 __le16 seq_id;
3409 __le16 target_id;
3410 __le64 resp_addr;
3411 __le32 flags;
3412 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
3413 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0
3414 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL
3415 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL
3416 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
3417 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
3418 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL
3419 __le32 enables;
3420 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL
3421 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL
3422 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL
3423 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL
3424 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL
3425 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL
3426 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL
3427 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL
3428 u8 port_id;
3429 u8 pri0_cos_queue_id;
3430 u8 pri1_cos_queue_id;
3431 u8 pri2_cos_queue_id;
3432 u8 pri3_cos_queue_id;
3433 u8 pri4_cos_queue_id;
3434 u8 pri5_cos_queue_id;
3435 u8 pri6_cos_queue_id;
3436 u8 pri7_cos_queue_id;
3437 u8 unused_0[7];
3438 };
3439
3440 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
3441 struct hwrm_queue_pri2cos_cfg_output {
3442 __le16 error_code;
3443 __le16 req_type;
3444 __le16 seq_id;
3445 __le16 resp_len;
3446 u8 unused_0[7];
3447 u8 valid;
3448 };
3449
3450 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
3451 struct hwrm_queue_cos2bw_qcfg_input {
3452 __le16 req_type;
3453 __le16 cmpl_ring;
3454 __le16 seq_id;
3455 __le16 target_id;
3456 __le64 resp_addr;
3457 __le16 port_id;
3458 u8 unused_0[6];
3459 };
3460
3461 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
3462 struct hwrm_queue_cos2bw_qcfg_output {
3463 __le16 error_code;
3464 __le16 req_type;
3465 __le16 seq_id;
3466 __le16 resp_len;
3467 u8 queue_id0;
3468 u8 unused_0;
3469 __le16 unused_1;
3470 __le32 queue_id0_min_bw;
3471 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3472 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
3473 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
3474 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
3475 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
3476 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
3477 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3478 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
3479 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3480 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3481 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3482 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3483 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3484 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3485 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
3486 __le32 queue_id0_max_bw;
3487 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3488 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
3489 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
3490 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
3491 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
3492 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
3493 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3494 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
3495 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3496 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3497 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3498 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3499 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3500 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3501 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
3502 u8 queue_id0_tsa_assign;
3503 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
3504 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
3505 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3506 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
3507 u8 queue_id0_pri_lvl;
3508 u8 queue_id0_bw_weight;
3509 u8 queue_id1;
3510 __le32 queue_id1_min_bw;
3511 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3512 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
3513 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
3514 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
3515 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
3516 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES
3517 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3518 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
3519 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3520 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3521 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3522 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3523 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3524 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3525 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
3526 __le32 queue_id1_max_bw;
3527 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3528 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
3529 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
3530 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
3531 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
3532 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES
3533 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3534 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
3535 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3536 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3537 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3538 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3539 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3540 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3541 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
3542 u8 queue_id1_tsa_assign;
3543 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
3544 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
3545 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3546 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
3547 u8 queue_id1_pri_lvl;
3548 u8 queue_id1_bw_weight;
3549 u8 queue_id2;
3550 __le32 queue_id2_min_bw;
3551 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3552 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
3553 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
3554 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
3555 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
3556 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES
3557 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3558 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
3559 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3560 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3561 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3562 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3563 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3564 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3565 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
3566 __le32 queue_id2_max_bw;
3567 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3568 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
3569 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
3570 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
3571 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
3572 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES
3573 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
3575 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3576 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3580 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3581 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
3582 u8 queue_id2_tsa_assign;
3583 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
3584 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
3585 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3586 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
3587 u8 queue_id2_pri_lvl;
3588 u8 queue_id2_bw_weight;
3589 u8 queue_id3;
3590 __le32 queue_id3_min_bw;
3591 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3592 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
3593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
3594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
3595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
3596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES
3597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
3599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3605 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
3606 __le32 queue_id3_max_bw;
3607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3608 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
3609 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
3610 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
3611 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
3612 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES
3613 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
3615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3620 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3621 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
3622 u8 queue_id3_tsa_assign;
3623 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
3624 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
3625 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3626 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
3627 u8 queue_id3_pri_lvl;
3628 u8 queue_id3_bw_weight;
3629 u8 queue_id4;
3630 __le32 queue_id4_min_bw;
3631 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3632 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
3633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
3634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
3635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
3636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES
3637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
3639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3645 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
3646 __le32 queue_id4_max_bw;
3647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
3649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
3650 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
3651 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
3652 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES
3653 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
3655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3660 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3661 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
3662 u8 queue_id4_tsa_assign;
3663 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
3664 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
3665 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3666 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
3667 u8 queue_id4_pri_lvl;
3668 u8 queue_id4_bw_weight;
3669 u8 queue_id5;
3670 __le32 queue_id5_min_bw;
3671 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3672 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
3673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
3674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
3675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
3676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES
3677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
3679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3685 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
3686 __le32 queue_id5_max_bw;
3687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3688 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
3689 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
3690 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
3691 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
3692 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES
3693 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
3695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3700 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3701 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
3702 u8 queue_id5_tsa_assign;
3703 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
3704 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
3705 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3706 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
3707 u8 queue_id5_pri_lvl;
3708 u8 queue_id5_bw_weight;
3709 u8 queue_id6;
3710 __le32 queue_id6_min_bw;
3711 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3712 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
3713 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
3714 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
3715 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
3716 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES
3717 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3718 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
3719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3725 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
3726 __le32 queue_id6_max_bw;
3727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3728 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
3729 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
3730 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
3731 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
3732 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES
3733 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3734 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
3735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
3742 u8 queue_id6_tsa_assign;
3743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
3744 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
3745 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3746 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
3747 u8 queue_id6_pri_lvl;
3748 u8 queue_id6_bw_weight;
3749 u8 queue_id7;
3750 __le32 queue_id7_min_bw;
3751 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3752 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
3753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
3754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
3755 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
3756 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES
3757 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
3759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3765 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
3766 __le32 queue_id7_max_bw;
3767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
3769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
3770 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
3771 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
3772 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES
3773 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
3775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
3782 u8 queue_id7_tsa_assign;
3783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
3784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
3785 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3786 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
3787 u8 queue_id7_pri_lvl;
3788 u8 queue_id7_bw_weight;
3789 u8 unused_2[4];
3790 u8 valid;
3791 };
3792
3793 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
3794 struct hwrm_queue_cos2bw_cfg_input {
3795 __le16 req_type;
3796 __le16 cmpl_ring;
3797 __le16 seq_id;
3798 __le16 target_id;
3799 __le64 resp_addr;
3800 __le32 flags;
3801 __le32 enables;
3802 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
3803 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
3804 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
3805 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
3806 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
3807 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
3808 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
3809 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
3810 __le16 port_id;
3811 u8 queue_id0;
3812 u8 unused_0;
3813 __le32 queue_id0_min_bw;
3814 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3815 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
3816 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
3817 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
3818 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
3819 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
3820 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3821 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
3822 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3823 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3824 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3825 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3826 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3827 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3828 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
3829 __le32 queue_id0_max_bw;
3830 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3831 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
3832 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
3833 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
3834 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
3835 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
3836 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3837 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
3838 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3839 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3840 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3841 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3842 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3843 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3844 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
3845 u8 queue_id0_tsa_assign;
3846 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
3847 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
3848 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3849 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
3850 u8 queue_id0_pri_lvl;
3851 u8 queue_id0_bw_weight;
3852 u8 queue_id1;
3853 __le32 queue_id1_min_bw;
3854 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3855 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
3856 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
3857 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
3858 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
3859 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES
3860 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3861 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
3862 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3863 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3864 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3865 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3866 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3867 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3868 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
3869 __le32 queue_id1_max_bw;
3870 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3871 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
3872 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
3873 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
3874 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
3875 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES
3876 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3877 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
3878 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3879 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3880 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3881 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3882 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3883 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3884 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
3885 u8 queue_id1_tsa_assign;
3886 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
3887 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
3888 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3889 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
3890 u8 queue_id1_pri_lvl;
3891 u8 queue_id1_bw_weight;
3892 u8 queue_id2;
3893 __le32 queue_id2_min_bw;
3894 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3895 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
3896 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
3897 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
3898 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
3899 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES
3900 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3901 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
3902 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3903 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3904 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3905 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3906 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3907 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3908 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
3909 __le32 queue_id2_max_bw;
3910 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3911 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
3912 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
3913 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
3914 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
3915 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES
3916 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3917 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
3918 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3919 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3920 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3923 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3924 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
3925 u8 queue_id2_tsa_assign;
3926 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
3927 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
3928 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3929 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
3930 u8 queue_id2_pri_lvl;
3931 u8 queue_id2_bw_weight;
3932 u8 queue_id3;
3933 __le32 queue_id3_min_bw;
3934 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3935 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
3936 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
3937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
3938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
3939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES
3940 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
3942 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3943 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3944 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3945 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3947 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
3949 __le32 queue_id3_max_bw;
3950 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3951 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
3952 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
3953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
3954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
3955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES
3956 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3957 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
3958 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3959 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3960 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3961 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3963 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3964 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
3965 u8 queue_id3_tsa_assign;
3966 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
3967 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
3968 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3969 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
3970 u8 queue_id3_pri_lvl;
3971 u8 queue_id3_bw_weight;
3972 u8 queue_id4;
3973 __le32 queue_id4_min_bw;
3974 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3975 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
3976 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
3977 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
3978 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
3979 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES
3980 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
3982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
3989 __le32 queue_id4_max_bw;
3990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3991 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
3992 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
3993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
3994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
3995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES
3996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3997 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
3998 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3999 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4000 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4003 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4004 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
4005 u8 queue_id4_tsa_assign;
4006 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
4007 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
4008 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
4010 u8 queue_id4_pri_lvl;
4011 u8 queue_id4_bw_weight;
4012 u8 queue_id5;
4013 __le32 queue_id5_min_bw;
4014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
4016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
4017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
4018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
4019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES
4020 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
4022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
4029 __le32 queue_id5_max_bw;
4030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4031 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
4032 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
4033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
4034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
4035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES
4036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4037 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
4038 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4039 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4040 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
4045 u8 queue_id5_tsa_assign;
4046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
4047 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
4048 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4049 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
4050 u8 queue_id5_pri_lvl;
4051 u8 queue_id5_bw_weight;
4052 u8 queue_id6;
4053 __le32 queue_id6_min_bw;
4054 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4055 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
4056 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
4057 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
4058 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
4059 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES
4060 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4061 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
4062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
4069 __le32 queue_id6_max_bw;
4070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4071 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
4072 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
4073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
4074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
4075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES
4076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4077 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
4078 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4079 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4080 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
4085 u8 queue_id6_tsa_assign;
4086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
4087 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
4088 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4089 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
4090 u8 queue_id6_pri_lvl;
4091 u8 queue_id6_bw_weight;
4092 u8 queue_id7;
4093 __le32 queue_id7_min_bw;
4094 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4095 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
4096 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
4097 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
4098 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
4099 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES
4100 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4101 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
4102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
4109 __le32 queue_id7_max_bw;
4110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4111 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
4112 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
4113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
4114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
4115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES
4116 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4117 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
4118 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4119 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4120 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
4125 u8 queue_id7_tsa_assign;
4126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
4127 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
4128 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4129 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
4130 u8 queue_id7_pri_lvl;
4131 u8 queue_id7_bw_weight;
4132 u8 unused_1[5];
4133 };
4134
4135 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
4136 struct hwrm_queue_cos2bw_cfg_output {
4137 __le16 error_code;
4138 __le16 req_type;
4139 __le16 seq_id;
4140 __le16 resp_len;
4141 u8 unused_0[7];
4142 u8 valid;
4143 };
4144
4145 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
4146 struct hwrm_queue_dscp_qcaps_input {
4147 __le16 req_type;
4148 __le16 cmpl_ring;
4149 __le16 seq_id;
4150 __le16 target_id;
4151 __le64 resp_addr;
4152 u8 port_id;
4153 u8 unused_0[7];
4154 };
4155
4156 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
4157 struct hwrm_queue_dscp_qcaps_output {
4158 __le16 error_code;
4159 __le16 req_type;
4160 __le16 seq_id;
4161 __le16 resp_len;
4162 u8 num_dscp_bits;
4163 u8 unused_0;
4164 __le16 max_entries;
4165 u8 unused_1[3];
4166 u8 valid;
4167 };
4168
4169 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
4170 struct hwrm_queue_dscp2pri_qcfg_input {
4171 __le16 req_type;
4172 __le16 cmpl_ring;
4173 __le16 seq_id;
4174 __le16 target_id;
4175 __le64 resp_addr;
4176 __le64 dest_data_addr;
4177 u8 port_id;
4178 u8 unused_0;
4179 __le16 dest_data_buffer_size;
4180 u8 unused_1[4];
4181 };
4182
4183 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
4184 struct hwrm_queue_dscp2pri_qcfg_output {
4185 __le16 error_code;
4186 __le16 req_type;
4187 __le16 seq_id;
4188 __le16 resp_len;
4189 __le16 entry_cnt;
4190 u8 default_pri;
4191 u8 unused_0[4];
4192 u8 valid;
4193 };
4194
4195 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
4196 struct hwrm_queue_dscp2pri_cfg_input {
4197 __le16 req_type;
4198 __le16 cmpl_ring;
4199 __le16 seq_id;
4200 __le16 target_id;
4201 __le64 resp_addr;
4202 __le64 src_data_addr;
4203 __le32 flags;
4204 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL
4205 __le32 enables;
4206 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL
4207 u8 port_id;
4208 u8 default_pri;
4209 __le16 entry_cnt;
4210 u8 unused_0[4];
4211 };
4212
4213 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
4214 struct hwrm_queue_dscp2pri_cfg_output {
4215 __le16 error_code;
4216 __le16 req_type;
4217 __le16 seq_id;
4218 __le16 resp_len;
4219 u8 unused_0[7];
4220 u8 valid;
4221 };
4222
4223 /* hwrm_vnic_alloc_input (size:192b/24B) */
4224 struct hwrm_vnic_alloc_input {
4225 __le16 req_type;
4226 __le16 cmpl_ring;
4227 __le16 seq_id;
4228 __le16 target_id;
4229 __le64 resp_addr;
4230 __le32 flags;
4231 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
4232 u8 unused_0[4];
4233 };
4234
4235 /* hwrm_vnic_alloc_output (size:128b/16B) */
4236 struct hwrm_vnic_alloc_output {
4237 __le16 error_code;
4238 __le16 req_type;
4239 __le16 seq_id;
4240 __le16 resp_len;
4241 __le32 vnic_id;
4242 u8 unused_0[3];
4243 u8 valid;
4244 };
4245
4246 /* hwrm_vnic_free_input (size:192b/24B) */
4247 struct hwrm_vnic_free_input {
4248 __le16 req_type;
4249 __le16 cmpl_ring;
4250 __le16 seq_id;
4251 __le16 target_id;
4252 __le64 resp_addr;
4253 __le32 vnic_id;
4254 u8 unused_0[4];
4255 };
4256
4257 /* hwrm_vnic_free_output (size:128b/16B) */
4258 struct hwrm_vnic_free_output {
4259 __le16 error_code;
4260 __le16 req_type;
4261 __le16 seq_id;
4262 __le16 resp_len;
4263 u8 unused_0[7];
4264 u8 valid;
4265 };
4266
4267 /* hwrm_vnic_cfg_input (size:320b/40B) */
4268 struct hwrm_vnic_cfg_input {
4269 __le16 req_type;
4270 __le16 cmpl_ring;
4271 __le16 seq_id;
4272 __le16 target_id;
4273 __le64 resp_addr;
4274 __le32 flags;
4275 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
4276 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
4277 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
4278 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
4279 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
4280 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL
4281 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL
4282 __le32 enables;
4283 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
4284 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
4285 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
4286 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
4287 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
4288 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL
4289 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL
4290 __le16 vnic_id;
4291 __le16 dflt_ring_grp;
4292 __le16 rss_rule;
4293 __le16 cos_rule;
4294 __le16 lb_rule;
4295 __le16 mru;
4296 __le16 default_rx_ring_id;
4297 __le16 default_cmpl_ring_id;
4298 };
4299
4300 /* hwrm_vnic_cfg_output (size:128b/16B) */
4301 struct hwrm_vnic_cfg_output {
4302 __le16 error_code;
4303 __le16 req_type;
4304 __le16 seq_id;
4305 __le16 resp_len;
4306 u8 unused_0[7];
4307 u8 valid;
4308 };
4309
4310 /* hwrm_vnic_qcaps_input (size:192b/24B) */
4311 struct hwrm_vnic_qcaps_input {
4312 __le16 req_type;
4313 __le16 cmpl_ring;
4314 __le16 seq_id;
4315 __le16 target_id;
4316 __le64 resp_addr;
4317 __le32 enables;
4318 u8 unused_0[4];
4319 };
4320
4321 /* hwrm_vnic_qcaps_output (size:192b/24B) */
4322 struct hwrm_vnic_qcaps_output {
4323 __le16 error_code;
4324 __le16 req_type;
4325 __le16 seq_id;
4326 __le16 resp_len;
4327 __le16 mru;
4328 u8 unused_0[2];
4329 __le32 flags;
4330 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL
4331 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL
4332 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL
4333 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL
4334 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL
4335 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
4336 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
4337 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL
4338 u8 unused_1[7];
4339 u8 valid;
4340 };
4341
4342 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
4343 struct hwrm_vnic_tpa_cfg_input {
4344 __le16 req_type;
4345 __le16 cmpl_ring;
4346 __le16 seq_id;
4347 __le16 target_id;
4348 __le64 resp_addr;
4349 __le32 flags;
4350 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
4351 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
4352 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
4353 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
4354 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
4355 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
4356 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
4357 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
4358 __le32 enables;
4359 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
4360 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
4361 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
4362 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
4363 __le16 vnic_id;
4364 __le16 max_agg_segs;
4365 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL
4366 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL
4367 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL
4368 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL
4369 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
4370 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
4371 __le16 max_aggs;
4372 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL
4373 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL
4374 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL
4375 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL
4376 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL
4377 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
4378 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
4379 u8 unused_0[2];
4380 __le32 max_agg_timer;
4381 __le32 min_agg_len;
4382 };
4383
4384 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
4385 struct hwrm_vnic_tpa_cfg_output {
4386 __le16 error_code;
4387 __le16 req_type;
4388 __le16 seq_id;
4389 __le16 resp_len;
4390 u8 unused_0[7];
4391 u8 valid;
4392 };
4393
4394 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
4395 struct hwrm_vnic_tpa_qcfg_input {
4396 __le16 req_type;
4397 __le16 cmpl_ring;
4398 __le16 seq_id;
4399 __le16 target_id;
4400 __le64 resp_addr;
4401 __le16 vnic_id;
4402 u8 unused_0[6];
4403 };
4404
4405 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
4406 struct hwrm_vnic_tpa_qcfg_output {
4407 __le16 error_code;
4408 __le16 req_type;
4409 __le16 seq_id;
4410 __le16 resp_len;
4411 __le32 flags;
4412 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL
4413 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL
4414 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL
4415 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL
4416 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL
4417 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
4418 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL
4419 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL
4420 __le16 max_agg_segs;
4421 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL
4422 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL
4423 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL
4424 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL
4425 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
4426 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
4427 __le16 max_aggs;
4428 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL
4429 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL
4430 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL
4431 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL
4432 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL
4433 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
4434 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
4435 __le32 max_agg_timer;
4436 __le32 min_agg_len;
4437 u8 unused_0[7];
4438 u8 valid;
4439 };
4440
4441 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
4442 struct hwrm_vnic_rss_cfg_input {
4443 __le16 req_type;
4444 __le16 cmpl_ring;
4445 __le16 seq_id;
4446 __le16 target_id;
4447 __le64 resp_addr;
4448 __le32 hash_type;
4449 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
4450 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
4451 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
4452 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
4453 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
4454 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
4455 __le16 vnic_id;
4456 u8 ring_table_pair_index;
4457 u8 hash_mode_flags;
4458 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL
4459 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
4460 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
4461 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
4462 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
4463 __le64 ring_grp_tbl_addr;
4464 __le64 hash_key_tbl_addr;
4465 __le16 rss_ctx_idx;
4466 u8 unused_1[6];
4467 };
4468
4469 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
4470 struct hwrm_vnic_rss_cfg_output {
4471 __le16 error_code;
4472 __le16 req_type;
4473 __le16 seq_id;
4474 __le16 resp_len;
4475 u8 unused_0[7];
4476 u8 valid;
4477 };
4478
4479 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
4480 struct hwrm_vnic_plcmodes_cfg_input {
4481 __le16 req_type;
4482 __le16 cmpl_ring;
4483 __le16 seq_id;
4484 __le16 target_id;
4485 __le64 resp_addr;
4486 __le32 flags;
4487 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
4488 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
4489 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
4490 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
4491 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
4492 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
4493 __le32 enables;
4494 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
4495 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
4496 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
4497 __le32 vnic_id;
4498 __le16 jumbo_thresh;
4499 __le16 hds_offset;
4500 __le16 hds_threshold;
4501 u8 unused_0[6];
4502 };
4503
4504 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
4505 struct hwrm_vnic_plcmodes_cfg_output {
4506 __le16 error_code;
4507 __le16 req_type;
4508 __le16 seq_id;
4509 __le16 resp_len;
4510 u8 unused_0[7];
4511 u8 valid;
4512 };
4513
4514 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
4515 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
4516 __le16 req_type;
4517 __le16 cmpl_ring;
4518 __le16 seq_id;
4519 __le16 target_id;
4520 __le64 resp_addr;
4521 };
4522
4523 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
4524 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
4525 __le16 error_code;
4526 __le16 req_type;
4527 __le16 seq_id;
4528 __le16 resp_len;
4529 __le16 rss_cos_lb_ctx_id;
4530 u8 unused_0[5];
4531 u8 valid;
4532 };
4533
4534 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
4535 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
4536 __le16 req_type;
4537 __le16 cmpl_ring;
4538 __le16 seq_id;
4539 __le16 target_id;
4540 __le64 resp_addr;
4541 __le16 rss_cos_lb_ctx_id;
4542 u8 unused_0[6];
4543 };
4544
4545 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
4546 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
4547 __le16 error_code;
4548 __le16 req_type;
4549 __le16 seq_id;
4550 __le16 resp_len;
4551 u8 unused_0[7];
4552 u8 valid;
4553 };
4554
4555 /* hwrm_ring_alloc_input (size:704b/88B) */
4556 struct hwrm_ring_alloc_input {
4557 __le16 req_type;
4558 __le16 cmpl_ring;
4559 __le16 seq_id;
4560 __le16 target_id;
4561 __le64 resp_addr;
4562 __le32 enables;
4563 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
4564 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
4565 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
4566 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
4567 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
4568 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
4569 u8 ring_type;
4570 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
4571 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
4572 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
4573 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
4574 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL
4575 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL
4576 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ
4577 u8 unused_0[3];
4578 __le64 page_tbl_addr;
4579 __le32 fbo;
4580 u8 page_size;
4581 u8 page_tbl_depth;
4582 u8 unused_1[2];
4583 __le32 length;
4584 __le16 logical_id;
4585 __le16 cmpl_ring_id;
4586 __le16 queue_id;
4587 __le16 rx_buf_size;
4588 __le16 rx_ring_id;
4589 __le16 nq_ring_id;
4590 __le16 ring_arb_cfg;
4591 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL
4592 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0
4593 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL
4594 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL
4595 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
4596 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL
4597 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4
4598 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
4599 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
4600 __le16 unused_3;
4601 __le32 reserved3;
4602 __le32 stat_ctx_id;
4603 __le32 reserved4;
4604 __le32 max_bw;
4605 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4606 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0
4607 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL
4608 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
4609 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
4610 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
4611 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4612 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
4613 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4614 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4615 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4616 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4617 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4618 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4619 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
4620 u8 int_mode;
4621 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
4622 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL
4623 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL
4624 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
4625 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL
4626 u8 unused_4[3];
4627 __le64 cq_handle;
4628 };
4629
4630 /* hwrm_ring_alloc_output (size:128b/16B) */
4631 struct hwrm_ring_alloc_output {
4632 __le16 error_code;
4633 __le16 req_type;
4634 __le16 seq_id;
4635 __le16 resp_len;
4636 __le16 ring_id;
4637 __le16 logical_ring_id;
4638 u8 unused_0[3];
4639 u8 valid;
4640 };
4641
4642 /* hwrm_ring_free_input (size:192b/24B) */
4643 struct hwrm_ring_free_input {
4644 __le16 req_type;
4645 __le16 cmpl_ring;
4646 __le16 seq_id;
4647 __le16 target_id;
4648 __le64 resp_addr;
4649 u8 ring_type;
4650 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL
4651 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL
4652 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL
4653 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
4654 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL
4655 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL
4656 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ
4657 u8 unused_0;
4658 __le16 ring_id;
4659 u8 unused_1[4];
4660 };
4661
4662 /* hwrm_ring_free_output (size:128b/16B) */
4663 struct hwrm_ring_free_output {
4664 __le16 error_code;
4665 __le16 req_type;
4666 __le16 seq_id;
4667 __le16 resp_len;
4668 u8 unused_0[7];
4669 u8 valid;
4670 };
4671
4672 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
4673 struct hwrm_ring_aggint_qcaps_input {
4674 __le16 req_type;
4675 __le16 cmpl_ring;
4676 __le16 seq_id;
4677 __le16 target_id;
4678 __le64 resp_addr;
4679 };
4680
4681 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
4682 struct hwrm_ring_aggint_qcaps_output {
4683 __le16 error_code;
4684 __le16 req_type;
4685 __le16 seq_id;
4686 __le16 resp_len;
4687 __le32 cmpl_params;
4688 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL
4689 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL
4690 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL
4691 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL
4692 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL
4693 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL
4694 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL
4695 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL
4696 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL
4697 __le32 nq_params;
4698 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL
4699 __le16 num_cmpl_dma_aggr_min;
4700 __le16 num_cmpl_dma_aggr_max;
4701 __le16 num_cmpl_dma_aggr_during_int_min;
4702 __le16 num_cmpl_dma_aggr_during_int_max;
4703 __le16 cmpl_aggr_dma_tmr_min;
4704 __le16 cmpl_aggr_dma_tmr_max;
4705 __le16 cmpl_aggr_dma_tmr_during_int_min;
4706 __le16 cmpl_aggr_dma_tmr_during_int_max;
4707 __le16 int_lat_tmr_min_min;
4708 __le16 int_lat_tmr_min_max;
4709 __le16 int_lat_tmr_max_min;
4710 __le16 int_lat_tmr_max_max;
4711 __le16 num_cmpl_aggr_int_min;
4712 __le16 num_cmpl_aggr_int_max;
4713 __le16 timer_units;
4714 u8 unused_0[1];
4715 u8 valid;
4716 };
4717
4718 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
4719 struct hwrm_ring_cmpl_ring_qaggint_params_input {
4720 __le16 req_type;
4721 __le16 cmpl_ring;
4722 __le16 seq_id;
4723 __le16 target_id;
4724 __le64 resp_addr;
4725 __le16 ring_id;
4726 u8 unused_0[6];
4727 };
4728
4729 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
4730 struct hwrm_ring_cmpl_ring_qaggint_params_output {
4731 __le16 error_code;
4732 __le16 req_type;
4733 __le16 seq_id;
4734 __le16 resp_len;
4735 __le16 flags;
4736 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
4737 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
4738 __le16 num_cmpl_dma_aggr;
4739 __le16 num_cmpl_dma_aggr_during_int;
4740 __le16 cmpl_aggr_dma_tmr;
4741 __le16 cmpl_aggr_dma_tmr_during_int;
4742 __le16 int_lat_tmr_min;
4743 __le16 int_lat_tmr_max;
4744 __le16 num_cmpl_aggr_int;
4745 u8 unused_0[7];
4746 u8 valid;
4747 };
4748
4749 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
4750 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
4751 __le16 req_type;
4752 __le16 cmpl_ring;
4753 __le16 seq_id;
4754 __le16 target_id;
4755 __le64 resp_addr;
4756 __le16 ring_id;
4757 __le16 flags;
4758 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
4759 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
4760 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
4761 __le16 num_cmpl_dma_aggr;
4762 __le16 num_cmpl_dma_aggr_during_int;
4763 __le16 cmpl_aggr_dma_tmr;
4764 __le16 cmpl_aggr_dma_tmr_during_int;
4765 __le16 int_lat_tmr_min;
4766 __le16 int_lat_tmr_max;
4767 __le16 num_cmpl_aggr_int;
4768 __le16 enables;
4769 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL
4770 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL
4771 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL
4772 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL
4773 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL
4774 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL
4775 u8 unused_0[4];
4776 };
4777
4778 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
4779 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
4780 __le16 error_code;
4781 __le16 req_type;
4782 __le16 seq_id;
4783 __le16 resp_len;
4784 u8 unused_0[7];
4785 u8 valid;
4786 };
4787
4788 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
4789 struct hwrm_ring_grp_alloc_input {
4790 __le16 req_type;
4791 __le16 cmpl_ring;
4792 __le16 seq_id;
4793 __le16 target_id;
4794 __le64 resp_addr;
4795 __le16 cr;
4796 __le16 rr;
4797 __le16 ar;
4798 __le16 sc;
4799 };
4800
4801 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
4802 struct hwrm_ring_grp_alloc_output {
4803 __le16 error_code;
4804 __le16 req_type;
4805 __le16 seq_id;
4806 __le16 resp_len;
4807 __le32 ring_group_id;
4808 u8 unused_0[3];
4809 u8 valid;
4810 };
4811
4812 /* hwrm_ring_grp_free_input (size:192b/24B) */
4813 struct hwrm_ring_grp_free_input {
4814 __le16 req_type;
4815 __le16 cmpl_ring;
4816 __le16 seq_id;
4817 __le16 target_id;
4818 __le64 resp_addr;
4819 __le32 ring_group_id;
4820 u8 unused_0[4];
4821 };
4822
4823 /* hwrm_ring_grp_free_output (size:128b/16B) */
4824 struct hwrm_ring_grp_free_output {
4825 __le16 error_code;
4826 __le16 req_type;
4827 __le16 seq_id;
4828 __le16 resp_len;
4829 u8 unused_0[7];
4830 u8 valid;
4831 };
4832
4833 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
4834 struct hwrm_cfa_l2_filter_alloc_input {
4835 __le16 req_type;
4836 __le16 cmpl_ring;
4837 __le16 seq_id;
4838 __le16 target_id;
4839 __le64 resp_addr;
4840 __le32 flags;
4841 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
4842 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
4843 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
4844 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
4845 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
4846 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
4847 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
4848 __le32 enables;
4849 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
4850 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
4851 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
4852 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
4853 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
4854 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
4855 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
4856 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
4857 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
4858 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
4859 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
4860 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
4861 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
4862 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
4863 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
4864 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
4865 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
4866 u8 l2_addr[6];
4867 u8 unused_0[2];
4868 u8 l2_addr_mask[6];
4869 __le16 l2_ovlan;
4870 __le16 l2_ovlan_mask;
4871 __le16 l2_ivlan;
4872 __le16 l2_ivlan_mask;
4873 u8 unused_1[2];
4874 u8 t_l2_addr[6];
4875 u8 unused_2[2];
4876 u8 t_l2_addr_mask[6];
4877 __le16 t_l2_ovlan;
4878 __le16 t_l2_ovlan_mask;
4879 __le16 t_l2_ivlan;
4880 __le16 t_l2_ivlan_mask;
4881 u8 src_type;
4882 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
4883 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL
4884 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL
4885 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL
4886 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL
4887 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL
4888 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL
4889 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL
4890 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
4891 u8 unused_3;
4892 __le32 src_id;
4893 u8 tunnel_type;
4894 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
4895 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
4896 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
4897 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
4898 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
4899 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
4900 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
4901 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
4902 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
4903 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
4904 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
4905 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
4906 u8 unused_4;
4907 __le16 dst_id;
4908 __le16 mirror_vnic_id;
4909 u8 pri_hint;
4910 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
4911 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
4912 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
4913 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL
4914 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL
4915 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
4916 u8 unused_5;
4917 __le32 unused_6;
4918 __le64 l2_filter_id_hint;
4919 };
4920
4921 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
4922 struct hwrm_cfa_l2_filter_alloc_output {
4923 __le16 error_code;
4924 __le16 req_type;
4925 __le16 seq_id;
4926 __le16 resp_len;
4927 __le64 l2_filter_id;
4928 __le32 flow_id;
4929 u8 unused_0[3];
4930 u8 valid;
4931 };
4932
4933 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
4934 struct hwrm_cfa_l2_filter_free_input {
4935 __le16 req_type;
4936 __le16 cmpl_ring;
4937 __le16 seq_id;
4938 __le16 target_id;
4939 __le64 resp_addr;
4940 __le64 l2_filter_id;
4941 };
4942
4943 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
4944 struct hwrm_cfa_l2_filter_free_output {
4945 __le16 error_code;
4946 __le16 req_type;
4947 __le16 seq_id;
4948 __le16 resp_len;
4949 u8 unused_0[7];
4950 u8 valid;
4951 };
4952
4953 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
4954 struct hwrm_cfa_l2_filter_cfg_input {
4955 __le16 req_type;
4956 __le16 cmpl_ring;
4957 __le16 seq_id;
4958 __le16 target_id;
4959 __le64 resp_addr;
4960 __le32 flags;
4961 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
4962 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
4963 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
4964 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
4965 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
4966 __le32 enables;
4967 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
4968 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
4969 __le64 l2_filter_id;
4970 __le32 dst_id;
4971 __le32 new_mirror_vnic_id;
4972 };
4973
4974 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
4975 struct hwrm_cfa_l2_filter_cfg_output {
4976 __le16 error_code;
4977 __le16 req_type;
4978 __le16 seq_id;
4979 __le16 resp_len;
4980 u8 unused_0[7];
4981 u8 valid;
4982 };
4983
4984 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
4985 struct hwrm_cfa_l2_set_rx_mask_input {
4986 __le16 req_type;
4987 __le16 cmpl_ring;
4988 __le16 seq_id;
4989 __le16 target_id;
4990 __le64 resp_addr;
4991 __le32 vnic_id;
4992 __le32 mask;
4993 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
4994 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
4995 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
4996 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
4997 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
4998 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL
4999 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL
5000 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL
5001 __le64 mc_tbl_addr;
5002 __le32 num_mc_entries;
5003 u8 unused_0[4];
5004 __le64 vlan_tag_tbl_addr;
5005 __le32 num_vlan_tags;
5006 u8 unused_1[4];
5007 };
5008
5009 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
5010 struct hwrm_cfa_l2_set_rx_mask_output {
5011 __le16 error_code;
5012 __le16 req_type;
5013 __le16 seq_id;
5014 __le16 resp_len;
5015 u8 unused_0[7];
5016 u8 valid;
5017 };
5018
5019 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
5020 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
5021 u8 code;
5022 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL
5023 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
5024 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
5025 u8 unused_0[7];
5026 };
5027
5028 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
5029 struct hwrm_cfa_tunnel_filter_alloc_input {
5030 __le16 req_type;
5031 __le16 cmpl_ring;
5032 __le16 seq_id;
5033 __le16 target_id;
5034 __le64 resp_addr;
5035 __le32 flags;
5036 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
5037 __le32 enables;
5038 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
5039 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
5040 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
5041 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
5042 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
5043 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
5044 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
5045 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
5046 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
5047 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
5048 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
5049 __le64 l2_filter_id;
5050 u8 l2_addr[6];
5051 __le16 l2_ivlan;
5052 __le32 l3_addr[4];
5053 __le32 t_l3_addr[4];
5054 u8 l3_addr_type;
5055 u8 t_l3_addr_type;
5056 u8 tunnel_type;
5057 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5058 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5059 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5060 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5061 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5062 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5063 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5064 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5065 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5066 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5067 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5068 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5069 u8 tunnel_flags;
5070 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL
5071 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL
5072 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL
5073 __le32 vni;
5074 __le32 dst_vnic_id;
5075 __le32 mirror_vnic_id;
5076 };
5077
5078 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
5079 struct hwrm_cfa_tunnel_filter_alloc_output {
5080 __le16 error_code;
5081 __le16 req_type;
5082 __le16 seq_id;
5083 __le16 resp_len;
5084 __le64 tunnel_filter_id;
5085 __le32 flow_id;
5086 u8 unused_0[3];
5087 u8 valid;
5088 };
5089
5090 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
5091 struct hwrm_cfa_tunnel_filter_free_input {
5092 __le16 req_type;
5093 __le16 cmpl_ring;
5094 __le16 seq_id;
5095 __le16 target_id;
5096 __le64 resp_addr;
5097 __le64 tunnel_filter_id;
5098 };
5099
5100 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
5101 struct hwrm_cfa_tunnel_filter_free_output {
5102 __le16 error_code;
5103 __le16 req_type;
5104 __le16 seq_id;
5105 __le16 resp_len;
5106 u8 unused_0[7];
5107 u8 valid;
5108 };
5109
5110 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
5111 struct hwrm_vxlan_ipv4_hdr {
5112 u8 ver_hlen;
5113 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
5114 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
5115 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL
5116 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
5117 u8 tos;
5118 __be16 ip_id;
5119 __be16 flags_frag_offset;
5120 u8 ttl;
5121 u8 protocol;
5122 __be32 src_ip_addr;
5123 __be32 dest_ip_addr;
5124 };
5125
5126 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
5127 struct hwrm_vxlan_ipv6_hdr {
5128 __be32 ver_tc_flow_label;
5129 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL
5130 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL
5131 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL
5132 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL
5133 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL
5134 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
5135 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
5136 __be16 payload_len;
5137 u8 next_hdr;
5138 u8 ttl;
5139 __be32 src_ip_addr[4];
5140 __be32 dest_ip_addr[4];
5141 };
5142
5143 /* hwrm_cfa_encap_data_vxlan (size:576b/72B) */
5144 struct hwrm_cfa_encap_data_vxlan {
5145 u8 src_mac_addr[6];
5146 __le16 unused_0;
5147 u8 dst_mac_addr[6];
5148 u8 num_vlan_tags;
5149 u8 unused_1;
5150 __be16 ovlan_tpid;
5151 __be16 ovlan_tci;
5152 __be16 ivlan_tpid;
5153 __be16 ivlan_tci;
5154 __le32 l3[10];
5155 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
5156 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
5157 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
5158 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
5159 __be16 src_port;
5160 __be16 dst_port;
5161 __be32 vni;
5162 };
5163
5164 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
5165 struct hwrm_cfa_encap_record_alloc_input {
5166 __le16 req_type;
5167 __le16 cmpl_ring;
5168 __le16 seq_id;
5169 __le16 target_id;
5170 __le64 resp_addr;
5171 __le32 flags;
5172 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
5173 u8 encap_type;
5174 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
5175 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
5176 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
5177 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
5178 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
5179 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
5180 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
5181 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
5182 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE
5183 u8 unused_0[3];
5184 __le32 encap_data[20];
5185 };
5186
5187 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
5188 struct hwrm_cfa_encap_record_alloc_output {
5189 __le16 error_code;
5190 __le16 req_type;
5191 __le16 seq_id;
5192 __le16 resp_len;
5193 __le32 encap_record_id;
5194 u8 unused_0[3];
5195 u8 valid;
5196 };
5197
5198 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
5199 struct hwrm_cfa_encap_record_free_input {
5200 __le16 req_type;
5201 __le16 cmpl_ring;
5202 __le16 seq_id;
5203 __le16 target_id;
5204 __le64 resp_addr;
5205 __le32 encap_record_id;
5206 u8 unused_0[4];
5207 };
5208
5209 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
5210 struct hwrm_cfa_encap_record_free_output {
5211 __le16 error_code;
5212 __le16 req_type;
5213 __le16 seq_id;
5214 __le16 resp_len;
5215 u8 unused_0[7];
5216 u8 valid;
5217 };
5218
5219 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
5220 struct hwrm_cfa_ntuple_filter_alloc_input {
5221 __le16 req_type;
5222 __le16 cmpl_ring;
5223 __le16 seq_id;
5224 __le16 target_id;
5225 __le64 resp_addr;
5226 __le32 flags;
5227 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
5228 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
5229 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL
5230 __le32 enables;
5231 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
5232 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
5233 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
5234 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
5235 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
5236 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
5237 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
5238 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
5239 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
5240 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
5241 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
5242 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
5243 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
5244 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
5245 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
5246 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
5247 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
5248 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
5249 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
5250 __le64 l2_filter_id;
5251 u8 src_macaddr[6];
5252 __be16 ethertype;
5253 u8 ip_addr_type;
5254 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
5255 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
5256 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
5257 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
5258 u8 ip_protocol;
5259 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
5260 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
5261 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
5262 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
5263 __le16 dst_id;
5264 __le16 mirror_vnic_id;
5265 u8 tunnel_type;
5266 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5267 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5268 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5269 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5270 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5271 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5272 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5273 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5274 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5275 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5276 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5277 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5278 u8 pri_hint;
5279 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
5280 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL
5281 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL
5282 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL
5283 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL
5284 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST
5285 __be32 src_ipaddr[4];
5286 __be32 src_ipaddr_mask[4];
5287 __be32 dst_ipaddr[4];
5288 __be32 dst_ipaddr_mask[4];
5289 __be16 src_port;
5290 __be16 src_port_mask;
5291 __be16 dst_port;
5292 __be16 dst_port_mask;
5293 __le64 ntuple_filter_id_hint;
5294 };
5295
5296 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
5297 struct hwrm_cfa_ntuple_filter_alloc_output {
5298 __le16 error_code;
5299 __le16 req_type;
5300 __le16 seq_id;
5301 __le16 resp_len;
5302 __le64 ntuple_filter_id;
5303 __le32 flow_id;
5304 u8 unused_0[3];
5305 u8 valid;
5306 };
5307
5308 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
5309 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
5310 u8 code;
5311 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
5312 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL
5313 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
5314 u8 unused_0[7];
5315 };
5316
5317 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
5318 struct hwrm_cfa_ntuple_filter_free_input {
5319 __le16 req_type;
5320 __le16 cmpl_ring;
5321 __le16 seq_id;
5322 __le16 target_id;
5323 __le64 resp_addr;
5324 __le64 ntuple_filter_id;
5325 };
5326
5327 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
5328 struct hwrm_cfa_ntuple_filter_free_output {
5329 __le16 error_code;
5330 __le16 req_type;
5331 __le16 seq_id;
5332 __le16 resp_len;
5333 u8 unused_0[7];
5334 u8 valid;
5335 };
5336
5337 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
5338 struct hwrm_cfa_ntuple_filter_cfg_input {
5339 __le16 req_type;
5340 __le16 cmpl_ring;
5341 __le16 seq_id;
5342 __le16 target_id;
5343 __le64 resp_addr;
5344 __le32 enables;
5345 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
5346 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
5347 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
5348 u8 unused_0[4];
5349 __le64 ntuple_filter_id;
5350 __le32 new_dst_id;
5351 __le32 new_mirror_vnic_id;
5352 __le16 new_meter_instance_id;
5353 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
5354 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
5355 u8 unused_1[6];
5356 };
5357
5358 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
5359 struct hwrm_cfa_ntuple_filter_cfg_output {
5360 __le16 error_code;
5361 __le16 req_type;
5362 __le16 seq_id;
5363 __le16 resp_len;
5364 u8 unused_0[7];
5365 u8 valid;
5366 };
5367
5368 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
5369 struct hwrm_cfa_decap_filter_alloc_input {
5370 __le16 req_type;
5371 __le16 cmpl_ring;
5372 __le16 seq_id;
5373 __le16 target_id;
5374 __le64 resp_addr;
5375 __le32 flags;
5376 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL
5377 __le32 enables;
5378 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL
5379 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL
5380 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL
5381 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL
5382 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL
5383 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL
5384 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL
5385 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL
5386 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL
5387 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL
5388 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL
5389 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL
5390 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL
5391 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL
5392 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL
5393 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
5394 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
5395 __be32 tunnel_id;
5396 u8 tunnel_type;
5397 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5398 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5399 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5400 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5401 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5402 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5403 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5404 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5405 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5406 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5407 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5408 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5409 u8 unused_0;
5410 __le16 unused_1;
5411 u8 src_macaddr[6];
5412 u8 unused_2[2];
5413 u8 dst_macaddr[6];
5414 __be16 ovlan_vid;
5415 __be16 ivlan_vid;
5416 __be16 t_ovlan_vid;
5417 __be16 t_ivlan_vid;
5418 __be16 ethertype;
5419 u8 ip_addr_type;
5420 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
5421 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
5422 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
5423 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
5424 u8 ip_protocol;
5425 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
5426 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
5427 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
5428 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
5429 __le16 unused_3;
5430 __le32 unused_4;
5431 __be32 src_ipaddr[4];
5432 __be32 dst_ipaddr[4];
5433 __be16 src_port;
5434 __be16 dst_port;
5435 __le16 dst_id;
5436 __le16 l2_ctxt_ref_id;
5437 };
5438
5439 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
5440 struct hwrm_cfa_decap_filter_alloc_output {
5441 __le16 error_code;
5442 __le16 req_type;
5443 __le16 seq_id;
5444 __le16 resp_len;
5445 __le32 decap_filter_id;
5446 u8 unused_0[3];
5447 u8 valid;
5448 };
5449
5450 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
5451 struct hwrm_cfa_decap_filter_free_input {
5452 __le16 req_type;
5453 __le16 cmpl_ring;
5454 __le16 seq_id;
5455 __le16 target_id;
5456 __le64 resp_addr;
5457 __le32 decap_filter_id;
5458 u8 unused_0[4];
5459 };
5460
5461 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
5462 struct hwrm_cfa_decap_filter_free_output {
5463 __le16 error_code;
5464 __le16 req_type;
5465 __le16 seq_id;
5466 __le16 resp_len;
5467 u8 unused_0[7];
5468 u8 valid;
5469 };
5470
5471 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
5472 struct hwrm_cfa_flow_alloc_input {
5473 __le16 req_type;
5474 __le16 cmpl_ring;
5475 __le16 seq_id;
5476 __le16 target_id;
5477 __le64 resp_addr;
5478 __le16 flags;
5479 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
5480 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
5481 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
5482 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
5483 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
5484 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
5485 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
5486 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
5487 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
5488 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
5489 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
5490 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
5491 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
5492 __le16 src_fid;
5493 __le32 tunnel_handle;
5494 __le16 action_flags;
5495 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
5496 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
5497 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
5498 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
5499 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
5500 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
5501 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
5502 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
5503 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
5504 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
5505 __le16 dst_fid;
5506 __be16 l2_rewrite_vlan_tpid;
5507 __be16 l2_rewrite_vlan_tci;
5508 __le16 act_meter_id;
5509 __le16 ref_flow_handle;
5510 __be16 ethertype;
5511 __be16 outer_vlan_tci;
5512 __be16 dmac[3];
5513 __be16 inner_vlan_tci;
5514 __be16 smac[3];
5515 u8 ip_dst_mask_len;
5516 u8 ip_src_mask_len;
5517 __be32 ip_dst[4];
5518 __be32 ip_src[4];
5519 __be16 l4_src_port;
5520 __be16 l4_src_port_mask;
5521 __be16 l4_dst_port;
5522 __be16 l4_dst_port_mask;
5523 __be32 nat_ip_address[4];
5524 __be16 l2_rewrite_dmac[3];
5525 __be16 nat_port;
5526 __be16 l2_rewrite_smac[3];
5527 u8 ip_proto;
5528 u8 unused_0;
5529 };
5530
5531 /* hwrm_cfa_flow_alloc_output (size:128b/16B) */
5532 struct hwrm_cfa_flow_alloc_output {
5533 __le16 error_code;
5534 __le16 req_type;
5535 __le16 seq_id;
5536 __le16 resp_len;
5537 __le16 flow_handle;
5538 u8 unused_0[5];
5539 u8 valid;
5540 };
5541
5542 /* hwrm_cfa_flow_free_input (size:192b/24B) */
5543 struct hwrm_cfa_flow_free_input {
5544 __le16 req_type;
5545 __le16 cmpl_ring;
5546 __le16 seq_id;
5547 __le16 target_id;
5548 __le64 resp_addr;
5549 __le16 flow_handle;
5550 u8 unused_0[6];
5551 };
5552
5553 /* hwrm_cfa_flow_free_output (size:256b/32B) */
5554 struct hwrm_cfa_flow_free_output {
5555 __le16 error_code;
5556 __le16 req_type;
5557 __le16 seq_id;
5558 __le16 resp_len;
5559 __le64 packet;
5560 __le64 byte;
5561 u8 unused_0[7];
5562 u8 valid;
5563 };
5564
5565 /* hwrm_cfa_flow_stats_input (size:320b/40B) */
5566 struct hwrm_cfa_flow_stats_input {
5567 __le16 req_type;
5568 __le16 cmpl_ring;
5569 __le16 seq_id;
5570 __le16 target_id;
5571 __le64 resp_addr;
5572 __le16 num_flows;
5573 __le16 flow_handle_0;
5574 __le16 flow_handle_1;
5575 __le16 flow_handle_2;
5576 __le16 flow_handle_3;
5577 __le16 flow_handle_4;
5578 __le16 flow_handle_5;
5579 __le16 flow_handle_6;
5580 __le16 flow_handle_7;
5581 __le16 flow_handle_8;
5582 __le16 flow_handle_9;
5583 u8 unused_0[2];
5584 };
5585
5586 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
5587 struct hwrm_cfa_flow_stats_output {
5588 __le16 error_code;
5589 __le16 req_type;
5590 __le16 seq_id;
5591 __le16 resp_len;
5592 __le64 packet_0;
5593 __le64 packet_1;
5594 __le64 packet_2;
5595 __le64 packet_3;
5596 __le64 packet_4;
5597 __le64 packet_5;
5598 __le64 packet_6;
5599 __le64 packet_7;
5600 __le64 packet_8;
5601 __le64 packet_9;
5602 __le64 byte_0;
5603 __le64 byte_1;
5604 __le64 byte_2;
5605 __le64 byte_3;
5606 __le64 byte_4;
5607 __le64 byte_5;
5608 __le64 byte_6;
5609 __le64 byte_7;
5610 __le64 byte_8;
5611 __le64 byte_9;
5612 u8 unused_0[7];
5613 u8 valid;
5614 };
5615
5616 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
5617 struct hwrm_cfa_vfr_alloc_input {
5618 __le16 req_type;
5619 __le16 cmpl_ring;
5620 __le16 seq_id;
5621 __le16 target_id;
5622 __le64 resp_addr;
5623 __le16 vf_id;
5624 __le16 reserved;
5625 u8 unused_0[4];
5626 char vfr_name[32];
5627 };
5628
5629 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
5630 struct hwrm_cfa_vfr_alloc_output {
5631 __le16 error_code;
5632 __le16 req_type;
5633 __le16 seq_id;
5634 __le16 resp_len;
5635 __le16 rx_cfa_code;
5636 __le16 tx_cfa_action;
5637 u8 unused_0[3];
5638 u8 valid;
5639 };
5640
5641 /* hwrm_cfa_vfr_free_input (size:384b/48B) */
5642 struct hwrm_cfa_vfr_free_input {
5643 __le16 req_type;
5644 __le16 cmpl_ring;
5645 __le16 seq_id;
5646 __le16 target_id;
5647 __le64 resp_addr;
5648 char vfr_name[32];
5649 };
5650
5651 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
5652 struct hwrm_cfa_vfr_free_output {
5653 __le16 error_code;
5654 __le16 req_type;
5655 __le16 seq_id;
5656 __le16 resp_len;
5657 u8 unused_0[7];
5658 u8 valid;
5659 };
5660
5661 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
5662 struct hwrm_tunnel_dst_port_query_input {
5663 __le16 req_type;
5664 __le16 cmpl_ring;
5665 __le16 seq_id;
5666 __le16 target_id;
5667 __le64 resp_addr;
5668 u8 tunnel_type;
5669 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5670 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5671 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5672 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5673 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1
5674 u8 unused_0[7];
5675 };
5676
5677 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
5678 struct hwrm_tunnel_dst_port_query_output {
5679 __le16 error_code;
5680 __le16 req_type;
5681 __le16 seq_id;
5682 __le16 resp_len;
5683 __le16 tunnel_dst_port_id;
5684 __be16 tunnel_dst_port_val;
5685 u8 unused_0[3];
5686 u8 valid;
5687 };
5688
5689 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
5690 struct hwrm_tunnel_dst_port_alloc_input {
5691 __le16 req_type;
5692 __le16 cmpl_ring;
5693 __le16 seq_id;
5694 __le16 target_id;
5695 __le64 resp_addr;
5696 u8 tunnel_type;
5697 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5698 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5699 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5700 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5701 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1
5702 u8 unused_0;
5703 __be16 tunnel_dst_port_val;
5704 u8 unused_1[4];
5705 };
5706
5707 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
5708 struct hwrm_tunnel_dst_port_alloc_output {
5709 __le16 error_code;
5710 __le16 req_type;
5711 __le16 seq_id;
5712 __le16 resp_len;
5713 __le16 tunnel_dst_port_id;
5714 u8 unused_0[5];
5715 u8 valid;
5716 };
5717
5718 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
5719 struct hwrm_tunnel_dst_port_free_input {
5720 __le16 req_type;
5721 __le16 cmpl_ring;
5722 __le16 seq_id;
5723 __le16 target_id;
5724 __le64 resp_addr;
5725 u8 tunnel_type;
5726 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5727 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5728 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5729 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5730 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1
5731 u8 unused_0;
5732 __le16 tunnel_dst_port_id;
5733 u8 unused_1[4];
5734 };
5735
5736 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
5737 struct hwrm_tunnel_dst_port_free_output {
5738 __le16 error_code;
5739 __le16 req_type;
5740 __le16 seq_id;
5741 __le16 resp_len;
5742 u8 unused_1[7];
5743 u8 valid;
5744 };
5745
5746 /* ctx_hw_stats (size:1280b/160B) */
5747 struct ctx_hw_stats {
5748 __le64 rx_ucast_pkts;
5749 __le64 rx_mcast_pkts;
5750 __le64 rx_bcast_pkts;
5751 __le64 rx_discard_pkts;
5752 __le64 rx_drop_pkts;
5753 __le64 rx_ucast_bytes;
5754 __le64 rx_mcast_bytes;
5755 __le64 rx_bcast_bytes;
5756 __le64 tx_ucast_pkts;
5757 __le64 tx_mcast_pkts;
5758 __le64 tx_bcast_pkts;
5759 __le64 tx_discard_pkts;
5760 __le64 tx_drop_pkts;
5761 __le64 tx_ucast_bytes;
5762 __le64 tx_mcast_bytes;
5763 __le64 tx_bcast_bytes;
5764 __le64 tpa_pkts;
5765 __le64 tpa_bytes;
5766 __le64 tpa_events;
5767 __le64 tpa_aborts;
5768 };
5769
5770 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
5771 struct hwrm_stat_ctx_alloc_input {
5772 __le16 req_type;
5773 __le16 cmpl_ring;
5774 __le16 seq_id;
5775 __le16 target_id;
5776 __le64 resp_addr;
5777 __le64 stats_dma_addr;
5778 __le32 update_period_ms;
5779 u8 stat_ctx_flags;
5780 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL
5781 u8 unused_0[3];
5782 };
5783
5784 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
5785 struct hwrm_stat_ctx_alloc_output {
5786 __le16 error_code;
5787 __le16 req_type;
5788 __le16 seq_id;
5789 __le16 resp_len;
5790 __le32 stat_ctx_id;
5791 u8 unused_0[3];
5792 u8 valid;
5793 };
5794
5795 /* hwrm_stat_ctx_free_input (size:192b/24B) */
5796 struct hwrm_stat_ctx_free_input {
5797 __le16 req_type;
5798 __le16 cmpl_ring;
5799 __le16 seq_id;
5800 __le16 target_id;
5801 __le64 resp_addr;
5802 __le32 stat_ctx_id;
5803 u8 unused_0[4];
5804 };
5805
5806 /* hwrm_stat_ctx_free_output (size:128b/16B) */
5807 struct hwrm_stat_ctx_free_output {
5808 __le16 error_code;
5809 __le16 req_type;
5810 __le16 seq_id;
5811 __le16 resp_len;
5812 __le32 stat_ctx_id;
5813 u8 unused_0[3];
5814 u8 valid;
5815 };
5816
5817 /* hwrm_stat_ctx_query_input (size:192b/24B) */
5818 struct hwrm_stat_ctx_query_input {
5819 __le16 req_type;
5820 __le16 cmpl_ring;
5821 __le16 seq_id;
5822 __le16 target_id;
5823 __le64 resp_addr;
5824 __le32 stat_ctx_id;
5825 u8 unused_0[4];
5826 };
5827
5828 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
5829 struct hwrm_stat_ctx_query_output {
5830 __le16 error_code;
5831 __le16 req_type;
5832 __le16 seq_id;
5833 __le16 resp_len;
5834 __le64 tx_ucast_pkts;
5835 __le64 tx_mcast_pkts;
5836 __le64 tx_bcast_pkts;
5837 __le64 tx_err_pkts;
5838 __le64 tx_drop_pkts;
5839 __le64 tx_ucast_bytes;
5840 __le64 tx_mcast_bytes;
5841 __le64 tx_bcast_bytes;
5842 __le64 rx_ucast_pkts;
5843 __le64 rx_mcast_pkts;
5844 __le64 rx_bcast_pkts;
5845 __le64 rx_err_pkts;
5846 __le64 rx_drop_pkts;
5847 __le64 rx_ucast_bytes;
5848 __le64 rx_mcast_bytes;
5849 __le64 rx_bcast_bytes;
5850 __le64 rx_agg_pkts;
5851 __le64 rx_agg_bytes;
5852 __le64 rx_agg_events;
5853 __le64 rx_agg_aborts;
5854 u8 unused_0[7];
5855 u8 valid;
5856 };
5857
5858 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
5859 struct hwrm_stat_ctx_clr_stats_input {
5860 __le16 req_type;
5861 __le16 cmpl_ring;
5862 __le16 seq_id;
5863 __le16 target_id;
5864 __le64 resp_addr;
5865 __le32 stat_ctx_id;
5866 u8 unused_0[4];
5867 };
5868
5869 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
5870 struct hwrm_stat_ctx_clr_stats_output {
5871 __le16 error_code;
5872 __le16 req_type;
5873 __le16 seq_id;
5874 __le16 resp_len;
5875 u8 unused_0[7];
5876 u8 valid;
5877 };
5878
5879 /* hwrm_pcie_qstats_input (size:256b/32B) */
5880 struct hwrm_pcie_qstats_input {
5881 __le16 req_type;
5882 __le16 cmpl_ring;
5883 __le16 seq_id;
5884 __le16 target_id;
5885 __le64 resp_addr;
5886 __le16 pcie_stat_size;
5887 u8 unused_0[6];
5888 __le64 pcie_stat_host_addr;
5889 };
5890
5891 /* hwrm_pcie_qstats_output (size:128b/16B) */
5892 struct hwrm_pcie_qstats_output {
5893 __le16 error_code;
5894 __le16 req_type;
5895 __le16 seq_id;
5896 __le16 resp_len;
5897 __le16 pcie_stat_size;
5898 u8 unused_0[5];
5899 u8 valid;
5900 };
5901
5902 /* pcie_ctx_hw_stats (size:768b/96B) */
5903 struct pcie_ctx_hw_stats {
5904 __le64 pcie_pl_signal_integrity;
5905 __le64 pcie_dl_signal_integrity;
5906 __le64 pcie_tl_signal_integrity;
5907 __le64 pcie_link_integrity;
5908 __le64 pcie_tx_traffic_rate;
5909 __le64 pcie_rx_traffic_rate;
5910 __le64 pcie_tx_dllp_statistics;
5911 __le64 pcie_rx_dllp_statistics;
5912 __le64 pcie_equalization_time;
5913 __le32 pcie_ltssm_histogram[4];
5914 __le64 pcie_recovery_histogram;
5915 };
5916
5917 /* hwrm_fw_reset_input (size:192b/24B) */
5918 struct hwrm_fw_reset_input {
5919 __le16 req_type;
5920 __le16 cmpl_ring;
5921 __le16 seq_id;
5922 __le16 target_id;
5923 __le64 resp_addr;
5924 u8 embedded_proc_type;
5925 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
5926 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
5927 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
5928 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
5929 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
5930 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
5931 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
5932 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
5933 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
5934 u8 selfrst_status;
5935 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
5936 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
5937 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
5938 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST
5939 u8 host_idx;
5940 u8 unused_0[5];
5941 };
5942
5943 /* hwrm_fw_reset_output (size:128b/16B) */
5944 struct hwrm_fw_reset_output {
5945 __le16 error_code;
5946 __le16 req_type;
5947 __le16 seq_id;
5948 __le16 resp_len;
5949 u8 selfrst_status;
5950 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
5951 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
5952 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
5953 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST
5954 u8 unused_0[6];
5955 u8 valid;
5956 };
5957
5958 /* hwrm_fw_qstatus_input (size:192b/24B) */
5959 struct hwrm_fw_qstatus_input {
5960 __le16 req_type;
5961 __le16 cmpl_ring;
5962 __le16 seq_id;
5963 __le16 target_id;
5964 __le64 resp_addr;
5965 u8 embedded_proc_type;
5966 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
5967 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
5968 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
5969 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
5970 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
5971 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
5972 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
5973 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
5974 u8 unused_0[7];
5975 };
5976
5977 /* hwrm_fw_qstatus_output (size:128b/16B) */
5978 struct hwrm_fw_qstatus_output {
5979 __le16 error_code;
5980 __le16 req_type;
5981 __le16 seq_id;
5982 __le16 resp_len;
5983 u8 selfrst_status;
5984 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
5985 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
5986 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
5987 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST
5988 u8 unused_0[6];
5989 u8 valid;
5990 };
5991
5992 /* hwrm_fw_set_time_input (size:256b/32B) */
5993 struct hwrm_fw_set_time_input {
5994 __le16 req_type;
5995 __le16 cmpl_ring;
5996 __le16 seq_id;
5997 __le16 target_id;
5998 __le64 resp_addr;
5999 __le16 year;
6000 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
6001 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN
6002 u8 month;
6003 u8 day;
6004 u8 hour;
6005 u8 minute;
6006 u8 second;
6007 u8 unused_0;
6008 __le16 millisecond;
6009 __le16 zone;
6010 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL
6011 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL
6012 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN
6013 u8 unused_1[4];
6014 };
6015
6016 /* hwrm_fw_set_time_output (size:128b/16B) */
6017 struct hwrm_fw_set_time_output {
6018 __le16 error_code;
6019 __le16 req_type;
6020 __le16 seq_id;
6021 __le16 resp_len;
6022 u8 unused_0[7];
6023 u8 valid;
6024 };
6025
6026 /* hwrm_struct_hdr (size:128b/16B) */
6027 struct hwrm_struct_hdr {
6028 __le16 struct_id;
6029 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
6030 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
6031 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
6032 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
6033 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
6034 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
6035 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
6036 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
6037 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
6038 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
6039 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2
6040 __le16 len;
6041 u8 version;
6042 u8 count;
6043 __le16 subtype;
6044 __le16 next_offset;
6045 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
6046 u8 unused_0[6];
6047 };
6048
6049 /* hwrm_struct_data_dcbx_app (size:64b/8B) */
6050 struct hwrm_struct_data_dcbx_app {
6051 __be16 protocol_id;
6052 u8 protocol_selector;
6053 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
6054 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
6055 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
6056 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
6057 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
6058 u8 priority;
6059 u8 valid;
6060 u8 unused_0[3];
6061 };
6062
6063 /* hwrm_fw_set_structured_data_input (size:256b/32B) */
6064 struct hwrm_fw_set_structured_data_input {
6065 __le16 req_type;
6066 __le16 cmpl_ring;
6067 __le16 seq_id;
6068 __le16 target_id;
6069 __le64 resp_addr;
6070 __le64 src_data_addr;
6071 __le16 data_len;
6072 u8 hdr_cnt;
6073 u8 unused_0[5];
6074 };
6075
6076 /* hwrm_fw_set_structured_data_output (size:128b/16B) */
6077 struct hwrm_fw_set_structured_data_output {
6078 __le16 error_code;
6079 __le16 req_type;
6080 __le16 seq_id;
6081 __le16 resp_len;
6082 u8 unused_0[7];
6083 u8 valid;
6084 };
6085
6086 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
6087 struct hwrm_fw_set_structured_data_cmd_err {
6088 u8 code;
6089 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
6090 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
6091 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL
6092 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
6093 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
6094 u8 unused_0[7];
6095 };
6096
6097 /* hwrm_fw_get_structured_data_input (size:256b/32B) */
6098 struct hwrm_fw_get_structured_data_input {
6099 __le16 req_type;
6100 __le16 cmpl_ring;
6101 __le16 seq_id;
6102 __le16 target_id;
6103 __le64 resp_addr;
6104 __le64 dest_data_addr;
6105 __le16 data_len;
6106 __le16 structure_id;
6107 __le16 subtype;
6108 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL
6109 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL
6110 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL
6111 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL
6112 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
6113 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL
6114 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL
6115 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL
6116 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL
6117 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL
6118 u8 count;
6119 u8 unused_0;
6120 };
6121
6122 /* hwrm_fw_get_structured_data_output (size:128b/16B) */
6123 struct hwrm_fw_get_structured_data_output {
6124 __le16 error_code;
6125 __le16 req_type;
6126 __le16 seq_id;
6127 __le16 resp_len;
6128 u8 hdr_cnt;
6129 u8 unused_0[6];
6130 u8 valid;
6131 };
6132
6133 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
6134 struct hwrm_fw_get_structured_data_cmd_err {
6135 u8 code;
6136 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
6137 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
6138 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
6139 u8 unused_0[7];
6140 };
6141
6142 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
6143 struct hwrm_exec_fwd_resp_input {
6144 __le16 req_type;
6145 __le16 cmpl_ring;
6146 __le16 seq_id;
6147 __le16 target_id;
6148 __le64 resp_addr;
6149 __le32 encap_request[26];
6150 __le16 encap_resp_target_id;
6151 u8 unused_0[6];
6152 };
6153
6154 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
6155 struct hwrm_exec_fwd_resp_output {
6156 __le16 error_code;
6157 __le16 req_type;
6158 __le16 seq_id;
6159 __le16 resp_len;
6160 u8 unused_0[7];
6161 u8 valid;
6162 };
6163
6164 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
6165 struct hwrm_reject_fwd_resp_input {
6166 __le16 req_type;
6167 __le16 cmpl_ring;
6168 __le16 seq_id;
6169 __le16 target_id;
6170 __le64 resp_addr;
6171 __le32 encap_request[26];
6172 __le16 encap_resp_target_id;
6173 u8 unused_0[6];
6174 };
6175
6176 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
6177 struct hwrm_reject_fwd_resp_output {
6178 __le16 error_code;
6179 __le16 req_type;
6180 __le16 seq_id;
6181 __le16 resp_len;
6182 u8 unused_0[7];
6183 u8 valid;
6184 };
6185
6186 /* hwrm_fwd_resp_input (size:1024b/128B) */
6187 struct hwrm_fwd_resp_input {
6188 __le16 req_type;
6189 __le16 cmpl_ring;
6190 __le16 seq_id;
6191 __le16 target_id;
6192 __le64 resp_addr;
6193 __le16 encap_resp_target_id;
6194 __le16 encap_resp_cmpl_ring;
6195 __le16 encap_resp_len;
6196 u8 unused_0;
6197 u8 unused_1;
6198 __le64 encap_resp_addr;
6199 __le32 encap_resp[24];
6200 };
6201
6202 /* hwrm_fwd_resp_output (size:128b/16B) */
6203 struct hwrm_fwd_resp_output {
6204 __le16 error_code;
6205 __le16 req_type;
6206 __le16 seq_id;
6207 __le16 resp_len;
6208 u8 unused_0[7];
6209 u8 valid;
6210 };
6211
6212 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
6213 struct hwrm_fwd_async_event_cmpl_input {
6214 __le16 req_type;
6215 __le16 cmpl_ring;
6216 __le16 seq_id;
6217 __le16 target_id;
6218 __le64 resp_addr;
6219 __le16 encap_async_event_target_id;
6220 u8 unused_0[6];
6221 __le32 encap_async_event_cmpl[4];
6222 };
6223
6224 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
6225 struct hwrm_fwd_async_event_cmpl_output {
6226 __le16 error_code;
6227 __le16 req_type;
6228 __le16 seq_id;
6229 __le16 resp_len;
6230 u8 unused_0[7];
6231 u8 valid;
6232 };
6233
6234 /* hwrm_temp_monitor_query_input (size:128b/16B) */
6235 struct hwrm_temp_monitor_query_input {
6236 __le16 req_type;
6237 __le16 cmpl_ring;
6238 __le16 seq_id;
6239 __le16 target_id;
6240 __le64 resp_addr;
6241 };
6242
6243 /* hwrm_temp_monitor_query_output (size:128b/16B) */
6244 struct hwrm_temp_monitor_query_output {
6245 __le16 error_code;
6246 __le16 req_type;
6247 __le16 seq_id;
6248 __le16 resp_len;
6249 u8 temp;
6250 u8 unused_0[6];
6251 u8 valid;
6252 };
6253
6254 /* hwrm_wol_filter_alloc_input (size:512b/64B) */
6255 struct hwrm_wol_filter_alloc_input {
6256 __le16 req_type;
6257 __le16 cmpl_ring;
6258 __le16 seq_id;
6259 __le16 target_id;
6260 __le64 resp_addr;
6261 __le32 flags;
6262 __le32 enables;
6263 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL
6264 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL
6265 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL
6266 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL
6267 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL
6268 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL
6269 __le16 port_id;
6270 u8 wol_type;
6271 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
6272 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL
6273 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL
6274 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
6275 u8 unused_0[5];
6276 u8 mac_address[6];
6277 __le16 pattern_offset;
6278 __le16 pattern_buf_size;
6279 __le16 pattern_mask_size;
6280 u8 unused_1[4];
6281 __le64 pattern_buf_addr;
6282 __le64 pattern_mask_addr;
6283 };
6284
6285 /* hwrm_wol_filter_alloc_output (size:128b/16B) */
6286 struct hwrm_wol_filter_alloc_output {
6287 __le16 error_code;
6288 __le16 req_type;
6289 __le16 seq_id;
6290 __le16 resp_len;
6291 u8 wol_filter_id;
6292 u8 unused_0[6];
6293 u8 valid;
6294 };
6295
6296 /* hwrm_wol_filter_free_input (size:256b/32B) */
6297 struct hwrm_wol_filter_free_input {
6298 __le16 req_type;
6299 __le16 cmpl_ring;
6300 __le16 seq_id;
6301 __le16 target_id;
6302 __le64 resp_addr;
6303 __le32 flags;
6304 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL
6305 __le32 enables;
6306 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL
6307 __le16 port_id;
6308 u8 wol_filter_id;
6309 u8 unused_0[5];
6310 };
6311
6312 /* hwrm_wol_filter_free_output (size:128b/16B) */
6313 struct hwrm_wol_filter_free_output {
6314 __le16 error_code;
6315 __le16 req_type;
6316 __le16 seq_id;
6317 __le16 resp_len;
6318 u8 unused_0[7];
6319 u8 valid;
6320 };
6321
6322 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */
6323 struct hwrm_wol_filter_qcfg_input {
6324 __le16 req_type;
6325 __le16 cmpl_ring;
6326 __le16 seq_id;
6327 __le16 target_id;
6328 __le64 resp_addr;
6329 __le16 port_id;
6330 __le16 handle;
6331 u8 unused_0[4];
6332 __le64 pattern_buf_addr;
6333 __le16 pattern_buf_size;
6334 u8 unused_1[6];
6335 __le64 pattern_mask_addr;
6336 __le16 pattern_mask_size;
6337 u8 unused_2[6];
6338 };
6339
6340 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */
6341 struct hwrm_wol_filter_qcfg_output {
6342 __le16 error_code;
6343 __le16 req_type;
6344 __le16 seq_id;
6345 __le16 resp_len;
6346 __le16 next_handle;
6347 u8 wol_filter_id;
6348 u8 wol_type;
6349 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
6350 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL
6351 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL
6352 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
6353 __le32 unused_0;
6354 u8 mac_address[6];
6355 __le16 pattern_offset;
6356 __le16 pattern_size;
6357 __le16 pattern_mask_size;
6358 u8 unused_1[3];
6359 u8 valid;
6360 };
6361
6362 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */
6363 struct hwrm_wol_reason_qcfg_input {
6364 __le16 req_type;
6365 __le16 cmpl_ring;
6366 __le16 seq_id;
6367 __le16 target_id;
6368 __le64 resp_addr;
6369 __le16 port_id;
6370 u8 unused_0[6];
6371 __le64 wol_pkt_buf_addr;
6372 __le16 wol_pkt_buf_size;
6373 u8 unused_1[6];
6374 };
6375
6376 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */
6377 struct hwrm_wol_reason_qcfg_output {
6378 __le16 error_code;
6379 __le16 req_type;
6380 __le16 seq_id;
6381 __le16 resp_len;
6382 u8 wol_filter_id;
6383 u8 wol_reason;
6384 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
6385 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL
6386 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL
6387 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
6388 u8 wol_pkt_len;
6389 u8 unused_0[4];
6390 u8 valid;
6391 };
6392
6393 /* coredump_segment_record (size:128b/16B) */
6394 struct coredump_segment_record {
6395 __le16 component_id;
6396 __le16 segment_id;
6397 __le16 max_instances;
6398 u8 version_hi;
6399 u8 version_low;
6400 u8 seg_flags;
6401 u8 unused_0[7];
6402 };
6403
6404 /* hwrm_dbg_coredump_list_input (size:256b/32B) */
6405 struct hwrm_dbg_coredump_list_input {
6406 __le16 req_type;
6407 __le16 cmpl_ring;
6408 __le16 seq_id;
6409 __le16 target_id;
6410 __le64 resp_addr;
6411 __le64 host_dest_addr;
6412 __le32 host_buf_len;
6413 __le16 seq_no;
6414 u8 unused_0[2];
6415 };
6416
6417 /* hwrm_dbg_coredump_list_output (size:128b/16B) */
6418 struct hwrm_dbg_coredump_list_output {
6419 __le16 error_code;
6420 __le16 req_type;
6421 __le16 seq_id;
6422 __le16 resp_len;
6423 u8 flags;
6424 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL
6425 u8 unused_0;
6426 __le16 total_segments;
6427 __le16 data_len;
6428 u8 unused_1;
6429 u8 valid;
6430 };
6431
6432 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
6433 struct hwrm_dbg_coredump_initiate_input {
6434 __le16 req_type;
6435 __le16 cmpl_ring;
6436 __le16 seq_id;
6437 __le16 target_id;
6438 __le64 resp_addr;
6439 __le16 component_id;
6440 __le16 segment_id;
6441 __le16 instance;
6442 __le16 unused_0;
6443 u8 seg_flags;
6444 u8 unused_1[7];
6445 };
6446
6447 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
6448 struct hwrm_dbg_coredump_initiate_output {
6449 __le16 error_code;
6450 __le16 req_type;
6451 __le16 seq_id;
6452 __le16 resp_len;
6453 u8 unused_0[7];
6454 u8 valid;
6455 };
6456
6457 /* coredump_data_hdr (size:128b/16B) */
6458 struct coredump_data_hdr {
6459 __le32 address;
6460 __le32 flags_length;
6461 __le32 instance;
6462 __le32 next_offset;
6463 };
6464
6465 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
6466 struct hwrm_dbg_coredump_retrieve_input {
6467 __le16 req_type;
6468 __le16 cmpl_ring;
6469 __le16 seq_id;
6470 __le16 target_id;
6471 __le64 resp_addr;
6472 __le64 host_dest_addr;
6473 __le32 host_buf_len;
6474 __le32 unused_0;
6475 __le16 component_id;
6476 __le16 segment_id;
6477 __le16 instance;
6478 __le16 unused_1;
6479 u8 seg_flags;
6480 u8 unused_2;
6481 __le16 unused_3;
6482 __le32 unused_4;
6483 __le32 seq_no;
6484 __le32 unused_5;
6485 };
6486
6487 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
6488 struct hwrm_dbg_coredump_retrieve_output {
6489 __le16 error_code;
6490 __le16 req_type;
6491 __le16 seq_id;
6492 __le16 resp_len;
6493 u8 flags;
6494 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL
6495 u8 unused_0;
6496 __le16 data_len;
6497 u8 unused_1[3];
6498 u8 valid;
6499 };
6500
6501 /* hwrm_nvm_read_input (size:320b/40B) */
6502 struct hwrm_nvm_read_input {
6503 __le16 req_type;
6504 __le16 cmpl_ring;
6505 __le16 seq_id;
6506 __le16 target_id;
6507 __le64 resp_addr;
6508 __le64 host_dest_addr;
6509 __le16 dir_idx;
6510 u8 unused_0[2];
6511 __le32 offset;
6512 __le32 len;
6513 u8 unused_1[4];
6514 };
6515
6516 /* hwrm_nvm_read_output (size:128b/16B) */
6517 struct hwrm_nvm_read_output {
6518 __le16 error_code;
6519 __le16 req_type;
6520 __le16 seq_id;
6521 __le16 resp_len;
6522 u8 unused_0[7];
6523 u8 valid;
6524 };
6525
6526 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
6527 struct hwrm_nvm_get_dir_entries_input {
6528 __le16 req_type;
6529 __le16 cmpl_ring;
6530 __le16 seq_id;
6531 __le16 target_id;
6532 __le64 resp_addr;
6533 __le64 host_dest_addr;
6534 };
6535
6536 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
6537 struct hwrm_nvm_get_dir_entries_output {
6538 __le16 error_code;
6539 __le16 req_type;
6540 __le16 seq_id;
6541 __le16 resp_len;
6542 u8 unused_0[7];
6543 u8 valid;
6544 };
6545
6546 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
6547 struct hwrm_nvm_get_dir_info_input {
6548 __le16 req_type;
6549 __le16 cmpl_ring;
6550 __le16 seq_id;
6551 __le16 target_id;
6552 __le64 resp_addr;
6553 };
6554
6555 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
6556 struct hwrm_nvm_get_dir_info_output {
6557 __le16 error_code;
6558 __le16 req_type;
6559 __le16 seq_id;
6560 __le16 resp_len;
6561 __le32 entries;
6562 __le32 entry_length;
6563 u8 unused_0[7];
6564 u8 valid;
6565 };
6566
6567 /* hwrm_nvm_write_input (size:384b/48B) */
6568 struct hwrm_nvm_write_input {
6569 __le16 req_type;
6570 __le16 cmpl_ring;
6571 __le16 seq_id;
6572 __le16 target_id;
6573 __le64 resp_addr;
6574 __le64 host_src_addr;
6575 __le16 dir_type;
6576 __le16 dir_ordinal;
6577 __le16 dir_ext;
6578 __le16 dir_attr;
6579 __le32 dir_data_length;
6580 __le16 option;
6581 __le16 flags;
6582 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
6583 __le32 dir_item_length;
6584 __le32 unused_0;
6585 };
6586
6587 /* hwrm_nvm_write_output (size:128b/16B) */
6588 struct hwrm_nvm_write_output {
6589 __le16 error_code;
6590 __le16 req_type;
6591 __le16 seq_id;
6592 __le16 resp_len;
6593 __le32 dir_item_length;
6594 __le16 dir_idx;
6595 u8 unused_0;
6596 u8 valid;
6597 };
6598
6599 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
6600 struct hwrm_nvm_write_cmd_err {
6601 u8 code;
6602 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL
6603 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
6604 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
6605 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE
6606 u8 unused_0[7];
6607 };
6608
6609 /* hwrm_nvm_modify_input (size:320b/40B) */
6610 struct hwrm_nvm_modify_input {
6611 __le16 req_type;
6612 __le16 cmpl_ring;
6613 __le16 seq_id;
6614 __le16 target_id;
6615 __le64 resp_addr;
6616 __le64 host_src_addr;
6617 __le16 dir_idx;
6618 u8 unused_0[2];
6619 __le32 offset;
6620 __le32 len;
6621 u8 unused_1[4];
6622 };
6623
6624 /* hwrm_nvm_modify_output (size:128b/16B) */
6625 struct hwrm_nvm_modify_output {
6626 __le16 error_code;
6627 __le16 req_type;
6628 __le16 seq_id;
6629 __le16 resp_len;
6630 u8 unused_0[7];
6631 u8 valid;
6632 };
6633
6634 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
6635 struct hwrm_nvm_find_dir_entry_input {
6636 __le16 req_type;
6637 __le16 cmpl_ring;
6638 __le16 seq_id;
6639 __le16 target_id;
6640 __le64 resp_addr;
6641 __le32 enables;
6642 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
6643 __le16 dir_idx;
6644 __le16 dir_type;
6645 __le16 dir_ordinal;
6646 __le16 dir_ext;
6647 u8 opt_ordinal;
6648 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
6649 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
6650 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL
6651 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL
6652 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL
6653 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
6654 u8 unused_0[3];
6655 };
6656
6657 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
6658 struct hwrm_nvm_find_dir_entry_output {
6659 __le16 error_code;
6660 __le16 req_type;
6661 __le16 seq_id;
6662 __le16 resp_len;
6663 __le32 dir_item_length;
6664 __le32 dir_data_length;
6665 __le32 fw_ver;
6666 __le16 dir_ordinal;
6667 __le16 dir_idx;
6668 u8 unused_0[7];
6669 u8 valid;
6670 };
6671
6672 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
6673 struct hwrm_nvm_erase_dir_entry_input {
6674 __le16 req_type;
6675 __le16 cmpl_ring;
6676 __le16 seq_id;
6677 __le16 target_id;
6678 __le64 resp_addr;
6679 __le16 dir_idx;
6680 u8 unused_0[6];
6681 };
6682
6683 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
6684 struct hwrm_nvm_erase_dir_entry_output {
6685 __le16 error_code;
6686 __le16 req_type;
6687 __le16 seq_id;
6688 __le16 resp_len;
6689 u8 unused_0[7];
6690 u8 valid;
6691 };
6692
6693 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
6694 struct hwrm_nvm_get_dev_info_input {
6695 __le16 req_type;
6696 __le16 cmpl_ring;
6697 __le16 seq_id;
6698 __le16 target_id;
6699 __le64 resp_addr;
6700 };
6701
6702 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
6703 struct hwrm_nvm_get_dev_info_output {
6704 __le16 error_code;
6705 __le16 req_type;
6706 __le16 seq_id;
6707 __le16 resp_len;
6708 __le16 manufacturer_id;
6709 __le16 device_id;
6710 __le32 sector_size;
6711 __le32 nvram_size;
6712 __le32 reserved_size;
6713 __le32 available_size;
6714 u8 unused_0[3];
6715 u8 valid;
6716 };
6717
6718 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
6719 struct hwrm_nvm_mod_dir_entry_input {
6720 __le16 req_type;
6721 __le16 cmpl_ring;
6722 __le16 seq_id;
6723 __le16 target_id;
6724 __le64 resp_addr;
6725 __le32 enables;
6726 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
6727 __le16 dir_idx;
6728 __le16 dir_ordinal;
6729 __le16 dir_ext;
6730 __le16 dir_attr;
6731 __le32 checksum;
6732 };
6733
6734 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
6735 struct hwrm_nvm_mod_dir_entry_output {
6736 __le16 error_code;
6737 __le16 req_type;
6738 __le16 seq_id;
6739 __le16 resp_len;
6740 u8 unused_0[7];
6741 u8 valid;
6742 };
6743
6744 /* hwrm_nvm_verify_update_input (size:192b/24B) */
6745 struct hwrm_nvm_verify_update_input {
6746 __le16 req_type;
6747 __le16 cmpl_ring;
6748 __le16 seq_id;
6749 __le16 target_id;
6750 __le64 resp_addr;
6751 __le16 dir_type;
6752 __le16 dir_ordinal;
6753 __le16 dir_ext;
6754 u8 unused_0[2];
6755 };
6756
6757 /* hwrm_nvm_verify_update_output (size:128b/16B) */
6758 struct hwrm_nvm_verify_update_output {
6759 __le16 error_code;
6760 __le16 req_type;
6761 __le16 seq_id;
6762 __le16 resp_len;
6763 u8 unused_0[7];
6764 u8 valid;
6765 };
6766
6767 /* hwrm_nvm_install_update_input (size:192b/24B) */
6768 struct hwrm_nvm_install_update_input {
6769 __le16 req_type;
6770 __le16 cmpl_ring;
6771 __le16 seq_id;
6772 __le16 target_id;
6773 __le64 resp_addr;
6774 __le32 install_type;
6775 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
6776 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL
6777 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
6778 __le16 flags;
6779 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL
6780 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL
6781 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL
6782 u8 unused_0[2];
6783 };
6784
6785 /* hwrm_nvm_install_update_output (size:192b/24B) */
6786 struct hwrm_nvm_install_update_output {
6787 __le16 error_code;
6788 __le16 req_type;
6789 __le16 seq_id;
6790 __le16 resp_len;
6791 __le64 installed_items;
6792 u8 result;
6793 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
6794 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS
6795 u8 problem_item;
6796 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL
6797 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
6798 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
6799 u8 reset_required;
6800 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL
6801 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL
6802 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
6803 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
6804 u8 unused_0[4];
6805 u8 valid;
6806 };
6807
6808 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
6809 struct hwrm_nvm_install_update_cmd_err {
6810 u8 code;
6811 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL
6812 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
6813 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
6814 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
6815 u8 unused_0[7];
6816 };
6817
6818 /* hwrm_nvm_get_variable_input (size:320b/40B) */
6819 struct hwrm_nvm_get_variable_input {
6820 __le16 req_type;
6821 __le16 cmpl_ring;
6822 __le16 seq_id;
6823 __le16 target_id;
6824 __le64 resp_addr;
6825 __le64 dest_data_addr;
6826 __le16 data_len;
6827 __le16 option_num;
6828 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
6829 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
6830 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
6831 __le16 dimensions;
6832 __le16 index_0;
6833 __le16 index_1;
6834 __le16 index_2;
6835 __le16 index_3;
6836 u8 flags;
6837 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL
6838 u8 unused_0;
6839 };
6840
6841 /* hwrm_nvm_get_variable_output (size:128b/16B) */
6842 struct hwrm_nvm_get_variable_output {
6843 __le16 error_code;
6844 __le16 req_type;
6845 __le16 seq_id;
6846 __le16 resp_len;
6847 __le16 data_len;
6848 __le16 option_num;
6849 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL
6850 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
6851 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
6852 u8 unused_0[3];
6853 u8 valid;
6854 };
6855
6856 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
6857 struct hwrm_nvm_get_variable_cmd_err {
6858 u8 code;
6859 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
6860 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
6861 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
6862 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
6863 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
6864 u8 unused_0[7];
6865 };
6866
6867 /* hwrm_nvm_set_variable_input (size:320b/40B) */
6868 struct hwrm_nvm_set_variable_input {
6869 __le16 req_type;
6870 __le16 cmpl_ring;
6871 __le16 seq_id;
6872 __le16 target_id;
6873 __le64 resp_addr;
6874 __le64 src_data_addr;
6875 __le16 data_len;
6876 __le16 option_num;
6877 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
6878 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
6879 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
6880 __le16 dimensions;
6881 __le16 index_0;
6882 __le16 index_1;
6883 __le16 index_2;
6884 __le16 index_3;
6885 u8 flags;
6886 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL
6887 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL
6888 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1
6889 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1)
6890 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1)
6891 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1)
6892 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1)
6893 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
6894 u8 unused_0;
6895 };
6896
6897 /* hwrm_nvm_set_variable_output (size:128b/16B) */
6898 struct hwrm_nvm_set_variable_output {
6899 __le16 error_code;
6900 __le16 req_type;
6901 __le16 seq_id;
6902 __le16 resp_len;
6903 u8 unused_0[7];
6904 u8 valid;
6905 };
6906
6907 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
6908 struct hwrm_nvm_set_variable_cmd_err {
6909 u8 code;
6910 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
6911 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
6912 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
6913 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
6914 u8 unused_0[7];
6915 };
6916
6917 /* hwrm_selftest_qlist_input (size:128b/16B) */
6918 struct hwrm_selftest_qlist_input {
6919 __le16 req_type;
6920 __le16 cmpl_ring;
6921 __le16 seq_id;
6922 __le16 target_id;
6923 __le64 resp_addr;
6924 };
6925
6926 /* hwrm_selftest_qlist_output (size:2240b/280B) */
6927 struct hwrm_selftest_qlist_output {
6928 __le16 error_code;
6929 __le16 req_type;
6930 __le16 seq_id;
6931 __le16 resp_len;
6932 u8 num_tests;
6933 u8 available_tests;
6934 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL
6935 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL
6936 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL
6937 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL
6938 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL
6939 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL
6940 u8 offline_tests;
6941 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL
6942 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL
6943 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL
6944 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL
6945 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL
6946 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL
6947 u8 unused_0;
6948 __le16 test_timeout;
6949 u8 unused_1[2];
6950 char test0_name[32];
6951 char test1_name[32];
6952 char test2_name[32];
6953 char test3_name[32];
6954 char test4_name[32];
6955 char test5_name[32];
6956 char test6_name[32];
6957 char test7_name[32];
6958 u8 unused_2[7];
6959 u8 valid;
6960 };
6961
6962 /* hwrm_selftest_exec_input (size:192b/24B) */
6963 struct hwrm_selftest_exec_input {
6964 __le16 req_type;
6965 __le16 cmpl_ring;
6966 __le16 seq_id;
6967 __le16 target_id;
6968 __le64 resp_addr;
6969 u8 flags;
6970 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL
6971 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL
6972 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL
6973 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL
6974 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL
6975 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL
6976 u8 unused_0[7];
6977 };
6978
6979 /* hwrm_selftest_exec_output (size:128b/16B) */
6980 struct hwrm_selftest_exec_output {
6981 __le16 error_code;
6982 __le16 req_type;
6983 __le16 seq_id;
6984 __le16 resp_len;
6985 u8 requested_tests;
6986 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL
6987 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL
6988 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL
6989 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL
6990 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL
6991 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL
6992 u8 test_success;
6993 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL
6994 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL
6995 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL
6996 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL
6997 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL
6998 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL
6999 u8 unused_0[5];
7000 u8 valid;
7001 };
7002
7003 /* hwrm_selftest_irq_input (size:128b/16B) */
7004 struct hwrm_selftest_irq_input {
7005 __le16 req_type;
7006 __le16 cmpl_ring;
7007 __le16 seq_id;
7008 __le16 target_id;
7009 __le64 resp_addr;
7010 };
7011
7012 /* hwrm_selftest_irq_output (size:128b/16B) */
7013 struct hwrm_selftest_irq_output {
7014 __le16 error_code;
7015 __le16 req_type;
7016 __le16 seq_id;
7017 __le16 resp_len;
7018 u8 unused_0[7];
7019 u8 valid;
7020 };
7021
7022 #endif /* _BNXT_HSI_H_ */
Linux with added FPC-III support