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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
blobc7667017c1a3f5a8e48b69f8f3e3a8293f01fde7
1 /*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014-2017 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) "bcmgenet: " fmt
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/string.h>
20 #include <linux/if_ether.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm.h>
27 #include <linux/clk.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
33 #include <net/arp.h>
34
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41 #include <linux/in.h>
42 #include <linux/ip.h>
43 #include <linux/ipv6.h>
44 #include <linux/phy.h>
45 #include <linux/platform_data/bcmgenet.h>
46
47 #include <asm/unaligned.h>
48
49 #include "bcmgenet.h"
50
51 /* Maximum number of hardware queues, downsized if needed */
52 #define GENET_MAX_MQ_CNT 4
53
54 /* Default highest priority queue for multi queue support */
55 #define GENET_Q0_PRIORITY 0
56
57 #define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
59 #define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
61
62 #define RX_BUF_LENGTH 2048
63 #define SKB_ALIGNMENT 32
64
65 /* Tx/Rx DMA register offset, skip 256 descriptors */
66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75 /* Forward declarations */
76 static void bcmgenet_set_rx_mode(struct net_device *dev);
77
78 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
79 {
80 /* MIPS chips strapped for BE will automagically configure the
81 * peripheral registers for CPU-native byte order.
82 */
83 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
84 __raw_writel(value, offset);
85 else
86 writel_relaxed(value, offset);
87 }
88
89 static inline u32 bcmgenet_readl(void __iomem *offset)
90 {
91 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
92 return __raw_readl(offset);
93 else
94 return readl_relaxed(offset);
95 }
96
97 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
98 void __iomem *d, u32 value)
99 {
100 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
101 }
102
103 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
104 void __iomem *d)
105 {
106 return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
107 }
108
109 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
110 void __iomem *d,
111 dma_addr_t addr)
112 {
113 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
114
115 /* Register writes to GISB bus can take couple hundred nanoseconds
116 * and are done for each packet, save these expensive writes unless
117 * the platform is explicitly configured for 64-bits/LPAE.
118 */
119 #ifdef CONFIG_PHYS_ADDR_T_64BIT
120 if (priv->hw_params->flags & GENET_HAS_40BITS)
121 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
122 #endif
123 }
124
125 /* Combined address + length/status setter */
126 static inline void dmadesc_set(struct bcmgenet_priv *priv,
127 void __iomem *d, dma_addr_t addr, u32 val)
128 {
129 dmadesc_set_addr(priv, d, addr);
130 dmadesc_set_length_status(priv, d, val);
131 }
132
133 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
134 void __iomem *d)
135 {
136 dma_addr_t addr;
137
138 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
139
140 /* Register writes to GISB bus can take couple hundred nanoseconds
141 * and are done for each packet, save these expensive writes unless
142 * the platform is explicitly configured for 64-bits/LPAE.
143 */
144 #ifdef CONFIG_PHYS_ADDR_T_64BIT
145 if (priv->hw_params->flags & GENET_HAS_40BITS)
146 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
147 #endif
148 return addr;
149 }
150
151 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
152
153 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
154 NETIF_MSG_LINK)
155
156 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
157 {
158 if (GENET_IS_V1(priv))
159 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
160 else
161 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
162 }
163
164 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
165 {
166 if (GENET_IS_V1(priv))
167 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
168 else
169 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
170 }
171
172 /* These macros are defined to deal with register map change
173 * between GENET1.1 and GENET2. Only those currently being used
174 * by driver are defined.
175 */
176 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
177 {
178 if (GENET_IS_V1(priv))
179 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
180 else
181 return bcmgenet_readl(priv->base +
182 priv->hw_params->tbuf_offset + TBUF_CTRL);
183 }
184
185 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
186 {
187 if (GENET_IS_V1(priv))
188 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
189 else
190 bcmgenet_writel(val, priv->base +
191 priv->hw_params->tbuf_offset + TBUF_CTRL);
192 }
193
194 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
195 {
196 if (GENET_IS_V1(priv))
197 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
198 else
199 return bcmgenet_readl(priv->base +
200 priv->hw_params->tbuf_offset + TBUF_BP_MC);
201 }
202
203 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
204 {
205 if (GENET_IS_V1(priv))
206 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
207 else
208 bcmgenet_writel(val, priv->base +
209 priv->hw_params->tbuf_offset + TBUF_BP_MC);
210 }
211
212 /* RX/TX DMA register accessors */
213 enum dma_reg {
214 DMA_RING_CFG = 0,
215 DMA_CTRL,
216 DMA_STATUS,
217 DMA_SCB_BURST_SIZE,
218 DMA_ARB_CTRL,
219 DMA_PRIORITY_0,
220 DMA_PRIORITY_1,
221 DMA_PRIORITY_2,
222 DMA_INDEX2RING_0,
223 DMA_INDEX2RING_1,
224 DMA_INDEX2RING_2,
225 DMA_INDEX2RING_3,
226 DMA_INDEX2RING_4,
227 DMA_INDEX2RING_5,
228 DMA_INDEX2RING_6,
229 DMA_INDEX2RING_7,
230 DMA_RING0_TIMEOUT,
231 DMA_RING1_TIMEOUT,
232 DMA_RING2_TIMEOUT,
233 DMA_RING3_TIMEOUT,
234 DMA_RING4_TIMEOUT,
235 DMA_RING5_TIMEOUT,
236 DMA_RING6_TIMEOUT,
237 DMA_RING7_TIMEOUT,
238 DMA_RING8_TIMEOUT,
239 DMA_RING9_TIMEOUT,
240 DMA_RING10_TIMEOUT,
241 DMA_RING11_TIMEOUT,
242 DMA_RING12_TIMEOUT,
243 DMA_RING13_TIMEOUT,
244 DMA_RING14_TIMEOUT,
245 DMA_RING15_TIMEOUT,
246 DMA_RING16_TIMEOUT,
247 };
248
249 static const u8 bcmgenet_dma_regs_v3plus[] = {
250 [DMA_RING_CFG] = 0x00,
251 [DMA_CTRL] = 0x04,
252 [DMA_STATUS] = 0x08,
253 [DMA_SCB_BURST_SIZE] = 0x0C,
254 [DMA_ARB_CTRL] = 0x2C,
255 [DMA_PRIORITY_0] = 0x30,
256 [DMA_PRIORITY_1] = 0x34,
257 [DMA_PRIORITY_2] = 0x38,
258 [DMA_RING0_TIMEOUT] = 0x2C,
259 [DMA_RING1_TIMEOUT] = 0x30,
260 [DMA_RING2_TIMEOUT] = 0x34,
261 [DMA_RING3_TIMEOUT] = 0x38,
262 [DMA_RING4_TIMEOUT] = 0x3c,
263 [DMA_RING5_TIMEOUT] = 0x40,
264 [DMA_RING6_TIMEOUT] = 0x44,
265 [DMA_RING7_TIMEOUT] = 0x48,
266 [DMA_RING8_TIMEOUT] = 0x4c,
267 [DMA_RING9_TIMEOUT] = 0x50,
268 [DMA_RING10_TIMEOUT] = 0x54,
269 [DMA_RING11_TIMEOUT] = 0x58,
270 [DMA_RING12_TIMEOUT] = 0x5c,
271 [DMA_RING13_TIMEOUT] = 0x60,
272 [DMA_RING14_TIMEOUT] = 0x64,
273 [DMA_RING15_TIMEOUT] = 0x68,
274 [DMA_RING16_TIMEOUT] = 0x6C,
275 [DMA_INDEX2RING_0] = 0x70,
276 [DMA_INDEX2RING_1] = 0x74,
277 [DMA_INDEX2RING_2] = 0x78,
278 [DMA_INDEX2RING_3] = 0x7C,
279 [DMA_INDEX2RING_4] = 0x80,
280 [DMA_INDEX2RING_5] = 0x84,
281 [DMA_INDEX2RING_6] = 0x88,
282 [DMA_INDEX2RING_7] = 0x8C,
283 };
284
285 static const u8 bcmgenet_dma_regs_v2[] = {
286 [DMA_RING_CFG] = 0x00,
287 [DMA_CTRL] = 0x04,
288 [DMA_STATUS] = 0x08,
289 [DMA_SCB_BURST_SIZE] = 0x0C,
290 [DMA_ARB_CTRL] = 0x30,
291 [DMA_PRIORITY_0] = 0x34,
292 [DMA_PRIORITY_1] = 0x38,
293 [DMA_PRIORITY_2] = 0x3C,
294 [DMA_RING0_TIMEOUT] = 0x2C,
295 [DMA_RING1_TIMEOUT] = 0x30,
296 [DMA_RING2_TIMEOUT] = 0x34,
297 [DMA_RING3_TIMEOUT] = 0x38,
298 [DMA_RING4_TIMEOUT] = 0x3c,
299 [DMA_RING5_TIMEOUT] = 0x40,
300 [DMA_RING6_TIMEOUT] = 0x44,
301 [DMA_RING7_TIMEOUT] = 0x48,
302 [DMA_RING8_TIMEOUT] = 0x4c,
303 [DMA_RING9_TIMEOUT] = 0x50,
304 [DMA_RING10_TIMEOUT] = 0x54,
305 [DMA_RING11_TIMEOUT] = 0x58,
306 [DMA_RING12_TIMEOUT] = 0x5c,
307 [DMA_RING13_TIMEOUT] = 0x60,
308 [DMA_RING14_TIMEOUT] = 0x64,
309 [DMA_RING15_TIMEOUT] = 0x68,
310 [DMA_RING16_TIMEOUT] = 0x6C,
311 };
312
313 static const u8 bcmgenet_dma_regs_v1[] = {
314 [DMA_CTRL] = 0x00,
315 [DMA_STATUS] = 0x04,
316 [DMA_SCB_BURST_SIZE] = 0x0C,
317 [DMA_ARB_CTRL] = 0x30,
318 [DMA_PRIORITY_0] = 0x34,
319 [DMA_PRIORITY_1] = 0x38,
320 [DMA_PRIORITY_2] = 0x3C,
321 [DMA_RING0_TIMEOUT] = 0x2C,
322 [DMA_RING1_TIMEOUT] = 0x30,
323 [DMA_RING2_TIMEOUT] = 0x34,
324 [DMA_RING3_TIMEOUT] = 0x38,
325 [DMA_RING4_TIMEOUT] = 0x3c,
326 [DMA_RING5_TIMEOUT] = 0x40,
327 [DMA_RING6_TIMEOUT] = 0x44,
328 [DMA_RING7_TIMEOUT] = 0x48,
329 [DMA_RING8_TIMEOUT] = 0x4c,
330 [DMA_RING9_TIMEOUT] = 0x50,
331 [DMA_RING10_TIMEOUT] = 0x54,
332 [DMA_RING11_TIMEOUT] = 0x58,
333 [DMA_RING12_TIMEOUT] = 0x5c,
334 [DMA_RING13_TIMEOUT] = 0x60,
335 [DMA_RING14_TIMEOUT] = 0x64,
336 [DMA_RING15_TIMEOUT] = 0x68,
337 [DMA_RING16_TIMEOUT] = 0x6C,
338 };
339
340 /* Set at runtime once bcmgenet version is known */
341 static const u8 *bcmgenet_dma_regs;
342
343 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
344 {
345 return netdev_priv(dev_get_drvdata(dev));
346 }
347
348 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
349 enum dma_reg r)
350 {
351 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
352 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
353 }
354
355 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
356 u32 val, enum dma_reg r)
357 {
358 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
359 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
360 }
361
362 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
363 enum dma_reg r)
364 {
365 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
366 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
367 }
368
369 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
370 u32 val, enum dma_reg r)
371 {
372 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
373 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
374 }
375
376 /* RDMA/TDMA ring registers and accessors
377 * we merge the common fields and just prefix with T/D the registers
378 * having different meaning depending on the direction
379 */
380 enum dma_ring_reg {
381 TDMA_READ_PTR = 0,
382 RDMA_WRITE_PTR = TDMA_READ_PTR,
383 TDMA_READ_PTR_HI,
384 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
385 TDMA_CONS_INDEX,
386 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
387 TDMA_PROD_INDEX,
388 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
389 DMA_RING_BUF_SIZE,
390 DMA_START_ADDR,
391 DMA_START_ADDR_HI,
392 DMA_END_ADDR,
393 DMA_END_ADDR_HI,
394 DMA_MBUF_DONE_THRESH,
395 TDMA_FLOW_PERIOD,
396 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
397 TDMA_WRITE_PTR,
398 RDMA_READ_PTR = TDMA_WRITE_PTR,
399 TDMA_WRITE_PTR_HI,
400 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
401 };
402
403 /* GENET v4 supports 40-bits pointer addressing
404 * for obvious reasons the LO and HI word parts
405 * are contiguous, but this offsets the other
406 * registers.
407 */
408 static const u8 genet_dma_ring_regs_v4[] = {
409 [TDMA_READ_PTR] = 0x00,
410 [TDMA_READ_PTR_HI] = 0x04,
411 [TDMA_CONS_INDEX] = 0x08,
412 [TDMA_PROD_INDEX] = 0x0C,
413 [DMA_RING_BUF_SIZE] = 0x10,
414 [DMA_START_ADDR] = 0x14,
415 [DMA_START_ADDR_HI] = 0x18,
416 [DMA_END_ADDR] = 0x1C,
417 [DMA_END_ADDR_HI] = 0x20,
418 [DMA_MBUF_DONE_THRESH] = 0x24,
419 [TDMA_FLOW_PERIOD] = 0x28,
420 [TDMA_WRITE_PTR] = 0x2C,
421 [TDMA_WRITE_PTR_HI] = 0x30,
422 };
423
424 static const u8 genet_dma_ring_regs_v123[] = {
425 [TDMA_READ_PTR] = 0x00,
426 [TDMA_CONS_INDEX] = 0x04,
427 [TDMA_PROD_INDEX] = 0x08,
428 [DMA_RING_BUF_SIZE] = 0x0C,
429 [DMA_START_ADDR] = 0x10,
430 [DMA_END_ADDR] = 0x14,
431 [DMA_MBUF_DONE_THRESH] = 0x18,
432 [TDMA_FLOW_PERIOD] = 0x1C,
433 [TDMA_WRITE_PTR] = 0x20,
434 };
435
436 /* Set at runtime once GENET version is known */
437 static const u8 *genet_dma_ring_regs;
438
439 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
440 unsigned int ring,
441 enum dma_ring_reg r)
442 {
443 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
444 (DMA_RING_SIZE * ring) +
445 genet_dma_ring_regs[r]);
446 }
447
448 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
449 unsigned int ring, u32 val,
450 enum dma_ring_reg r)
451 {
452 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
453 (DMA_RING_SIZE * ring) +
454 genet_dma_ring_regs[r]);
455 }
456
457 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
458 unsigned int ring,
459 enum dma_ring_reg r)
460 {
461 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
462 (DMA_RING_SIZE * ring) +
463 genet_dma_ring_regs[r]);
464 }
465
466 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
467 unsigned int ring, u32 val,
468 enum dma_ring_reg r)
469 {
470 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
471 (DMA_RING_SIZE * ring) +
472 genet_dma_ring_regs[r]);
473 }
474
475 static int bcmgenet_begin(struct net_device *dev)
476 {
477 struct bcmgenet_priv *priv = netdev_priv(dev);
478
479 /* Turn on the clock */
480 return clk_prepare_enable(priv->clk);
481 }
482
483 static void bcmgenet_complete(struct net_device *dev)
484 {
485 struct bcmgenet_priv *priv = netdev_priv(dev);
486
487 /* Turn off the clock */
488 clk_disable_unprepare(priv->clk);
489 }
490
491 static int bcmgenet_get_link_ksettings(struct net_device *dev,
492 struct ethtool_link_ksettings *cmd)
493 {
494 if (!netif_running(dev))
495 return -EINVAL;
496
497 if (!dev->phydev)
498 return -ENODEV;
499
500 phy_ethtool_ksettings_get(dev->phydev, cmd);
501
502 return 0;
503 }
504
505 static int bcmgenet_set_link_ksettings(struct net_device *dev,
506 const struct ethtool_link_ksettings *cmd)
507 {
508 if (!netif_running(dev))
509 return -EINVAL;
510
511 if (!dev->phydev)
512 return -ENODEV;
513
514 return phy_ethtool_ksettings_set(dev->phydev, cmd);
515 }
516
517 static int bcmgenet_set_rx_csum(struct net_device *dev,
518 netdev_features_t wanted)
519 {
520 struct bcmgenet_priv *priv = netdev_priv(dev);
521 u32 rbuf_chk_ctrl;
522 bool rx_csum_en;
523
524 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
525
526 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
527
528 /* enable rx checksumming */
529 if (rx_csum_en)
530 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
531 else
532 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
533 priv->desc_rxchk_en = rx_csum_en;
534
535 /* If UniMAC forwards CRC, we need to skip over it to get
536 * a valid CHK bit to be set in the per-packet status word
537 */
538 if (rx_csum_en && priv->crc_fwd_en)
539 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
540 else
541 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
542
543 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
544
545 return 0;
546 }
547
548 static int bcmgenet_set_tx_csum(struct net_device *dev,
549 netdev_features_t wanted)
550 {
551 struct bcmgenet_priv *priv = netdev_priv(dev);
552 bool desc_64b_en;
553 u32 tbuf_ctrl, rbuf_ctrl;
554
555 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
556 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
557
558 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
559
560 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
561 if (desc_64b_en) {
562 tbuf_ctrl |= RBUF_64B_EN;
563 rbuf_ctrl |= RBUF_64B_EN;
564 } else {
565 tbuf_ctrl &= ~RBUF_64B_EN;
566 rbuf_ctrl &= ~RBUF_64B_EN;
567 }
568 priv->desc_64b_en = desc_64b_en;
569
570 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
571 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
572
573 return 0;
574 }
575
576 static int bcmgenet_set_features(struct net_device *dev,
577 netdev_features_t features)
578 {
579 netdev_features_t changed = features ^ dev->features;
580 netdev_features_t wanted = dev->wanted_features;
581 int ret = 0;
582
583 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
584 ret = bcmgenet_set_tx_csum(dev, wanted);
585 if (changed & (NETIF_F_RXCSUM))
586 ret = bcmgenet_set_rx_csum(dev, wanted);
587
588 return ret;
589 }
590
591 static u32 bcmgenet_get_msglevel(struct net_device *dev)
592 {
593 struct bcmgenet_priv *priv = netdev_priv(dev);
594
595 return priv->msg_enable;
596 }
597
598 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
599 {
600 struct bcmgenet_priv *priv = netdev_priv(dev);
601
602 priv->msg_enable = level;
603 }
604
605 static int bcmgenet_get_coalesce(struct net_device *dev,
606 struct ethtool_coalesce *ec)
607 {
608 struct bcmgenet_priv *priv = netdev_priv(dev);
609 struct bcmgenet_rx_ring *ring;
610 unsigned int i;
611
612 ec->tx_max_coalesced_frames =
613 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
614 DMA_MBUF_DONE_THRESH);
615 ec->rx_max_coalesced_frames =
616 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
617 DMA_MBUF_DONE_THRESH);
618 ec->rx_coalesce_usecs =
619 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
620
621 for (i = 0; i < priv->hw_params->rx_queues; i++) {
622 ring = &priv->rx_rings[i];
623 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
624 }
625 ring = &priv->rx_rings[DESC_INDEX];
626 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
627
628 return 0;
629 }
630
631 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
632 u32 usecs, u32 pkts)
633 {
634 struct bcmgenet_priv *priv = ring->priv;
635 unsigned int i = ring->index;
636 u32 reg;
637
638 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
639
640 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
641 reg &= ~DMA_TIMEOUT_MASK;
642 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
643 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
644 }
645
646 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
647 struct ethtool_coalesce *ec)
648 {
649 struct net_dim_cq_moder moder;
650 u32 usecs, pkts;
651
652 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
653 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
654 usecs = ring->rx_coalesce_usecs;
655 pkts = ring->rx_max_coalesced_frames;
656
657 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
658 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
659 usecs = moder.usec;
660 pkts = moder.pkts;
661 }
662
663 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
664 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
665 }
666
667 static int bcmgenet_set_coalesce(struct net_device *dev,
668 struct ethtool_coalesce *ec)
669 {
670 struct bcmgenet_priv *priv = netdev_priv(dev);
671 unsigned int i;
672
673 /* Base system clock is 125Mhz, DMA timeout is this reference clock
674 * divided by 1024, which yields roughly 8.192us, our maximum value
675 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
676 */
677 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
678 ec->tx_max_coalesced_frames == 0 ||
679 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
680 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
681 return -EINVAL;
682
683 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
684 return -EINVAL;
685
686 /* GENET TDMA hardware does not support a configurable timeout, but will
687 * always generate an interrupt either after MBDONE packets have been
688 * transmitted, or when the ring is empty.
689 */
690 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
691 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low ||
692 ec->use_adaptive_tx_coalesce)
693 return -EOPNOTSUPP;
694
695 /* Program all TX queues with the same values, as there is no
696 * ethtool knob to do coalescing on a per-queue basis
697 */
698 for (i = 0; i < priv->hw_params->tx_queues; i++)
699 bcmgenet_tdma_ring_writel(priv, i,
700 ec->tx_max_coalesced_frames,
701 DMA_MBUF_DONE_THRESH);
702 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
703 ec->tx_max_coalesced_frames,
704 DMA_MBUF_DONE_THRESH);
705
706 for (i = 0; i < priv->hw_params->rx_queues; i++)
707 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
708 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
709
710 return 0;
711 }
712
713 /* standard ethtool support functions. */
714 enum bcmgenet_stat_type {
715 BCMGENET_STAT_NETDEV = -1,
716 BCMGENET_STAT_MIB_RX,
717 BCMGENET_STAT_MIB_TX,
718 BCMGENET_STAT_RUNT,
719 BCMGENET_STAT_MISC,
720 BCMGENET_STAT_SOFT,
721 };
722
723 struct bcmgenet_stats {
724 char stat_string[ETH_GSTRING_LEN];
725 int stat_sizeof;
726 int stat_offset;
727 enum bcmgenet_stat_type type;
728 /* reg offset from UMAC base for misc counters */
729 u16 reg_offset;
730 };
731
732 #define STAT_NETDEV(m) { \
733 .stat_string = __stringify(m), \
734 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
735 .stat_offset = offsetof(struct net_device_stats, m), \
736 .type = BCMGENET_STAT_NETDEV, \
737 }
738
739 #define STAT_GENET_MIB(str, m, _type) { \
740 .stat_string = str, \
741 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
742 .stat_offset = offsetof(struct bcmgenet_priv, m), \
743 .type = _type, \
744 }
745
746 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
747 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
748 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
749 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
750
751 #define STAT_GENET_MISC(str, m, offset) { \
752 .stat_string = str, \
753 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
754 .stat_offset = offsetof(struct bcmgenet_priv, m), \
755 .type = BCMGENET_STAT_MISC, \
756 .reg_offset = offset, \
757 }
758
759 #define STAT_GENET_Q(num) \
760 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
761 tx_rings[num].packets), \
762 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
763 tx_rings[num].bytes), \
764 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
765 rx_rings[num].bytes), \
766 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
767 rx_rings[num].packets), \
768 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
769 rx_rings[num].errors), \
770 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
771 rx_rings[num].dropped)
772
773 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
774 * between the end of TX stats and the beginning of the RX RUNT
775 */
776 #define BCMGENET_STAT_OFFSET 0xc
777
778 /* Hardware counters must be kept in sync because the order/offset
779 * is important here (order in structure declaration = order in hardware)
780 */
781 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
782 /* general stats */
783 STAT_NETDEV(rx_packets),
784 STAT_NETDEV(tx_packets),
785 STAT_NETDEV(rx_bytes),
786 STAT_NETDEV(tx_bytes),
787 STAT_NETDEV(rx_errors),
788 STAT_NETDEV(tx_errors),
789 STAT_NETDEV(rx_dropped),
790 STAT_NETDEV(tx_dropped),
791 STAT_NETDEV(multicast),
792 /* UniMAC RSV counters */
793 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
794 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
795 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
796 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
797 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
798 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
799 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
800 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
801 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
802 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
803 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
804 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
805 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
806 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
807 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
808 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
809 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
810 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
811 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
812 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
813 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
814 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
815 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
816 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
817 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
818 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
819 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
820 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
821 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
822 /* UniMAC TSV counters */
823 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
824 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
825 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
826 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
827 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
828 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
829 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
830 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
831 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
832 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
833 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
834 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
835 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
836 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
837 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
838 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
839 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
840 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
841 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
842 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
843 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
844 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
845 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
846 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
847 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
848 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
849 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
850 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
851 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
852 /* UniMAC RUNT counters */
853 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
854 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
855 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
856 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
857 /* Misc UniMAC counters */
858 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
859 UMAC_RBUF_OVFL_CNT_V1),
860 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
861 UMAC_RBUF_ERR_CNT_V1),
862 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
863 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
864 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
865 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
866 /* Per TX queues */
867 STAT_GENET_Q(0),
868 STAT_GENET_Q(1),
869 STAT_GENET_Q(2),
870 STAT_GENET_Q(3),
871 STAT_GENET_Q(16),
872 };
873
874 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
875
876 static void bcmgenet_get_drvinfo(struct net_device *dev,
877 struct ethtool_drvinfo *info)
878 {
879 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
880 strlcpy(info->version, "v2.0", sizeof(info->version));
881 }
882
883 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
884 {
885 switch (string_set) {
886 case ETH_SS_STATS:
887 return BCMGENET_STATS_LEN;
888 default:
889 return -EOPNOTSUPP;
890 }
891 }
892
893 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
894 u8 *data)
895 {
896 int i;
897
898 switch (stringset) {
899 case ETH_SS_STATS:
900 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
901 memcpy(data + i * ETH_GSTRING_LEN,
902 bcmgenet_gstrings_stats[i].stat_string,
903 ETH_GSTRING_LEN);
904 }
905 break;
906 }
907 }
908
909 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
910 {
911 u16 new_offset;
912 u32 val;
913
914 switch (offset) {
915 case UMAC_RBUF_OVFL_CNT_V1:
916 if (GENET_IS_V2(priv))
917 new_offset = RBUF_OVFL_CNT_V2;
918 else
919 new_offset = RBUF_OVFL_CNT_V3PLUS;
920
921 val = bcmgenet_rbuf_readl(priv, new_offset);
922 /* clear if overflowed */
923 if (val == ~0)
924 bcmgenet_rbuf_writel(priv, 0, new_offset);
925 break;
926 case UMAC_RBUF_ERR_CNT_V1:
927 if (GENET_IS_V2(priv))
928 new_offset = RBUF_ERR_CNT_V2;
929 else
930 new_offset = RBUF_ERR_CNT_V3PLUS;
931
932 val = bcmgenet_rbuf_readl(priv, new_offset);
933 /* clear if overflowed */
934 if (val == ~0)
935 bcmgenet_rbuf_writel(priv, 0, new_offset);
936 break;
937 default:
938 val = bcmgenet_umac_readl(priv, offset);
939 /* clear if overflowed */
940 if (val == ~0)
941 bcmgenet_umac_writel(priv, 0, offset);
942 break;
943 }
944
945 return val;
946 }
947
948 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
949 {
950 int i, j = 0;
951
952 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
953 const struct bcmgenet_stats *s;
954 u8 offset = 0;
955 u32 val = 0;
956 char *p;
957
958 s = &bcmgenet_gstrings_stats[i];
959 switch (s->type) {
960 case BCMGENET_STAT_NETDEV:
961 case BCMGENET_STAT_SOFT:
962 continue;
963 case BCMGENET_STAT_RUNT:
964 offset += BCMGENET_STAT_OFFSET;
965 /* fall through */
966 case BCMGENET_STAT_MIB_TX:
967 offset += BCMGENET_STAT_OFFSET;
968 /* fall through */
969 case BCMGENET_STAT_MIB_RX:
970 val = bcmgenet_umac_readl(priv,
971 UMAC_MIB_START + j + offset);
972 offset = 0; /* Reset Offset */
973 break;
974 case BCMGENET_STAT_MISC:
975 if (GENET_IS_V1(priv)) {
976 val = bcmgenet_umac_readl(priv, s->reg_offset);
977 /* clear if overflowed */
978 if (val == ~0)
979 bcmgenet_umac_writel(priv, 0,
980 s->reg_offset);
981 } else {
982 val = bcmgenet_update_stat_misc(priv,
983 s->reg_offset);
984 }
985 break;
986 }
987
988 j += s->stat_sizeof;
989 p = (char *)priv + s->stat_offset;
990 *(u32 *)p = val;
991 }
992 }
993
994 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
995 struct ethtool_stats *stats,
996 u64 *data)
997 {
998 struct bcmgenet_priv *priv = netdev_priv(dev);
999 int i;
1000
1001 if (netif_running(dev))
1002 bcmgenet_update_mib_counters(priv);
1003
1004 dev->netdev_ops->ndo_get_stats(dev);
1005
1006 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1007 const struct bcmgenet_stats *s;
1008 char *p;
1009
1010 s = &bcmgenet_gstrings_stats[i];
1011 if (s->type == BCMGENET_STAT_NETDEV)
1012 p = (char *)&dev->stats;
1013 else
1014 p = (char *)priv;
1015 p += s->stat_offset;
1016 if (sizeof(unsigned long) != sizeof(u32) &&
1017 s->stat_sizeof == sizeof(unsigned long))
1018 data[i] = *(unsigned long *)p;
1019 else
1020 data[i] = *(u32 *)p;
1021 }
1022 }
1023
1024 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1025 {
1026 struct bcmgenet_priv *priv = netdev_priv(dev);
1027 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1028 u32 reg;
1029
1030 if (enable && !priv->clk_eee_enabled) {
1031 clk_prepare_enable(priv->clk_eee);
1032 priv->clk_eee_enabled = true;
1033 }
1034
1035 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1036 if (enable)
1037 reg |= EEE_EN;
1038 else
1039 reg &= ~EEE_EN;
1040 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1041
1042 /* Enable EEE and switch to a 27Mhz clock automatically */
1043 reg = bcmgenet_readl(priv->base + off);
1044 if (enable)
1045 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1046 else
1047 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1048 bcmgenet_writel(reg, priv->base + off);
1049
1050 /* Do the same for thing for RBUF */
1051 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1052 if (enable)
1053 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1054 else
1055 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1056 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1057
1058 if (!enable && priv->clk_eee_enabled) {
1059 clk_disable_unprepare(priv->clk_eee);
1060 priv->clk_eee_enabled = false;
1061 }
1062
1063 priv->eee.eee_enabled = enable;
1064 priv->eee.eee_active = enable;
1065 }
1066
1067 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1068 {
1069 struct bcmgenet_priv *priv = netdev_priv(dev);
1070 struct ethtool_eee *p = &priv->eee;
1071
1072 if (GENET_IS_V1(priv))
1073 return -EOPNOTSUPP;
1074
1075 if (!dev->phydev)
1076 return -ENODEV;
1077
1078 e->eee_enabled = p->eee_enabled;
1079 e->eee_active = p->eee_active;
1080 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1081
1082 return phy_ethtool_get_eee(dev->phydev, e);
1083 }
1084
1085 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1086 {
1087 struct bcmgenet_priv *priv = netdev_priv(dev);
1088 struct ethtool_eee *p = &priv->eee;
1089 int ret = 0;
1090
1091 if (GENET_IS_V1(priv))
1092 return -EOPNOTSUPP;
1093
1094 if (!dev->phydev)
1095 return -ENODEV;
1096
1097 p->eee_enabled = e->eee_enabled;
1098
1099 if (!p->eee_enabled) {
1100 bcmgenet_eee_enable_set(dev, false);
1101 } else {
1102 ret = phy_init_eee(dev->phydev, 0);
1103 if (ret) {
1104 netif_err(priv, hw, dev, "EEE initialization failed\n");
1105 return ret;
1106 }
1107
1108 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1109 bcmgenet_eee_enable_set(dev, true);
1110 }
1111
1112 return phy_ethtool_set_eee(dev->phydev, e);
1113 }
1114
1115 /* standard ethtool support functions. */
1116 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1117 .begin = bcmgenet_begin,
1118 .complete = bcmgenet_complete,
1119 .get_strings = bcmgenet_get_strings,
1120 .get_sset_count = bcmgenet_get_sset_count,
1121 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1122 .get_drvinfo = bcmgenet_get_drvinfo,
1123 .get_link = ethtool_op_get_link,
1124 .get_msglevel = bcmgenet_get_msglevel,
1125 .set_msglevel = bcmgenet_set_msglevel,
1126 .get_wol = bcmgenet_get_wol,
1127 .set_wol = bcmgenet_set_wol,
1128 .get_eee = bcmgenet_get_eee,
1129 .set_eee = bcmgenet_set_eee,
1130 .nway_reset = phy_ethtool_nway_reset,
1131 .get_coalesce = bcmgenet_get_coalesce,
1132 .set_coalesce = bcmgenet_set_coalesce,
1133 .get_link_ksettings = bcmgenet_get_link_ksettings,
1134 .set_link_ksettings = bcmgenet_set_link_ksettings,
1135 };
1136
1137 /* Power down the unimac, based on mode. */
1138 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1139 enum bcmgenet_power_mode mode)
1140 {
1141 int ret = 0;
1142 u32 reg;
1143
1144 switch (mode) {
1145 case GENET_POWER_CABLE_SENSE:
1146 phy_detach(priv->dev->phydev);
1147 break;
1148
1149 case GENET_POWER_WOL_MAGIC:
1150 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1151 break;
1152
1153 case GENET_POWER_PASSIVE:
1154 /* Power down LED */
1155 if (priv->hw_params->flags & GENET_HAS_EXT) {
1156 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1157 if (GENET_IS_V5(priv))
1158 reg |= EXT_PWR_DOWN_PHY_EN |
1159 EXT_PWR_DOWN_PHY_RD |
1160 EXT_PWR_DOWN_PHY_SD |
1161 EXT_PWR_DOWN_PHY_RX |
1162 EXT_PWR_DOWN_PHY_TX |
1163 EXT_IDDQ_GLBL_PWR;
1164 else
1165 reg |= EXT_PWR_DOWN_PHY;
1166
1167 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1168 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1169
1170 bcmgenet_phy_power_set(priv->dev, false);
1171 }
1172 break;
1173 default:
1174 break;
1175 }
1176
1177 return ret;
1178 }
1179
1180 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1181 enum bcmgenet_power_mode mode)
1182 {
1183 u32 reg;
1184
1185 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1186 return;
1187
1188 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1189
1190 switch (mode) {
1191 case GENET_POWER_PASSIVE:
1192 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1193 if (GENET_IS_V5(priv)) {
1194 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1195 EXT_PWR_DOWN_PHY_RD |
1196 EXT_PWR_DOWN_PHY_SD |
1197 EXT_PWR_DOWN_PHY_RX |
1198 EXT_PWR_DOWN_PHY_TX |
1199 EXT_IDDQ_GLBL_PWR);
1200 reg |= EXT_PHY_RESET;
1201 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1202 mdelay(1);
1203
1204 reg &= ~EXT_PHY_RESET;
1205 } else {
1206 reg &= ~EXT_PWR_DOWN_PHY;
1207 reg |= EXT_PWR_DN_EN_LD;
1208 }
1209 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1210 bcmgenet_phy_power_set(priv->dev, true);
1211 break;
1212
1213 case GENET_POWER_CABLE_SENSE:
1214 /* enable APD */
1215 if (!GENET_IS_V5(priv)) {
1216 reg |= EXT_PWR_DN_EN_LD;
1217 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1218 }
1219 break;
1220 case GENET_POWER_WOL_MAGIC:
1221 bcmgenet_wol_power_up_cfg(priv, mode);
1222 return;
1223 default:
1224 break;
1225 }
1226 }
1227
1228 /* ioctl handle special commands that are not present in ethtool. */
1229 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1230 {
1231 if (!netif_running(dev))
1232 return -EINVAL;
1233
1234 if (!dev->phydev)
1235 return -ENODEV;
1236
1237 return phy_mii_ioctl(dev->phydev, rq, cmd);
1238 }
1239
1240 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1241 struct bcmgenet_tx_ring *ring)
1242 {
1243 struct enet_cb *tx_cb_ptr;
1244
1245 tx_cb_ptr = ring->cbs;
1246 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1247
1248 /* Advancing local write pointer */
1249 if (ring->write_ptr == ring->end_ptr)
1250 ring->write_ptr = ring->cb_ptr;
1251 else
1252 ring->write_ptr++;
1253
1254 return tx_cb_ptr;
1255 }
1256
1257 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1258 struct bcmgenet_tx_ring *ring)
1259 {
1260 struct enet_cb *tx_cb_ptr;
1261
1262 tx_cb_ptr = ring->cbs;
1263 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1264
1265 /* Rewinding local write pointer */
1266 if (ring->write_ptr == ring->cb_ptr)
1267 ring->write_ptr = ring->end_ptr;
1268 else
1269 ring->write_ptr--;
1270
1271 return tx_cb_ptr;
1272 }
1273
1274 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1275 {
1276 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1277 INTRL2_CPU_MASK_SET);
1278 }
1279
1280 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1281 {
1282 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1283 INTRL2_CPU_MASK_CLEAR);
1284 }
1285
1286 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1287 {
1288 bcmgenet_intrl2_1_writel(ring->priv,
1289 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1290 INTRL2_CPU_MASK_SET);
1291 }
1292
1293 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1294 {
1295 bcmgenet_intrl2_1_writel(ring->priv,
1296 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1297 INTRL2_CPU_MASK_CLEAR);
1298 }
1299
1300 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1301 {
1302 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1303 INTRL2_CPU_MASK_SET);
1304 }
1305
1306 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1307 {
1308 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1309 INTRL2_CPU_MASK_CLEAR);
1310 }
1311
1312 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1313 {
1314 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1315 INTRL2_CPU_MASK_CLEAR);
1316 }
1317
1318 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1319 {
1320 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1321 INTRL2_CPU_MASK_SET);
1322 }
1323
1324 /* Simple helper to free a transmit control block's resources
1325 * Returns an skb when the last transmit control block associated with the
1326 * skb is freed. The skb should be freed by the caller if necessary.
1327 */
1328 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1329 struct enet_cb *cb)
1330 {
1331 struct sk_buff *skb;
1332
1333 skb = cb->skb;
1334
1335 if (skb) {
1336 cb->skb = NULL;
1337 if (cb == GENET_CB(skb)->first_cb)
1338 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1339 dma_unmap_len(cb, dma_len),
1340 DMA_TO_DEVICE);
1341 else
1342 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1343 dma_unmap_len(cb, dma_len),
1344 DMA_TO_DEVICE);
1345 dma_unmap_addr_set(cb, dma_addr, 0);
1346
1347 if (cb == GENET_CB(skb)->last_cb)
1348 return skb;
1349
1350 } else if (dma_unmap_addr(cb, dma_addr)) {
1351 dma_unmap_page(dev,
1352 dma_unmap_addr(cb, dma_addr),
1353 dma_unmap_len(cb, dma_len),
1354 DMA_TO_DEVICE);
1355 dma_unmap_addr_set(cb, dma_addr, 0);
1356 }
1357
1358 return NULL;
1359 }
1360
1361 /* Simple helper to free a receive control block's resources */
1362 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1363 struct enet_cb *cb)
1364 {
1365 struct sk_buff *skb;
1366
1367 skb = cb->skb;
1368 cb->skb = NULL;
1369
1370 if (dma_unmap_addr(cb, dma_addr)) {
1371 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1372 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1373 dma_unmap_addr_set(cb, dma_addr, 0);
1374 }
1375
1376 return skb;
1377 }
1378
1379 /* Unlocked version of the reclaim routine */
1380 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1381 struct bcmgenet_tx_ring *ring)
1382 {
1383 struct bcmgenet_priv *priv = netdev_priv(dev);
1384 unsigned int txbds_processed = 0;
1385 unsigned int bytes_compl = 0;
1386 unsigned int pkts_compl = 0;
1387 unsigned int txbds_ready;
1388 unsigned int c_index;
1389 struct sk_buff *skb;
1390
1391 /* Clear status before servicing to reduce spurious interrupts */
1392 if (ring->index == DESC_INDEX)
1393 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1394 INTRL2_CPU_CLEAR);
1395 else
1396 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1397 INTRL2_CPU_CLEAR);
1398
1399 /* Compute how many buffers are transmitted since last xmit call */
1400 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1401 & DMA_C_INDEX_MASK;
1402 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1403
1404 netif_dbg(priv, tx_done, dev,
1405 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1406 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1407
1408 /* Reclaim transmitted buffers */
1409 while (txbds_processed < txbds_ready) {
1410 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1411 &priv->tx_cbs[ring->clean_ptr]);
1412 if (skb) {
1413 pkts_compl++;
1414 bytes_compl += GENET_CB(skb)->bytes_sent;
1415 dev_consume_skb_any(skb);
1416 }
1417
1418 txbds_processed++;
1419 if (likely(ring->clean_ptr < ring->end_ptr))
1420 ring->clean_ptr++;
1421 else
1422 ring->clean_ptr = ring->cb_ptr;
1423 }
1424
1425 ring->free_bds += txbds_processed;
1426 ring->c_index = c_index;
1427
1428 ring->packets += pkts_compl;
1429 ring->bytes += bytes_compl;
1430
1431 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1432 pkts_compl, bytes_compl);
1433
1434 return txbds_processed;
1435 }
1436
1437 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1438 struct bcmgenet_tx_ring *ring)
1439 {
1440 unsigned int released;
1441
1442 spin_lock_bh(&ring->lock);
1443 released = __bcmgenet_tx_reclaim(dev, ring);
1444 spin_unlock_bh(&ring->lock);
1445
1446 return released;
1447 }
1448
1449 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1450 {
1451 struct bcmgenet_tx_ring *ring =
1452 container_of(napi, struct bcmgenet_tx_ring, napi);
1453 unsigned int work_done = 0;
1454 struct netdev_queue *txq;
1455
1456 spin_lock(&ring->lock);
1457 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1458 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1459 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1460 netif_tx_wake_queue(txq);
1461 }
1462 spin_unlock(&ring->lock);
1463
1464 if (work_done == 0) {
1465 napi_complete(napi);
1466 ring->int_enable(ring);
1467
1468 return 0;
1469 }
1470
1471 return budget;
1472 }
1473
1474 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1475 {
1476 struct bcmgenet_priv *priv = netdev_priv(dev);
1477 int i;
1478
1479 if (netif_is_multiqueue(dev)) {
1480 for (i = 0; i < priv->hw_params->tx_queues; i++)
1481 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1482 }
1483
1484 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1485 }
1486
1487 /* Reallocate the SKB to put enough headroom in front of it and insert
1488 * the transmit checksum offsets in the descriptors
1489 */
1490 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1491 struct sk_buff *skb)
1492 {
1493 struct status_64 *status = NULL;
1494 struct sk_buff *new_skb;
1495 u16 offset;
1496 u8 ip_proto;
1497 __be16 ip_ver;
1498 u32 tx_csum_info;
1499
1500 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1501 /* If 64 byte status block enabled, must make sure skb has
1502 * enough headroom for us to insert 64B status block.
1503 */
1504 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1505 dev_kfree_skb(skb);
1506 if (!new_skb) {
1507 dev->stats.tx_dropped++;
1508 return NULL;
1509 }
1510 skb = new_skb;
1511 }
1512
1513 skb_push(skb, sizeof(*status));
1514 status = (struct status_64 *)skb->data;
1515
1516 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1517 ip_ver = skb->protocol;
1518 switch (ip_ver) {
1519 case htons(ETH_P_IP):
1520 ip_proto = ip_hdr(skb)->protocol;
1521 break;
1522 case htons(ETH_P_IPV6):
1523 ip_proto = ipv6_hdr(skb)->nexthdr;
1524 break;
1525 default:
1526 return skb;
1527 }
1528
1529 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1530 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1531 (offset + skb->csum_offset);
1532
1533 /* Set the length valid bit for TCP and UDP and just set
1534 * the special UDP flag for IPv4, else just set to 0.
1535 */
1536 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1537 tx_csum_info |= STATUS_TX_CSUM_LV;
1538 if (ip_proto == IPPROTO_UDP &&
1539 ip_ver == htons(ETH_P_IP))
1540 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1541 } else {
1542 tx_csum_info = 0;
1543 }
1544
1545 status->tx_csum_info = tx_csum_info;
1546 }
1547
1548 return skb;
1549 }
1550
1551 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1552 {
1553 struct bcmgenet_priv *priv = netdev_priv(dev);
1554 struct device *kdev = &priv->pdev->dev;
1555 struct bcmgenet_tx_ring *ring = NULL;
1556 struct enet_cb *tx_cb_ptr;
1557 struct netdev_queue *txq;
1558 int nr_frags, index;
1559 dma_addr_t mapping;
1560 unsigned int size;
1561 skb_frag_t *frag;
1562 u32 len_stat;
1563 int ret;
1564 int i;
1565
1566 index = skb_get_queue_mapping(skb);
1567 /* Mapping strategy:
1568 * queue_mapping = 0, unclassified, packet xmited through ring16
1569 * queue_mapping = 1, goes to ring 0. (highest priority queue
1570 * queue_mapping = 2, goes to ring 1.
1571 * queue_mapping = 3, goes to ring 2.
1572 * queue_mapping = 4, goes to ring 3.
1573 */
1574 if (index == 0)
1575 index = DESC_INDEX;
1576 else
1577 index -= 1;
1578
1579 ring = &priv->tx_rings[index];
1580 txq = netdev_get_tx_queue(dev, ring->queue);
1581
1582 nr_frags = skb_shinfo(skb)->nr_frags;
1583
1584 spin_lock(&ring->lock);
1585 if (ring->free_bds <= (nr_frags + 1)) {
1586 if (!netif_tx_queue_stopped(txq)) {
1587 netif_tx_stop_queue(txq);
1588 netdev_err(dev,
1589 "%s: tx ring %d full when queue %d awake\n",
1590 __func__, index, ring->queue);
1591 }
1592 ret = NETDEV_TX_BUSY;
1593 goto out;
1594 }
1595
1596 /* Retain how many bytes will be sent on the wire, without TSB inserted
1597 * by transmit checksum offload
1598 */
1599 GENET_CB(skb)->bytes_sent = skb->len;
1600
1601 /* set the SKB transmit checksum */
1602 if (priv->desc_64b_en) {
1603 skb = bcmgenet_put_tx_csum(dev, skb);
1604 if (!skb) {
1605 ret = NETDEV_TX_OK;
1606 goto out;
1607 }
1608 }
1609
1610 for (i = 0; i <= nr_frags; i++) {
1611 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1612
1613 BUG_ON(!tx_cb_ptr);
1614
1615 if (!i) {
1616 /* Transmit single SKB or head of fragment list */
1617 GENET_CB(skb)->first_cb = tx_cb_ptr;
1618 size = skb_headlen(skb);
1619 mapping = dma_map_single(kdev, skb->data, size,
1620 DMA_TO_DEVICE);
1621 } else {
1622 /* xmit fragment */
1623 frag = &skb_shinfo(skb)->frags[i - 1];
1624 size = skb_frag_size(frag);
1625 mapping = skb_frag_dma_map(kdev, frag, 0, size,
1626 DMA_TO_DEVICE);
1627 }
1628
1629 ret = dma_mapping_error(kdev, mapping);
1630 if (ret) {
1631 priv->mib.tx_dma_failed++;
1632 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1633 ret = NETDEV_TX_OK;
1634 goto out_unmap_frags;
1635 }
1636 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1637 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1638
1639 tx_cb_ptr->skb = skb;
1640
1641 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1642 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1643
1644 /* Note: if we ever change from DMA_TX_APPEND_CRC below we
1645 * will need to restore software padding of "runt" packets
1646 */
1647 if (!i) {
1648 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1649 if (skb->ip_summed == CHECKSUM_PARTIAL)
1650 len_stat |= DMA_TX_DO_CSUM;
1651 }
1652 if (i == nr_frags)
1653 len_stat |= DMA_EOP;
1654
1655 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1656 }
1657
1658 GENET_CB(skb)->last_cb = tx_cb_ptr;
1659 skb_tx_timestamp(skb);
1660
1661 /* Decrement total BD count and advance our write pointer */
1662 ring->free_bds -= nr_frags + 1;
1663 ring->prod_index += nr_frags + 1;
1664 ring->prod_index &= DMA_P_INDEX_MASK;
1665
1666 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1667
1668 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1669 netif_tx_stop_queue(txq);
1670
1671 if (!skb->xmit_more || netif_xmit_stopped(txq))
1672 /* Packets are ready, update producer index */
1673 bcmgenet_tdma_ring_writel(priv, ring->index,
1674 ring->prod_index, TDMA_PROD_INDEX);
1675 out:
1676 spin_unlock(&ring->lock);
1677
1678 return ret;
1679
1680 out_unmap_frags:
1681 /* Back up for failed control block mapping */
1682 bcmgenet_put_txcb(priv, ring);
1683
1684 /* Unmap successfully mapped control blocks */
1685 while (i-- > 0) {
1686 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1687 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1688 }
1689
1690 dev_kfree_skb(skb);
1691 goto out;
1692 }
1693
1694 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1695 struct enet_cb *cb)
1696 {
1697 struct device *kdev = &priv->pdev->dev;
1698 struct sk_buff *skb;
1699 struct sk_buff *rx_skb;
1700 dma_addr_t mapping;
1701
1702 /* Allocate a new Rx skb */
1703 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
1704 GFP_ATOMIC | __GFP_NOWARN);
1705 if (!skb) {
1706 priv->mib.alloc_rx_buff_failed++;
1707 netif_err(priv, rx_err, priv->dev,
1708 "%s: Rx skb allocation failed\n", __func__);
1709 return NULL;
1710 }
1711
1712 /* DMA-map the new Rx skb */
1713 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1714 DMA_FROM_DEVICE);
1715 if (dma_mapping_error(kdev, mapping)) {
1716 priv->mib.rx_dma_failed++;
1717 dev_kfree_skb_any(skb);
1718 netif_err(priv, rx_err, priv->dev,
1719 "%s: Rx skb DMA mapping failed\n", __func__);
1720 return NULL;
1721 }
1722
1723 /* Grab the current Rx skb from the ring and DMA-unmap it */
1724 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1725
1726 /* Put the new Rx skb on the ring */
1727 cb->skb = skb;
1728 dma_unmap_addr_set(cb, dma_addr, mapping);
1729 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1730 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1731
1732 /* Return the current Rx skb to caller */
1733 return rx_skb;
1734 }
1735
1736 /* bcmgenet_desc_rx - descriptor based rx process.
1737 * this could be called from bottom half, or from NAPI polling method.
1738 */
1739 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1740 unsigned int budget)
1741 {
1742 struct bcmgenet_priv *priv = ring->priv;
1743 struct net_device *dev = priv->dev;
1744 struct enet_cb *cb;
1745 struct sk_buff *skb;
1746 u32 dma_length_status;
1747 unsigned long dma_flag;
1748 int len;
1749 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1750 unsigned int bytes_processed = 0;
1751 unsigned int p_index, mask;
1752 unsigned int discards;
1753 unsigned int chksum_ok = 0;
1754
1755 /* Clear status before servicing to reduce spurious interrupts */
1756 if (ring->index == DESC_INDEX) {
1757 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1758 INTRL2_CPU_CLEAR);
1759 } else {
1760 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1761 bcmgenet_intrl2_1_writel(priv,
1762 mask,
1763 INTRL2_CPU_CLEAR);
1764 }
1765
1766 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1767
1768 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1769 DMA_P_INDEX_DISCARD_CNT_MASK;
1770 if (discards > ring->old_discards) {
1771 discards = discards - ring->old_discards;
1772 ring->errors += discards;
1773 ring->old_discards += discards;
1774
1775 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1776 if (ring->old_discards >= 0xC000) {
1777 ring->old_discards = 0;
1778 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1779 RDMA_PROD_INDEX);
1780 }
1781 }
1782
1783 p_index &= DMA_P_INDEX_MASK;
1784 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1785
1786 netif_dbg(priv, rx_status, dev,
1787 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1788
1789 while ((rxpktprocessed < rxpkttoprocess) &&
1790 (rxpktprocessed < budget)) {
1791 cb = &priv->rx_cbs[ring->read_ptr];
1792 skb = bcmgenet_rx_refill(priv, cb);
1793
1794 if (unlikely(!skb)) {
1795 ring->dropped++;
1796 goto next;
1797 }
1798
1799 if (!priv->desc_64b_en) {
1800 dma_length_status =
1801 dmadesc_get_length_status(priv, cb->bd_addr);
1802 } else {
1803 struct status_64 *status;
1804
1805 status = (struct status_64 *)skb->data;
1806 dma_length_status = status->length_status;
1807 }
1808
1809 /* DMA flags and length are still valid no matter how
1810 * we got the Receive Status Vector (64B RSB or register)
1811 */
1812 dma_flag = dma_length_status & 0xffff;
1813 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1814
1815 netif_dbg(priv, rx_status, dev,
1816 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1817 __func__, p_index, ring->c_index,
1818 ring->read_ptr, dma_length_status);
1819
1820 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1821 netif_err(priv, rx_status, dev,
1822 "dropping fragmented packet!\n");
1823 ring->errors++;
1824 dev_kfree_skb_any(skb);
1825 goto next;
1826 }
1827
1828 /* report errors */
1829 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1830 DMA_RX_OV |
1831 DMA_RX_NO |
1832 DMA_RX_LG |
1833 DMA_RX_RXER))) {
1834 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1835 (unsigned int)dma_flag);
1836 if (dma_flag & DMA_RX_CRC_ERROR)
1837 dev->stats.rx_crc_errors++;
1838 if (dma_flag & DMA_RX_OV)
1839 dev->stats.rx_over_errors++;
1840 if (dma_flag & DMA_RX_NO)
1841 dev->stats.rx_frame_errors++;
1842 if (dma_flag & DMA_RX_LG)
1843 dev->stats.rx_length_errors++;
1844 dev->stats.rx_errors++;
1845 dev_kfree_skb_any(skb);
1846 goto next;
1847 } /* error packet */
1848
1849 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1850 priv->desc_rxchk_en;
1851
1852 skb_put(skb, len);
1853 if (priv->desc_64b_en) {
1854 skb_pull(skb, 64);
1855 len -= 64;
1856 }
1857
1858 if (likely(chksum_ok))
1859 skb->ip_summed = CHECKSUM_UNNECESSARY;
1860
1861 /* remove hardware 2bytes added for IP alignment */
1862 skb_pull(skb, 2);
1863 len -= 2;
1864
1865 if (priv->crc_fwd_en) {
1866 skb_trim(skb, len - ETH_FCS_LEN);
1867 len -= ETH_FCS_LEN;
1868 }
1869
1870 bytes_processed += len;
1871
1872 /*Finish setting up the received SKB and send it to the kernel*/
1873 skb->protocol = eth_type_trans(skb, priv->dev);
1874 ring->packets++;
1875 ring->bytes += len;
1876 if (dma_flag & DMA_RX_MULT)
1877 dev->stats.multicast++;
1878
1879 /* Notify kernel */
1880 napi_gro_receive(&ring->napi, skb);
1881 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1882
1883 next:
1884 rxpktprocessed++;
1885 if (likely(ring->read_ptr < ring->end_ptr))
1886 ring->read_ptr++;
1887 else
1888 ring->read_ptr = ring->cb_ptr;
1889
1890 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1891 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1892 }
1893
1894 ring->dim.bytes = bytes_processed;
1895 ring->dim.packets = rxpktprocessed;
1896
1897 return rxpktprocessed;
1898 }
1899
1900 /* Rx NAPI polling method */
1901 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1902 {
1903 struct bcmgenet_rx_ring *ring = container_of(napi,
1904 struct bcmgenet_rx_ring, napi);
1905 struct net_dim_sample dim_sample;
1906 unsigned int work_done;
1907
1908 work_done = bcmgenet_desc_rx(ring, budget);
1909
1910 if (work_done < budget) {
1911 napi_complete_done(napi, work_done);
1912 ring->int_enable(ring);
1913 }
1914
1915 if (ring->dim.use_dim) {
1916 net_dim_sample(ring->dim.event_ctr, ring->dim.packets,
1917 ring->dim.bytes, &dim_sample);
1918 net_dim(&ring->dim.dim, dim_sample);
1919 }
1920
1921 return work_done;
1922 }
1923
1924 static void bcmgenet_dim_work(struct work_struct *work)
1925 {
1926 struct net_dim *dim = container_of(work, struct net_dim, work);
1927 struct bcmgenet_net_dim *ndim =
1928 container_of(dim, struct bcmgenet_net_dim, dim);
1929 struct bcmgenet_rx_ring *ring =
1930 container_of(ndim, struct bcmgenet_rx_ring, dim);
1931 struct net_dim_cq_moder cur_profile =
1932 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
1933
1934 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
1935 dim->state = NET_DIM_START_MEASURE;
1936 }
1937
1938 /* Assign skb to RX DMA descriptor. */
1939 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1940 struct bcmgenet_rx_ring *ring)
1941 {
1942 struct enet_cb *cb;
1943 struct sk_buff *skb;
1944 int i;
1945
1946 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1947
1948 /* loop here for each buffer needing assign */
1949 for (i = 0; i < ring->size; i++) {
1950 cb = ring->cbs + i;
1951 skb = bcmgenet_rx_refill(priv, cb);
1952 if (skb)
1953 dev_consume_skb_any(skb);
1954 if (!cb->skb)
1955 return -ENOMEM;
1956 }
1957
1958 return 0;
1959 }
1960
1961 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1962 {
1963 struct sk_buff *skb;
1964 struct enet_cb *cb;
1965 int i;
1966
1967 for (i = 0; i < priv->num_rx_bds; i++) {
1968 cb = &priv->rx_cbs[i];
1969
1970 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1971 if (skb)
1972 dev_consume_skb_any(skb);
1973 }
1974 }
1975
1976 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1977 {
1978 u32 reg;
1979
1980 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1981 if (enable)
1982 reg |= mask;
1983 else
1984 reg &= ~mask;
1985 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1986
1987 /* UniMAC stops on a packet boundary, wait for a full-size packet
1988 * to be processed
1989 */
1990 if (enable == 0)
1991 usleep_range(1000, 2000);
1992 }
1993
1994 static void reset_umac(struct bcmgenet_priv *priv)
1995 {
1996 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1997 bcmgenet_rbuf_ctrl_set(priv, 0);
1998 udelay(10);
1999
2000 /* disable MAC while updating its registers */
2001 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
2002
2003 /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
2004 bcmgenet_umac_writel(priv, CMD_SW_RESET | CMD_LCL_LOOP_EN, UMAC_CMD);
2005 }
2006
2007 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2008 {
2009 /* Mask all interrupts.*/
2010 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2011 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2012 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2013 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2014 }
2015
2016 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2017 {
2018 u32 int0_enable = 0;
2019
2020 /* Monitor cable plug/unplugged event for internal PHY, external PHY
2021 * and MoCA PHY
2022 */
2023 if (priv->internal_phy) {
2024 int0_enable |= UMAC_IRQ_LINK_EVENT;
2025 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2026 int0_enable |= UMAC_IRQ_PHY_DET_R;
2027 } else if (priv->ext_phy) {
2028 int0_enable |= UMAC_IRQ_LINK_EVENT;
2029 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2030 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2031 int0_enable |= UMAC_IRQ_LINK_EVENT;
2032 }
2033 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2034 }
2035
2036 static void init_umac(struct bcmgenet_priv *priv)
2037 {
2038 struct device *kdev = &priv->pdev->dev;
2039 u32 reg;
2040 u32 int0_enable = 0;
2041
2042 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2043
2044 reset_umac(priv);
2045
2046 /* clear tx/rx counter */
2047 bcmgenet_umac_writel(priv,
2048 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2049 UMAC_MIB_CTRL);
2050 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2051
2052 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2053
2054 /* init rx registers, enable ip header optimization */
2055 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2056 reg |= RBUF_ALIGN_2B;
2057 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2058
2059 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2060 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2061
2062 bcmgenet_intr_disable(priv);
2063
2064 /* Configure backpressure vectors for MoCA */
2065 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2066 reg = bcmgenet_bp_mc_get(priv);
2067 reg |= BIT(priv->hw_params->bp_in_en_shift);
2068
2069 /* bp_mask: back pressure mask */
2070 if (netif_is_multiqueue(priv->dev))
2071 reg |= priv->hw_params->bp_in_mask;
2072 else
2073 reg &= ~priv->hw_params->bp_in_mask;
2074 bcmgenet_bp_mc_set(priv, reg);
2075 }
2076
2077 /* Enable MDIO interrupts on GENET v3+ */
2078 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2079 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2080
2081 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2082
2083 dev_dbg(kdev, "done init umac\n");
2084 }
2085
2086 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2087 void (*cb)(struct work_struct *work))
2088 {
2089 struct bcmgenet_net_dim *dim = &ring->dim;
2090
2091 INIT_WORK(&dim->dim.work, cb);
2092 dim->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2093 dim->event_ctr = 0;
2094 dim->packets = 0;
2095 dim->bytes = 0;
2096 }
2097
2098 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2099 {
2100 struct bcmgenet_net_dim *dim = &ring->dim;
2101 struct net_dim_cq_moder moder;
2102 u32 usecs, pkts;
2103
2104 usecs = ring->rx_coalesce_usecs;
2105 pkts = ring->rx_max_coalesced_frames;
2106
2107 /* If DIM was enabled, re-apply default parameters */
2108 if (dim->use_dim) {
2109 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2110 usecs = moder.usec;
2111 pkts = moder.pkts;
2112 }
2113
2114 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2115 }
2116
2117 /* Initialize a Tx ring along with corresponding hardware registers */
2118 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2119 unsigned int index, unsigned int size,
2120 unsigned int start_ptr, unsigned int end_ptr)
2121 {
2122 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2123 u32 words_per_bd = WORDS_PER_BD(priv);
2124 u32 flow_period_val = 0;
2125
2126 spin_lock_init(&ring->lock);
2127 ring->priv = priv;
2128 ring->index = index;
2129 if (index == DESC_INDEX) {
2130 ring->queue = 0;
2131 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2132 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2133 } else {
2134 ring->queue = index + 1;
2135 ring->int_enable = bcmgenet_tx_ring_int_enable;
2136 ring->int_disable = bcmgenet_tx_ring_int_disable;
2137 }
2138 ring->cbs = priv->tx_cbs + start_ptr;
2139 ring->size = size;
2140 ring->clean_ptr = start_ptr;
2141 ring->c_index = 0;
2142 ring->free_bds = size;
2143 ring->write_ptr = start_ptr;
2144 ring->cb_ptr = start_ptr;
2145 ring->end_ptr = end_ptr - 1;
2146 ring->prod_index = 0;
2147
2148 /* Set flow period for ring != 16 */
2149 if (index != DESC_INDEX)
2150 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2151
2152 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2153 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2154 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2155 /* Disable rate control for now */
2156 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2157 TDMA_FLOW_PERIOD);
2158 bcmgenet_tdma_ring_writel(priv, index,
2159 ((size << DMA_RING_SIZE_SHIFT) |
2160 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2161
2162 /* Set start and end address, read and write pointers */
2163 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2164 DMA_START_ADDR);
2165 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2166 TDMA_READ_PTR);
2167 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2168 TDMA_WRITE_PTR);
2169 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2170 DMA_END_ADDR);
2171
2172 /* Initialize Tx NAPI */
2173 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2174 NAPI_POLL_WEIGHT);
2175 }
2176
2177 /* Initialize a RDMA ring */
2178 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2179 unsigned int index, unsigned int size,
2180 unsigned int start_ptr, unsigned int end_ptr)
2181 {
2182 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2183 u32 words_per_bd = WORDS_PER_BD(priv);
2184 int ret;
2185
2186 ring->priv = priv;
2187 ring->index = index;
2188 if (index == DESC_INDEX) {
2189 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2190 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2191 } else {
2192 ring->int_enable = bcmgenet_rx_ring_int_enable;
2193 ring->int_disable = bcmgenet_rx_ring_int_disable;
2194 }
2195 ring->cbs = priv->rx_cbs + start_ptr;
2196 ring->size = size;
2197 ring->c_index = 0;
2198 ring->read_ptr = start_ptr;
2199 ring->cb_ptr = start_ptr;
2200 ring->end_ptr = end_ptr - 1;
2201
2202 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2203 if (ret)
2204 return ret;
2205
2206 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2207 bcmgenet_init_rx_coalesce(ring);
2208
2209 /* Initialize Rx NAPI */
2210 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2211 NAPI_POLL_WEIGHT);
2212
2213 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2214 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2215 bcmgenet_rdma_ring_writel(priv, index,
2216 ((size << DMA_RING_SIZE_SHIFT) |
2217 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2218 bcmgenet_rdma_ring_writel(priv, index,
2219 (DMA_FC_THRESH_LO <<
2220 DMA_XOFF_THRESHOLD_SHIFT) |
2221 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2222
2223 /* Set start and end address, read and write pointers */
2224 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2225 DMA_START_ADDR);
2226 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2227 RDMA_READ_PTR);
2228 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2229 RDMA_WRITE_PTR);
2230 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2231 DMA_END_ADDR);
2232
2233 return ret;
2234 }
2235
2236 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2237 {
2238 unsigned int i;
2239 struct bcmgenet_tx_ring *ring;
2240
2241 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2242 ring = &priv->tx_rings[i];
2243 napi_enable(&ring->napi);
2244 ring->int_enable(ring);
2245 }
2246
2247 ring = &priv->tx_rings[DESC_INDEX];
2248 napi_enable(&ring->napi);
2249 ring->int_enable(ring);
2250 }
2251
2252 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2253 {
2254 unsigned int i;
2255 struct bcmgenet_tx_ring *ring;
2256
2257 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2258 ring = &priv->tx_rings[i];
2259 napi_disable(&ring->napi);
2260 }
2261
2262 ring = &priv->tx_rings[DESC_INDEX];
2263 napi_disable(&ring->napi);
2264 }
2265
2266 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2267 {
2268 unsigned int i;
2269 struct bcmgenet_tx_ring *ring;
2270
2271 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2272 ring = &priv->tx_rings[i];
2273 netif_napi_del(&ring->napi);
2274 }
2275
2276 ring = &priv->tx_rings[DESC_INDEX];
2277 netif_napi_del(&ring->napi);
2278 }
2279
2280 /* Initialize Tx queues
2281 *
2282 * Queues 0-3 are priority-based, each one has 32 descriptors,
2283 * with queue 0 being the highest priority queue.
2284 *
2285 * Queue 16 is the default Tx queue with
2286 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2287 *
2288 * The transmit control block pool is then partitioned as follows:
2289 * - Tx queue 0 uses tx_cbs[0..31]
2290 * - Tx queue 1 uses tx_cbs[32..63]
2291 * - Tx queue 2 uses tx_cbs[64..95]
2292 * - Tx queue 3 uses tx_cbs[96..127]
2293 * - Tx queue 16 uses tx_cbs[128..255]
2294 */
2295 static void bcmgenet_init_tx_queues(struct net_device *dev)
2296 {
2297 struct bcmgenet_priv *priv = netdev_priv(dev);
2298 u32 i, dma_enable;
2299 u32 dma_ctrl, ring_cfg;
2300 u32 dma_priority[3] = {0, 0, 0};
2301
2302 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2303 dma_enable = dma_ctrl & DMA_EN;
2304 dma_ctrl &= ~DMA_EN;
2305 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2306
2307 dma_ctrl = 0;
2308 ring_cfg = 0;
2309
2310 /* Enable strict priority arbiter mode */
2311 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2312
2313 /* Initialize Tx priority queues */
2314 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2315 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2316 i * priv->hw_params->tx_bds_per_q,
2317 (i + 1) * priv->hw_params->tx_bds_per_q);
2318 ring_cfg |= (1 << i);
2319 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2320 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2321 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2322 }
2323
2324 /* Initialize Tx default queue 16 */
2325 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2326 priv->hw_params->tx_queues *
2327 priv->hw_params->tx_bds_per_q,
2328 TOTAL_DESC);
2329 ring_cfg |= (1 << DESC_INDEX);
2330 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2331 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2332 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2333 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2334
2335 /* Set Tx queue priorities */
2336 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2337 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2338 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2339
2340 /* Enable Tx queues */
2341 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2342
2343 /* Enable Tx DMA */
2344 if (dma_enable)
2345 dma_ctrl |= DMA_EN;
2346 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2347 }
2348
2349 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2350 {
2351 unsigned int i;
2352 struct bcmgenet_rx_ring *ring;
2353
2354 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2355 ring = &priv->rx_rings[i];
2356 napi_enable(&ring->napi);
2357 ring->int_enable(ring);
2358 }
2359
2360 ring = &priv->rx_rings[DESC_INDEX];
2361 napi_enable(&ring->napi);
2362 ring->int_enable(ring);
2363 }
2364
2365 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2366 {
2367 unsigned int i;
2368 struct bcmgenet_rx_ring *ring;
2369
2370 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2371 ring = &priv->rx_rings[i];
2372 napi_disable(&ring->napi);
2373 cancel_work_sync(&ring->dim.dim.work);
2374 }
2375
2376 ring = &priv->rx_rings[DESC_INDEX];
2377 napi_disable(&ring->napi);
2378 cancel_work_sync(&ring->dim.dim.work);
2379 }
2380
2381 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2382 {
2383 unsigned int i;
2384 struct bcmgenet_rx_ring *ring;
2385
2386 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2387 ring = &priv->rx_rings[i];
2388 netif_napi_del(&ring->napi);
2389 }
2390
2391 ring = &priv->rx_rings[DESC_INDEX];
2392 netif_napi_del(&ring->napi);
2393 }
2394
2395 /* Initialize Rx queues
2396 *
2397 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2398 * used to direct traffic to these queues.
2399 *
2400 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2401 */
2402 static int bcmgenet_init_rx_queues(struct net_device *dev)
2403 {
2404 struct bcmgenet_priv *priv = netdev_priv(dev);
2405 u32 i;
2406 u32 dma_enable;
2407 u32 dma_ctrl;
2408 u32 ring_cfg;
2409 int ret;
2410
2411 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2412 dma_enable = dma_ctrl & DMA_EN;
2413 dma_ctrl &= ~DMA_EN;
2414 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2415
2416 dma_ctrl = 0;
2417 ring_cfg = 0;
2418
2419 /* Initialize Rx priority queues */
2420 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2421 ret = bcmgenet_init_rx_ring(priv, i,
2422 priv->hw_params->rx_bds_per_q,
2423 i * priv->hw_params->rx_bds_per_q,
2424 (i + 1) *
2425 priv->hw_params->rx_bds_per_q);
2426 if (ret)
2427 return ret;
2428
2429 ring_cfg |= (1 << i);
2430 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2431 }
2432
2433 /* Initialize Rx default queue 16 */
2434 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2435 priv->hw_params->rx_queues *
2436 priv->hw_params->rx_bds_per_q,
2437 TOTAL_DESC);
2438 if (ret)
2439 return ret;
2440
2441 ring_cfg |= (1 << DESC_INDEX);
2442 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2443
2444 /* Enable rings */
2445 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2446
2447 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2448 if (dma_enable)
2449 dma_ctrl |= DMA_EN;
2450 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2451
2452 return 0;
2453 }
2454
2455 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2456 {
2457 int ret = 0;
2458 int timeout = 0;
2459 u32 reg;
2460 u32 dma_ctrl;
2461 int i;
2462
2463 /* Disable TDMA to stop add more frames in TX DMA */
2464 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2465 reg &= ~DMA_EN;
2466 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2467
2468 /* Check TDMA status register to confirm TDMA is disabled */
2469 while (timeout++ < DMA_TIMEOUT_VAL) {
2470 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2471 if (reg & DMA_DISABLED)
2472 break;
2473
2474 udelay(1);
2475 }
2476
2477 if (timeout == DMA_TIMEOUT_VAL) {
2478 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2479 ret = -ETIMEDOUT;
2480 }
2481
2482 /* Wait 10ms for packet drain in both tx and rx dma */
2483 usleep_range(10000, 20000);
2484
2485 /* Disable RDMA */
2486 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2487 reg &= ~DMA_EN;
2488 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2489
2490 timeout = 0;
2491 /* Check RDMA status register to confirm RDMA is disabled */
2492 while (timeout++ < DMA_TIMEOUT_VAL) {
2493 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2494 if (reg & DMA_DISABLED)
2495 break;
2496
2497 udelay(1);
2498 }
2499
2500 if (timeout == DMA_TIMEOUT_VAL) {
2501 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2502 ret = -ETIMEDOUT;
2503 }
2504
2505 dma_ctrl = 0;
2506 for (i = 0; i < priv->hw_params->rx_queues; i++)
2507 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2508 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2509 reg &= ~dma_ctrl;
2510 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2511
2512 dma_ctrl = 0;
2513 for (i = 0; i < priv->hw_params->tx_queues; i++)
2514 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2515 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2516 reg &= ~dma_ctrl;
2517 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2518
2519 return ret;
2520 }
2521
2522 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2523 {
2524 struct netdev_queue *txq;
2525 struct sk_buff *skb;
2526 struct enet_cb *cb;
2527 int i;
2528
2529 bcmgenet_fini_rx_napi(priv);
2530 bcmgenet_fini_tx_napi(priv);
2531
2532 for (i = 0; i < priv->num_tx_bds; i++) {
2533 cb = priv->tx_cbs + i;
2534 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, cb);
2535 if (skb)
2536 dev_kfree_skb(skb);
2537 }
2538
2539 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2540 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2541 netdev_tx_reset_queue(txq);
2542 }
2543
2544 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2545 netdev_tx_reset_queue(txq);
2546
2547 bcmgenet_free_rx_buffers(priv);
2548 kfree(priv->rx_cbs);
2549 kfree(priv->tx_cbs);
2550 }
2551
2552 /* init_edma: Initialize DMA control register */
2553 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2554 {
2555 int ret;
2556 unsigned int i;
2557 struct enet_cb *cb;
2558
2559 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2560
2561 /* Initialize common Rx ring structures */
2562 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2563 priv->num_rx_bds = TOTAL_DESC;
2564 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2565 GFP_KERNEL);
2566 if (!priv->rx_cbs)
2567 return -ENOMEM;
2568
2569 for (i = 0; i < priv->num_rx_bds; i++) {
2570 cb = priv->rx_cbs + i;
2571 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2572 }
2573
2574 /* Initialize common TX ring structures */
2575 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2576 priv->num_tx_bds = TOTAL_DESC;
2577 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2578 GFP_KERNEL);
2579 if (!priv->tx_cbs) {
2580 kfree(priv->rx_cbs);
2581 return -ENOMEM;
2582 }
2583
2584 for (i = 0; i < priv->num_tx_bds; i++) {
2585 cb = priv->tx_cbs + i;
2586 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2587 }
2588
2589 /* Init rDma */
2590 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2591
2592 /* Initialize Rx queues */
2593 ret = bcmgenet_init_rx_queues(priv->dev);
2594 if (ret) {
2595 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2596 bcmgenet_free_rx_buffers(priv);
2597 kfree(priv->rx_cbs);
2598 kfree(priv->tx_cbs);
2599 return ret;
2600 }
2601
2602 /* Init tDma */
2603 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2604
2605 /* Initialize Tx queues */
2606 bcmgenet_init_tx_queues(priv->dev);
2607
2608 return 0;
2609 }
2610
2611 /* Interrupt bottom half */
2612 static void bcmgenet_irq_task(struct work_struct *work)
2613 {
2614 unsigned int status;
2615 struct bcmgenet_priv *priv = container_of(
2616 work, struct bcmgenet_priv, bcmgenet_irq_work);
2617
2618 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2619
2620 spin_lock_irq(&priv->lock);
2621 status = priv->irq0_stat;
2622 priv->irq0_stat = 0;
2623 spin_unlock_irq(&priv->lock);
2624
2625 if (status & UMAC_IRQ_PHY_DET_R &&
2626 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
2627 phy_init_hw(priv->dev->phydev);
2628 genphy_config_aneg(priv->dev->phydev);
2629 }
2630
2631 /* Link UP/DOWN event */
2632 if (status & UMAC_IRQ_LINK_EVENT)
2633 phy_mac_interrupt(priv->dev->phydev);
2634
2635 }
2636
2637 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2638 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2639 {
2640 struct bcmgenet_priv *priv = dev_id;
2641 struct bcmgenet_rx_ring *rx_ring;
2642 struct bcmgenet_tx_ring *tx_ring;
2643 unsigned int index, status;
2644
2645 /* Read irq status */
2646 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2647 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2648
2649 /* clear interrupts */
2650 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2651
2652 netif_dbg(priv, intr, priv->dev,
2653 "%s: IRQ=0x%x\n", __func__, status);
2654
2655 /* Check Rx priority queue interrupts */
2656 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2657 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2658 continue;
2659
2660 rx_ring = &priv->rx_rings[index];
2661 rx_ring->dim.event_ctr++;
2662
2663 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2664 rx_ring->int_disable(rx_ring);
2665 __napi_schedule_irqoff(&rx_ring->napi);
2666 }
2667 }
2668
2669 /* Check Tx priority queue interrupts */
2670 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2671 if (!(status & BIT(index)))
2672 continue;
2673
2674 tx_ring = &priv->tx_rings[index];
2675
2676 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2677 tx_ring->int_disable(tx_ring);
2678 __napi_schedule_irqoff(&tx_ring->napi);
2679 }
2680 }
2681
2682 return IRQ_HANDLED;
2683 }
2684
2685 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2686 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2687 {
2688 struct bcmgenet_priv *priv = dev_id;
2689 struct bcmgenet_rx_ring *rx_ring;
2690 struct bcmgenet_tx_ring *tx_ring;
2691 unsigned int status;
2692 unsigned long flags;
2693
2694 /* Read irq status */
2695 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2696 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2697
2698 /* clear interrupts */
2699 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2700
2701 netif_dbg(priv, intr, priv->dev,
2702 "IRQ=0x%x\n", status);
2703
2704 if (status & UMAC_IRQ_RXDMA_DONE) {
2705 rx_ring = &priv->rx_rings[DESC_INDEX];
2706 rx_ring->dim.event_ctr++;
2707
2708 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2709 rx_ring->int_disable(rx_ring);
2710 __napi_schedule_irqoff(&rx_ring->napi);
2711 }
2712 }
2713
2714 if (status & UMAC_IRQ_TXDMA_DONE) {
2715 tx_ring = &priv->tx_rings[DESC_INDEX];
2716
2717 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2718 tx_ring->int_disable(tx_ring);
2719 __napi_schedule_irqoff(&tx_ring->napi);
2720 }
2721 }
2722
2723 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2724 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2725 wake_up(&priv->wq);
2726 }
2727
2728 /* all other interested interrupts handled in bottom half */
2729 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
2730 if (status) {
2731 /* Save irq status for bottom-half processing. */
2732 spin_lock_irqsave(&priv->lock, flags);
2733 priv->irq0_stat |= status;
2734 spin_unlock_irqrestore(&priv->lock, flags);
2735
2736 schedule_work(&priv->bcmgenet_irq_work);
2737 }
2738
2739 return IRQ_HANDLED;
2740 }
2741
2742 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2743 {
2744 struct bcmgenet_priv *priv = dev_id;
2745
2746 pm_wakeup_event(&priv->pdev->dev, 0);
2747
2748 return IRQ_HANDLED;
2749 }
2750
2751 #ifdef CONFIG_NET_POLL_CONTROLLER
2752 static void bcmgenet_poll_controller(struct net_device *dev)
2753 {
2754 struct bcmgenet_priv *priv = netdev_priv(dev);
2755
2756 /* Invoke the main RX/TX interrupt handler */
2757 disable_irq(priv->irq0);
2758 bcmgenet_isr0(priv->irq0, priv);
2759 enable_irq(priv->irq0);
2760
2761 /* And the interrupt handler for RX/TX priority queues */
2762 disable_irq(priv->irq1);
2763 bcmgenet_isr1(priv->irq1, priv);
2764 enable_irq(priv->irq1);
2765 }
2766 #endif
2767
2768 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2769 {
2770 u32 reg;
2771
2772 reg = bcmgenet_rbuf_ctrl_get(priv);
2773 reg |= BIT(1);
2774 bcmgenet_rbuf_ctrl_set(priv, reg);
2775 udelay(10);
2776
2777 reg &= ~BIT(1);
2778 bcmgenet_rbuf_ctrl_set(priv, reg);
2779 udelay(10);
2780 }
2781
2782 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2783 unsigned char *addr)
2784 {
2785 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2786 (addr[2] << 8) | addr[3], UMAC_MAC0);
2787 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2788 }
2789
2790 /* Returns a reusable dma control register value */
2791 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2792 {
2793 u32 reg;
2794 u32 dma_ctrl;
2795
2796 /* disable DMA */
2797 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2798 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2799 reg &= ~dma_ctrl;
2800 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2801
2802 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2803 reg &= ~dma_ctrl;
2804 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2805
2806 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2807 udelay(10);
2808 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2809
2810 return dma_ctrl;
2811 }
2812
2813 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2814 {
2815 u32 reg;
2816
2817 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2818 reg |= dma_ctrl;
2819 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2820
2821 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2822 reg |= dma_ctrl;
2823 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2824 }
2825
2826 /* bcmgenet_hfb_clear
2827 *
2828 * Clear Hardware Filter Block and disable all filtering.
2829 */
2830 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2831 {
2832 u32 i;
2833
2834 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2835 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2836 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2837
2838 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2839 bcmgenet_rdma_writel(priv, 0x0, i);
2840
2841 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2842 bcmgenet_hfb_reg_writel(priv, 0x0,
2843 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2844
2845 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2846 priv->hw_params->hfb_filter_size; i++)
2847 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2848 }
2849
2850 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2851 {
2852 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2853 return;
2854
2855 bcmgenet_hfb_clear(priv);
2856 }
2857
2858 static void bcmgenet_netif_start(struct net_device *dev)
2859 {
2860 struct bcmgenet_priv *priv = netdev_priv(dev);
2861
2862 /* Start the network engine */
2863 bcmgenet_set_rx_mode(dev);
2864 bcmgenet_enable_rx_napi(priv);
2865
2866 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2867
2868 bcmgenet_enable_tx_napi(priv);
2869
2870 /* Monitor link interrupts now */
2871 bcmgenet_link_intr_enable(priv);
2872
2873 phy_start(dev->phydev);
2874 }
2875
2876 static int bcmgenet_open(struct net_device *dev)
2877 {
2878 struct bcmgenet_priv *priv = netdev_priv(dev);
2879 unsigned long dma_ctrl;
2880 u32 reg;
2881 int ret;
2882
2883 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2884
2885 /* Turn on the clock */
2886 clk_prepare_enable(priv->clk);
2887
2888 /* If this is an internal GPHY, power it back on now, before UniMAC is
2889 * brought out of reset as absolutely no UniMAC activity is allowed
2890 */
2891 if (priv->internal_phy)
2892 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2893
2894 /* take MAC out of reset */
2895 bcmgenet_umac_reset(priv);
2896
2897 init_umac(priv);
2898
2899 /* Make sure we reflect the value of CRC_CMD_FWD */
2900 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2901 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2902
2903 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2904
2905 if (priv->internal_phy) {
2906 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2907 reg |= EXT_ENERGY_DET_MASK;
2908 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2909 }
2910
2911 /* Disable RX/TX DMA and flush TX queues */
2912 dma_ctrl = bcmgenet_dma_disable(priv);
2913
2914 /* Reinitialize TDMA and RDMA and SW housekeeping */
2915 ret = bcmgenet_init_dma(priv);
2916 if (ret) {
2917 netdev_err(dev, "failed to initialize DMA\n");
2918 goto err_clk_disable;
2919 }
2920
2921 /* Always enable ring 16 - descriptor ring */
2922 bcmgenet_enable_dma(priv, dma_ctrl);
2923
2924 /* HFB init */
2925 bcmgenet_hfb_init(priv);
2926
2927 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2928 dev->name, priv);
2929 if (ret < 0) {
2930 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2931 goto err_fini_dma;
2932 }
2933
2934 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2935 dev->name, priv);
2936 if (ret < 0) {
2937 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2938 goto err_irq0;
2939 }
2940
2941 ret = bcmgenet_mii_probe(dev);
2942 if (ret) {
2943 netdev_err(dev, "failed to connect to PHY\n");
2944 goto err_irq1;
2945 }
2946
2947 bcmgenet_netif_start(dev);
2948
2949 netif_tx_start_all_queues(dev);
2950
2951 return 0;
2952
2953 err_irq1:
2954 free_irq(priv->irq1, priv);
2955 err_irq0:
2956 free_irq(priv->irq0, priv);
2957 err_fini_dma:
2958 bcmgenet_dma_teardown(priv);
2959 bcmgenet_fini_dma(priv);
2960 err_clk_disable:
2961 if (priv->internal_phy)
2962 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2963 clk_disable_unprepare(priv->clk);
2964 return ret;
2965 }
2966
2967 static void bcmgenet_netif_stop(struct net_device *dev)
2968 {
2969 struct bcmgenet_priv *priv = netdev_priv(dev);
2970
2971 bcmgenet_disable_tx_napi(priv);
2972 netif_tx_disable(dev);
2973
2974 /* Disable MAC receive */
2975 umac_enable_set(priv, CMD_RX_EN, false);
2976
2977 bcmgenet_dma_teardown(priv);
2978
2979 /* Disable MAC transmit. TX DMA disabled must be done before this */
2980 umac_enable_set(priv, CMD_TX_EN, false);
2981
2982 phy_stop(dev->phydev);
2983 bcmgenet_disable_rx_napi(priv);
2984 bcmgenet_intr_disable(priv);
2985
2986 /* Wait for pending work items to complete. Since interrupts are
2987 * disabled no new work will be scheduled.
2988 */
2989 cancel_work_sync(&priv->bcmgenet_irq_work);
2990
2991 priv->old_link = -1;
2992 priv->old_speed = -1;
2993 priv->old_duplex = -1;
2994 priv->old_pause = -1;
2995
2996 /* tx reclaim */
2997 bcmgenet_tx_reclaim_all(dev);
2998 bcmgenet_fini_dma(priv);
2999 }
3000
3001 static int bcmgenet_close(struct net_device *dev)
3002 {
3003 struct bcmgenet_priv *priv = netdev_priv(dev);
3004 int ret = 0;
3005
3006 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3007
3008 bcmgenet_netif_stop(dev);
3009
3010 /* Really kill the PHY state machine and disconnect from it */
3011 phy_disconnect(dev->phydev);
3012
3013 free_irq(priv->irq0, priv);
3014 free_irq(priv->irq1, priv);
3015
3016 if (priv->internal_phy)
3017 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3018
3019 clk_disable_unprepare(priv->clk);
3020
3021 return ret;
3022 }
3023
3024 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3025 {
3026 struct bcmgenet_priv *priv = ring->priv;
3027 u32 p_index, c_index, intsts, intmsk;
3028 struct netdev_queue *txq;
3029 unsigned int free_bds;
3030 bool txq_stopped;
3031
3032 if (!netif_msg_tx_err(priv))
3033 return;
3034
3035 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3036
3037 spin_lock(&ring->lock);
3038 if (ring->index == DESC_INDEX) {
3039 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3040 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3041 } else {
3042 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3043 intmsk = 1 << ring->index;
3044 }
3045 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3046 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3047 txq_stopped = netif_tx_queue_stopped(txq);
3048 free_bds = ring->free_bds;
3049 spin_unlock(&ring->lock);
3050
3051 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3052 "TX queue status: %s, interrupts: %s\n"
3053 "(sw)free_bds: %d (sw)size: %d\n"
3054 "(sw)p_index: %d (hw)p_index: %d\n"
3055 "(sw)c_index: %d (hw)c_index: %d\n"
3056 "(sw)clean_p: %d (sw)write_p: %d\n"
3057 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3058 ring->index, ring->queue,
3059 txq_stopped ? "stopped" : "active",
3060 intsts & intmsk ? "enabled" : "disabled",
3061 free_bds, ring->size,
3062 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3063 ring->c_index, c_index & DMA_C_INDEX_MASK,
3064 ring->clean_ptr, ring->write_ptr,
3065 ring->cb_ptr, ring->end_ptr);
3066 }
3067
3068 static void bcmgenet_timeout(struct net_device *dev)
3069 {
3070 struct bcmgenet_priv *priv = netdev_priv(dev);
3071 u32 int0_enable = 0;
3072 u32 int1_enable = 0;
3073 unsigned int q;
3074
3075 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3076
3077 for (q = 0; q < priv->hw_params->tx_queues; q++)
3078 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3079 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3080
3081 bcmgenet_tx_reclaim_all(dev);
3082
3083 for (q = 0; q < priv->hw_params->tx_queues; q++)
3084 int1_enable |= (1 << q);
3085
3086 int0_enable = UMAC_IRQ_TXDMA_DONE;
3087
3088 /* Re-enable TX interrupts if disabled */
3089 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3090 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3091
3092 netif_trans_update(dev);
3093
3094 dev->stats.tx_errors++;
3095
3096 netif_tx_wake_all_queues(dev);
3097 }
3098
3099 #define MAX_MDF_FILTER 17
3100
3101 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3102 unsigned char *addr,
3103 int *i)
3104 {
3105 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3106 UMAC_MDF_ADDR + (*i * 4));
3107 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3108 addr[4] << 8 | addr[5],
3109 UMAC_MDF_ADDR + ((*i + 1) * 4));
3110 *i += 2;
3111 }
3112
3113 static void bcmgenet_set_rx_mode(struct net_device *dev)
3114 {
3115 struct bcmgenet_priv *priv = netdev_priv(dev);
3116 struct netdev_hw_addr *ha;
3117 int i, nfilter;
3118 u32 reg;
3119
3120 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3121
3122 /* Number of filters needed */
3123 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3124
3125 /*
3126 * Turn on promicuous mode for three scenarios
3127 * 1. IFF_PROMISC flag is set
3128 * 2. IFF_ALLMULTI flag is set
3129 * 3. The number of filters needed exceeds the number filters
3130 * supported by the hardware.
3131 */
3132 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3133 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3134 (nfilter > MAX_MDF_FILTER)) {
3135 reg |= CMD_PROMISC;
3136 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3137 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3138 return;
3139 } else {
3140 reg &= ~CMD_PROMISC;
3141 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3142 }
3143
3144 /* update MDF filter */
3145 i = 0;
3146 /* Broadcast */
3147 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3148 /* my own address.*/
3149 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3150
3151 /* Unicast */
3152 netdev_for_each_uc_addr(ha, dev)
3153 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3154
3155 /* Multicast */
3156 netdev_for_each_mc_addr(ha, dev)
3157 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3158
3159 /* Enable filters */
3160 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3161 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3162 }
3163
3164 /* Set the hardware MAC address. */
3165 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3166 {
3167 struct sockaddr *addr = p;
3168
3169 /* Setting the MAC address at the hardware level is not possible
3170 * without disabling the UniMAC RX/TX enable bits.
3171 */
3172 if (netif_running(dev))
3173 return -EBUSY;
3174
3175 ether_addr_copy(dev->dev_addr, addr->sa_data);
3176
3177 return 0;
3178 }
3179
3180 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3181 {
3182 struct bcmgenet_priv *priv = netdev_priv(dev);
3183 unsigned long tx_bytes = 0, tx_packets = 0;
3184 unsigned long rx_bytes = 0, rx_packets = 0;
3185 unsigned long rx_errors = 0, rx_dropped = 0;
3186 struct bcmgenet_tx_ring *tx_ring;
3187 struct bcmgenet_rx_ring *rx_ring;
3188 unsigned int q;
3189
3190 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3191 tx_ring = &priv->tx_rings[q];
3192 tx_bytes += tx_ring->bytes;
3193 tx_packets += tx_ring->packets;
3194 }
3195 tx_ring = &priv->tx_rings[DESC_INDEX];
3196 tx_bytes += tx_ring->bytes;
3197 tx_packets += tx_ring->packets;
3198
3199 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3200 rx_ring = &priv->rx_rings[q];
3201
3202 rx_bytes += rx_ring->bytes;
3203 rx_packets += rx_ring->packets;
3204 rx_errors += rx_ring->errors;
3205 rx_dropped += rx_ring->dropped;
3206 }
3207 rx_ring = &priv->rx_rings[DESC_INDEX];
3208 rx_bytes += rx_ring->bytes;
3209 rx_packets += rx_ring->packets;
3210 rx_errors += rx_ring->errors;
3211 rx_dropped += rx_ring->dropped;
3212
3213 dev->stats.tx_bytes = tx_bytes;
3214 dev->stats.tx_packets = tx_packets;
3215 dev->stats.rx_bytes = rx_bytes;
3216 dev->stats.rx_packets = rx_packets;
3217 dev->stats.rx_errors = rx_errors;
3218 dev->stats.rx_missed_errors = rx_errors;
3219 dev->stats.rx_dropped = rx_dropped;
3220 return &dev->stats;
3221 }
3222
3223 static const struct net_device_ops bcmgenet_netdev_ops = {
3224 .ndo_open = bcmgenet_open,
3225 .ndo_stop = bcmgenet_close,
3226 .ndo_start_xmit = bcmgenet_xmit,
3227 .ndo_tx_timeout = bcmgenet_timeout,
3228 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3229 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3230 .ndo_do_ioctl = bcmgenet_ioctl,
3231 .ndo_set_features = bcmgenet_set_features,
3232 #ifdef CONFIG_NET_POLL_CONTROLLER
3233 .ndo_poll_controller = bcmgenet_poll_controller,
3234 #endif
3235 .ndo_get_stats = bcmgenet_get_stats,
3236 };
3237
3238 /* Array of GENET hardware parameters/characteristics */
3239 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3240 [GENET_V1] = {
3241 .tx_queues = 0,
3242 .tx_bds_per_q = 0,
3243 .rx_queues = 0,
3244 .rx_bds_per_q = 0,
3245 .bp_in_en_shift = 16,
3246 .bp_in_mask = 0xffff,
3247 .hfb_filter_cnt = 16,
3248 .qtag_mask = 0x1F,
3249 .hfb_offset = 0x1000,
3250 .rdma_offset = 0x2000,
3251 .tdma_offset = 0x3000,
3252 .words_per_bd = 2,
3253 },
3254 [GENET_V2] = {
3255 .tx_queues = 4,
3256 .tx_bds_per_q = 32,
3257 .rx_queues = 0,
3258 .rx_bds_per_q = 0,
3259 .bp_in_en_shift = 16,
3260 .bp_in_mask = 0xffff,
3261 .hfb_filter_cnt = 16,
3262 .qtag_mask = 0x1F,
3263 .tbuf_offset = 0x0600,
3264 .hfb_offset = 0x1000,
3265 .hfb_reg_offset = 0x2000,
3266 .rdma_offset = 0x3000,
3267 .tdma_offset = 0x4000,
3268 .words_per_bd = 2,
3269 .flags = GENET_HAS_EXT,
3270 },
3271 [GENET_V3] = {
3272 .tx_queues = 4,
3273 .tx_bds_per_q = 32,
3274 .rx_queues = 0,
3275 .rx_bds_per_q = 0,
3276 .bp_in_en_shift = 17,
3277 .bp_in_mask = 0x1ffff,
3278 .hfb_filter_cnt = 48,
3279 .hfb_filter_size = 128,
3280 .qtag_mask = 0x3F,
3281 .tbuf_offset = 0x0600,
3282 .hfb_offset = 0x8000,
3283 .hfb_reg_offset = 0xfc00,
3284 .rdma_offset = 0x10000,
3285 .tdma_offset = 0x11000,
3286 .words_per_bd = 2,
3287 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3288 GENET_HAS_MOCA_LINK_DET,
3289 },
3290 [GENET_V4] = {
3291 .tx_queues = 4,
3292 .tx_bds_per_q = 32,
3293 .rx_queues = 0,
3294 .rx_bds_per_q = 0,
3295 .bp_in_en_shift = 17,
3296 .bp_in_mask = 0x1ffff,
3297 .hfb_filter_cnt = 48,
3298 .hfb_filter_size = 128,
3299 .qtag_mask = 0x3F,
3300 .tbuf_offset = 0x0600,
3301 .hfb_offset = 0x8000,
3302 .hfb_reg_offset = 0xfc00,
3303 .rdma_offset = 0x2000,
3304 .tdma_offset = 0x4000,
3305 .words_per_bd = 3,
3306 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3307 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3308 },
3309 [GENET_V5] = {
3310 .tx_queues = 4,
3311 .tx_bds_per_q = 32,
3312 .rx_queues = 0,
3313 .rx_bds_per_q = 0,
3314 .bp_in_en_shift = 17,
3315 .bp_in_mask = 0x1ffff,
3316 .hfb_filter_cnt = 48,
3317 .hfb_filter_size = 128,
3318 .qtag_mask = 0x3F,
3319 .tbuf_offset = 0x0600,
3320 .hfb_offset = 0x8000,
3321 .hfb_reg_offset = 0xfc00,
3322 .rdma_offset = 0x2000,
3323 .tdma_offset = 0x4000,
3324 .words_per_bd = 3,
3325 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3326 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3327 },
3328 };
3329
3330 /* Infer hardware parameters from the detected GENET version */
3331 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3332 {
3333 struct bcmgenet_hw_params *params;
3334 u32 reg;
3335 u8 major;
3336 u16 gphy_rev;
3337
3338 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3339 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3340 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3341 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3342 } else if (GENET_IS_V3(priv)) {
3343 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3344 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3345 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3346 } else if (GENET_IS_V2(priv)) {
3347 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3348 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3349 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3350 } else if (GENET_IS_V1(priv)) {
3351 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3352 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3353 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3354 }
3355
3356 /* enum genet_version starts at 1 */
3357 priv->hw_params = &bcmgenet_hw_params[priv->version];
3358 params = priv->hw_params;
3359
3360 /* Read GENET HW version */
3361 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3362 major = (reg >> 24 & 0x0f);
3363 if (major == 6)
3364 major = 5;
3365 else if (major == 5)
3366 major = 4;
3367 else if (major == 0)
3368 major = 1;
3369 if (major != priv->version) {
3370 dev_err(&priv->pdev->dev,
3371 "GENET version mismatch, got: %d, configured for: %d\n",
3372 major, priv->version);
3373 }
3374
3375 /* Print the GENET core version */
3376 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3377 major, (reg >> 16) & 0x0f, reg & 0xffff);
3378
3379 /* Store the integrated PHY revision for the MDIO probing function
3380 * to pass this information to the PHY driver. The PHY driver expects
3381 * to find the PHY major revision in bits 15:8 while the GENET register
3382 * stores that information in bits 7:0, account for that.
3383 *
3384 * On newer chips, starting with PHY revision G0, a new scheme is
3385 * deployed similar to the Starfighter 2 switch with GPHY major
3386 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3387 * is reserved as well as special value 0x01ff, we have a small
3388 * heuristic to check for the new GPHY revision and re-arrange things
3389 * so the GPHY driver is happy.
3390 */
3391 gphy_rev = reg & 0xffff;
3392
3393 if (GENET_IS_V5(priv)) {
3394 /* The EPHY revision should come from the MDIO registers of
3395 * the PHY not from GENET.
3396 */
3397 if (gphy_rev != 0) {
3398 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3399 gphy_rev);
3400 }
3401 /* This is reserved so should require special treatment */
3402 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3403 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3404 return;
3405 /* This is the good old scheme, just GPHY major, no minor nor patch */
3406 } else if ((gphy_rev & 0xf0) != 0) {
3407 priv->gphy_rev = gphy_rev << 8;
3408 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3409 } else if ((gphy_rev & 0xff00) != 0) {
3410 priv->gphy_rev = gphy_rev;
3411 }
3412
3413 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3414 if (!(params->flags & GENET_HAS_40BITS))
3415 pr_warn("GENET does not support 40-bits PA\n");
3416 #endif
3417
3418 pr_debug("Configuration for version: %d\n"
3419 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3420 "BP << en: %2d, BP msk: 0x%05x\n"
3421 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3422 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3423 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3424 "Words/BD: %d\n",
3425 priv->version,
3426 params->tx_queues, params->tx_bds_per_q,
3427 params->rx_queues, params->rx_bds_per_q,
3428 params->bp_in_en_shift, params->bp_in_mask,
3429 params->hfb_filter_cnt, params->qtag_mask,
3430 params->tbuf_offset, params->hfb_offset,
3431 params->hfb_reg_offset,
3432 params->rdma_offset, params->tdma_offset,
3433 params->words_per_bd);
3434 }
3435
3436 static const struct of_device_id bcmgenet_match[] = {
3437 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3438 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3439 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3440 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3441 { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3442 { },
3443 };
3444 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3445
3446 static int bcmgenet_probe(struct platform_device *pdev)
3447 {
3448 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3449 struct device_node *dn = pdev->dev.of_node;
3450 const struct of_device_id *of_id = NULL;
3451 struct bcmgenet_priv *priv;
3452 struct net_device *dev;
3453 const void *macaddr;
3454 struct resource *r;
3455 unsigned int i;
3456 int err = -EIO;
3457 const char *phy_mode_str;
3458
3459 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3460 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3461 GENET_MAX_MQ_CNT + 1);
3462 if (!dev) {
3463 dev_err(&pdev->dev, "can't allocate net device\n");
3464 return -ENOMEM;
3465 }
3466
3467 if (dn) {
3468 of_id = of_match_node(bcmgenet_match, dn);
3469 if (!of_id)
3470 return -EINVAL;
3471 }
3472
3473 priv = netdev_priv(dev);
3474 priv->irq0 = platform_get_irq(pdev, 0);
3475 priv->irq1 = platform_get_irq(pdev, 1);
3476 priv->wol_irq = platform_get_irq(pdev, 2);
3477 if (!priv->irq0 || !priv->irq1) {
3478 dev_err(&pdev->dev, "can't find IRQs\n");
3479 err = -EINVAL;
3480 goto err;
3481 }
3482
3483 if (dn) {
3484 macaddr = of_get_mac_address(dn);
3485 if (!macaddr) {
3486 dev_err(&pdev->dev, "can't find MAC address\n");
3487 err = -EINVAL;
3488 goto err;
3489 }
3490 } else {
3491 macaddr = pd->mac_address;
3492 }
3493
3494 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3495 priv->base = devm_ioremap_resource(&pdev->dev, r);
3496 if (IS_ERR(priv->base)) {
3497 err = PTR_ERR(priv->base);
3498 goto err;
3499 }
3500
3501 spin_lock_init(&priv->lock);
3502
3503 SET_NETDEV_DEV(dev, &pdev->dev);
3504 dev_set_drvdata(&pdev->dev, dev);
3505 ether_addr_copy(dev->dev_addr, macaddr);
3506 dev->watchdog_timeo = 2 * HZ;
3507 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3508 dev->netdev_ops = &bcmgenet_netdev_ops;
3509
3510 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3511
3512 /* Set hardware features */
3513 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3514 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3515
3516 /* Request the WOL interrupt and advertise suspend if available */
3517 priv->wol_irq_disabled = true;
3518 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3519 dev->name, priv);
3520 if (!err)
3521 device_set_wakeup_capable(&pdev->dev, 1);
3522
3523 /* Set the needed headroom to account for any possible
3524 * features enabling/disabling at runtime
3525 */
3526 dev->needed_headroom += 64;
3527
3528 netdev_boot_setup_check(dev);
3529
3530 priv->dev = dev;
3531 priv->pdev = pdev;
3532 if (of_id)
3533 priv->version = (enum bcmgenet_version)of_id->data;
3534 else
3535 priv->version = pd->genet_version;
3536
3537 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3538 if (IS_ERR(priv->clk)) {
3539 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3540 priv->clk = NULL;
3541 }
3542
3543 clk_prepare_enable(priv->clk);
3544
3545 bcmgenet_set_hw_params(priv);
3546
3547 /* Mii wait queue */
3548 init_waitqueue_head(&priv->wq);
3549 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3550 priv->rx_buf_len = RX_BUF_LENGTH;
3551 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3552
3553 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3554 if (IS_ERR(priv->clk_wol)) {
3555 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3556 priv->clk_wol = NULL;
3557 }
3558
3559 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3560 if (IS_ERR(priv->clk_eee)) {
3561 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3562 priv->clk_eee = NULL;
3563 }
3564
3565 /* If this is an internal GPHY, power it on now, before UniMAC is
3566 * brought out of reset as absolutely no UniMAC activity is allowed
3567 */
3568 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3569 !strcasecmp(phy_mode_str, "internal"))
3570 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3571
3572 reset_umac(priv);
3573
3574 err = bcmgenet_mii_init(dev);
3575 if (err)
3576 goto err_clk_disable;
3577
3578 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3579 * just the ring 16 descriptor based TX
3580 */
3581 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3582 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3583
3584 /* Set default coalescing parameters */
3585 for (i = 0; i < priv->hw_params->rx_queues; i++)
3586 priv->rx_rings[i].rx_max_coalesced_frames = 1;
3587 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
3588
3589 /* libphy will determine the link state */
3590 netif_carrier_off(dev);
3591
3592 /* Turn off the main clock, WOL clock is handled separately */
3593 clk_disable_unprepare(priv->clk);
3594
3595 err = register_netdev(dev);
3596 if (err)
3597 goto err;
3598
3599 return err;
3600
3601 err_clk_disable:
3602 clk_disable_unprepare(priv->clk);
3603 err:
3604 free_netdev(dev);
3605 return err;
3606 }
3607
3608 static int bcmgenet_remove(struct platform_device *pdev)
3609 {
3610 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3611
3612 dev_set_drvdata(&pdev->dev, NULL);
3613 unregister_netdev(priv->dev);
3614 bcmgenet_mii_exit(priv->dev);
3615 free_netdev(priv->dev);
3616
3617 return 0;
3618 }
3619
3620 #ifdef CONFIG_PM_SLEEP
3621 static int bcmgenet_resume(struct device *d)
3622 {
3623 struct net_device *dev = dev_get_drvdata(d);
3624 struct bcmgenet_priv *priv = netdev_priv(dev);
3625 unsigned long dma_ctrl;
3626 int ret;
3627 u32 reg;
3628
3629 if (!netif_running(dev))
3630 return 0;
3631
3632 /* Turn on the clock */
3633 ret = clk_prepare_enable(priv->clk);
3634 if (ret)
3635 return ret;
3636
3637 /* If this is an internal GPHY, power it back on now, before UniMAC is
3638 * brought out of reset as absolutely no UniMAC activity is allowed
3639 */
3640 if (priv->internal_phy)
3641 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3642
3643 bcmgenet_umac_reset(priv);
3644
3645 init_umac(priv);
3646
3647 /* From WOL-enabled suspend, switch to regular clock */
3648 if (priv->wolopts)
3649 clk_disable_unprepare(priv->clk_wol);
3650
3651 phy_init_hw(dev->phydev);
3652
3653 /* Speed settings must be restored */
3654 genphy_config_aneg(dev->phydev);
3655 bcmgenet_mii_config(priv->dev, false);
3656
3657 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3658
3659 if (priv->internal_phy) {
3660 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3661 reg |= EXT_ENERGY_DET_MASK;
3662 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3663 }
3664
3665 if (priv->wolopts)
3666 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3667
3668 /* Disable RX/TX DMA and flush TX queues */
3669 dma_ctrl = bcmgenet_dma_disable(priv);
3670
3671 /* Reinitialize TDMA and RDMA and SW housekeeping */
3672 ret = bcmgenet_init_dma(priv);
3673 if (ret) {
3674 netdev_err(dev, "failed to initialize DMA\n");
3675 goto out_clk_disable;
3676 }
3677
3678 /* Always enable ring 16 - descriptor ring */
3679 bcmgenet_enable_dma(priv, dma_ctrl);
3680
3681 if (!device_may_wakeup(d))
3682 phy_resume(dev->phydev);
3683
3684 if (priv->eee.eee_enabled)
3685 bcmgenet_eee_enable_set(dev, true);
3686
3687 bcmgenet_netif_start(dev);
3688
3689 netif_device_attach(dev);
3690
3691 return 0;
3692
3693 out_clk_disable:
3694 if (priv->internal_phy)
3695 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3696 clk_disable_unprepare(priv->clk);
3697 return ret;
3698 }
3699
3700 static int bcmgenet_suspend(struct device *d)
3701 {
3702 struct net_device *dev = dev_get_drvdata(d);
3703 struct bcmgenet_priv *priv = netdev_priv(dev);
3704 int ret = 0;
3705
3706 if (!netif_running(dev))
3707 return 0;
3708
3709 netif_device_detach(dev);
3710
3711 bcmgenet_netif_stop(dev);
3712
3713 if (!device_may_wakeup(d))
3714 phy_suspend(dev->phydev);
3715
3716 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3717 if (device_may_wakeup(d) && priv->wolopts) {
3718 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3719 clk_prepare_enable(priv->clk_wol);
3720 } else if (priv->internal_phy) {
3721 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3722 }
3723
3724 /* Turn off the clocks */
3725 clk_disable_unprepare(priv->clk);
3726
3727 if (ret)
3728 bcmgenet_resume(d);
3729
3730 return ret;
3731 }
3732 #endif /* CONFIG_PM_SLEEP */
3733
3734 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3735
3736 static struct platform_driver bcmgenet_driver = {
3737 .probe = bcmgenet_probe,
3738 .remove = bcmgenet_remove,
3739 .driver = {
3740 .name = "bcmgenet",
3741 .of_match_table = bcmgenet_match,
3742 .pm = &bcmgenet_pm_ops,
3743 },
3744 };
3745 module_platform_driver(bcmgenet_driver);
3746
3747 MODULE_AUTHOR("Broadcom Corporation");
3748 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3749 MODULE_ALIAS("platform:bcmgenet");
3750 MODULE_LICENSE("GPL");
Linux with added FPC-III support