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Linux 4.19.133
[linux/fpc-iii.git] / drivers / net / ethernet / cavium / thunder / thunder_bgx.c
blobe5fc89813852c800d73c5d6d8cc24f7602f2a2a2
1 /*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/phy.h>
16 #include <linux/of.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19
20 #include "nic_reg.h"
21 #include "nic.h"
22 #include "thunder_bgx.h"
23
24 #define DRV_NAME "thunder_bgx"
25 #define DRV_VERSION "1.0"
26
27 /* RX_DMAC_CTL configuration */
28 enum MCAST_MODE {
29 MCAST_MODE_REJECT = 0x0,
30 MCAST_MODE_ACCEPT = 0x1,
31 MCAST_MODE_CAM_FILTER = 0x2,
32 RSVD = 0x3
33 };
34
35 #define BCAST_ACCEPT BIT(0)
36 #define CAM_ACCEPT BIT(3)
37 #define MCAST_MODE_MASK 0x3
38 #define BGX_MCAST_MODE(x) (x << 1)
39
40 struct dmac_map {
41 u64 vf_map;
42 u64 dmac;
43 };
44
45 struct lmac {
46 struct bgx *bgx;
47 /* actual number of DMACs configured */
48 u8 dmacs_cfg;
49 /* overal number of possible DMACs could be configured per LMAC */
50 u8 dmacs_count;
51 struct dmac_map *dmacs; /* DMAC:VFs tracking filter array */
52 u8 mac[ETH_ALEN];
53 u8 lmac_type;
54 u8 lane_to_sds;
55 bool use_training;
56 bool autoneg;
57 bool link_up;
58 int lmacid; /* ID within BGX */
59 int lmacid_bd; /* ID on board */
60 struct net_device netdev;
61 struct phy_device *phydev;
62 unsigned int last_duplex;
63 unsigned int last_link;
64 unsigned int last_speed;
65 bool is_sgmii;
66 struct delayed_work dwork;
67 struct workqueue_struct *check_link;
68 };
69
70 struct bgx {
71 u8 bgx_id;
72 struct lmac lmac[MAX_LMAC_PER_BGX];
73 u8 lmac_count;
74 u8 max_lmac;
75 u8 acpi_lmac_idx;
76 void __iomem *reg_base;
77 struct pci_dev *pdev;
78 bool is_dlm;
79 bool is_rgx;
80 };
81
82 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
83 static int lmac_count; /* Total no of LMACs in system */
84
85 static int bgx_xaui_check_link(struct lmac *lmac);
86
87 /* Supported devices */
88 static const struct pci_device_id bgx_id_table[] = {
89 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
90 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
91 { 0, } /* end of table */
92 };
93
94 MODULE_AUTHOR("Cavium Inc");
95 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
96 MODULE_LICENSE("GPL v2");
97 MODULE_VERSION(DRV_VERSION);
98 MODULE_DEVICE_TABLE(pci, bgx_id_table);
99
100 /* The Cavium ThunderX network controller can *only* be found in SoCs
101 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
102 * registers on this platform are implicitly strongly ordered with respect
103 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
104 * with no memory barriers in this driver. The readq()/writeq() functions add
105 * explicit ordering operation which in this case are redundant, and only
106 * add overhead.
107 */
108
109 /* Register read/write APIs */
110 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
111 {
112 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
113
114 return readq_relaxed(addr);
115 }
116
117 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
118 {
119 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
120
121 writeq_relaxed(val, addr);
122 }
123
124 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
125 {
126 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
127
128 writeq_relaxed(val | readq_relaxed(addr), addr);
129 }
130
131 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
132 {
133 int timeout = 100;
134 u64 reg_val;
135
136 while (timeout) {
137 reg_val = bgx_reg_read(bgx, lmac, reg);
138 if (zero && !(reg_val & mask))
139 return 0;
140 if (!zero && (reg_val & mask))
141 return 0;
142 usleep_range(1000, 2000);
143 timeout--;
144 }
145 return 1;
146 }
147
148 static int max_bgx_per_node;
149 static void set_max_bgx_per_node(struct pci_dev *pdev)
150 {
151 u16 sdevid;
152
153 if (max_bgx_per_node)
154 return;
155
156 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
157 switch (sdevid) {
158 case PCI_SUBSYS_DEVID_81XX_BGX:
159 case PCI_SUBSYS_DEVID_81XX_RGX:
160 max_bgx_per_node = MAX_BGX_PER_CN81XX;
161 break;
162 case PCI_SUBSYS_DEVID_83XX_BGX:
163 max_bgx_per_node = MAX_BGX_PER_CN83XX;
164 break;
165 case PCI_SUBSYS_DEVID_88XX_BGX:
166 default:
167 max_bgx_per_node = MAX_BGX_PER_CN88XX;
168 break;
169 }
170 }
171
172 static struct bgx *get_bgx(int node, int bgx_idx)
173 {
174 int idx = (node * max_bgx_per_node) + bgx_idx;
175
176 return bgx_vnic[idx];
177 }
178
179 /* Return number of BGX present in HW */
180 unsigned bgx_get_map(int node)
181 {
182 int i;
183 unsigned map = 0;
184
185 for (i = 0; i < max_bgx_per_node; i++) {
186 if (bgx_vnic[(node * max_bgx_per_node) + i])
187 map |= (1 << i);
188 }
189
190 return map;
191 }
192 EXPORT_SYMBOL(bgx_get_map);
193
194 /* Return number of LMAC configured for this BGX */
195 int bgx_get_lmac_count(int node, int bgx_idx)
196 {
197 struct bgx *bgx;
198
199 bgx = get_bgx(node, bgx_idx);
200 if (bgx)
201 return bgx->lmac_count;
202
203 return 0;
204 }
205 EXPORT_SYMBOL(bgx_get_lmac_count);
206
207 /* Returns the current link status of LMAC */
208 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
209 {
210 struct bgx_link_status *link = (struct bgx_link_status *)status;
211 struct bgx *bgx;
212 struct lmac *lmac;
213
214 bgx = get_bgx(node, bgx_idx);
215 if (!bgx)
216 return;
217
218 lmac = &bgx->lmac[lmacid];
219 link->mac_type = lmac->lmac_type;
220 link->link_up = lmac->link_up;
221 link->duplex = lmac->last_duplex;
222 link->speed = lmac->last_speed;
223 }
224 EXPORT_SYMBOL(bgx_get_lmac_link_state);
225
226 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
227 {
228 struct bgx *bgx = get_bgx(node, bgx_idx);
229
230 if (bgx)
231 return bgx->lmac[lmacid].mac;
232
233 return NULL;
234 }
235 EXPORT_SYMBOL(bgx_get_lmac_mac);
236
237 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
238 {
239 struct bgx *bgx = get_bgx(node, bgx_idx);
240
241 if (!bgx)
242 return;
243
244 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
245 }
246 EXPORT_SYMBOL(bgx_set_lmac_mac);
247
248 static void bgx_flush_dmac_cam_filter(struct bgx *bgx, int lmacid)
249 {
250 struct lmac *lmac = NULL;
251 u8 idx = 0;
252
253 lmac = &bgx->lmac[lmacid];
254 /* reset CAM filters */
255 for (idx = 0; idx < lmac->dmacs_count; idx++)
256 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM +
257 ((lmacid * lmac->dmacs_count) + idx) *
258 sizeof(u64), 0);
259 }
260
261 static void bgx_lmac_remove_filters(struct lmac *lmac, u8 vf_id)
262 {
263 int i = 0;
264
265 if (!lmac)
266 return;
267
268 /* We've got reset filters request from some of attached VF, while the
269 * others might want to keep their configuration. So in this case lets
270 * iterate over all of configured filters and decrease number of
271 * referencies. if some addresses get zero refs remove them from list
272 */
273 for (i = lmac->dmacs_cfg - 1; i >= 0; i--) {
274 lmac->dmacs[i].vf_map &= ~BIT_ULL(vf_id);
275 if (!lmac->dmacs[i].vf_map) {
276 lmac->dmacs_cfg--;
277 lmac->dmacs[i].dmac = 0;
278 lmac->dmacs[i].vf_map = 0;
279 }
280 }
281 }
282
283 static int bgx_lmac_save_filter(struct lmac *lmac, u64 dmac, u8 vf_id)
284 {
285 u8 i = 0;
286
287 if (!lmac)
288 return -1;
289
290 /* At the same time we could have several VFs 'attached' to some
291 * particular LMAC, and each VF is represented as network interface
292 * for kernel. So from user perspective it should be possible to
293 * manipulate with its' (VF) receive modes. However from PF
294 * driver perspective we need to keep track of filter configurations
295 * for different VFs to prevent filter values dupes
296 */
297 for (i = 0; i < lmac->dmacs_cfg; i++) {
298 if (lmac->dmacs[i].dmac == dmac) {
299 lmac->dmacs[i].vf_map |= BIT_ULL(vf_id);
300 return -1;
301 }
302 }
303
304 if (!(lmac->dmacs_cfg < lmac->dmacs_count))
305 return -1;
306
307 /* keep it for further tracking */
308 lmac->dmacs[lmac->dmacs_cfg].dmac = dmac;
309 lmac->dmacs[lmac->dmacs_cfg].vf_map = BIT_ULL(vf_id);
310 lmac->dmacs_cfg++;
311 return 0;
312 }
313
314 static int bgx_set_dmac_cam_filter_mac(struct bgx *bgx, int lmacid,
315 u64 cam_dmac, u8 idx)
316 {
317 struct lmac *lmac = NULL;
318 u64 cfg = 0;
319
320 /* skip zero addresses as meaningless */
321 if (!cam_dmac || !bgx)
322 return -1;
323
324 lmac = &bgx->lmac[lmacid];
325
326 /* configure DCAM filtering for designated LMAC */
327 cfg = RX_DMACX_CAM_LMACID(lmacid & LMAC_ID_MASK) |
328 RX_DMACX_CAM_EN | cam_dmac;
329 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM +
330 ((lmacid * lmac->dmacs_count) + idx) * sizeof(u64), cfg);
331 return 0;
332 }
333
334 void bgx_set_dmac_cam_filter(int node, int bgx_idx, int lmacid,
335 u64 cam_dmac, u8 vf_id)
336 {
337 struct bgx *bgx = get_bgx(node, bgx_idx);
338 struct lmac *lmac = NULL;
339
340 if (!bgx)
341 return;
342
343 lmac = &bgx->lmac[lmacid];
344
345 if (!cam_dmac)
346 cam_dmac = ether_addr_to_u64(lmac->mac);
347
348 /* since we might have several VFs attached to particular LMAC
349 * and kernel could call mcast config for each of them with the
350 * same MAC, check if requested MAC is already in filtering list and
351 * updare/prepare list of MACs to be applied later to HW filters
352 */
353 bgx_lmac_save_filter(lmac, cam_dmac, vf_id);
354 }
355 EXPORT_SYMBOL(bgx_set_dmac_cam_filter);
356
357 void bgx_set_xcast_mode(int node, int bgx_idx, int lmacid, u8 mode)
358 {
359 struct bgx *bgx = get_bgx(node, bgx_idx);
360 struct lmac *lmac = NULL;
361 u64 cfg = 0;
362 u8 i = 0;
363
364 if (!bgx)
365 return;
366
367 lmac = &bgx->lmac[lmacid];
368
369 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL);
370 if (mode & BGX_XCAST_BCAST_ACCEPT)
371 cfg |= BCAST_ACCEPT;
372 else
373 cfg &= ~BCAST_ACCEPT;
374
375 /* disable all MCASTs and DMAC filtering */
376 cfg &= ~(CAM_ACCEPT | BGX_MCAST_MODE(MCAST_MODE_MASK));
377
378 /* check requested bits and set filtergin mode appropriately */
379 if (mode & (BGX_XCAST_MCAST_ACCEPT)) {
380 cfg |= (BGX_MCAST_MODE(MCAST_MODE_ACCEPT));
381 } else if (mode & BGX_XCAST_MCAST_FILTER) {
382 cfg |= (BGX_MCAST_MODE(MCAST_MODE_CAM_FILTER) | CAM_ACCEPT);
383 for (i = 0; i < lmac->dmacs_cfg; i++)
384 bgx_set_dmac_cam_filter_mac(bgx, lmacid,
385 lmac->dmacs[i].dmac, i);
386 }
387 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, cfg);
388 }
389 EXPORT_SYMBOL(bgx_set_xcast_mode);
390
391 void bgx_reset_xcast_mode(int node, int bgx_idx, int lmacid, u8 vf_id)
392 {
393 struct bgx *bgx = get_bgx(node, bgx_idx);
394
395 if (!bgx)
396 return;
397
398 bgx_lmac_remove_filters(&bgx->lmac[lmacid], vf_id);
399 bgx_flush_dmac_cam_filter(bgx, lmacid);
400 bgx_set_xcast_mode(node, bgx_idx, lmacid,
401 (BGX_XCAST_BCAST_ACCEPT | BGX_XCAST_MCAST_ACCEPT));
402 }
403 EXPORT_SYMBOL(bgx_reset_xcast_mode);
404
405 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
406 {
407 struct bgx *bgx = get_bgx(node, bgx_idx);
408 struct lmac *lmac;
409 u64 cfg;
410
411 if (!bgx)
412 return;
413 lmac = &bgx->lmac[lmacid];
414
415 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
416 if (enable) {
417 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
418
419 /* enable TX FIFO Underflow interrupt */
420 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1S,
421 GMI_TXX_INT_UNDFLW);
422 } else {
423 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
424
425 /* Disable TX FIFO Underflow interrupt */
426 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1C,
427 GMI_TXX_INT_UNDFLW);
428 }
429 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
430
431 if (bgx->is_rgx)
432 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
433 }
434 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
435
436 /* Enables or disables timestamp insertion by BGX for Rx packets */
437 void bgx_config_timestamping(int node, int bgx_idx, int lmacid, bool enable)
438 {
439 struct bgx *bgx = get_bgx(node, bgx_idx);
440 struct lmac *lmac;
441 u64 csr_offset, cfg;
442
443 if (!bgx)
444 return;
445
446 lmac = &bgx->lmac[lmacid];
447
448 if (lmac->lmac_type == BGX_MODE_SGMII ||
449 lmac->lmac_type == BGX_MODE_QSGMII ||
450 lmac->lmac_type == BGX_MODE_RGMII)
451 csr_offset = BGX_GMP_GMI_RXX_FRM_CTL;
452 else
453 csr_offset = BGX_SMUX_RX_FRM_CTL;
454
455 cfg = bgx_reg_read(bgx, lmacid, csr_offset);
456
457 if (enable)
458 cfg |= BGX_PKT_RX_PTP_EN;
459 else
460 cfg &= ~BGX_PKT_RX_PTP_EN;
461 bgx_reg_write(bgx, lmacid, csr_offset, cfg);
462 }
463 EXPORT_SYMBOL(bgx_config_timestamping);
464
465 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause)
466 {
467 struct pfc *pfc = (struct pfc *)pause;
468 struct bgx *bgx = get_bgx(node, bgx_idx);
469 struct lmac *lmac;
470 u64 cfg;
471
472 if (!bgx)
473 return;
474 lmac = &bgx->lmac[lmacid];
475 if (lmac->is_sgmii)
476 return;
477
478 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
479 pfc->fc_rx = cfg & RX_EN;
480 pfc->fc_tx = cfg & TX_EN;
481 pfc->autoneg = 0;
482 }
483 EXPORT_SYMBOL(bgx_lmac_get_pfc);
484
485 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause)
486 {
487 struct pfc *pfc = (struct pfc *)pause;
488 struct bgx *bgx = get_bgx(node, bgx_idx);
489 struct lmac *lmac;
490 u64 cfg;
491
492 if (!bgx)
493 return;
494 lmac = &bgx->lmac[lmacid];
495 if (lmac->is_sgmii)
496 return;
497
498 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
499 cfg &= ~(RX_EN | TX_EN);
500 cfg |= (pfc->fc_rx ? RX_EN : 0x00);
501 cfg |= (pfc->fc_tx ? TX_EN : 0x00);
502 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, cfg);
503 }
504 EXPORT_SYMBOL(bgx_lmac_set_pfc);
505
506 static void bgx_sgmii_change_link_state(struct lmac *lmac)
507 {
508 struct bgx *bgx = lmac->bgx;
509 u64 cmr_cfg;
510 u64 port_cfg = 0;
511 u64 misc_ctl = 0;
512 bool tx_en, rx_en;
513
514 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
515 tx_en = cmr_cfg & CMR_PKT_TX_EN;
516 rx_en = cmr_cfg & CMR_PKT_RX_EN;
517 cmr_cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
518 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
519
520 /* Wait for BGX RX to be idle */
521 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
522 GMI_PORT_CFG_RX_IDLE, false)) {
523 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI RX not idle\n",
524 bgx->bgx_id, lmac->lmacid);
525 return;
526 }
527
528 /* Wait for BGX TX to be idle */
529 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
530 GMI_PORT_CFG_TX_IDLE, false)) {
531 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI TX not idle\n",
532 bgx->bgx_id, lmac->lmacid);
533 return;
534 }
535
536 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
537 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
538
539 if (lmac->link_up) {
540 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
541 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
542 port_cfg |= (lmac->last_duplex << 2);
543 } else {
544 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
545 }
546
547 switch (lmac->last_speed) {
548 case 10:
549 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
550 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
551 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
552 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
553 misc_ctl |= 50; /* samp_pt */
554 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
555 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
556 break;
557 case 100:
558 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
559 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
560 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
561 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
562 misc_ctl |= 5; /* samp_pt */
563 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
564 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
565 break;
566 case 1000:
567 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
568 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
569 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
570 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
571 misc_ctl |= 1; /* samp_pt */
572 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
573 if (lmac->last_duplex)
574 bgx_reg_write(bgx, lmac->lmacid,
575 BGX_GMP_GMI_TXX_BURST, 0);
576 else
577 bgx_reg_write(bgx, lmac->lmacid,
578 BGX_GMP_GMI_TXX_BURST, 8192);
579 break;
580 default:
581 break;
582 }
583 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
584 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
585
586 /* Restore CMR config settings */
587 cmr_cfg |= (rx_en ? CMR_PKT_RX_EN : 0) | (tx_en ? CMR_PKT_TX_EN : 0);
588 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
589
590 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
591 xcv_setup_link(lmac->link_up, lmac->last_speed);
592 }
593
594 static void bgx_lmac_handler(struct net_device *netdev)
595 {
596 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
597 struct phy_device *phydev;
598 int link_changed = 0;
599
600 if (!lmac)
601 return;
602
603 phydev = lmac->phydev;
604
605 if (!phydev->link && lmac->last_link)
606 link_changed = -1;
607
608 if (phydev->link &&
609 (lmac->last_duplex != phydev->duplex ||
610 lmac->last_link != phydev->link ||
611 lmac->last_speed != phydev->speed)) {
612 link_changed = 1;
613 }
614
615 lmac->last_link = phydev->link;
616 lmac->last_speed = phydev->speed;
617 lmac->last_duplex = phydev->duplex;
618
619 if (!link_changed)
620 return;
621
622 if (link_changed > 0)
623 lmac->link_up = true;
624 else
625 lmac->link_up = false;
626
627 if (lmac->is_sgmii)
628 bgx_sgmii_change_link_state(lmac);
629 else
630 bgx_xaui_check_link(lmac);
631 }
632
633 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
634 {
635 struct bgx *bgx;
636
637 bgx = get_bgx(node, bgx_idx);
638 if (!bgx)
639 return 0;
640
641 if (idx > 8)
642 lmac = 0;
643 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
644 }
645 EXPORT_SYMBOL(bgx_get_rx_stats);
646
647 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
648 {
649 struct bgx *bgx;
650
651 bgx = get_bgx(node, bgx_idx);
652 if (!bgx)
653 return 0;
654
655 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
656 }
657 EXPORT_SYMBOL(bgx_get_tx_stats);
658
659 /* Configure BGX LMAC in internal loopback mode */
660 void bgx_lmac_internal_loopback(int node, int bgx_idx,
661 int lmac_idx, bool enable)
662 {
663 struct bgx *bgx;
664 struct lmac *lmac;
665 u64 cfg;
666
667 bgx = get_bgx(node, bgx_idx);
668 if (!bgx)
669 return;
670
671 lmac = &bgx->lmac[lmac_idx];
672 if (lmac->is_sgmii) {
673 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
674 if (enable)
675 cfg |= PCS_MRX_CTL_LOOPBACK1;
676 else
677 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
678 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
679 } else {
680 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
681 if (enable)
682 cfg |= SPU_CTL_LOOPBACK;
683 else
684 cfg &= ~SPU_CTL_LOOPBACK;
685 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
686 }
687 }
688 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
689
690 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
691 {
692 int lmacid = lmac->lmacid;
693 u64 cfg;
694
695 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
696 /* max packet size */
697 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
698
699 /* Disable frame alignment if using preamble */
700 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
701 if (cfg & 1)
702 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
703
704 /* Enable lmac */
705 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
706
707 /* PCS reset */
708 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
709 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
710 PCS_MRX_CTL_RESET, true)) {
711 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
712 return -1;
713 }
714
715 /* power down, reset autoneg, autoneg enable */
716 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
717 cfg &= ~PCS_MRX_CTL_PWR_DN;
718 cfg |= PCS_MRX_CTL_RST_AN;
719 if (lmac->phydev) {
720 cfg |= PCS_MRX_CTL_AN_EN;
721 } else {
722 /* In scenarios where PHY driver is not present or it's a
723 * non-standard PHY, FW sets AN_EN to inform Linux driver
724 * to do auto-neg and link polling or not.
725 */
726 if (cfg & PCS_MRX_CTL_AN_EN)
727 lmac->autoneg = true;
728 }
729 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
730
731 if (lmac->lmac_type == BGX_MODE_QSGMII) {
732 /* Disable disparity check for QSGMII */
733 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
734 cfg &= ~PCS_MISC_CTL_DISP_EN;
735 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
736 return 0;
737 }
738
739 if ((lmac->lmac_type == BGX_MODE_SGMII) && lmac->phydev) {
740 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
741 PCS_MRX_STATUS_AN_CPT, false)) {
742 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
743 return -1;
744 }
745 }
746
747 return 0;
748 }
749
750 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
751 {
752 u64 cfg;
753 int lmacid = lmac->lmacid;
754
755 /* Reset SPU */
756 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
757 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
758 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
759 return -1;
760 }
761
762 /* Disable LMAC */
763 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
764 cfg &= ~CMR_EN;
765 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
766
767 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
768 /* Set interleaved running disparity for RXAUI */
769 if (lmac->lmac_type == BGX_MODE_RXAUI)
770 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
771 SPU_MISC_CTL_INTLV_RDISP);
772
773 /* Clear receive packet disable */
774 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
775 cfg &= ~SPU_MISC_CTL_RX_DIS;
776 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
777
778 /* clear all interrupts */
779 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
780 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
781 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
782 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
783 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
784 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
785
786 if (lmac->use_training) {
787 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
788 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
789 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
790 /* training enable */
791 bgx_reg_modify(bgx, lmacid,
792 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
793 }
794
795 /* Append FCS to each packet */
796 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
797
798 /* Disable forward error correction */
799 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
800 cfg &= ~SPU_FEC_CTL_FEC_EN;
801 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
802
803 /* Disable autoneg */
804 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
805 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
806 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
807
808 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
809 if (lmac->lmac_type == BGX_MODE_10G_KR)
810 cfg |= (1 << 23);
811 else if (lmac->lmac_type == BGX_MODE_40G_KR)
812 cfg |= (1 << 24);
813 else
814 cfg &= ~((1 << 23) | (1 << 24));
815 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
816 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
817
818 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
819 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
820 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
821
822 /* Enable lmac */
823 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
824
825 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
826 cfg &= ~SPU_CTL_LOW_POWER;
827 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
828
829 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
830 cfg &= ~SMU_TX_CTL_UNI_EN;
831 cfg |= SMU_TX_CTL_DIC_EN;
832 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
833
834 /* Enable receive and transmission of pause frames */
835 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, ((0xffffULL << 32) |
836 BCK_EN | DRP_EN | TX_EN | RX_EN));
837 /* Configure pause time and interval */
838 bgx_reg_write(bgx, lmacid,
839 BGX_SMUX_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME);
840 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL);
841 cfg &= ~0xFFFFull;
842 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL,
843 cfg | (DEFAULT_PAUSE_TIME - 0x1000));
844 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_ZERO, 0x01);
845
846 /* take lmac_count into account */
847 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
848 /* max packet size */
849 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
850
851 return 0;
852 }
853
854 static int bgx_xaui_check_link(struct lmac *lmac)
855 {
856 struct bgx *bgx = lmac->bgx;
857 int lmacid = lmac->lmacid;
858 int lmac_type = lmac->lmac_type;
859 u64 cfg;
860
861 if (lmac->use_training) {
862 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
863 if (!(cfg & (1ull << 13))) {
864 cfg = (1ull << 13) | (1ull << 14);
865 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
866 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
867 cfg |= (1ull << 0);
868 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
869 return -1;
870 }
871 }
872
873 /* wait for PCS to come out of reset */
874 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
875 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
876 return -1;
877 }
878
879 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
880 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
881 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
882 SPU_BR_STATUS_BLK_LOCK, false)) {
883 dev_err(&bgx->pdev->dev,
884 "SPU_BR_STATUS_BLK_LOCK not completed\n");
885 return -1;
886 }
887 } else {
888 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
889 SPU_BX_STATUS_RX_ALIGN, false)) {
890 dev_err(&bgx->pdev->dev,
891 "SPU_BX_STATUS_RX_ALIGN not completed\n");
892 return -1;
893 }
894 }
895
896 /* Clear rcvflt bit (latching high) and read it back */
897 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
898 bgx_reg_modify(bgx, lmacid,
899 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
900 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
901 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
902 if (lmac->use_training) {
903 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
904 if (!(cfg & (1ull << 13))) {
905 cfg = (1ull << 13) | (1ull << 14);
906 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
907 cfg = bgx_reg_read(bgx, lmacid,
908 BGX_SPUX_BR_PMD_CRTL);
909 cfg |= (1ull << 0);
910 bgx_reg_write(bgx, lmacid,
911 BGX_SPUX_BR_PMD_CRTL, cfg);
912 return -1;
913 }
914 }
915 return -1;
916 }
917
918 /* Wait for BGX RX to be idle */
919 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
920 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
921 return -1;
922 }
923
924 /* Wait for BGX TX to be idle */
925 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
926 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
927 return -1;
928 }
929
930 /* Check for MAC RX faults */
931 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
932 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
933 cfg &= SMU_RX_CTL_STATUS;
934 if (!cfg)
935 return 0;
936
937 /* Rx local/remote fault seen.
938 * Do lmac reinit to see if condition recovers
939 */
940 bgx_lmac_xaui_init(bgx, lmac);
941
942 return -1;
943 }
944
945 static void bgx_poll_for_sgmii_link(struct lmac *lmac)
946 {
947 u64 pcs_link, an_result;
948 u8 speed;
949
950 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
951 BGX_GMP_PCS_MRX_STATUS);
952
953 /*Link state bit is sticky, read it again*/
954 if (!(pcs_link & PCS_MRX_STATUS_LINK))
955 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
956 BGX_GMP_PCS_MRX_STATUS);
957
958 if (bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_GMP_PCS_MRX_STATUS,
959 PCS_MRX_STATUS_AN_CPT, false)) {
960 lmac->link_up = false;
961 lmac->last_speed = SPEED_UNKNOWN;
962 lmac->last_duplex = DUPLEX_UNKNOWN;
963 goto next_poll;
964 }
965
966 lmac->link_up = ((pcs_link & PCS_MRX_STATUS_LINK) != 0) ? true : false;
967 an_result = bgx_reg_read(lmac->bgx, lmac->lmacid,
968 BGX_GMP_PCS_ANX_AN_RESULTS);
969
970 speed = (an_result >> 3) & 0x3;
971 lmac->last_duplex = (an_result >> 1) & 0x1;
972 switch (speed) {
973 case 0:
974 lmac->last_speed = 10;
975 break;
976 case 1:
977 lmac->last_speed = 100;
978 break;
979 case 2:
980 lmac->last_speed = 1000;
981 break;
982 default:
983 lmac->link_up = false;
984 lmac->last_speed = SPEED_UNKNOWN;
985 lmac->last_duplex = DUPLEX_UNKNOWN;
986 break;
987 }
988
989 next_poll:
990
991 if (lmac->last_link != lmac->link_up) {
992 if (lmac->link_up)
993 bgx_sgmii_change_link_state(lmac);
994 lmac->last_link = lmac->link_up;
995 }
996
997 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 3);
998 }
999
1000 static void bgx_poll_for_link(struct work_struct *work)
1001 {
1002 struct lmac *lmac;
1003 u64 spu_link, smu_link;
1004
1005 lmac = container_of(work, struct lmac, dwork.work);
1006 if (lmac->is_sgmii) {
1007 bgx_poll_for_sgmii_link(lmac);
1008 return;
1009 }
1010
1011 /* Receive link is latching low. Force it high and verify it */
1012 bgx_reg_modify(lmac->bgx, lmac->lmacid,
1013 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
1014 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
1015 SPU_STATUS1_RCV_LNK, false);
1016
1017 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
1018 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
1019
1020 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
1021 !(smu_link & SMU_RX_CTL_STATUS)) {
1022 lmac->link_up = 1;
1023 if (lmac->lmac_type == BGX_MODE_XLAUI)
1024 lmac->last_speed = 40000;
1025 else
1026 lmac->last_speed = 10000;
1027 lmac->last_duplex = 1;
1028 } else {
1029 lmac->link_up = 0;
1030 lmac->last_speed = SPEED_UNKNOWN;
1031 lmac->last_duplex = DUPLEX_UNKNOWN;
1032 }
1033
1034 if (lmac->last_link != lmac->link_up) {
1035 if (lmac->link_up) {
1036 if (bgx_xaui_check_link(lmac)) {
1037 /* Errors, clear link_up state */
1038 lmac->link_up = 0;
1039 lmac->last_speed = SPEED_UNKNOWN;
1040 lmac->last_duplex = DUPLEX_UNKNOWN;
1041 }
1042 }
1043 lmac->last_link = lmac->link_up;
1044 }
1045
1046 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
1047 }
1048
1049 static int phy_interface_mode(u8 lmac_type)
1050 {
1051 if (lmac_type == BGX_MODE_QSGMII)
1052 return PHY_INTERFACE_MODE_QSGMII;
1053 if (lmac_type == BGX_MODE_RGMII)
1054 return PHY_INTERFACE_MODE_RGMII;
1055
1056 return PHY_INTERFACE_MODE_SGMII;
1057 }
1058
1059 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
1060 {
1061 struct lmac *lmac;
1062 u64 cfg;
1063
1064 lmac = &bgx->lmac[lmacid];
1065 lmac->bgx = bgx;
1066
1067 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
1068 (lmac->lmac_type == BGX_MODE_QSGMII) ||
1069 (lmac->lmac_type == BGX_MODE_RGMII)) {
1070 lmac->is_sgmii = 1;
1071 if (bgx_lmac_sgmii_init(bgx, lmac))
1072 return -1;
1073 } else {
1074 lmac->is_sgmii = 0;
1075 if (bgx_lmac_xaui_init(bgx, lmac))
1076 return -1;
1077 }
1078
1079 if (lmac->is_sgmii) {
1080 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
1081 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
1082 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
1083 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
1084 } else {
1085 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
1086 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
1087 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
1088 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
1089 }
1090
1091 /* actual number of filters available to exact LMAC */
1092 lmac->dmacs_count = (RX_DMAC_COUNT / bgx->lmac_count);
1093 lmac->dmacs = kcalloc(lmac->dmacs_count, sizeof(*lmac->dmacs),
1094 GFP_KERNEL);
1095 if (!lmac->dmacs)
1096 return -ENOMEM;
1097
1098 /* Enable lmac */
1099 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
1100
1101 /* Restore default cfg, incase low level firmware changed it */
1102 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
1103
1104 if ((lmac->lmac_type != BGX_MODE_XFI) &&
1105 (lmac->lmac_type != BGX_MODE_XLAUI) &&
1106 (lmac->lmac_type != BGX_MODE_40G_KR) &&
1107 (lmac->lmac_type != BGX_MODE_10G_KR)) {
1108 if (!lmac->phydev) {
1109 if (lmac->autoneg) {
1110 bgx_reg_write(bgx, lmacid,
1111 BGX_GMP_PCS_LINKX_TIMER,
1112 PCS_LINKX_TIMER_COUNT);
1113 goto poll;
1114 } else {
1115 /* Default to below link speed and duplex */
1116 lmac->link_up = true;
1117 lmac->last_speed = 1000;
1118 lmac->last_duplex = 1;
1119 bgx_sgmii_change_link_state(lmac);
1120 return 0;
1121 }
1122 }
1123 lmac->phydev->dev_flags = 0;
1124
1125 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
1126 bgx_lmac_handler,
1127 phy_interface_mode(lmac->lmac_type)))
1128 return -ENODEV;
1129
1130 phy_start(lmac->phydev);
1131 return 0;
1132 }
1133
1134 poll:
1135 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
1136 WQ_MEM_RECLAIM, 1);
1137 if (!lmac->check_link)
1138 return -ENOMEM;
1139 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
1140 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
1141
1142 return 0;
1143 }
1144
1145 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
1146 {
1147 struct lmac *lmac;
1148 u64 cfg;
1149
1150 lmac = &bgx->lmac[lmacid];
1151 if (lmac->check_link) {
1152 /* Destroy work queue */
1153 cancel_delayed_work_sync(&lmac->dwork);
1154 destroy_workqueue(lmac->check_link);
1155 }
1156
1157 /* Disable packet reception */
1158 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1159 cfg &= ~CMR_PKT_RX_EN;
1160 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1161
1162 /* Give chance for Rx/Tx FIFO to get drained */
1163 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
1164 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
1165
1166 /* Disable packet transmission */
1167 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1168 cfg &= ~CMR_PKT_TX_EN;
1169 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1170
1171 /* Disable serdes lanes */
1172 if (!lmac->is_sgmii)
1173 bgx_reg_modify(bgx, lmacid,
1174 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
1175 else
1176 bgx_reg_modify(bgx, lmacid,
1177 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
1178
1179 /* Disable LMAC */
1180 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1181 cfg &= ~CMR_EN;
1182 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1183
1184 bgx_flush_dmac_cam_filter(bgx, lmacid);
1185 kfree(lmac->dmacs);
1186
1187 if ((lmac->lmac_type != BGX_MODE_XFI) &&
1188 (lmac->lmac_type != BGX_MODE_XLAUI) &&
1189 (lmac->lmac_type != BGX_MODE_40G_KR) &&
1190 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
1191 phy_disconnect(lmac->phydev);
1192
1193 lmac->phydev = NULL;
1194 }
1195
1196 static void bgx_init_hw(struct bgx *bgx)
1197 {
1198 int i;
1199 struct lmac *lmac;
1200
1201 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
1202 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
1203 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
1204
1205 /* Set lmac type and lane2serdes mapping */
1206 for (i = 0; i < bgx->lmac_count; i++) {
1207 lmac = &bgx->lmac[i];
1208 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
1209 (lmac->lmac_type << 8) | lmac->lane_to_sds);
1210 bgx->lmac[i].lmacid_bd = lmac_count;
1211 lmac_count++;
1212 }
1213
1214 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
1215 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
1216
1217 /* Set the backpressure AND mask */
1218 for (i = 0; i < bgx->lmac_count; i++)
1219 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
1220 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
1221 (i * MAX_BGX_CHANS_PER_LMAC));
1222
1223 /* Disable all MAC filtering */
1224 for (i = 0; i < RX_DMAC_COUNT; i++)
1225 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
1226
1227 /* Disable MAC steering (NCSI traffic) */
1228 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
1229 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
1230 }
1231
1232 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
1233 {
1234 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
1235 }
1236
1237 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
1238 {
1239 struct device *dev = &bgx->pdev->dev;
1240 struct lmac *lmac;
1241 char str[27];
1242
1243 if (!bgx->is_dlm && lmacid)
1244 return;
1245
1246 lmac = &bgx->lmac[lmacid];
1247 if (!bgx->is_dlm)
1248 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
1249 else
1250 sprintf(str, "BGX%d LMAC%d mode", bgx->bgx_id, lmacid);
1251
1252 switch (lmac->lmac_type) {
1253 case BGX_MODE_SGMII:
1254 dev_info(dev, "%s: SGMII\n", (char *)str);
1255 break;
1256 case BGX_MODE_XAUI:
1257 dev_info(dev, "%s: XAUI\n", (char *)str);
1258 break;
1259 case BGX_MODE_RXAUI:
1260 dev_info(dev, "%s: RXAUI\n", (char *)str);
1261 break;
1262 case BGX_MODE_XFI:
1263 if (!lmac->use_training)
1264 dev_info(dev, "%s: XFI\n", (char *)str);
1265 else
1266 dev_info(dev, "%s: 10G_KR\n", (char *)str);
1267 break;
1268 case BGX_MODE_XLAUI:
1269 if (!lmac->use_training)
1270 dev_info(dev, "%s: XLAUI\n", (char *)str);
1271 else
1272 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
1273 break;
1274 case BGX_MODE_QSGMII:
1275 dev_info(dev, "%s: QSGMII\n", (char *)str);
1276 break;
1277 case BGX_MODE_RGMII:
1278 dev_info(dev, "%s: RGMII\n", (char *)str);
1279 break;
1280 case BGX_MODE_INVALID:
1281 /* Nothing to do */
1282 break;
1283 }
1284 }
1285
1286 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
1287 {
1288 switch (lmac->lmac_type) {
1289 case BGX_MODE_SGMII:
1290 case BGX_MODE_XFI:
1291 lmac->lane_to_sds = lmac->lmacid;
1292 break;
1293 case BGX_MODE_XAUI:
1294 case BGX_MODE_XLAUI:
1295 case BGX_MODE_RGMII:
1296 lmac->lane_to_sds = 0xE4;
1297 break;
1298 case BGX_MODE_RXAUI:
1299 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
1300 break;
1301 case BGX_MODE_QSGMII:
1302 /* There is no way to determine if DLM0/2 is QSGMII or
1303 * DLM1/3 is configured to QSGMII as bootloader will
1304 * configure all LMACs, so take whatever is configured
1305 * by low level firmware.
1306 */
1307 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
1308 break;
1309 default:
1310 lmac->lane_to_sds = 0;
1311 break;
1312 }
1313 }
1314
1315 static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
1316 {
1317 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
1318 (lmac->lmac_type != BGX_MODE_40G_KR)) {
1319 lmac->use_training = 0;
1320 return;
1321 }
1322
1323 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
1324 SPU_PMD_CRTL_TRAIN_EN;
1325 }
1326
1327 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
1328 {
1329 struct lmac *lmac;
1330 u64 cmr_cfg;
1331 u8 lmac_type;
1332 u8 lane_to_sds;
1333
1334 lmac = &bgx->lmac[idx];
1335
1336 if (!bgx->is_dlm || bgx->is_rgx) {
1337 /* Read LMAC0 type to figure out QLM mode
1338 * This is configured by low level firmware
1339 */
1340 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
1341 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
1342 if (bgx->is_rgx)
1343 lmac->lmac_type = BGX_MODE_RGMII;
1344 lmac_set_training(bgx, lmac, 0);
1345 lmac_set_lane2sds(bgx, lmac);
1346 return;
1347 }
1348
1349 /* For DLMs or SLMs on 80/81/83xx so many lane configurations
1350 * are possible and vary across boards. Also Kernel doesn't have
1351 * any way to identify board type/info and since firmware does,
1352 * just take lmac type and serdes lane config as is.
1353 */
1354 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
1355 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
1356 lane_to_sds = (u8)(cmr_cfg & 0xFF);
1357 /* Check if config is reset value */
1358 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
1359 lmac->lmac_type = BGX_MODE_INVALID;
1360 else
1361 lmac->lmac_type = lmac_type;
1362 lmac->lane_to_sds = lane_to_sds;
1363 lmac_set_training(bgx, lmac, lmac->lmacid);
1364 }
1365
1366 static void bgx_get_qlm_mode(struct bgx *bgx)
1367 {
1368 struct lmac *lmac;
1369 u8 idx;
1370
1371 /* Init all LMAC's type to invalid */
1372 for (idx = 0; idx < bgx->max_lmac; idx++) {
1373 lmac = &bgx->lmac[idx];
1374 lmac->lmacid = idx;
1375 lmac->lmac_type = BGX_MODE_INVALID;
1376 lmac->use_training = false;
1377 }
1378
1379 /* It is assumed that low level firmware sets this value */
1380 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
1381 if (bgx->lmac_count > bgx->max_lmac)
1382 bgx->lmac_count = bgx->max_lmac;
1383
1384 for (idx = 0; idx < bgx->lmac_count; idx++) {
1385 bgx_set_lmac_config(bgx, idx);
1386 bgx_print_qlm_mode(bgx, idx);
1387 }
1388 }
1389
1390 #ifdef CONFIG_ACPI
1391
1392 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1393 u8 *dst)
1394 {
1395 u8 mac[ETH_ALEN];
1396 int ret;
1397
1398 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
1399 "mac-address", mac, ETH_ALEN);
1400 if (ret)
1401 goto out;
1402
1403 if (!is_valid_ether_addr(mac)) {
1404 dev_err(dev, "MAC address invalid: %pM\n", mac);
1405 ret = -EINVAL;
1406 goto out;
1407 }
1408
1409 dev_info(dev, "MAC address set to: %pM\n", mac);
1410
1411 memcpy(dst, mac, ETH_ALEN);
1412 out:
1413 return ret;
1414 }
1415
1416 /* Currently only sets the MAC address. */
1417 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1418 u32 lvl, void *context, void **rv)
1419 {
1420 struct bgx *bgx = context;
1421 struct device *dev = &bgx->pdev->dev;
1422 struct acpi_device *adev;
1423
1424 if (acpi_bus_get_device(handle, &adev))
1425 goto out;
1426
1427 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac);
1428
1429 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev);
1430
1431 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx;
1432 bgx->acpi_lmac_idx++; /* move to next LMAC */
1433 out:
1434 return AE_OK;
1435 }
1436
1437 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1438 void *context, void **ret_val)
1439 {
1440 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1441 struct bgx *bgx = context;
1442 char bgx_sel[5];
1443
1444 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1445 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1446 pr_warn("Invalid link device\n");
1447 return AE_OK;
1448 }
1449
1450 if (strncmp(string.pointer, bgx_sel, 4))
1451 return AE_OK;
1452
1453 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1454 bgx_acpi_register_phy, NULL, bgx, NULL);
1455
1456 kfree(string.pointer);
1457 return AE_CTRL_TERMINATE;
1458 }
1459
1460 static int bgx_init_acpi_phy(struct bgx *bgx)
1461 {
1462 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1463 return 0;
1464 }
1465
1466 #else
1467
1468 static int bgx_init_acpi_phy(struct bgx *bgx)
1469 {
1470 return -ENODEV;
1471 }
1472
1473 #endif /* CONFIG_ACPI */
1474
1475 #if IS_ENABLED(CONFIG_OF_MDIO)
1476
1477 static int bgx_init_of_phy(struct bgx *bgx)
1478 {
1479 struct fwnode_handle *fwn;
1480 struct device_node *node = NULL;
1481 u8 lmac = 0;
1482
1483 device_for_each_child_node(&bgx->pdev->dev, fwn) {
1484 struct phy_device *pd;
1485 struct device_node *phy_np;
1486 const char *mac;
1487
1488 /* Should always be an OF node. But if it is not, we
1489 * cannot handle it, so exit the loop.
1490 */
1491 node = to_of_node(fwn);
1492 if (!node)
1493 break;
1494
1495 mac = of_get_mac_address(node);
1496 if (mac)
1497 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1498
1499 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1500 bgx->lmac[lmac].lmacid = lmac;
1501
1502 phy_np = of_parse_phandle(node, "phy-handle", 0);
1503 /* If there is no phy or defective firmware presents
1504 * this cortina phy, for which there is no driver
1505 * support, ignore it.
1506 */
1507 if (phy_np &&
1508 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1509 /* Wait until the phy drivers are available */
1510 pd = of_phy_find_device(phy_np);
1511 if (!pd)
1512 goto defer;
1513 bgx->lmac[lmac].phydev = pd;
1514 }
1515
1516 lmac++;
1517 if (lmac == bgx->max_lmac) {
1518 of_node_put(node);
1519 break;
1520 }
1521 }
1522 return 0;
1523
1524 defer:
1525 /* We are bailing out, try not to leak device reference counts
1526 * for phy devices we may have already found.
1527 */
1528 while (lmac) {
1529 if (bgx->lmac[lmac].phydev) {
1530 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1531 bgx->lmac[lmac].phydev = NULL;
1532 }
1533 lmac--;
1534 }
1535 of_node_put(node);
1536 return -EPROBE_DEFER;
1537 }
1538
1539 #else
1540
1541 static int bgx_init_of_phy(struct bgx *bgx)
1542 {
1543 return -ENODEV;
1544 }
1545
1546 #endif /* CONFIG_OF_MDIO */
1547
1548 static int bgx_init_phy(struct bgx *bgx)
1549 {
1550 if (!acpi_disabled)
1551 return bgx_init_acpi_phy(bgx);
1552
1553 return bgx_init_of_phy(bgx);
1554 }
1555
1556 static irqreturn_t bgx_intr_handler(int irq, void *data)
1557 {
1558 struct bgx *bgx = (struct bgx *)data;
1559 u64 status, val;
1560 int lmac;
1561
1562 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1563 status = bgx_reg_read(bgx, lmac, BGX_GMP_GMI_TXX_INT);
1564 if (status & GMI_TXX_INT_UNDFLW) {
1565 pci_err(bgx->pdev, "BGX%d lmac%d UNDFLW\n",
1566 bgx->bgx_id, lmac);
1567 val = bgx_reg_read(bgx, lmac, BGX_CMRX_CFG);
1568 val &= ~CMR_EN;
1569 bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
1570 val |= CMR_EN;
1571 bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
1572 }
1573 /* clear interrupts */
1574 bgx_reg_write(bgx, lmac, BGX_GMP_GMI_TXX_INT, status);
1575 }
1576
1577 return IRQ_HANDLED;
1578 }
1579
1580 static void bgx_register_intr(struct pci_dev *pdev)
1581 {
1582 struct bgx *bgx = pci_get_drvdata(pdev);
1583 int ret;
1584
1585 ret = pci_alloc_irq_vectors(pdev, BGX_LMAC_VEC_OFFSET,
1586 BGX_LMAC_VEC_OFFSET, PCI_IRQ_ALL_TYPES);
1587 if (ret < 0) {
1588 pci_err(pdev, "Req for #%d msix vectors failed\n",
1589 BGX_LMAC_VEC_OFFSET);
1590 return;
1591 }
1592 ret = pci_request_irq(pdev, GMPX_GMI_TX_INT, bgx_intr_handler, NULL,
1593 bgx, "BGX%d", bgx->bgx_id);
1594 if (ret)
1595 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1596 }
1597
1598 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1599 {
1600 int err;
1601 struct device *dev = &pdev->dev;
1602 struct bgx *bgx = NULL;
1603 u8 lmac;
1604 u16 sdevid;
1605
1606 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1607 if (!bgx)
1608 return -ENOMEM;
1609 bgx->pdev = pdev;
1610
1611 pci_set_drvdata(pdev, bgx);
1612
1613 err = pcim_enable_device(pdev);
1614 if (err) {
1615 dev_err(dev, "Failed to enable PCI device\n");
1616 pci_set_drvdata(pdev, NULL);
1617 return err;
1618 }
1619
1620 err = pci_request_regions(pdev, DRV_NAME);
1621 if (err) {
1622 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1623 goto err_disable_device;
1624 }
1625
1626 /* MAP configuration registers */
1627 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1628 if (!bgx->reg_base) {
1629 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1630 err = -ENOMEM;
1631 goto err_release_regions;
1632 }
1633
1634 set_max_bgx_per_node(pdev);
1635
1636 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1637 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
1638 bgx->bgx_id = (pci_resource_start(pdev,
1639 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
1640 bgx->bgx_id += nic_get_node_id(pdev) * max_bgx_per_node;
1641 bgx->max_lmac = MAX_LMAC_PER_BGX;
1642 bgx_vnic[bgx->bgx_id] = bgx;
1643 } else {
1644 bgx->is_rgx = true;
1645 bgx->max_lmac = 1;
1646 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1647 bgx_vnic[bgx->bgx_id] = bgx;
1648 xcv_init_hw();
1649 }
1650
1651 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1652 * BGX i.e BGX2 can be split across 2 DLMs.
1653 */
1654 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1655 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1656 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1657 bgx->is_dlm = true;
1658
1659 bgx_get_qlm_mode(bgx);
1660
1661 err = bgx_init_phy(bgx);
1662 if (err)
1663 goto err_enable;
1664
1665 bgx_init_hw(bgx);
1666
1667 bgx_register_intr(pdev);
1668
1669 /* Enable all LMACs */
1670 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1671 err = bgx_lmac_enable(bgx, lmac);
1672 if (err) {
1673 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1674 bgx->bgx_id, lmac);
1675 while (lmac)
1676 bgx_lmac_disable(bgx, --lmac);
1677 goto err_enable;
1678 }
1679 }
1680
1681 return 0;
1682
1683 err_enable:
1684 bgx_vnic[bgx->bgx_id] = NULL;
1685 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1686 err_release_regions:
1687 pci_release_regions(pdev);
1688 err_disable_device:
1689 pci_disable_device(pdev);
1690 pci_set_drvdata(pdev, NULL);
1691 return err;
1692 }
1693
1694 static void bgx_remove(struct pci_dev *pdev)
1695 {
1696 struct bgx *bgx = pci_get_drvdata(pdev);
1697 u8 lmac;
1698
1699 /* Disable all LMACs */
1700 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1701 bgx_lmac_disable(bgx, lmac);
1702
1703 pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx);
1704
1705 bgx_vnic[bgx->bgx_id] = NULL;
1706 pci_release_regions(pdev);
1707 pci_disable_device(pdev);
1708 pci_set_drvdata(pdev, NULL);
1709 }
1710
1711 static struct pci_driver bgx_driver = {
1712 .name = DRV_NAME,
1713 .id_table = bgx_id_table,
1714 .probe = bgx_probe,
1715 .remove = bgx_remove,
1716 };
1717
1718 static int __init bgx_init_module(void)
1719 {
1720 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1721
1722 return pci_register_driver(&bgx_driver);
1723 }
1724
1725 static void __exit bgx_cleanup_module(void)
1726 {
1727 pci_unregister_driver(&bgx_driver);
1728 }
1729
1730 module_init(bgx_init_module);
1731 module_exit(bgx_cleanup_module);
Linux with added FPC-III support