| blob | 0be96cee27bd107e5af9cecd8a72ffc6c1ca7b46 |
1 /*
2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
43 #include <dt-bindings/clock/rk3328-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3328-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
51 / {
52 compatible = "rockchip,rk3328";
54 interrupt-parent = <&gic>;
55 #address-cells = <2>;
56 #size-cells = <2>;
58 aliases {
59 serial0 = &uart0;
60 serial1 = &uart1;
61 serial2 = &uart2;
62 i2c0 = &i2c0;
63 i2c1 = &i2c1;
64 i2c2 = &i2c2;
65 i2c3 = &i2c3;
66 };
68 cpus {
69 #address-cells = <2>;
70 #size-cells = <0>;
72 cpu0: cpu@0 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a53", "arm,armv8";
75 reg = <0x0 0x0>;
76 clocks = <&cru ARMCLK>;
77 enable-method = "psci";
78 next-level-cache = <&l2>;
79 };
81 cpu1: cpu@1 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a53", "arm,armv8";
84 reg = <0x0 0x1>;
85 clocks = <&cru ARMCLK>;
86 enable-method = "psci";
87 next-level-cache = <&l2>;
88 };
90 cpu2: cpu@2 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a53", "arm,armv8";
93 reg = <0x0 0x2>;
94 clocks = <&cru ARMCLK>;
95 enable-method = "psci";
96 next-level-cache = <&l2>;
97 };
99 cpu3: cpu@3 {
100 device_type = "cpu";
101 compatible = "arm,cortex-a53", "arm,armv8";
102 reg = <0x0 0x3>;
103 clocks = <&cru ARMCLK>;
104 enable-method = "psci";
105 next-level-cache = <&l2>;
106 };
108 l2: l2-cache0 {
109 compatible = "cache";
110 };
111 };
113 amba {
114 compatible = "simple-bus";
115 #address-cells = <2>;
116 #size-cells = <2>;
117 ranges;
119 dmac: dmac@ff1f0000 {
120 compatible = "arm,pl330", "arm,primecell";
121 reg = <0x0 0xff1f0000 0x0 0x4000>;
122 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&cru ACLK_DMAC>;
125 clock-names = "apb_pclk";
126 #dma-cells = <1>;
127 };
128 };
130 arm-pmu {
131 compatible = "arm,cortex-a53-pmu";
132 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
136 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
137 };
139 psci {
140 compatible = "arm,psci-1.0", "arm,psci-0.2";
141 method = "smc";
142 };
144 timer {
145 compatible = "arm,armv8-timer";
146 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
147 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
148 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
149 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
150 };
152 xin24m: xin24m {
153 compatible = "fixed-clock";
154 #clock-cells = <0>;
155 clock-frequency = <24000000>;
156 clock-output-names = "xin24m";
157 };
159 grf: syscon@ff100000 {
160 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
161 reg = <0x0 0xff100000 0x0 0x1000>;
162 #address-cells = <1>;
163 #size-cells = <1>;
165 power: power-controller {
166 compatible = "rockchip,rk3328-power-controller";
167 #power-domain-cells = <1>;
168 #address-cells = <1>;
169 #size-cells = <0>;
171 pd_hevc@RK3328_PD_HEVC {
172 reg = <RK3328_PD_HEVC>;
173 };
174 pd_video@RK3328_PD_VIDEO {
175 reg = <RK3328_PD_VIDEO>;
176 };
177 pd_vpu@RK3328_PD_VPU {
178 reg = <RK3328_PD_VPU>;
179 };
180 };
182 reboot-mode {
183 compatible = "syscon-reboot-mode";
184 offset = <0x5c8>;
185 mode-normal = <BOOT_NORMAL>;
186 mode-recovery = <BOOT_RECOVERY>;
187 mode-bootloader = <BOOT_FASTBOOT>;
188 mode-loader = <BOOT_BL_DOWNLOAD>;
189 };
191 };
193 uart0: serial@ff110000 {
194 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
195 reg = <0x0 0xff110000 0x0 0x100>;
196 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
198 clock-names = "baudclk", "apb_pclk";
199 dmas = <&dmac 2>, <&dmac 3>;
200 #dma-cells = <2>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
203 reg-io-width = <4>;
204 reg-shift = <2>;
205 status = "disabled";
206 };
208 uart1: serial@ff120000 {
209 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
210 reg = <0x0 0xff120000 0x0 0x100>;
211 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
213 clock-names = "sclk_uart", "pclk_uart";
214 dmas = <&dmac 4>, <&dmac 5>;
215 #dma-cells = <2>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
218 reg-io-width = <4>;
219 reg-shift = <2>;
220 status = "disabled";
221 };
223 uart2: serial@ff130000 {
224 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
225 reg = <0x0 0xff130000 0x0 0x100>;
226 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
228 clock-names = "baudclk", "apb_pclk";
229 dmas = <&dmac 6>, <&dmac 7>;
230 #dma-cells = <2>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&uart2m1_xfer>;
233 reg-io-width = <4>;
234 reg-shift = <2>;
235 status = "disabled";
236 };
238 i2c0: i2c@ff150000 {
239 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
240 reg = <0x0 0xff150000 0x0 0x1000>;
241 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
242 #address-cells = <1>;
243 #size-cells = <0>;
244 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
245 clock-names = "i2c", "pclk";
246 pinctrl-names = "default";
247 pinctrl-0 = <&i2c0_xfer>;
248 status = "disabled";
249 };
251 i2c1: i2c@ff160000 {
252 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
253 reg = <0x0 0xff160000 0x0 0x1000>;
254 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
258 clock-names = "i2c", "pclk";
259 pinctrl-names = "default";
260 pinctrl-0 = <&i2c1_xfer>;
261 status = "disabled";
262 };
264 i2c2: i2c@ff170000 {
265 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
266 reg = <0x0 0xff170000 0x0 0x1000>;
267 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
268 #address-cells = <1>;
269 #size-cells = <0>;
270 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
271 clock-names = "i2c", "pclk";
272 pinctrl-names = "default";
273 pinctrl-0 = <&i2c2_xfer>;
274 status = "disabled";
275 };
277 i2c3: i2c@ff180000 {
278 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
279 reg = <0x0 0xff180000 0x0 0x1000>;
280 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
284 clock-names = "i2c", "pclk";
285 pinctrl-names = "default";
286 pinctrl-0 = <&i2c3_xfer>;
287 status = "disabled";
288 };
290 spi0: spi@ff190000 {
291 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
292 reg = <0x0 0xff190000 0x0 0x1000>;
293 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
297 clock-names = "spiclk", "apb_pclk";
298 dmas = <&dmac 8>, <&dmac 9>;
299 dma-names = "tx", "rx";
300 pinctrl-names = "default";
301 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
302 status = "disabled";
303 };
305 wdt: watchdog@ff1a0000 {
306 compatible = "snps,dw-wdt";
307 reg = <0x0 0xff1a0000 0x0 0x100>;
308 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
309 };
311 saradc: adc@ff280000 {
312 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
313 reg = <0x0 0xff280000 0x0 0x100>;
314 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
315 #io-channel-cells = <1>;
316 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
317 clock-names = "saradc", "apb_pclk";
318 resets = <&cru SRST_SARADC_P>;
319 reset-names = "saradc-apb";
320 status = "disabled";
321 };
323 cru: clock-controller@ff440000 {
324 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
325 reg = <0x0 0xff440000 0x0 0x1000>;
326 rockchip,grf = <&grf>;
327 #clock-cells = <1>;
328 #reset-cells = <1>;
329 assigned-clocks =
330 /*
331 * CPLL should run at 1200, but that is to high for
332 * the initial dividers of most of its children.
333 * We need set cpll child clk div first,
334 * and then set the cpll frequency.
335 */
336 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
337 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
338 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
339 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
340 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
341 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
342 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
343 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
344 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
345 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
346 <&cru SCLK_WIFI>, <&cru ARMCLK>,
347 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
348 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
349 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
350 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
351 <&cru SCLK_RTC32K>;
352 assigned-clock-parents =
353 <&cru HDMIPHY>, <&cru PLL_APLL>,
354 <&cru PLL_GPLL>, <&xin24m>,
355 <&xin24m>, <&xin24m>;
356 assigned-clock-rates =
357 <0>, <61440000>,
358 <0>, <24000000>,
359 <24000000>, <24000000>,
360 <15000000>, <15000000>,
361 <100000000>, <100000000>,
362 <100000000>, <100000000>,
363 <50000000>, <100000000>,
364 <100000000>, <100000000>,
365 <50000000>, <50000000>,
366 <50000000>, <50000000>,
367 <24000000>, <600000000>,
368 <491520000>, <1200000000>,
369 <150000000>, <75000000>,
370 <75000000>, <150000000>,
371 <75000000>, <75000000>,
372 <32768>;
373 };
375 sdmmc: dwmmc@ff500000 {
376 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
377 reg = <0x0 0xff500000 0x0 0x4000>;
378 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
380 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
381 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
382 fifo-depth = <0x100>;
383 status = "disabled";
384 };
386 sdio: dwmmc@ff510000 {
387 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
388 reg = <0x0 0xff510000 0x0 0x4000>;
389 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
391 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
392 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
393 fifo-depth = <0x100>;
394 status = "disabled";
395 };
397 emmc: dwmmc@ff520000 {
398 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
399 reg = <0x0 0xff520000 0x0 0x4000>;
400 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
402 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
403 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
404 fifo-depth = <0x100>;
405 status = "disabled";
406 };
408 gmac2io: ethernet@ff540000 {
409 compatible = "rockchip,rk3328-gmac";
410 reg = <0x0 0xff540000 0x0 0x10000>;
411 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
412 interrupt-names = "macirq";
413 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
414 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
415 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
416 <&cru PCLK_MAC2IO>;
417 clock-names = "stmmaceth", "mac_clk_rx",
418 "mac_clk_tx", "clk_mac_ref",
419 "clk_mac_refout", "aclk_mac",
420 "pclk_mac";
421 resets = <&cru SRST_GMAC2IO_A>;
422 reset-names = "stmmaceth";
423 rockchip,grf = <&grf>;
424 status = "disabled";
425 };
427 gic: interrupt-controller@ff811000 {
428 compatible = "arm,gic-400";
429 #interrupt-cells = <3>;
430 #address-cells = <0>;
431 interrupt-controller;
432 reg = <0x0 0xff811000 0 0x1000>,
433 <0x0 0xff812000 0 0x2000>,
434 <0x0 0xff814000 0 0x2000>,
435 <0x0 0xff816000 0 0x2000>;
436 interrupts = <GIC_PPI 9
437 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
438 };
440 pinctrl: pinctrl {
441 compatible = "rockchip,rk3328-pinctrl";
442 rockchip,grf = <&grf>;
443 #address-cells = <2>;
444 #size-cells = <2>;
445 ranges;
447 gpio0: gpio0@ff210000 {
448 compatible = "rockchip,gpio-bank";
449 reg = <0x0 0xff210000 0x0 0x100>;
450 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&cru PCLK_GPIO0>;
453 gpio-controller;
454 #gpio-cells = <2>;
456 interrupt-controller;
457 #interrupt-cells = <2>;
458 };
460 gpio1: gpio1@ff220000 {
461 compatible = "rockchip,gpio-bank";
462 reg = <0x0 0xff220000 0x0 0x100>;
463 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&cru PCLK_GPIO1>;
466 gpio-controller;
467 #gpio-cells = <2>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
471 };
473 gpio2: gpio2@ff230000 {
474 compatible = "rockchip,gpio-bank";
475 reg = <0x0 0xff230000 0x0 0x100>;
476 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cru PCLK_GPIO2>;
479 gpio-controller;
480 #gpio-cells = <2>;
482 interrupt-controller;
483 #interrupt-cells = <2>;
484 };
486 gpio3: gpio3@ff240000 {
487 compatible = "rockchip,gpio-bank";
488 reg = <0x0 0xff240000 0x0 0x100>;
489 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&cru PCLK_GPIO3>;
492 gpio-controller;
493 #gpio-cells = <2>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 };
499 pcfg_pull_up: pcfg-pull-up {
500 bias-pull-up;
501 };
503 pcfg_pull_down: pcfg-pull-down {
504 bias-pull-down;
505 };
507 pcfg_pull_none: pcfg-pull-none {
508 bias-disable;
509 };
511 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
512 bias-disable;
513 drive-strength = <2>;
514 };
516 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
517 bias-pull-up;
518 drive-strength = <2>;
519 };
521 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
522 bias-pull-up;
523 drive-strength = <4>;
524 };
526 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
527 bias-disable;
528 drive-strength = <4>;
529 };
531 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
532 bias-pull-down;
533 drive-strength = <4>;
534 };
536 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
537 bias-disable;
538 drive-strength = <8>;
539 };
541 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
542 bias-pull-up;
543 drive-strength = <8>;
544 };
546 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
547 bias-disable;
548 drive-strength = <12>;
549 };
551 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
552 bias-pull-up;
553 drive-strength = <12>;
554 };
556 pcfg_output_high: pcfg-output-high {
557 output-high;
558 };
560 pcfg_output_low: pcfg-output-low {
561 output-low;
562 };
564 pcfg_input_high: pcfg-input-high {
565 bias-pull-up;
566 input-enable;
567 };
569 pcfg_input: pcfg-input {
570 input-enable;
571 };
573 i2c0 {
574 i2c0_xfer: i2c0-xfer {
575 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
576 <2 RK_PD1 1 &pcfg_pull_none>;
577 };
578 };
580 i2c1 {
581 i2c1_xfer: i2c1-xfer {
582 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
583 <2 RK_PA5 2 &pcfg_pull_none>;
584 };
585 };
587 i2c2 {
588 i2c2_xfer: i2c2-xfer {
589 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
590 <2 RK_PB6 1 &pcfg_pull_none>;
591 };
592 };
594 i2c3 {
595 i2c3_xfer: i2c3-xfer {
596 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
597 <0 RK_PA6 2 &pcfg_pull_none>;
598 };
599 i2c3_gpio: i2c3-gpio {
600 rockchip,pins =
601 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
602 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
603 };
604 };
606 hdmi_i2c {
607 hdmii2c_xfer: hdmii2c-xfer {
608 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
609 <0 RK_PA6 1 &pcfg_pull_none>;
610 };
611 };
613 tsadc {
614 otp_gpio: otp-gpio {
615 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
616 };
618 otp_out: otp-out {
619 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
620 };
621 };
623 uart0 {
624 uart0_xfer: uart0-xfer {
625 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
626 <1 RK_PB0 1 &pcfg_pull_none>;
627 };
629 uart0_cts: uart0-cts {
630 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
631 };
633 uart0_rts: uart0-rts {
634 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
635 };
637 uart0_rts_gpio: uart0-rts-gpio {
638 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
639 };
640 };
642 uart1 {
643 uart1_xfer: uart1-xfer {
644 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
645 <3 RK_PA6 4 &pcfg_pull_none>;
646 };
648 uart1_cts: uart1-cts {
649 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
650 };
652 uart1_rts: uart1-rts {
653 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
654 };
656 uart1_rts_gpio: uart1-rts-gpio {
657 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
658 };
659 };
661 uart2-0 {
662 uart2m0_xfer: uart2m0-xfer {
663 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
664 <1 RK_PA1 2 &pcfg_pull_none>;
665 };
666 };
668 uart2-1 {
669 uart2m1_xfer: uart2m1-xfer {
670 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
671 <2 RK_PA1 1 &pcfg_pull_none>;
672 };
673 };
675 spi0-0 {
676 spi0m0_clk: spi0m0-clk {
677 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
678 };
680 spi0m0_cs0: spi0m0-cs0 {
681 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
682 };
684 spi0m0_tx: spi0m0-tx {
685 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
686 };
688 spi0m0_rx: spi0m0-rx {
689 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
690 };
692 spi0m0_cs1: spi0m0-cs1 {
693 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
694 };
695 };
697 spi0-1 {
698 spi0m1_clk: spi0m1-clk {
699 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
700 };
702 spi0m1_cs0: spi0m1-cs0 {
703 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
704 };
706 spi0m1_tx: spi0m1-tx {
707 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
708 };
710 spi0m1_rx: spi0m1-rx {
711 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
712 };
714 spi0m1_cs1: spi0m1-cs1 {
715 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
716 };
717 };
719 spi0-2 {
720 spi0m2_clk: spi0m2-clk {
721 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
722 };
724 spi0m2_cs0: spi0m2-cs0 {
725 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
726 };
728 spi0m2_tx: spi0m2-tx {
729 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
730 };
732 spi0m2_rx: spi0m2-rx {
733 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
734 };
735 };
737 i2s1 {
738 i2s1_mclk: i2s1-mclk {
739 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
740 };
742 i2s1_sclk: i2s1-sclk {
743 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
744 };
746 i2s1_lrckrx: i2s1-lrckrx {
747 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
748 };
750 i2s1_lrcktx: i2s1-lrcktx {
751 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
752 };
754 i2s1_sdi: i2s1-sdi {
755 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
756 };
758 i2s1_sdo: i2s1-sdo {
759 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
760 };
762 i2s1_sdio1: i2s1-sdio1 {
763 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
764 };
766 i2s1_sdio2: i2s1-sdio2 {
767 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
768 };
770 i2s1_sdio3: i2s1-sdio3 {
771 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
772 };
774 i2s1_sleep: i2s1-sleep {
775 rockchip,pins =
776 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
777 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
778 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
779 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
780 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
781 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
782 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
783 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
784 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
785 };
786 };
788 i2s2-0 {
789 i2s2m0_mclk: i2s2m0-mclk {
790 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
791 };
793 i2s2m0_sclk: i2s2m0-sclk {
794 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
795 };
797 i2s2m0_lrckrx: i2s2m0-lrckrx {
798 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
799 };
801 i2s2m0_lrcktx: i2s2m0-lrcktx {
802 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
803 };
805 i2s2m0_sdi: i2s2m0-sdi {
806 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
807 };
809 i2s2m0_sdo: i2s2m0-sdo {
810 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
811 };
813 i2s2m0_sleep: i2s2m0-sleep {
814 rockchip,pins =
815 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
816 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
817 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
818 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
819 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
820 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
821 };
822 };
824 i2s2-1 {
825 i2s2m1_mclk: i2s2m1-mclk {
826 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
827 };
829 i2s2m1_sclk: i2s2m1-sclk {
830 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
831 };
833 i2s2m1_lrckrx: i2sm1-lrckrx {
834 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
835 };
837 i2s2m1_lrcktx: i2s2m1-lrcktx {
838 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
839 };
841 i2s2m1_sdi: i2s2m1-sdi {
842 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
843 };
845 i2s2m1_sdo: i2s2m1-sdo {
846 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
847 };
849 i2s2m1_sleep: i2s2m1-sleep {
850 rockchip,pins =
851 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
852 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
853 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
854 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
855 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
856 };
857 };
859 spdif-0 {
860 spdifm0_tx: spdifm0-tx {
861 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
862 };
863 };
865 spdif-1 {
866 spdifm1_tx: spdifm1-tx {
867 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
868 };
869 };
871 spdif-2 {
872 spdifm2_tx: spdifm2-tx {
873 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
874 };
875 };
877 sdmmc0-0 {
878 sdmmc0m0_pwren: sdmmc0m0-pwren {
879 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
880 };
882 sdmmc0m0_gpio: sdmmc0m0-gpio {
883 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
884 };
885 };
887 sdmmc0-1 {
888 sdmmc0m1_pwren: sdmmc0m1-pwren {
889 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
890 };
892 sdmmc0m1_gpio: sdmmc0m1-gpio {
893 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
894 };
895 };
897 sdmmc0 {
898 sdmmc0_clk: sdmmc0-clk {
899 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
900 };
902 sdmmc0_cmd: sdmmc0-cmd {
903 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
904 };
906 sdmmc0_dectn: sdmmc0-dectn {
907 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
908 };
910 sdmmc0_wrprt: sdmmc0-wrprt {
911 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
912 };
914 sdmmc0_bus1: sdmmc0-bus1 {
915 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
916 };
918 sdmmc0_bus4: sdmmc0-bus4 {
919 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
920 <1 RK_PA1 1 &pcfg_pull_up_4ma>,
921 <1 RK_PA2 1 &pcfg_pull_up_4ma>,
922 <1 RK_PA3 1 &pcfg_pull_up_4ma>;
923 };
925 sdmmc0_gpio: sdmmc0-gpio {
926 rockchip,pins =
927 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
928 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
929 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
930 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
931 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
932 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
933 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
934 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
935 };
936 };
938 sdmmc0ext {
939 sdmmc0ext_clk: sdmmc0ext-clk {
940 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
941 };
943 sdmmc0ext_cmd: sdmmc0ext-cmd {
944 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
945 };
947 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
948 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
949 };
951 sdmmc0ext_dectn: sdmmc0ext-dectn {
952 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
953 };
955 sdmmc0ext_bus1: sdmmc0ext-bus1 {
956 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
957 };
959 sdmmc0ext_bus4: sdmmc0ext-bus4 {
960 rockchip,pins =
961 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
962 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
963 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
964 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
965 };
967 sdmmc0ext_gpio: sdmmc0ext-gpio {
968 rockchip,pins =
969 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
970 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
971 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
972 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
973 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
974 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
975 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
976 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
977 };
978 };
980 sdmmc1 {
981 sdmmc1_clk: sdmmc1-clk {
982 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
983 };
985 sdmmc1_cmd: sdmmc1-cmd {
986 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
987 };
989 sdmmc1_pwren: sdmmc1-pwren {
990 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
991 };
993 sdmmc1_wrprt: sdmmc1-wrprt {
994 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
995 };
997 sdmmc1_dectn: sdmmc1-dectn {
998 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
999 };
1001 sdmmc1_bus1: sdmmc1-bus1 {
1002 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1003 };
1005 sdmmc1_bus4: sdmmc1-bus4 {
1006 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1007 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1008 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1009 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1010 };
1012 sdmmc1_gpio: sdmmc1-gpio {
1013 rockchip,pins =
1014 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1015 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1016 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1017 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1018 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1019 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1020 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1021 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1022 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1023 };
1024 };
1026 emmc {
1027 emmc_clk: emmc-clk {
1028 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1029 };
1031 emmc_cmd: emmc-cmd {
1032 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1033 };
1035 emmc_pwren: emmc-pwren {
1036 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1037 };
1039 emmc_rstnout: emmc-rstnout {
1040 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1041 };
1043 emmc_bus1: emmc-bus1 {
1044 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1045 };
1047 emmc_bus4: emmc-bus4 {
1048 rockchip,pins =
1049 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1050 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1051 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1052 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1053 };
1055 emmc_bus8: emmc-bus8 {
1056 rockchip,pins =
1057 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1058 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1059 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1060 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1061 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1062 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1063 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1064 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1065 };
1066 };
1068 pwm0 {
1069 pwm0_pin: pwm0-pin {
1070 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1071 };
1072 };
1074 pwm1 {
1075 pwm1_pin: pwm1-pin {
1076 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1077 };
1078 };
1080 pwm2 {
1081 pwm2_pin: pwm2-pin {
1082 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1083 };
1084 };
1086 pwmir {
1087 pwmir_pin: pwmir-pin {
1088 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1089 };
1090 };
1092 gmac-1 {
1093 rgmiim1_pins: rgmiim1-pins {
1094 rockchip,pins =
1095 /* mac_txclk */
1096 <1 RK_PB4 2 &pcfg_pull_none_12ma>,
1097 /* mac_rxclk */
1098 <1 RK_PB5 2 &pcfg_pull_none_2ma>,
1099 /* mac_mdio */
1100 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1101 /* mac_txen */
1102 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1103 /* mac_clk */
1104 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1105 /* mac_rxdv */
1106 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1107 /* mac_mdc */
1108 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1109 /* mac_rxd1 */
1110 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1111 /* mac_rxd0 */
1112 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1113 /* mac_txd1 */
1114 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1115 /* mac_txd0 */
1116 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1117 /* mac_rxd3 */
1118 <1 RK_PB6 2 &pcfg_pull_none_2ma>,
1119 /* mac_rxd2 */
1120 <1 RK_PB7 2 &pcfg_pull_none_2ma>,
1121 /* mac_txd3 */
1122 <1 RK_PC0 2 &pcfg_pull_none_12ma>,
1123 /* mac_txd2 */
1124 <1 RK_PC1 2 &pcfg_pull_none_12ma>,
1126 /* mac_txclk */
1127 <0 RK_PB0 1 &pcfg_pull_none>,
1128 /* mac_txen */
1129 <0 RK_PB4 1 &pcfg_pull_none>,
1130 /* mac_clk */
1131 <0 RK_PD0 1 &pcfg_pull_none>,
1132 /* mac_txd1 */
1133 <0 RK_PC0 1 &pcfg_pull_none>,
1134 /* mac_txd0 */
1135 <0 RK_PC1 1 &pcfg_pull_none>,
1136 /* mac_txd3 */
1137 <0 RK_PC7 1 &pcfg_pull_none>,
1138 /* mac_txd2 */
1139 <0 RK_PC6 1 &pcfg_pull_none>;
1140 };
1142 rmiim1_pins: rmiim1-pins {
1143 rockchip,pins =
1144 /* mac_mdio */
1145 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1146 /* mac_txen */
1147 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1148 /* mac_clk */
1149 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1150 /* mac_rxer */
1151 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1152 /* mac_rxdv */
1153 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1154 /* mac_mdc */
1155 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1156 /* mac_rxd1 */
1157 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1158 /* mac_rxd0 */
1159 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1160 /* mac_txd1 */
1161 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1162 /* mac_txd0 */
1163 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1165 /* mac_mdio */
1166 <0 RK_PB3 1 &pcfg_pull_none>,
1167 /* mac_txen */
1168 <0 RK_PB4 1 &pcfg_pull_none>,
1169 /* mac_clk */
1170 <0 RK_PD0 1 &pcfg_pull_none>,
1171 /* mac_mdc */
1172 <0 RK_PC3 1 &pcfg_pull_none>,
1173 /* mac_txd1 */
1174 <0 RK_PC0 1 &pcfg_pull_none>,
1175 /* mac_txd0 */
1176 <0 RK_PC1 1 &pcfg_pull_none>;
1177 };
1178 };
1180 gmac2phy {
1181 fephyled_speed100: fephyled-speed100 {
1182 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1183 };
1185 fephyled_speed10: fephyled-speed10 {
1186 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1187 };
1189 fephyled_duplex: fephyled-duplex {
1190 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1191 };
1193 fephyled_rxm0: fephyled-rxm0 {
1194 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1195 };
1197 fephyled_txm0: fephyled-txm0 {
1198 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1199 };
1201 fephyled_linkm0: fephyled-linkm0 {
1202 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1203 };
1205 fephyled_rxm1: fephyled-rxm1 {
1206 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1207 };
1209 fephyled_txm1: fephyled-txm1 {
1210 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1211 };
1213 fephyled_linkm1: fephyled-linkm1 {
1214 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1215 };
1216 };
1218 tsadc_pin {
1219 tsadc_int: tsadc-int {
1220 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1221 };
1222 tsadc_gpio: tsadc-gpio {
1223 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1224 };
1225 };
1227 hdmi_pin {
1228 hdmi_cec: hdmi-cec {
1229 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1230 };
1232 hdmi_hpd: hdmi-hpd {
1233 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1234 };
1235 };
1237 cif-0 {
1238 dvp_d2d9_m0:dvp-d2d9-m0 {
1239 rockchip,pins =
1240 /* cif_d0 */
1241 <3 RK_PA4 2 &pcfg_pull_none>,
1242 /* cif_d1 */
1243 <3 RK_PA5 2 &pcfg_pull_none>,
1244 /* cif_d2 */
1245 <3 RK_PA6 2 &pcfg_pull_none>,
1246 /* cif_d3 */
1247 <3 RK_PA7 2 &pcfg_pull_none>,
1248 /* cif_d4 */
1249 <3 RK_PB0 2 &pcfg_pull_none>,
1250 /* cif_d5m0 */
1251 <3 RK_PB1 2 &pcfg_pull_none>,
1252 /* cif_d6m0 */
1253 <3 RK_PB2 2 &pcfg_pull_none>,
1254 /* cif_d7m0 */
1255 <3 RK_PB3 2 &pcfg_pull_none>,
1256 /* cif_href */
1257 <3 RK_PA1 2 &pcfg_pull_none>,
1258 /* cif_vsync */
1259 <3 RK_PA0 2 &pcfg_pull_none>,
1260 /* cif_clkoutm0 */
1261 <3 RK_PA3 2 &pcfg_pull_none>,
1262 /* cif_clkin */
1263 <3 RK_PA2 2 &pcfg_pull_none>;
1264 };
1265 };
1267 cif-1 {
1268 dvp_d2d9_m1:dvp-d2d9-m1 {
1269 rockchip,pins =
1270 /* cif_d0 */
1271 <3 RK_PA4 2 &pcfg_pull_none>,
1272 /* cif_d1 */
1273 <3 RK_PA5 2 &pcfg_pull_none>,
1274 /* cif_d2 */
1275 <3 RK_PA6 2 &pcfg_pull_none>,
1276 /* cif_d3 */
1277 <3 RK_PA7 2 &pcfg_pull_none>,
1278 /* cif_d4 */
1279 <3 RK_PB0 2 &pcfg_pull_none>,
1280 /* cif_d5m1 */
1281 <2 RK_PC0 4 &pcfg_pull_none>,
1282 /* cif_d6m1 */
1283 <2 RK_PC1 4 &pcfg_pull_none>,
1284 /* cif_d7m1 */
1285 <2 RK_PC2 4 &pcfg_pull_none>,
1286 /* cif_href */
1287 <3 RK_PA1 2 &pcfg_pull_none>,
1288 /* cif_vsync */
1289 <3 RK_PA0 2 &pcfg_pull_none>,
1290 /* cif_clkoutm1 */
1291 <2 RK_PB7 4 &pcfg_pull_none>,
1292 /* cif_clkin */
1293 <3 RK_PA2 2 &pcfg_pull_none>;
1294 };
1295 };
1296 };
1297 };