arch/m68k/coldfire/m525x.c

   1 /***************************************************************************/
   2
   3 /*
   4  *      525x.c  -- platform support for ColdFire 525x based boards
   5  *
   6  *      Copyright (C) 2012, Steven King <sfking@fdwdc.com>
   7  */
   8
   9 /***************************************************************************/
  10
  11 #include <linux/kernel.h>
  12 #include <linux/param.h>
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/platform_device.h>
  16 #include <asm/machdep.h>
  17 #include <asm/coldfire.h>
  18 #include <asm/mcfsim.h>
  19 #include <asm/mcfclk.h>
  20
  21 /***************************************************************************/
  22
  23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
  24 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  25 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
  26 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
  27 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
  28 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
  29 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
  30 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
  31 DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
  32
  33 struct clk *mcf_clks[] = {
  34         &clk_pll,
  35         &clk_sys,
  36         &clk_mcftmr0,
  37         &clk_mcftmr1,
  38         &clk_mcfuart0,
  39         &clk_mcfuart1,
  40         &clk_mcfqspi0,
  41         &clk_mcfi2c0,
  42         &clk_mcfi2c1,
  43         NULL
  44 };
  45
  46 /***************************************************************************/
  47
  48 static void __init m525x_qspi_init(void)
  49 {
  50 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  51         /* set the GPIO function for the qspi cs gpios */
  52         /* FIXME: replace with pinmux/pinctl support */
  53         u32 f = readl(MCFSIM2_GPIOFUNC);
  54         f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
  55         writel(f, MCFSIM2_GPIOFUNC);
  56
  57         /* QSPI irq setup */
  58         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
  59                MCFSIM_QSPIICR);
  60         mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
  61 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  62 }
  63
  64 static void __init m525x_i2c_init(void)
  65 {
  66 #if IS_ENABLED(CONFIG_I2C_IMX)
  67         u32 r;
  68
  69         /* first I2C controller uses regular irq setup */
  70         writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
  71                MCFSIM_I2CICR);
  72         mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
  73
  74         /* second I2C controller is completely different */
  75         r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
  76         r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
  77         r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
  78         writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
  79 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
  80 }
  81
  82 /***************************************************************************/
  83
  84 void __init config_BSP(char *commandp, int size)
  85 {
  86         mach_sched_init = hw_timer_init;
  87
  88         m525x_qspi_init();
  89         m525x_i2c_init();
  90 }
  91
  92 /***************************************************************************/