Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt

   1 Amlogic Meson AXG DWC PCIE SoC controller
   2
   3 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
   4 It shares common functions with the PCIe DesignWare core driver and
   5 inherits common properties defined in
   6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
   7
   8 Additional properties are described here:
   9
  10 Required properties:
  11 - compatible:
  12         should contain :
  13         - "amlogic,axg-pcie" for AXG SoC Family
  14         - "amlogic,g12a-pcie" for G12A SoC Family
  15         to identify the core.
  16 - reg:
  17         should contain the configuration address space.
  18 - reg-names: Must be
  19         - "elbi"        External local bus interface registers
  20         - "cfg"         Meson specific registers
  21         - "phy"         Meson PCIE PHY registers for AXG SoC Family
  22         - "config"      PCIe configuration space
  23 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
  24 - clocks: Must contain an entry for each entry in clock-names.
  25 - clock-names: Must include the following entries:
  26         - "pclk"       PCIe GEN 100M PLL clock
  27         - "port"       PCIe_x(A or B) RC clock gate
  28         - "general"    PCIe Phy clock
  29         - "mipi"       PCIe_x(A or B) 100M ref clock gate for AXG SoC Family
  30 - resets: phandle to the reset lines.
  31 - reset-names: must contain "phy" "port" and "apb"
  32        - "phy"         Share PHY reset for AXG SoC Family
  33        - "port"        Port A or B reset
  34        - "apb"         Share APB reset
  35 - phys: should contain a phandle to the shared phy for G12A SoC Family
  36 - device_type:
  37         should be "pci". As specified in designware-pcie.txt
  38
  39
  40 Example configuration:
  41
  42         pcie: pcie@f9800000 {
  43                         compatible = "amlogic,axg-pcie", "snps,dw-pcie";
  44                         reg = <0x0 0xf9800000 0x0 0x400000
  45                                         0x0 0xff646000 0x0 0x2000
  46                                         0x0 0xff644000 0x0 0x2000
  47                                         0x0 0xf9f00000 0x0 0x100000>;
  48                         reg-names = "elbi", "cfg", "phy", "config";
  49                         reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
  50                         interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
  51                         #interrupt-cells = <1>;
  52                         interrupt-map-mask = <0 0 0 0>;
  53                         interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
  54                         bus-range = <0x0 0xff>;
  55                         #address-cells = <3>;
  56                         #size-cells = <2>;
  57                         device_type = "pci";
  58                         ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
  59
  60                         clocks = <&clkc CLKID_USB
  61                                         &clkc CLKID_MIPI_ENABLE
  62                                         &clkc CLKID_PCIE_A
  63                                         &clkc CLKID_PCIE_CML_EN0>;
  64                         clock-names = "general",
  65                                         "mipi",
  66                                         "pclk",
  67                                         "port";
  68                         resets = <&reset RESET_PCIE_PHY>,
  69                                 <&reset RESET_PCIE_A>,
  70                                 <&reset RESET_PCIE_APB>;
  71                         reset-names = "phy",
  72                                         "port",
  73                                         "apb";
  74         };