| blob | 2932a29ae272e2e3ad8f171549f65d6b22913b6b |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada 375 family SoC
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 */
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
15 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
21 model = "Marvell Armada 375 family SoC";
22 compatible = "marvell,armada375";
24 aliases {
25 gpio0 = &gpio0;
26 gpio1 = &gpio1;
27 gpio2 = &gpio2;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 };
32 clocks {
33 /* 1 GHz fixed main PLL */
34 mainpll: mainpll {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <1000000000>;
38 };
39 /* 25 MHz reference crystal */
40 refclk: oscillator {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
44 };
45 };
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 enable-method = "marvell,armada-375-smp";
52 cpu0: cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a9";
55 reg = <0>;
56 };
57 cpu1: cpu@1 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a9";
60 reg = <1>;
61 };
62 };
64 pmu {
65 compatible = "arm,cortex-a9-pmu";
66 interrupts-extended = <&mpic 3>;
67 };
69 soc {
70 compatible = "marvell,armada375-mbus", "simple-bus";
71 #address-cells = <2>;
72 #size-cells = <1>;
73 controller = <&mbusc>;
74 interrupt-parent = <&gic>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
78 bootrom {
79 compatible = "marvell,bootrom";
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
81 };
83 devbus_bootcs: devbus-bootcs {
84 compatible = "marvell,mvebu-devbus";
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
87 #address-cells = <1>;
88 #size-cells = <1>;
89 clocks = <&coreclk 0>;
90 status = "disabled";
91 };
93 devbus_cs0: devbus-cs0 {
94 compatible = "marvell,mvebu-devbus";
95 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
96 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
97 #address-cells = <1>;
98 #size-cells = <1>;
99 clocks = <&coreclk 0>;
100 status = "disabled";
101 };
103 devbus_cs1: devbus-cs1 {
104 compatible = "marvell,mvebu-devbus";
105 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
106 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
107 #address-cells = <1>;
108 #size-cells = <1>;
109 clocks = <&coreclk 0>;
110 status = "disabled";
111 };
113 devbus_cs2: devbus-cs2 {
114 compatible = "marvell,mvebu-devbus";
115 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
116 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
117 #address-cells = <1>;
118 #size-cells = <1>;
119 clocks = <&coreclk 0>;
120 status = "disabled";
121 };
123 devbus_cs3: devbus-cs3 {
124 compatible = "marvell,mvebu-devbus";
125 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
126 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
127 #address-cells = <1>;
128 #size-cells = <1>;
129 clocks = <&coreclk 0>;
130 status = "disabled";
131 };
133 internal-regs {
134 compatible = "simple-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
139 L2: cache-controller@8000 {
140 compatible = "arm,pl310-cache";
141 reg = <0x8000 0x1000>;
142 cache-unified;
143 cache-level = <2>;
144 arm,double-linefill-incr = <0>;
145 arm,double-linefill-wrap = <0>;
146 arm,double-linefill = <0>;
147 prefetch-data = <1>;
148 };
150 scu: scu@c000 {
151 compatible = "arm,cortex-a9-scu";
152 reg = <0xc000 0x58>;
153 };
155 timer0: timer@c600 {
156 compatible = "arm,cortex-a9-twd-timer";
157 reg = <0xc600 0x20>;
158 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
159 clocks = <&coreclk 2>;
160 };
162 gic: interrupt-controller@d000 {
163 compatible = "arm,cortex-a9-gic";
164 #interrupt-cells = <3>;
165 #size-cells = <0>;
166 interrupt-controller;
167 reg = <0xd000 0x1000>,
168 <0xc100 0x100>;
169 };
171 mdio: mdio@c0054 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "marvell,orion-mdio";
175 reg = <0xc0054 0x4>;
176 clocks = <&gateclk 19>;
177 };
179 /* Network controller */
180 ethernet: ethernet@f0000 {
181 compatible = "marvell,armada-375-pp2";
182 reg = <0xf0000 0xa000>, /* Packet Processor regs */
183 <0xc0000 0x3060>, /* LMS regs */
184 <0xc4000 0x100>, /* eth0 regs */
185 <0xc5000 0x100>; /* eth1 regs */
186 clocks = <&gateclk 3>, <&gateclk 19>;
187 clock-names = "pp_clk", "gop_clk";
188 status = "disabled";
190 eth0: eth0 {
191 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
192 port-id = <0>;
193 status = "disabled";
194 };
196 eth1: eth1 {
197 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
198 port-id = <1>;
199 status = "disabled";
200 };
201 };
203 rtc: rtc@10300 {
204 compatible = "marvell,orion-rtc";
205 reg = <0x10300 0x20>;
206 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
207 };
209 spi0: spi@10600 {
210 compatible = "marvell,armada-375-spi",
211 "marvell,orion-spi";
212 reg = <0x10600 0x50>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215 cell-index = <0>;
216 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&coreclk 0>;
218 status = "disabled";
219 };
221 spi1: spi@10680 {
222 compatible = "marvell,armada-375-spi",
223 "marvell,orion-spi";
224 reg = <0x10680 0x50>;
225 #address-cells = <1>;
226 #size-cells = <0>;
227 cell-index = <1>;
228 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&coreclk 0>;
230 status = "disabled";
231 };
233 i2c0: i2c@11000 {
234 compatible = "marvell,mv64xxx-i2c";
235 reg = <0x11000 0x20>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
239 timeout-ms = <1000>;
240 clocks = <&coreclk 0>;
241 status = "disabled";
242 };
244 i2c1: i2c@11100 {
245 compatible = "marvell,mv64xxx-i2c";
246 reg = <0x11100 0x20>;
247 #address-cells = <1>;
248 #size-cells = <0>;
249 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
250 timeout-ms = <1000>;
251 clocks = <&coreclk 0>;
252 status = "disabled";
253 };
255 uart0: serial@12000 {
256 compatible = "snps,dw-apb-uart";
257 reg = <0x12000 0x100>;
258 reg-shift = <2>;
259 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
260 reg-io-width = <1>;
261 clocks = <&coreclk 0>;
262 status = "disabled";
263 };
265 uart1: serial@12100 {
266 compatible = "snps,dw-apb-uart";
267 reg = <0x12100 0x100>;
268 reg-shift = <2>;
269 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
270 reg-io-width = <1>;
271 clocks = <&coreclk 0>;
272 status = "disabled";
273 };
275 pinctrl: pinctrl@18000 {
276 compatible = "marvell,mv88f6720-pinctrl";
277 reg = <0x18000 0x24>;
279 i2c0_pins: i2c0-pins {
280 marvell,pins = "mpp14", "mpp15";
281 marvell,function = "i2c0";
282 };
284 i2c1_pins: i2c1-pins {
285 marvell,pins = "mpp61", "mpp62";
286 marvell,function = "i2c1";
287 };
289 nand_pins: nand-pins {
290 marvell,pins = "mpp0", "mpp1", "mpp2",
291 "mpp3", "mpp4", "mpp5",
292 "mpp6", "mpp7", "mpp8",
293 "mpp9", "mpp10", "mpp11",
294 "mpp12", "mpp13";
295 marvell,function = "nand";
296 };
298 sdio_pins: sdio-pins {
299 marvell,pins = "mpp24", "mpp25", "mpp26",
300 "mpp27", "mpp28", "mpp29";
301 marvell,function = "sd";
302 };
304 spi0_pins: spi0-pins {
305 marvell,pins = "mpp0", "mpp1", "mpp4",
306 "mpp5", "mpp8", "mpp9";
307 marvell,function = "spi0";
308 };
309 };
311 gpio0: gpio@18100 {
312 compatible = "marvell,orion-gpio";
313 reg = <0x18100 0x40>;
314 ngpios = <32>;
315 gpio-controller;
316 #gpio-cells = <2>;
317 interrupt-controller;
318 #interrupt-cells = <2>;
319 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
323 };
325 gpio1: gpio@18140 {
326 compatible = "marvell,orion-gpio";
327 reg = <0x18140 0x40>;
328 ngpios = <32>;
329 gpio-controller;
330 #gpio-cells = <2>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
337 };
339 gpio2: gpio@18180 {
340 compatible = "marvell,orion-gpio";
341 reg = <0x18180 0x40>;
342 ngpios = <3>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
347 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
348 };
350 systemc: system-controller@18200 {
351 compatible = "marvell,armada-375-system-controller";
352 reg = <0x18200 0x100>;
353 };
355 gateclk: clock-gating-control@18220 {
356 compatible = "marvell,armada-375-gating-clock";
357 reg = <0x18220 0x4>;
358 clocks = <&coreclk 0>;
359 #clock-cells = <1>;
360 };
362 usbcluster: usb-cluster@18400 {
363 compatible = "marvell,armada-375-usb-cluster";
364 reg = <0x18400 0x4>;
365 #phy-cells = <1>;
366 };
368 mbusc: mbus-controller@20000 {
369 compatible = "marvell,mbus-controller";
370 reg = <0x20000 0x100>, <0x20180 0x20>;
371 };
373 mpic: interrupt-controller@20a00 {
374 compatible = "marvell,mpic";
375 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
376 #interrupt-cells = <1>;
377 #size-cells = <1>;
378 interrupt-controller;
379 msi-controller;
380 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
381 };
383 timer1: timer@20300 {
384 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
385 reg = <0x20300 0x30>, <0x21040 0x30>;
386 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
387 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
388 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
389 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
390 <&mpic 5>,
391 <&mpic 6>;
392 clocks = <&coreclk 0>, <&refclk>;
393 clock-names = "nbclk", "fixed";
394 };
396 watchdog: watchdog@20300 {
397 compatible = "marvell,armada-375-wdt";
398 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
399 clocks = <&coreclk 0>, <&refclk>;
400 clock-names = "nbclk", "fixed";
401 };
403 cpurst: cpurst@20800 {
404 compatible = "marvell,armada-370-cpu-reset";
405 reg = <0x20800 0x10>;
406 };
408 coherencyfab: coherency-fabric@21010 {
409 compatible = "marvell,armada-375-coherency-fabric";
410 reg = <0x21010 0x1c>;
411 };
413 usb0: usb@50000 {
414 compatible = "marvell,orion-ehci";
415 reg = <0x50000 0x500>;
416 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&gateclk 18>;
418 phys = <&usbcluster PHY_TYPE_USB2>;
419 phy-names = "usb";
420 status = "disabled";
421 };
423 usb1: usb@54000 {
424 compatible = "marvell,orion-ehci";
425 reg = <0x54000 0x500>;
426 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&gateclk 26>;
428 status = "disabled";
429 };
431 usb2: usb3@58000 {
432 compatible = "marvell,armada-375-xhci";
433 reg = <0x58000 0x20000>,<0x5b880 0x80>;
434 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&gateclk 16>;
436 phys = <&usbcluster PHY_TYPE_USB3>;
437 phy-names = "usb";
438 status = "disabled";
439 };
441 xor0: xor@60800 {
442 compatible = "marvell,orion-xor";
443 reg = <0x60800 0x100
444 0x60A00 0x100>;
445 clocks = <&gateclk 22>;
446 status = "okay";
448 xor00 {
449 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
450 dmacap,memcpy;
451 dmacap,xor;
452 };
453 xor01 {
454 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
455 dmacap,memcpy;
456 dmacap,xor;
457 dmacap,memset;
458 };
459 };
461 xor1: xor@60900 {
462 compatible = "marvell,orion-xor";
463 reg = <0x60900 0x100
464 0x60b00 0x100>;
465 clocks = <&gateclk 23>;
466 status = "okay";
468 xor10 {
469 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
470 dmacap,memcpy;
471 dmacap,xor;
472 };
473 xor11 {
474 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
475 dmacap,memcpy;
476 dmacap,xor;
477 dmacap,memset;
478 };
479 };
481 cesa: crypto@90000 {
482 compatible = "marvell,armada-375-crypto";
483 reg = <0x90000 0x10000>;
484 reg-names = "regs";
485 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&gateclk 30>, <&gateclk 31>,
488 <&gateclk 28>, <&gateclk 29>;
489 clock-names = "cesa0", "cesa1",
490 "cesaz0", "cesaz1";
491 marvell,crypto-srams = <&crypto_sram0>,
492 <&crypto_sram1>;
493 marvell,crypto-sram-size = <0x800>;
494 };
496 sata: sata@a0000 {
497 compatible = "marvell,armada-370-sata";
498 reg = <0xa0000 0x5000>;
499 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&gateclk 14>, <&gateclk 20>;
501 clock-names = "0", "1";
502 status = "disabled";
503 };
505 nand_controller: nand-controller@d0000 {
506 compatible = "marvell,armada370-nand-controller";
507 reg = <0xd0000 0x54>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&gateclk 11>;
512 status = "disabled";
513 };
515 sdio: mvsdio@d4000 {
516 compatible = "marvell,orion-sdio";
517 reg = <0xd4000 0x200>;
518 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&gateclk 17>;
520 bus-width = <4>;
521 cap-sdio-irq;
522 cap-sd-highspeed;
523 cap-mmc-highspeed;
524 status = "disabled";
525 };
527 thermal: thermal@e8078 {
528 compatible = "marvell,armada375-thermal";
529 reg = <0xe8078 0x4>, <0xe807c 0x8>;
530 status = "okay";
531 };
533 coreclk: mvebu-sar@e8204 {
534 compatible = "marvell,armada-375-core-clock";
535 reg = <0xe8204 0x04>;
536 #clock-cells = <1>;
537 };
539 coredivclk: corediv-clock@e8250 {
540 compatible = "marvell,armada-375-corediv-clock";
541 reg = <0xe8250 0xc>;
542 #clock-cells = <1>;
543 clocks = <&mainpll>;
544 clock-output-names = "nand";
545 };
546 };
548 pciec: pcie@82000000 {
549 compatible = "marvell,armada-370-pcie";
550 status = "disabled";
551 device_type = "pci";
553 #address-cells = <3>;
554 #size-cells = <2>;
556 msi-parent = <&mpic>;
557 bus-range = <0x00 0xff>;
559 ranges =
560 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
561 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
562 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
563 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
564 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
565 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
567 pcie0: pcie@1,0 {
568 device_type = "pci";
569 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
570 reg = <0x0800 0 0 0 0>;
571 #address-cells = <3>;
572 #size-cells = <2>;
573 #interrupt-cells = <1>;
574 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
575 0x81000000 0 0 0x81000000 0x1 0 1 0>;
576 bus-range = <0x00 0xff>;
577 interrupt-map-mask = <0 0 0 0>;
578 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
579 marvell,pcie-port = <0>;
580 marvell,pcie-lane = <0>;
581 clocks = <&gateclk 5>;
582 status = "disabled";
583 };
585 pcie1: pcie@2,0 {
586 device_type = "pci";
587 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
588 reg = <0x1000 0 0 0 0>;
589 #address-cells = <3>;
590 #size-cells = <2>;
591 #interrupt-cells = <1>;
592 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
593 0x81000000 0 0 0x81000000 0x2 0 1 0>;
594 bus-range = <0x00 0xff>;
595 interrupt-map-mask = <0 0 0 0>;
596 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
597 marvell,pcie-port = <0>;
598 marvell,pcie-lane = <1>;
599 clocks = <&gateclk 6>;
600 status = "disabled";
601 };
603 };
605 crypto_sram0: sa-sram0 {
606 compatible = "mmio-sram";
607 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
608 clocks = <&gateclk 30>;
609 #address-cells = <1>;
610 #size-cells = <1>;
611 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
612 };
614 crypto_sram1: sa-sram1 {
615 compatible = "mmio-sram";
616 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
617 clocks = <&gateclk 31>;
618 #address-cells = <1>;
619 #size-cells = <1>;
620 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
621 };
622 };
623 };