| blob | 839491628e87b392cce339a83b8ec261ab70cbf3 |
1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/soc/bcm2835-pm.h>
8 /* firmware-provided startup stubs live here, where the secondary CPUs are
9 * spinning.
10 */
11 /memreserve/ 0x00000000 0x00001000;
13 /* This include file covers the common peripherals and configuration between
14 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
15 * bcm2835.dtsi and bcm2836.dtsi.
16 */
18 / {
19 compatible = "brcm,bcm2835";
20 model = "BCM2835";
21 #address-cells = <1>;
22 #size-cells = <1>;
24 aliases {
25 serial0 = &uart0;
26 serial1 = &uart1;
27 };
29 chosen {
30 stdout-path = "serial0:115200n8";
31 };
33 thermal-zones {
34 cpu_thermal: cpu-thermal {
35 polling-delay-passive = <0>;
36 polling-delay = <1000>;
38 trips {
39 cpu-crit {
40 temperature = <90000>;
41 hysteresis = <0>;
42 type = "critical";
43 };
44 };
46 cooling-maps {
47 };
48 };
49 };
51 soc {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
56 system_timer: timer@7e003000 {
57 compatible = "brcm,bcm2835-system-timer";
58 reg = <0x7e003000 0x1000>;
59 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
60 /* This could be a reference to BCM2835_CLOCK_TIMER,
61 * but we don't have the driver using the common clock
62 * support yet.
63 */
64 clock-frequency = <1000000>;
65 };
67 txp: txp@7e004000 {
68 compatible = "brcm,bcm2835-txp";
69 reg = <0x7e004000 0x20>;
70 interrupts = <1 11>;
71 };
73 clocks: cprman@7e101000 {
74 compatible = "brcm,bcm2835-cprman";
75 #clock-cells = <1>;
76 reg = <0x7e101000 0x2000>;
78 /* CPRMAN derives almost everything from the
79 * platform's oscillator. However, the DSI
80 * pixel clocks come from the DSI analog PHY.
81 */
82 clocks = <&clk_osc>,
83 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
84 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
85 };
87 rng@7e104000 {
88 compatible = "brcm,bcm2835-rng";
89 reg = <0x7e104000 0x10>;
90 interrupts = <2 29>;
91 };
93 mailbox: mailbox@7e00b880 {
94 compatible = "brcm,bcm2835-mbox";
95 reg = <0x7e00b880 0x40>;
96 interrupts = <0 1>;
97 #mbox-cells = <0>;
98 };
100 gpio: gpio@7e200000 {
101 compatible = "brcm,bcm2835-gpio";
102 reg = <0x7e200000 0xb4>;
103 /*
104 * The GPIO IP block is designed for 3 banks of GPIOs.
105 * Each bank has a GPIO interrupt for itself.
106 * There is an overall "any bank" interrupt.
107 * In order, these are GIC interrupts 17, 18, 19, 20.
108 * Since the BCM2835 only has 2 banks, the 2nd bank
109 * interrupt output appears to be mirrored onto the
110 * 3rd bank's interrupt signal.
111 * So, a bank0 interrupt shows up on 17, 20, and
112 * a bank1 interrupt shows up on 18, 19, 20!
113 */
114 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
116 gpio-controller;
117 #gpio-cells = <2>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
122 /* Defines common pin muxing groups
123 *
124 * While each pin can have its mux selected
125 * for various functions individually, some
126 * groups only make sense to switch to a
127 * particular function together.
128 */
129 dpi_gpio0: dpi_gpio0 {
130 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
131 12 13 14 15 16 17 18 19
132 20 21 22 23 24 25 26 27>;
133 brcm,function = <BCM2835_FSEL_ALT2>;
134 };
135 emmc_gpio22: emmc_gpio22 {
136 brcm,pins = <22 23 24 25 26 27>;
137 brcm,function = <BCM2835_FSEL_ALT3>;
138 };
139 emmc_gpio34: emmc_gpio34 {
140 brcm,pins = <34 35 36 37 38 39>;
141 brcm,function = <BCM2835_FSEL_ALT3>;
142 brcm,pull = <BCM2835_PUD_OFF
143 BCM2835_PUD_UP
144 BCM2835_PUD_UP
145 BCM2835_PUD_UP
146 BCM2835_PUD_UP
147 BCM2835_PUD_UP>;
148 };
149 emmc_gpio48: emmc_gpio48 {
150 brcm,pins = <48 49 50 51 52 53>;
151 brcm,function = <BCM2835_FSEL_ALT3>;
152 };
154 gpclk0_gpio4: gpclk0_gpio4 {
155 brcm,pins = <4>;
156 brcm,function = <BCM2835_FSEL_ALT0>;
157 };
158 gpclk1_gpio5: gpclk1_gpio5 {
159 brcm,pins = <5>;
160 brcm,function = <BCM2835_FSEL_ALT0>;
161 };
162 gpclk1_gpio42: gpclk1_gpio42 {
163 brcm,pins = <42>;
164 brcm,function = <BCM2835_FSEL_ALT0>;
165 };
166 gpclk1_gpio44: gpclk1_gpio44 {
167 brcm,pins = <44>;
168 brcm,function = <BCM2835_FSEL_ALT0>;
169 };
170 gpclk2_gpio6: gpclk2_gpio6 {
171 brcm,pins = <6>;
172 brcm,function = <BCM2835_FSEL_ALT0>;
173 };
174 gpclk2_gpio43: gpclk2_gpio43 {
175 brcm,pins = <43>;
176 brcm,function = <BCM2835_FSEL_ALT0>;
177 brcm,pull = <BCM2835_PUD_OFF>;
178 };
180 i2c0_gpio0: i2c0_gpio0 {
181 brcm,pins = <0 1>;
182 brcm,function = <BCM2835_FSEL_ALT0>;
183 };
184 i2c0_gpio28: i2c0_gpio28 {
185 brcm,pins = <28 29>;
186 brcm,function = <BCM2835_FSEL_ALT0>;
187 };
188 i2c0_gpio44: i2c0_gpio44 {
189 brcm,pins = <44 45>;
190 brcm,function = <BCM2835_FSEL_ALT1>;
191 };
192 i2c1_gpio2: i2c1_gpio2 {
193 brcm,pins = <2 3>;
194 brcm,function = <BCM2835_FSEL_ALT0>;
195 };
196 i2c1_gpio44: i2c1_gpio44 {
197 brcm,pins = <44 45>;
198 brcm,function = <BCM2835_FSEL_ALT2>;
199 };
201 jtag_gpio22: jtag_gpio22 {
202 brcm,pins = <22 23 24 25 26 27>;
203 brcm,function = <BCM2835_FSEL_ALT4>;
204 };
206 pcm_gpio18: pcm_gpio18 {
207 brcm,pins = <18 19 20 21>;
208 brcm,function = <BCM2835_FSEL_ALT0>;
209 };
210 pcm_gpio28: pcm_gpio28 {
211 brcm,pins = <28 29 30 31>;
212 brcm,function = <BCM2835_FSEL_ALT2>;
213 };
215 sdhost_gpio48: sdhost_gpio48 {
216 brcm,pins = <48 49 50 51 52 53>;
217 brcm,function = <BCM2835_FSEL_ALT0>;
218 };
220 spi0_gpio7: spi0_gpio7 {
221 brcm,pins = <7 8 9 10 11>;
222 brcm,function = <BCM2835_FSEL_ALT0>;
223 };
224 spi0_gpio35: spi0_gpio35 {
225 brcm,pins = <35 36 37 38 39>;
226 brcm,function = <BCM2835_FSEL_ALT0>;
227 };
228 spi1_gpio16: spi1_gpio16 {
229 brcm,pins = <16 17 18 19 20 21>;
230 brcm,function = <BCM2835_FSEL_ALT4>;
231 };
232 spi2_gpio40: spi2_gpio40 {
233 brcm,pins = <40 41 42 43 44 45>;
234 brcm,function = <BCM2835_FSEL_ALT4>;
235 };
237 uart0_gpio14: uart0_gpio14 {
238 brcm,pins = <14 15>;
239 brcm,function = <BCM2835_FSEL_ALT0>;
240 };
241 /* Separate from the uart0_gpio14 group
242 * because it conflicts with spi1_gpio16, and
243 * people often run uart0 on the two pins
244 * without flow control.
245 */
246 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
247 brcm,pins = <16 17>;
248 brcm,function = <BCM2835_FSEL_ALT3>;
249 };
250 uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
251 brcm,pins = <30 31>;
252 brcm,function = <BCM2835_FSEL_ALT3>;
253 brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
254 };
255 uart0_gpio32: uart0_gpio32 {
256 brcm,pins = <32 33>;
257 brcm,function = <BCM2835_FSEL_ALT3>;
258 brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
259 };
260 uart0_gpio36: uart0_gpio36 {
261 brcm,pins = <36 37>;
262 brcm,function = <BCM2835_FSEL_ALT2>;
263 };
264 uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
265 brcm,pins = <38 39>;
266 brcm,function = <BCM2835_FSEL_ALT2>;
267 };
269 uart1_gpio14: uart1_gpio14 {
270 brcm,pins = <14 15>;
271 brcm,function = <BCM2835_FSEL_ALT5>;
272 };
273 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
274 brcm,pins = <16 17>;
275 brcm,function = <BCM2835_FSEL_ALT5>;
276 };
277 uart1_gpio32: uart1_gpio32 {
278 brcm,pins = <32 33>;
279 brcm,function = <BCM2835_FSEL_ALT5>;
280 };
281 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
282 brcm,pins = <30 31>;
283 brcm,function = <BCM2835_FSEL_ALT5>;
284 };
285 uart1_gpio40: uart1_gpio40 {
286 brcm,pins = <40 41>;
287 brcm,function = <BCM2835_FSEL_ALT5>;
288 };
289 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
290 brcm,pins = <42 43>;
291 brcm,function = <BCM2835_FSEL_ALT5>;
292 };
293 };
295 uart0: serial@7e201000 {
296 compatible = "arm,pl011", "arm,primecell";
297 reg = <0x7e201000 0x200>;
298 interrupts = <2 25>;
299 clocks = <&clocks BCM2835_CLOCK_UART>,
300 <&clocks BCM2835_CLOCK_VPU>;
301 clock-names = "uartclk", "apb_pclk";
302 arm,primecell-periphid = <0x00241011>;
303 };
305 sdhost: mmc@7e202000 {
306 compatible = "brcm,bcm2835-sdhost";
307 reg = <0x7e202000 0x100>;
308 interrupts = <2 24>;
309 clocks = <&clocks BCM2835_CLOCK_VPU>;
310 status = "disabled";
311 };
313 i2s: i2s@7e203000 {
314 compatible = "brcm,bcm2835-i2s";
315 reg = <0x7e203000 0x24>;
316 clocks = <&clocks BCM2835_CLOCK_PCM>;
317 status = "disabled";
318 };
320 spi: spi@7e204000 {
321 compatible = "brcm,bcm2835-spi";
322 reg = <0x7e204000 0x200>;
323 interrupts = <2 22>;
324 clocks = <&clocks BCM2835_CLOCK_VPU>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327 status = "disabled";
328 };
330 i2c0: i2c@7e205000 {
331 compatible = "brcm,bcm2835-i2c";
332 reg = <0x7e205000 0x200>;
333 interrupts = <2 21>;
334 clocks = <&clocks BCM2835_CLOCK_VPU>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 status = "disabled";
338 };
340 dpi: dpi@7e208000 {
341 compatible = "brcm,bcm2835-dpi";
342 reg = <0x7e208000 0x8c>;
343 clocks = <&clocks BCM2835_CLOCK_VPU>,
344 <&clocks BCM2835_CLOCK_DPI>;
345 clock-names = "core", "pixel";
346 #address-cells = <1>;
347 #size-cells = <0>;
348 status = "disabled";
349 };
351 dsi0: dsi@7e209000 {
352 compatible = "brcm,bcm2835-dsi0";
353 reg = <0x7e209000 0x78>;
354 interrupts = <2 4>;
355 #address-cells = <1>;
356 #size-cells = <0>;
357 #clock-cells = <1>;
359 clocks = <&clocks BCM2835_PLLA_DSI0>,
360 <&clocks BCM2835_CLOCK_DSI0E>,
361 <&clocks BCM2835_CLOCK_DSI0P>;
362 clock-names = "phy", "escape", "pixel";
364 clock-output-names = "dsi0_byte",
365 "dsi0_ddr2",
366 "dsi0_ddr";
368 };
370 aux: aux@7e215000 {
371 compatible = "brcm,bcm2835-aux";
372 #clock-cells = <1>;
373 reg = <0x7e215000 0x8>;
374 clocks = <&clocks BCM2835_CLOCK_VPU>;
375 };
377 uart1: serial@7e215040 {
378 compatible = "brcm,bcm2835-aux-uart";
379 reg = <0x7e215040 0x40>;
380 interrupts = <1 29>;
381 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
382 status = "disabled";
383 };
385 spi1: spi@7e215080 {
386 compatible = "brcm,bcm2835-aux-spi";
387 reg = <0x7e215080 0x40>;
388 interrupts = <1 29>;
389 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
390 #address-cells = <1>;
391 #size-cells = <0>;
392 status = "disabled";
393 };
395 spi2: spi@7e2150c0 {
396 compatible = "brcm,bcm2835-aux-spi";
397 reg = <0x7e2150c0 0x40>;
398 interrupts = <1 29>;
399 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
400 #address-cells = <1>;
401 #size-cells = <0>;
402 status = "disabled";
403 };
405 pwm: pwm@7e20c000 {
406 compatible = "brcm,bcm2835-pwm";
407 reg = <0x7e20c000 0x28>;
408 clocks = <&clocks BCM2835_CLOCK_PWM>;
409 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
410 assigned-clock-rates = <10000000>;
411 #pwm-cells = <2>;
412 status = "disabled";
413 };
415 sdhci: sdhci@7e300000 {
416 compatible = "brcm,bcm2835-sdhci";
417 reg = <0x7e300000 0x100>;
418 interrupts = <2 30>;
419 clocks = <&clocks BCM2835_CLOCK_EMMC>;
420 status = "disabled";
421 };
423 hvs@7e400000 {
424 compatible = "brcm,bcm2835-hvs";
425 reg = <0x7e400000 0x6000>;
426 interrupts = <2 1>;
427 };
429 dsi1: dsi@7e700000 {
430 compatible = "brcm,bcm2835-dsi1";
431 reg = <0x7e700000 0x8c>;
432 interrupts = <2 12>;
433 #address-cells = <1>;
434 #size-cells = <0>;
435 #clock-cells = <1>;
437 clocks = <&clocks BCM2835_PLLD_DSI1>,
438 <&clocks BCM2835_CLOCK_DSI1E>,
439 <&clocks BCM2835_CLOCK_DSI1P>;
440 clock-names = "phy", "escape", "pixel";
442 clock-output-names = "dsi1_byte",
443 "dsi1_ddr2",
444 "dsi1_ddr";
446 status = "disabled";
447 };
449 i2c1: i2c@7e804000 {
450 compatible = "brcm,bcm2835-i2c";
451 reg = <0x7e804000 0x1000>;
452 interrupts = <2 21>;
453 clocks = <&clocks BCM2835_CLOCK_VPU>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 status = "disabled";
457 };
459 vec: vec@7e806000 {
460 compatible = "brcm,bcm2835-vec";
461 reg = <0x7e806000 0x1000>;
462 clocks = <&clocks BCM2835_CLOCK_VEC>;
463 interrupts = <2 27>;
464 status = "disabled";
465 };
467 usb: usb@7e980000 {
468 compatible = "brcm,bcm2835-usb";
469 reg = <0x7e980000 0x10000>;
470 interrupts = <1 9>;
471 #address-cells = <1>;
472 #size-cells = <0>;
473 clocks = <&clk_usb>;
474 clock-names = "otg";
475 phys = <&usbphy>;
476 phy-names = "usb2-phy";
477 };
478 };
480 clocks {
481 /* The oscillator is the root of the clock tree. */
482 clk_osc: clk-osc {
483 compatible = "fixed-clock";
484 #clock-cells = <0>;
485 clock-output-names = "osc";
486 clock-frequency = <19200000>;
487 };
489 clk_usb: clk-usb {
490 compatible = "fixed-clock";
491 #clock-cells = <0>;
492 clock-output-names = "otg";
493 clock-frequency = <480000000>;
494 };
495 };
497 usbphy: phy {
498 compatible = "usb-nop-xceiv";
499 #phy-cells = <0>;
500 };
501 };