arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/sound/fsl-imx-audmux.h>
   8
   9 / {
  10         chosen {
  11                 stdout-path = &uart1;
  12         };
  13
  14         aliases {
  15                 mdio-gpio0 = &mdio1;
  16                 rtc0 = &ds1341;
  17         };
  18
  19         mdio1: mdio {
  20                 compatible = "virtual,mdio-gpio";
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23                 pinctrl-names = "default";
  24                 pinctrl-0 = <&pinctrl_mdio1>;
  25                 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
  26                          &gpio6 4 GPIO_ACTIVE_HIGH>;
  27
  28                 phy: ethernet-phy@0 {
  29                         pinctrl-0 = <&pinctrl_rmii_phy_irq>;
  30                         pinctrl-names = "default";
  31                         reg = <0>;
  32                         interrupt-parent = <&gpio3>;
  33                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
  34                 };
  35         };
  36
  37         reg_28p0v: regulator-28p0v {
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "28V_IN";
  40                 regulator-min-microvolt = <28000000>;
  41                 regulator-max-microvolt = <28000000>;
  42                 regulator-always-on;
  43         };
  44
  45         reg_12p0v: regulator-12p0v {
  46                 compatible = "regulator-fixed";
  47                 vin-supply = <&reg_28p0v>;
  48                 regulator-name = "12V_MAIN";
  49                 regulator-min-microvolt = <12000000>;
  50                 regulator-max-microvolt = <12000000>;
  51                 regulator-always-on;
  52         };
  53
  54         reg_5p0v_main: regulator-5p0v-main {
  55                 compatible = "regulator-fixed";
  56                 vin-supply = <&reg_12p0v>;
  57                 regulator-name = "5V_MAIN";
  58                 regulator-min-microvolt = <5000000>;
  59                 regulator-max-microvolt = <5000000>;
  60                 regulator-always-on;
  61         };
  62
  63         reg_5p0v_user_usb: regulator-5p0v-user-usb {
  64                 compatible = "regulator-fixed";
  65                 pinctrl-names = "default";
  66                 pinctrl-0 = <&pinctrl_reg_user_usb>;
  67                 vin-supply = <&reg_5p0v_main>;
  68                 regulator-name = "5V_USER_USB";
  69                 regulator-min-microvolt = <5000000>;
  70                 regulator-max-microvolt = <5000000>;
  71                 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
  72                 startup-delay-us = <1000>;
  73         };
  74
  75         reg_3p3v_pmic: regulator-3p3v-pmic {
  76                 compatible = "regulator-fixed";
  77                 vin-supply = <&reg_12p0v>;
  78                 regulator-name = "PMIC_3V3";
  79                 regulator-min-microvolt = <3300000>;
  80                 regulator-max-microvolt = <3300000>;
  81                 regulator-always-on;
  82         };
  83
  84         reg_3p3v: regulator-3p3v {
  85                 compatible = "regulator-fixed";
  86                 vin-supply = <&reg_3p3v_pmic>;
  87                 regulator-name = "GEN_3V3";
  88                 regulator-min-microvolt = <3300000>;
  89                 regulator-max-microvolt = <3300000>;
  90                 regulator-always-on;
  91         };
  92
  93         reg_3p3v_sd: regulator-3p3v-sd {
  94                 compatible = "regulator-fixed";
  95                 pinctrl-names = "default";
  96                 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
  97                 vin-supply = <&reg_3p3v>;
  98                 regulator-name = "3V3_SD";
  99                 regulator-min-microvolt = <3300000>;
 100                 regulator-max-microvolt = <3300000>;
 101                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
 102                 startup-delay-us = <1000>;
 103                 enable-active-high;
 104                 regulator-always-on;
 105         };
 106
 107         reg_3p3v_display: regulator-3p3v-display {
 108                 compatible = "regulator-fixed";
 109                 vin-supply = <&reg_12p0v>;
 110                 regulator-name = "3V3_DISPLAY";
 111                 regulator-min-microvolt = <3300000>;
 112                 regulator-max-microvolt = <3300000>;
 113                 regulator-always-on;
 114         };
 115
 116         reg_3p3v_ssd: regulator-3p3v-ssd {
 117                 compatible = "regulator-fixed";
 118                 vin-supply = <&reg_12p0v>;
 119                 regulator-name = "3V3_SSD";
 120                 regulator-min-microvolt = <3300000>;
 121                 regulator-max-microvolt = <3300000>;
 122                 regulator-always-on;
 123         };
 124
 125         sound1 {
 126                 compatible = "simple-audio-card";
 127                 simple-audio-card,name = "Front";
 128                 simple-audio-card,format = "i2s";
 129                 simple-audio-card,bitclock-master = <&sound1_codec>;
 130                 simple-audio-card,frame-master = <&sound1_codec>;
 131                 simple-audio-card,widgets =
 132                         "Headphone", "Headphone Jack";
 133                 simple-audio-card,routing =
 134                         "Headphone Jack", "HPLEFT",
 135                         "Headphone Jack", "HPRIGHT",
 136                         "LEFTIN", "HPL",
 137                         "RIGHTIN", "HPR";
 138                 simple-audio-card,aux-devs = <&hpa1>;
 139
 140                 sound1_cpu: simple-audio-card,cpu {
 141                         sound-dai = <&ssi2>;
 142                 };
 143
 144                 sound1_codec: simple-audio-card,codec {
 145                         sound-dai = <&codec1>;
 146                         clocks = <&cs2000>;
 147                 };
 148         };
 149
 150         sound2 {
 151                 compatible = "simple-audio-card";
 152                 simple-audio-card,name = "Back";
 153                 simple-audio-card,format = "i2s";
 154                 simple-audio-card,bitclock-master = <&sound2_codec>;
 155                 simple-audio-card,frame-master = <&sound2_codec>;
 156                 simple-audio-card,widgets =
 157                         "Headphone", "Headphone Jack";
 158                 simple-audio-card,routing =
 159                         "Headphone Jack", "HPLEFT",
 160                         "Headphone Jack", "HPRIGHT",
 161                         "LEFTIN", "HPL",
 162                         "RIGHTIN", "HPR";
 163                 simple-audio-card,aux-devs = <&hpa2>;
 164
 165                 sound2_cpu: simple-audio-card,cpu {
 166                         sound-dai = <&ssi1>;
 167                 };
 168
 169                 sound2_codec: simple-audio-card,codec {
 170                         sound-dai = <&codec2>;
 171                         clocks = <&cs2000>;
 172                 };
 173         };
 174
 175         panel {
 176                 power-supply = <&reg_3p3v_display>;
 177                 backlight = <&sp_backlight>;
 178                 status = "disabled";
 179
 180                 port {
 181                         panel_in: endpoint {
 182                                 remote-endpoint = <&lvds0_out>;
 183                         };
 184                 };
 185         };
 186
 187         disp0: disp0 {
 188                 #address-cells = <1>;
 189                 #size-cells = <0>;
 190                 compatible = "fsl,imx-parallel-display";
 191                 pinctrl-names = "default";
 192                 pinctrl-0 = <&pinctrl_disp0>;
 193                 status = "disabled";
 194
 195                 port@0 {
 196                         reg = <0>;
 197
 198                         disp0_in_0: endpoint {
 199                                 remote-endpoint = <&ipu1_di0_disp0>;
 200                         };
 201                 };
 202
 203                 port@1 {
 204                         reg = <1>;
 205
 206                         disp0_out: endpoint {
 207                                 remote-endpoint = <&tc358767_in>;
 208                         };
 209                 };
 210         };
 211
 212         cs2000_ref: cs2000-ref {
 213                 compatible = "fixed-clock";
 214                 #clock-cells = <0>;
 215                 clock-frequency = <24576000>;
 216         };
 217
 218         cs2000_in_dummy: cs2000-in-dummy {
 219                 compatible = "fixed-clock";
 220                 #clock-cells = <0>;
 221                 clock-frequency = <0>;
 222         };
 223
 224         edp_refclk: edp-refclk {
 225                 compatible = "fixed-clock";
 226                 #clock-cells = <0>;
 227                 clock-frequency = <19200000>;
 228         };
 229 };
 230
 231 &cpu0 {
 232         fsl,soc-operating-points = <
 233                 /* ARM kHz  SOC-PU uV */
 234                 1200000 1300000
 235                 996000  1275000
 236                 852000  1275000
 237                 792000  1200000
 238                 396000  1200000
 239         >;
 240 };
 241
 242 &reg_arm {
 243         vin-supply = <&sw1a_reg>;
 244 };
 245
 246 &reg_pu {
 247         vin-supply = <&sw1c_reg>;
 248 };
 249
 250 &reg_soc {
 251         vin-supply = <&sw1c_reg>;
 252 };
 253
 254 &ldb {
 255         lvds-channel@0 {
 256                 port@4 {
 257                         reg = <4>;
 258
 259                         lvds0_out: endpoint {
 260                                 remote-endpoint = <&panel_in>;
 261                         };
 262                 };
 263         };
 264 };
 265
 266 &uart1 {
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&pinctrl_uart1>;
 269         status = "okay";
 270 };
 271
 272 &uart3 {
 273         pinctrl-names = "default";
 274         pinctrl-0 = <&pinctrl_uart3>;
 275         uart-has-rtscts;
 276         linux,rs485-enabled-at-boot-time;
 277         status = "okay";
 278 };
 279
 280 &uart4 {
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&pinctrl_uart4>;
 283         status = "okay";
 284
 285         rave-sp {
 286                 compatible = "zii,rave-sp-rdu2";
 287                 current-speed = <1000000>;
 288                 #address-cells = <1>;
 289                 #size-cells = <1>;
 290
 291                 watchdog {
 292                         compatible = "zii,rave-sp-watchdog";
 293                 };
 294
 295                 sp_backlight: backlight {
 296                         compatible = "zii,rave-sp-backlight";
 297                 };
 298
 299                 pwrbutton {
 300                         compatible = "zii,rave-sp-pwrbutton";
 301                 };
 302
 303                 eeprom@a3 {
 304                         compatible = "zii,rave-sp-eeprom";
 305                         reg = <0xa3 0x4000>;
 306                         #address-cells = <1>;
 307                         #size-cells = <1>;
 308                         zii,eeprom-name = "dds-eeprom";
 309                 };
 310
 311                 eeprom@a4 {
 312                         compatible = "zii,rave-sp-eeprom";
 313                         reg = <0xa4 0x4000>;
 314                         #address-cells = <1>;
 315                         #size-cells = <1>;
 316                         zii,eeprom-name = "main-eeprom";
 317                 };
 318         };
 319 };
 320
 321 &ecspi1 {
 322         pinctrl-names = "default";
 323         pinctrl-0 = <&pinctrl_ecspi1>;
 324         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
 325         status = "okay";
 326
 327         flash@0 {
 328                 compatible = "st,m25p128", "jedec,spi-nor";
 329                 spi-max-frequency = <20000000>;
 330                 reg = <0>;
 331         };
 332 };
 333
 334 &i2c1 {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pinctrl_i2c1>;
 337         clock-frequency = <100000>;
 338         status = "okay";
 339
 340         codec2: codec@18 {
 341                 compatible = "ti,tlv320dac3100";
 342                 pinctrl-names = "default";
 343                 pinctrl-0 = <&pinctrl_codec2>;
 344                 reg = <0x18>;
 345                 #sound-dai-cells = <0>;
 346                 HPVDD-supply = <&reg_3p3v>;
 347                 SPRVDD-supply = <&reg_3p3v>;
 348                 SPLVDD-supply = <&reg_3p3v>;
 349                 AVDD-supply = <&reg_3p3v>;
 350                 IOVDD-supply = <&reg_3p3v>;
 351                 DVDD-supply = <&vgen4_reg>;
 352                 reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 353         };
 354
 355         accel@1c {
 356                 pinctrl-names = "default";
 357                 pinctrl-0 = <&pinctrl_accel>;
 358                 compatible = "fsl,mma8451";
 359                 reg = <0x1c>;
 360                 interrupt-parent = <&gpio1>;
 361                 interrupt-names = "INT2";
 362                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 363                 vdd-supply = <&reg_3p3v>;
 364                 vddio-supply = <&reg_3p3v>;
 365         };
 366
 367         hpa2: amp@60 {
 368                 compatible = "ti,tpa6130a2";
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&pinctrl_tpa2>;
 371                 reg = <0x60>;
 372                 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 373                 Vdd-supply = <&reg_5p0v_main>;
 374         };
 375
 376         edp-bridge@68 {
 377                 compatible = "toshiba,tc358767";
 378                 pinctrl-names = "default";
 379                 pinctrl-0 = <&pinctrl_tc358767>;
 380                 reg = <0x68>;
 381                 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 382                 clock-names = "ref";
 383                 clocks = <&edp_refclk>;
 384                 status = "disabled";
 385
 386                 ports {
 387                         #address-cells = <1>;
 388                         #size-cells = <0>;
 389
 390                         port@1 {
 391                                 reg = <1>;
 392
 393                                 tc358767_in: endpoint {
 394                                         remote-endpoint = <&disp0_out>;
 395                                 };
 396                         };
 397                 };
 398         };
 399 };
 400
 401 &i2c2 {
 402         pinctrl-names = "default";
 403         pinctrl-0 = <&pinctrl_i2c2>;
 404         clock-frequency = <100000>;
 405         status = "okay";
 406
 407         pmic@8 {
 408                 compatible = "fsl,pfuze100";
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&pinctrl_pfuze100_irq>;
 411                 reg = <0x08>;
 412                 interrupt-parent = <&gpio7>;
 413                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 414
 415                 regulators {
 416                         sw1a_reg: sw1ab {
 417                                 regulator-min-microvolt = <300000>;
 418                                 regulator-max-microvolt = <1875000>;
 419                                 regulator-boot-on;
 420                                 regulator-always-on;
 421                                 regulator-ramp-delay = <6250>;
 422                         };
 423
 424                         sw1c_reg: sw1c {
 425                                 regulator-min-microvolt = <300000>;
 426                                 regulator-max-microvolt = <1875000>;
 427                                 regulator-boot-on;
 428                                 regulator-always-on;
 429                                 regulator-ramp-delay = <6250>;
 430                         };
 431
 432                         sw2_reg: sw2 {
 433                                 regulator-min-microvolt = <800000>;
 434                                 regulator-max-microvolt = <3000000>;
 435                                 regulator-boot-on;
 436                                 regulator-always-on;
 437                         };
 438
 439                         sw3a_reg: sw3a {
 440                                 regulator-min-microvolt = <400000>;
 441                                 regulator-max-microvolt = <1500000>;
 442                                 regulator-boot-on;
 443                                 regulator-always-on;
 444                         };
 445
 446                         sw3b_reg: sw3b {
 447                                 regulator-min-microvolt = <400000>;
 448                                 regulator-max-microvolt = <1500000>;
 449                                 regulator-boot-on;
 450                                 regulator-always-on;
 451                         };
 452
 453                         sw4_reg: sw4 {
 454                                 regulator-min-microvolt = <800000>;
 455                                 regulator-max-microvolt = <1800000>;
 456                                 regulator-boot-on;
 457                                 regulator-always-on;
 458                         };
 459
 460                         snvs_reg: vsnvs {
 461                                 regulator-min-microvolt = <1000000>;
 462                                 regulator-max-microvolt = <3000000>;
 463                                 regulator-boot-on;
 464                                 regulator-always-on;
 465                         };
 466
 467                         vref_reg: vrefddr {
 468                                 regulator-boot-on;
 469                                 regulator-always-on;
 470                         };
 471
 472                         vgen2_reg: vgen2 {
 473                                 regulator-min-microvolt = <1000000>;
 474                                 regulator-max-microvolt = <1500000>;
 475                                 regulator-always-on;
 476                         };
 477
 478                         vgen4_reg: vgen4 {
 479                                 regulator-min-microvolt = <1200000>;
 480                                 regulator-max-microvolt = <1800000>;
 481                                 regulator-always-on;
 482                         };
 483
 484                         vgen5_reg: vgen5 {
 485                                 regulator-min-microvolt = <1800000>;
 486                                 regulator-max-microvolt = <2500000>;
 487                                 regulator-always-on;
 488                         };
 489
 490                         vgen6_reg: vgen6 {
 491                                 regulator-min-microvolt = <1800000>;
 492                                 regulator-max-microvolt = <2800000>;
 493                                 regulator-always-on;
 494                         };
 495                 };
 496         };
 497
 498         watchdog@38 {
 499                 compatible = "zii,rave-wdt";
 500                 reg = <0x38>;
 501         };
 502
 503         temp-sense@48 {
 504                 compatible = "national,lm75";
 505                 reg = <0x48>;
 506         };
 507
 508         cs2000: clkgen@4e {
 509                 compatible = "cirrus,cs2000-cp";
 510                 reg = <0x4e>;
 511                 #clock-cells = <0>;
 512                 clock-names = "clk_in", "ref_clk";
 513                 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
 514                 assigned-clocks = <&cs2000>;
 515                 assigned-clock-rates = <24000000>;
 516         };
 517
 518         eeprom@54 {
 519                 compatible = "atmel,24c128";
 520                 reg = <0x54>;
 521         };
 522
 523         ds1341: rtc@68 {
 524                 compatible = "dallas,ds1341";
 525                 reg = <0x68>;
 526         };
 527 };
 528
 529 &i2c3 {
 530         pinctrl-names = "default";
 531         pinctrl-0 = <&pinctrl_i2c3>;
 532         clock-frequency = <400000>;
 533         status = "okay";
 534
 535         codec1: codec@18 {
 536                 compatible = "ti,tlv320dac3100";
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&pinctrl_codec1>;
 539                 reg = <0x18>;
 540                 #sound-dai-cells = <0>;
 541                 HPVDD-supply = <&reg_3p3v>;
 542                 SPRVDD-supply = <&reg_3p3v>;
 543                 SPLVDD-supply = <&reg_3p3v>;
 544                 AVDD-supply = <&reg_3p3v>;
 545                 IOVDD-supply = <&reg_3p3v>;
 546                 DVDD-supply = <&vgen4_reg>;
 547                 reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 548         };
 549
 550         touchscreen@20 {
 551                 compatible = "syna,rmi4-i2c";
 552                 pinctrl-names = "default";
 553                 pinctrl-0 = <&pinctrl_ts>;
 554                 reg = <0x20>;
 555                 interrupt-parent = <&gpio1>;
 556                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 557                 vdd-supply = <&reg_5p0v_main>;
 558                 vio-supply = <&reg_3p3v>;
 559
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562
 563                 rmi4-f01@1 {
 564                         reg = <0x1>;
 565                         syna,nosleep-mode = <2>;
 566                 };
 567
 568                 rmi4-f11@11 {
 569                         reg = <0x11>;
 570                         touchscreen-inverted-x;
 571                         touchscreen-swapped-x-y;
 572                         syna,sensor-type = <1>;
 573                 };
 574
 575                 rmi4-f12@12 {
 576                         reg = <0x12>;
 577                         touchscreen-inverted-x;
 578                         touchscreen-swapped-x-y;
 579                         syna,sensor-type = <1>;
 580                 };
 581         };
 582
 583         touchscreen@2a {
 584                 compatible = "eeti,exc3000";
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&pinctrl_ts>;
 587                 reg = <0x2a>;
 588                 interrupt-parent = <&gpio1>;
 589                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 590                 touchscreen-inverted-x;
 591                 touchscreen-swapped-x-y;
 592                 status = "disabled";
 593         };
 594
 595         hpa1: amp@60 {
 596                 compatible = "ti,tpa6130a2";
 597                 pinctrl-names = "default";
 598                 pinctrl-0 = <&pinctrl_tpa1>;
 599                 reg = <0x60>;
 600                 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 601                 Vdd-supply = <&reg_5p0v_main>;
 602         };
 603 };
 604
 605 &ipu1_di0_disp0 {
 606         remote-endpoint = <&disp0_in_0>;
 607 };
 608
 609 &pcie {
 610         pinctrl-names = "default";
 611         pinctrl-0 = <&pinctrl_pcie>;
 612         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 613         status = "okay";
 614
 615         host@0 {
 616                 reg = <0 0 0 0 0>;
 617
 618                 #address-cells = <3>;
 619                 #size-cells = <2>;
 620
 621                 i210: i210@0 {
 622                         reg = <0 0 0 0 0>;
 623                 };
 624         };
 625 };
 626
 627 &usdhc2 {
 628         pinctrl-names = "default";
 629         pinctrl-0 = <&pinctrl_usdhc2>;
 630         bus-width = <4>;
 631         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 632         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 633         vmmc-supply = <&reg_3p3v_sd>;
 634         vqmmc-supply = <&reg_3p3v>;
 635         no-1-8-v;
 636         no-sdio;
 637         status = "okay";
 638 };
 639
 640 &usdhc3 {
 641         pinctrl-names = "default";
 642         pinctrl-0 = <&pinctrl_usdhc3>;
 643         bus-width = <4>;
 644         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 645         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 646         vmmc-supply = <&reg_3p3v_sd>;
 647         vqmmc-supply = <&reg_3p3v>;
 648         no-1-8-v;
 649         no-sdio;
 650         status = "okay";
 651 };
 652
 653 &usdhc4 {
 654         pinctrl-names = "default";
 655         pinctrl-0 = <&pinctrl_usdhc4>;
 656         bus-width = <8>;
 657         vmmc-supply = <&reg_3p3v>;
 658         vqmmc-supply = <&reg_3p3v>;
 659         no-1-8-v;
 660         non-removable;
 661         no-sdio;
 662         no-sd;
 663         status = "okay";
 664 };
 665
 666 &sata {
 667         target-supply = <&reg_3p3v_ssd>;
 668         status = "okay";
 669 };
 670
 671 &fec {
 672         pinctrl-names = "default";
 673         pinctrl-0 = <&pinctrl_enet>;
 674         phy-mode = "rmii";
 675         phy-handle = <&phy>;
 676         phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
 677         phy-reset-duration = <100>;
 678         phy-supply = <&reg_3p3v>;
 679         status = "okay";
 680
 681         mdio {
 682                 #address-cells = <1>;
 683                 #size-cells = <0>;
 684                 status = "okay";
 685
 686                 switch: switch@0 {
 687                         compatible = "marvell,mv88e6085";
 688                         pinctrl-0 = <&pinctrl_switch_irq>;
 689                         pinctrl-names = "default";
 690                         reg = <0>;
 691                         dsa,member = <0 0>;
 692                         eeprom-length = <512>;
 693                         interrupt-parent = <&gpio6>;
 694                         interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 695                         interrupt-controller;
 696                         #interrupt-cells = <2>;
 697
 698                         ports {
 699                                 #address-cells = <1>;
 700                                 #size-cells = <0>;
 701
 702                                 port@0 {
 703                                         reg = <0>;
 704                                         label = "gigabit_proc";
 705                                         phy-handle = <&switchphy0>;
 706                                 };
 707
 708                                 port@1 {
 709                                         reg = <1>;
 710                                         label = "netaux";
 711                                         phy-handle = <&switchphy1>;
 712                                 };
 713
 714                                 port@2 {
 715                                         reg = <2>;
 716                                         label = "cpu";
 717                                         ethernet = <&fec>;
 718
 719                                         fixed-link {
 720                                                 speed = <100>;
 721                                                 full-duplex;
 722                                         };
 723                                 };
 724
 725                                 port@3 {
 726                                         reg = <3>;
 727                                         label = "netright";
 728                                         phy-handle = <&switchphy3>;
 729                                 };
 730
 731                                 port@4 {
 732                                         reg = <4>;
 733                                         label = "netleft";
 734                                         phy-handle = <&switchphy4>;
 735                                 };
 736                         };
 737
 738                         mdio {
 739                                 #address-cells = <1>;
 740                                 #size-cells = <0>;
 741
 742                                 switchphy0: switchphy@0 {
 743                                         reg = <0>;
 744                                         interrupt-parent = <&switch>;
 745                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 746                                 };
 747
 748                                 switchphy1: switchphy@1 {
 749                                         reg = <1>;
 750                                         interrupt-parent = <&switch>;
 751                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 752                                 };
 753
 754                                 switchphy2: switchphy@2 {
 755                                         reg = <2>;
 756                                         interrupt-parent = <&switch>;
 757                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 758                                 };
 759
 760                                 switchphy3: switchphy@3 {
 761                                         reg = <3>;
 762                                         interrupt-parent = <&switch>;
 763                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 764                                 };
 765
 766                                 switchphy4: switchphy@4 {
 767                                         reg = <4>;
 768                                         interrupt-parent = <&switch>;
 769                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 770                                 };
 771                         };
 772                 };
 773         };
 774 };
 775
 776 &usbh1 {
 777         vbus-supply = <&reg_5p0v_main>;
 778         disable-over-current;
 779         status = "okay";
 780 };
 781
 782 &usbotg {
 783         vbus-supply = <&reg_5p0v_user_usb>;
 784         disable-over-current;
 785         dr_mode = "host";
 786         status = "okay";
 787 };
 788
 789 &snvs_rtc {
 790         status = "disabled";
 791 };
 792
 793 &ssi1 {
 794         status = "okay";
 795 };
 796
 797 &ssi2 {
 798         status = "okay";
 799 };
 800
 801 &audmux {
 802         pinctrl-names = "default";
 803         pinctrl-0 = <&pinctrl_audmux>;
 804         status = "okay";
 805
 806         ssi1 {
 807                 fsl,audmux-port = <0>;
 808                 fsl,port-config = <
 809                         (IMX_AUDMUX_V2_PTCR_SYN |
 810                          IMX_AUDMUX_V2_PTCR_TFSEL(2) |
 811                          IMX_AUDMUX_V2_PTCR_TCSEL(2) |
 812                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 813                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 814                         IMX_AUDMUX_V2_PDCR_RXDSEL(2)
 815                 >;
 816         };
 817
 818         aud3 {
 819                 fsl,audmux-port = <2>;
 820                 fsl,port-config = <
 821                         IMX_AUDMUX_V2_PTCR_SYN
 822                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
 823                 >;
 824         };
 825
 826         ssi2 {
 827                 fsl,audmux-port = <1>;
 828                 fsl,port-config = <
 829                         (IMX_AUDMUX_V2_PTCR_SYN |
 830                          IMX_AUDMUX_V2_PTCR_TFSEL(4) |
 831                          IMX_AUDMUX_V2_PTCR_TCSEL(4) |
 832                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 833                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 834                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 835                 >;
 836         };
 837
 838         aud5 {
 839                 fsl,audmux-port = <4>;
 840                 fsl,port-config = <
 841                         IMX_AUDMUX_V2_PTCR_SYN
 842                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
 843                 >;
 844         };
 845 };
 846
 847 &wdog1 {
 848         status = "disabled";
 849 };
 850
 851 &iomuxc {
 852         pinctrl_accel: accelgrp {
 853                 fsl,pins = <
 854                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x4001b000
 855                 >;
 856         };
 857
 858         pinctrl_audmux: audmuxgrp {
 859                 fsl,pins = <
 860                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0
 861                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x130b0
 862                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0
 863                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 864                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x130b0
 865                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 866                 >;
 867         };
 868
 869         pinctrl_codec1: dac1grp {
 870                 fsl,pins = <
 871                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x40000038
 872                 >;
 873         };
 874
 875         pinctrl_codec2: dac2grp {
 876                 fsl,pins = <
 877                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x40000038
 878                 >;
 879         };
 880
 881         pinctrl_disp0: disp0grp {
 882                 fsl,pins = <
 883                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
 884                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
 885                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
 886                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
 887                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
 888                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
 889                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
 890                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
 891                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
 892                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
 893                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
 894                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
 895                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
 896                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
 897                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
 898                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
 899                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
 900                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
 901                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
 902                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
 903                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
 904                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
 905                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
 906                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
 907                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
 908                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
 909                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
 910                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
 911                 >;
 912         };
 913
 914         pinctrl_ecspi1: ecspi1grp {
 915                 fsl,pins = <
 916                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 917                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 918                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 919                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b1
 920                 >;
 921         };
 922
 923         pinctrl_enet: enetgrp {
 924                 fsl,pins = <
 925                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x000b1
 926                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b1
 927                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x100f5
 928                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x100f5
 929                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x100c0
 930                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x100c0
 931                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x100f5
 932                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x100f5
 933                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x40010040
 934                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x100b0
 935                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 936                 >;
 937         };
 938
 939         pinctrl_i2c1: i2c1grp {
 940                 fsl,pins = <
 941                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 942                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 943                 >;
 944         };
 945
 946         pinctrl_i2c2: i2c2grp {
 947                 fsl,pins = <
 948                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 949                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 950                 >;
 951         };
 952
 953         pinctrl_i2c3: i2c3grp {
 954                 fsl,pins = <
 955                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 956                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 957                 >;
 958         };
 959
 960         pinctrl_mdio1: bitbangmdiogrp {
 961                 fsl,pins = <
 962                         /* Bitbang MDIO for DEB Switch */
 963                         MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x4001b030
 964                         MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04       0x40018830
 965                 >;
 966         };
 967
 968         pinctrl_pcie: pciegrp {
 969                 fsl,pins = <
 970                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x10038
 971                 >;
 972         };
 973
 974         pinctrl_pfuze100_irq: pfuze100grp {
 975                 fsl,pins = <
 976                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x40010000
 977                 >;
 978         };
 979
 980         pinctrl_reg_3p3v_sd: mmcsupply1grp {
 981                 fsl,pins = <
 982                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x858
 983                 >;
 984         };
 985
 986         pinctrl_reg_user_usb: usbotggrp {
 987                 fsl,pins = <
 988                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x40000038
 989                 >;
 990         };
 991
 992         pinctrl_rmii_phy_irq: phygrp {
 993                 fsl,pins = <
 994                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x40010000
 995                 >;
 996         };
 997
 998         pinctrl_switch_irq: switchgrp {
 999                 fsl,pins = <
1000                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x4001b000
1001                 >;
1002         };
1003
1004         pinctrl_tc358767: tc358767grp {
1005                 fsl,pins = <
1006                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x10
1007                 >;
1008         };
1009
1010         pinctrl_tpa1: tpa6130-1grp {
1011                 fsl,pins = <
1012                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x40000038
1013                 >;
1014         };
1015
1016         pinctrl_tpa2: tpa6130-2grp {
1017                 fsl,pins = <
1018                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x40000038
1019                 >;
1020         };
1021
1022         pinctrl_ts: tsgrp {
1023                 fsl,pins = <
1024                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x1b0b0
1025                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
1026                 >;
1027         };
1028
1029         pinctrl_uart1: uart1grp {
1030                 fsl,pins = <
1031                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
1032                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
1033                 >;
1034         };
1035
1036         pinctrl_uart3: uart3grp {
1037                 fsl,pins = <
1038                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
1039                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
1040                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
1041                 >;
1042         };
1043
1044         pinctrl_uart4: uart4grp {
1045                 fsl,pins = <
1046                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
1047                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
1048                 >;
1049         };
1050
1051         pinctrl_usdhc2: usdhc2grp {
1052                 fsl,pins = <
1053                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x10059
1054                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
1055                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
1056                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
1057                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
1058                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
1059                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x40010040
1060                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x40010040
1061                 >;
1062         };
1063
1064         pinctrl_usdhc3: usdhc3grp {
1065                 fsl,pins = <
1066                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x10059
1067                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10069
1068                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
1069                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
1070                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
1071                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
1072                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x40010040
1073                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x40010040
1074
1075                 >;
1076         };
1077
1078         pinctrl_usdhc4: usdhc4grp {
1079                 fsl,pins = <
1080                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
1081                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
1082                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
1083                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
1084                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
1085                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
1086                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
1087                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
1088                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
1089                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
1090                         MX6QDL_PAD_NANDF_ALE__SD4_RESET         0x1b0b1
1091                 >;
1092         };
1093 };