arch/arm/boot/dts/imx7d-sdb.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright (C) 2015 Freescale Semiconductor, Inc.
   4
   5 /dts-v1/;
   6
   7 #include "imx7d.dtsi"
   8
   9 / {
  10         model = "Freescale i.MX7 SabreSD Board";
  11         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  12
  13         chosen {
  14                 stdout-path = &uart1;
  15         };
  16
  17         memory@80000000 {
  18                 device_type = "memory";
  19                 reg = <0x80000000 0x80000000>;
  20         };
  21
  22         gpio-keys {
  23                 compatible = "gpio-keys";
  24                 pinctrl-names = "default";
  25                 pinctrl-0 = <&pinctrl_gpio_keys>;
  26
  27                 volume-up {
  28                         label = "Volume Up";
  29                         gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
  30                         linux,code = <KEY_VOLUMEUP>;
  31                         wakeup-source;
  32                 };
  33
  34                 volume-down {
  35                         label = "Volume Down";
  36                         gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
  37                         linux,code = <KEY_VOLUMEDOWN>;
  38                         wakeup-source;
  39                 };
  40         };
  41
  42         spi4 {
  43                 compatible = "spi-gpio";
  44                 pinctrl-names = "default";
  45                 pinctrl-0 = <&pinctrl_spi4>;
  46                 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  47                 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  48                 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  49                 num-chipselects = <1>;
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 extended_io: gpio-expander@0 {
  54                         compatible = "fairchild,74hc595";
  55                         gpio-controller;
  56                         #gpio-cells = <2>;
  57                         reg = <0>;
  58                         registers-number = <1>;
  59                         spi-max-frequency = <100000>;
  60                 };
  61         };
  62
  63         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  64                 compatible = "regulator-fixed";
  65                 regulator-name = "usb_otg1_vbus";
  66                 regulator-min-microvolt = <5000000>;
  67                 regulator-max-microvolt = <5000000>;
  68                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  69                 enable-active-high;
  70         };
  71
  72         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "usb_otg2_vbus";
  75                 pinctrl-names = "default";
  76                 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
  77                 regulator-min-microvolt = <5000000>;
  78                 regulator-max-microvolt = <5000000>;
  79                 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  80                 enable-active-high;
  81         };
  82
  83         reg_vref_1v8: regulator-vref-1v8 {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "vref-1v8";
  86                 regulator-min-microvolt = <1800000>;
  87                 regulator-max-microvolt = <1800000>;
  88         };
  89
  90         reg_brcm: regulator-brcm {
  91                 compatible = "regulator-fixed";
  92                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
  93                 enable-active-high;
  94                 regulator-name = "brcm_reg";
  95                 pinctrl-names = "default";
  96                 pinctrl-0 = <&pinctrl_brcm_reg>;
  97                 regulator-min-microvolt = <3300000>;
  98                 regulator-max-microvolt = <3300000>;
  99                 startup-delay-us = <200000>;
 100         };
 101
 102         reg_lcd_3v3: regulator-lcd-3v3 {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "lcd-3v3";
 105                 regulator-min-microvolt = <3300000>;
 106                 regulator-max-microvolt = <3300000>;
 107                 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
 108         };
 109
 110         reg_can2_3v3: regulator-can2-3v3 {
 111                 compatible = "regulator-fixed";
 112                 regulator-name = "can2-3v3";
 113                 pinctrl-names = "default";
 114                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
 115                 regulator-min-microvolt = <3300000>;
 116                 regulator-max-microvolt = <3300000>;
 117                 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
 118         };
 119
 120         reg_fec2_3v3: regulator-fec2-3v3 {
 121                 compatible = "regulator-fixed";
 122                 regulator-name = "fec2-3v3";
 123                 pinctrl-names = "default";
 124                 pinctrl-0 = <&pinctrl_enet2_reg>;
 125                 regulator-min-microvolt = <3300000>;
 126                 regulator-max-microvolt = <3300000>;
 127                 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
 128         };
 129
 130         backlight: backlight {
 131                 compatible = "pwm-backlight";
 132                 pwms = <&pwm1 0 5000000 0>;
 133                 brightness-levels = <0 4 8 16 32 64 128 255>;
 134                 default-brightness-level = <6>;
 135                 status = "okay";
 136         };
 137
 138         panel {
 139                 compatible = "innolux,at043tn24";
 140                 backlight = <&backlight>;
 141                 power-supply = <&reg_lcd_3v3>;
 142
 143                 port {
 144                         panel_in: endpoint {
 145                                 remote-endpoint = <&display_out>;
 146                         };
 147                 };
 148         };
 149 };
 150
 151 &adc1 {
 152         vref-supply = <&reg_vref_1v8>;
 153         status = "okay";
 154 };
 155
 156 &adc2 {
 157         vref-supply = <&reg_vref_1v8>;
 158         status = "okay";
 159 };
 160
 161 &cpu0 {
 162         cpu-supply = <&sw1a_reg>;
 163 };
 164
 165 &ecspi3 {
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_ecspi3>;
 168         cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 169         status = "okay";
 170
 171         tsc2046@0 {
 172                 compatible = "ti,tsc2046";
 173                 reg = <0>;
 174                 spi-max-frequency = <1000000>;
 175                 pinctrl-names ="default";
 176                 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
 177                 interrupt-parent = <&gpio2>;
 178                 interrupts = <29 0>;
 179                 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
 180                 ti,x-min = /bits/ 16 <0>;
 181                 ti,x-max = /bits/ 16 <0>;
 182                 ti,y-min = /bits/ 16 <0>;
 183                 ti,y-max = /bits/ 16 <0>;
 184                 ti,pressure-max = /bits/ 16 <0>;
 185                 ti,x-plate-ohms = /bits/ 16 <400>;
 186                 wakeup-source;
 187         };
 188 };
 189
 190 &fec1 {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_enet1>;
 193         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 194                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 195         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 196         assigned-clock-rates = <0>, <100000000>;
 197         phy-mode = "rgmii";
 198         phy-handle = <&ethphy0>;
 199         fsl,magic-packet;
 200         phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
 201         status = "okay";
 202
 203         mdio {
 204                 #address-cells = <1>;
 205                 #size-cells = <0>;
 206
 207                 ethphy0: ethernet-phy@0 {
 208                         reg = <0>;
 209                 };
 210
 211                 ethphy1: ethernet-phy@1 {
 212                         reg = <1>;
 213                 };
 214         };
 215 };
 216
 217 &fec2 {
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_enet2>;
 220         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 221                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 222         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 223         assigned-clock-rates = <0>, <100000000>;
 224         phy-mode = "rgmii";
 225         phy-handle = <&ethphy1>;
 226         phy-supply = <&reg_fec2_3v3>;
 227         fsl,magic-packet;
 228         status = "okay";
 229 };
 230
 231 &flexcan2 {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_flexcan2>;
 234         xceiver-supply = <&reg_can2_3v3>;
 235         status = "okay";
 236 };
 237
 238 &i2c1 {
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&pinctrl_i2c1>;
 241         status = "okay";
 242
 243         pmic: pfuze3000@8 {
 244                 compatible = "fsl,pfuze3000";
 245                 reg = <0x08>;
 246
 247                 regulators {
 248                         sw1a_reg: sw1a {
 249                                 regulator-min-microvolt = <700000>;
 250                                 regulator-max-microvolt = <1475000>;
 251                                 regulator-boot-on;
 252                                 regulator-always-on;
 253                                 regulator-ramp-delay = <6250>;
 254                         };
 255
 256                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 257                         sw1c_reg: sw1b {
 258                                 regulator-min-microvolt = <700000>;
 259                                 regulator-max-microvolt = <1475000>;
 260                                 regulator-boot-on;
 261                                 regulator-always-on;
 262                                 regulator-ramp-delay = <6250>;
 263                         };
 264
 265                         sw2_reg: sw2 {
 266                                 regulator-min-microvolt = <1800000>;
 267                                 regulator-max-microvolt = <1800000>;
 268                                 regulator-boot-on;
 269                                 regulator-always-on;
 270                         };
 271
 272                         sw3a_reg: sw3 {
 273                                 regulator-min-microvolt = <900000>;
 274                                 regulator-max-microvolt = <1650000>;
 275                                 regulator-boot-on;
 276                                 regulator-always-on;
 277                         };
 278
 279                         swbst_reg: swbst {
 280                                 regulator-min-microvolt = <5000000>;
 281                                 regulator-max-microvolt = <5150000>;
 282                         };
 283
 284                         snvs_reg: vsnvs {
 285                                 regulator-min-microvolt = <1000000>;
 286                                 regulator-max-microvolt = <3000000>;
 287                                 regulator-boot-on;
 288                                 regulator-always-on;
 289                         };
 290
 291                         vref_reg: vrefddr {
 292                                 regulator-boot-on;
 293                                 regulator-always-on;
 294                         };
 295
 296                         vgen1_reg: vldo1 {
 297                                 regulator-min-microvolt = <1800000>;
 298                                 regulator-max-microvolt = <3300000>;
 299                                 regulator-always-on;
 300                         };
 301
 302                         vgen2_reg: vldo2 {
 303                                 regulator-min-microvolt = <800000>;
 304                                 regulator-max-microvolt = <1550000>;
 305                         };
 306
 307                         vgen3_reg: vccsd {
 308                                 regulator-min-microvolt = <2850000>;
 309                                 regulator-max-microvolt = <3300000>;
 310                                 regulator-always-on;
 311                         };
 312
 313                         vgen4_reg: v33 {
 314                                 regulator-min-microvolt = <2850000>;
 315                                 regulator-max-microvolt = <3300000>;
 316                                 regulator-always-on;
 317                         };
 318
 319                         vgen5_reg: vldo3 {
 320                                 regulator-min-microvolt = <1800000>;
 321                                 regulator-max-microvolt = <3300000>;
 322                                 regulator-always-on;
 323                         };
 324
 325                         vgen6_reg: vldo4 {
 326                                 regulator-min-microvolt = <2800000>;
 327                                 regulator-max-microvolt = <2800000>;
 328                                 regulator-always-on;
 329                         };
 330                 };
 331         };
 332 };
 333
 334 &i2c2 {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pinctrl_i2c2>;
 337         status = "okay";
 338
 339         mpl3115@60 {
 340                 compatible = "fsl,mpl3115";
 341                 reg = <0x60>;
 342         };
 343 };
 344
 345 &i2c3 {
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_i2c3>;
 348         status = "okay";
 349 };
 350
 351 &i2c4 {
 352         pinctrl-names = "default";
 353         pinctrl-0 = <&pinctrl_i2c4>;
 354         status = "okay";
 355
 356         codec: wm8960@1a {
 357                 compatible = "wlf,wm8960";
 358                 reg = <0x1a>;
 359                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 360                 clock-names = "mclk";
 361                 wlf,shared-lrclk;
 362         };
 363 };
 364
 365 &lcdif {
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&pinctrl_lcdif>;
 368         status = "okay";
 369
 370         port {
 371                 display_out: endpoint {
 372                         remote-endpoint = <&panel_in>;
 373                 };
 374         };
 375 };
 376
 377 &pcie {
 378         reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
 379         status = "okay";
 380 };
 381
 382 &reg_1p0d {
 383         vin-supply = <&sw2_reg>;
 384 };
 385
 386 &reg_1p2 {
 387         vin-supply = <&sw2_reg>;
 388 };
 389
 390 &snvs_pwrkey {
 391         status = "okay";
 392 };
 393
 394 &uart1 {
 395         pinctrl-names = "default";
 396         pinctrl-0 = <&pinctrl_uart1>;
 397         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 398         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 399         status = "okay";
 400 };
 401
 402 &uart6 {
 403         pinctrl-names = "default";
 404         pinctrl-0 = <&pinctrl_uart6>;
 405         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 406         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 407         uart-has-rtscts;
 408         status = "okay";
 409 };
 410
 411 &usbotg1 {
 412         vbus-supply = <&reg_usb_otg1_vbus>;
 413         status = "okay";
 414 };
 415
 416 &usbotg2 {
 417         vbus-supply = <&reg_usb_otg2_vbus>;
 418         dr_mode = "host";
 419         status = "okay";
 420 };
 421
 422 &usdhc1 {
 423         pinctrl-names = "default";
 424         pinctrl-0 = <&pinctrl_usdhc1>;
 425         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 426         wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 427         wakeup-source;
 428         keep-power-in-suspend;
 429         status = "okay";
 430 };
 431
 432 &usdhc2 {
 433         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 434         pinctrl-0 = <&pinctrl_usdhc2>;
 435         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 436         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 437         wakeup-source;
 438         keep-power-in-suspend;
 439         non-removable;
 440         vmmc-supply = <&reg_brcm>;
 441         fsl,tuning-step = <2>;
 442         status = "okay";
 443 };
 444
 445 &usdhc3 {
 446         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 447         pinctrl-0 = <&pinctrl_usdhc3>;
 448         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 449         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 450         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 451         assigned-clock-rates = <400000000>;
 452         bus-width = <8>;
 453         fsl,tuning-step = <2>;
 454         non-removable;
 455         status = "okay";
 456 };
 457
 458 &wdog1 {
 459         pinctrl-names = "default";
 460         pinctrl-0 = <&pinctrl_wdog>;
 461         fsl,ext-reset-output;
 462 };
 463
 464 &iomuxc {
 465         pinctrl-names = "default";
 466         pinctrl-0 = <&pinctrl_hog>;
 467
 468         imx7d-sdb {
 469                 pinctrl_brcm_reg: brcmreggrp {
 470                         fsl,pins = <
 471                                 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x14
 472                         >;
 473                 };
 474
 475                 pinctrl_ecspi3: ecspi3grp {
 476                         fsl,pins = <
 477                                 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO      0x2
 478                                 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI      0x2
 479                                 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK      0x2
 480                                 MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x59
 481                         >;
 482                 };
 483
 484                 pinctrl_enet1: enet1grp {
 485                         fsl,pins = <
 486                                 MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 487                                 MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 488                                 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 489                                 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 490                                 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 491                                 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 492                                 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 493                                 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 494                                 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 495                                 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 496                                 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 497                                 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 498                                 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 499                                 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 500                         >;
 501                 };
 502
 503                 pinctrl_enet2: enet2grp {
 504                         fsl,pins = <
 505                                 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
 506                                 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
 507                                 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
 508                                 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
 509                                 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
 510                                 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
 511                                 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
 512                                 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
 513                                 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
 514                                 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
 515                                 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
 516                                 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
 517                         >;
 518                 };
 519
 520                 pinctrl_enet2_reg: enet2reggrp {
 521                         fsl,pins = <
 522                                 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4     0x14
 523                         >;
 524                 };
 525
 526                 pinctrl_flexcan2: flexcan2grp {
 527                         fsl,pins = <
 528                                 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
 529                                 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
 530                         >;
 531                 };
 532
 533                 pinctrl_flexcan2_reg: flexcan2reggrp {
 534                         fsl,pins = <
 535                                 MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x59    /* CAN_STBY */
 536                         >;
 537                 };
 538
 539                 pinctrl_gpio_keys: gpio_keysgrp {
 540                         fsl,pins = <
 541                                 MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x59
 542                                 MX7D_PAD_SD2_WP__GPIO5_IO10             0x59
 543                         >;
 544                 };
 545
 546                 pinctrl_hog: hoggrp {
 547                         fsl,pins = <
 548                                 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x34  /* bt reg on */
 549                         >;
 550                 };
 551
 552                 pinctrl_i2c1: i2c1grp {
 553                         fsl,pins = <
 554                                 MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 555                                 MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 556                         >;
 557                 };
 558
 559                 pinctrl_i2c2: i2c2grp {
 560                         fsl,pins = <
 561                                 MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 562                                 MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 563                         >;
 564                 };
 565
 566                 pinctrl_i2c3: i2c3grp {
 567                         fsl,pins = <
 568                                 MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 569                                 MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 570                         >;
 571                 };
 572
 573                 pinctrl_i2c4: i2c4grp {
 574                         fsl,pins = <
 575                                 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 576                                 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 577                         >;
 578                 };
 579
 580                 pinctrl_lcdif: lcdifgrp {
 581                         fsl,pins = <
 582                                 MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 583                                 MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 584                                 MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 585                                 MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 586                                 MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 587                                 MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 588                                 MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 589                                 MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 590                                 MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 591                                 MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 592                                 MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 593                                 MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 594                                 MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 595                                 MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 596                                 MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 597                                 MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 598                                 MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 599                                 MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 600                                 MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 601                                 MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 602                                 MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 603                                 MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 604                                 MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 605                                 MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 606                                 MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 607                                 MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 608                                 MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 609                                 MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 610                                 MX7D_PAD_LCD_RESET__LCD_RESET           0x79
 611                         >;
 612                 };
 613
 614                 pinctrl_spi4: spi4grp {
 615                         fsl,pins = <
 616                                 MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x59
 617                                 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
 618                                 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
 619                         >;
 620                 };
 621
 622                 pinctrl_tsc2046_pendown: tsc2046_pendown {
 623                         fsl,pins = <
 624                                 MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x59
 625                         >;
 626                 };
 627
 628                 pinctrl_uart1: uart1grp {
 629                         fsl,pins = <
 630                                 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 631                                 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 632                         >;
 633                 };
 634
 635                 pinctrl_uart5: uart5grp {
 636                         fsl,pins = <
 637                                 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX     0x79
 638                                 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX     0x79
 639                                 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS    0x79
 640                                 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS    0x79
 641                         >;
 642                 };
 643
 644                 pinctrl_uart6: uart6grp {
 645                         fsl,pins = <
 646                                 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 647                                 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 648                                 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 649                                 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 650                         >;
 651                 };
 652
 653                 pinctrl_usdhc1: usdhc1grp {
 654                         fsl,pins = <
 655                                 MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 656                                 MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 657                                 MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 658                                 MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 659                                 MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 660                                 MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 661                                 MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
 662                                 MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
 663                                 MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
 664                         >;
 665                 };
 666
 667                 pinctrl_usdhc2: usdhc2grp {
 668                         fsl,pins = <
 669                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 670                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 671                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 672                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 673                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 674                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 675                         >;
 676                 };
 677
 678                 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
 679                         fsl,pins = <
 680                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
 681                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
 682                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
 683                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
 684                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
 685                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
 686                         >;
 687                 };
 688
 689                 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
 690                         fsl,pins = <
 691                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
 692                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
 693                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
 694                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
 695                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
 696                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
 697                         >;
 698                 };
 699
 700
 701                 pinctrl_usdhc3: usdhc3grp {
 702                         fsl,pins = <
 703                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 704                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 705                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 706                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 707                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 708                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 709                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 710                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 711                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 712                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 713                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 714                         >;
 715                 };
 716
 717                 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 718                         fsl,pins = <
 719                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 720                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 721                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 722                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 723                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 724                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 725                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 726                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 727                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 728                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 729                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 730                         >;
 731                 };
 732
 733                 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 734                         fsl,pins = <
 735                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 736                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 737                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 738                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 739                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 740                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 741                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 742                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 743                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 744                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 745                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 746                         >;
 747                 };
 748         };
 749 };
 750
 751 &pwm1 {
 752         pinctrl-names = "default";
 753         pinctrl-0 = <&pinctrl_pwm1>;
 754         status = "okay";
 755 };
 756
 757 &iomuxc_lpsr {
 758         pinctrl_wdog: wdoggrp {
 759                 fsl,pins = <
 760                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B          0x74
 761                 >;
 762         };
 763
 764         pinctrl_pwm1: pwm1grp {
 765                 fsl,pins = <
 766                         MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT              0x30
 767                 >;
 768         };
 769
 770         pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
 771                 fsl,pins = <
 772                         MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7       0x14
 773                 >;
 774         };
 775 };