| blob | 27e48234f1c23cec5b8c165dabfd73f61d1fa1fe |
1 /*
2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
47 #include <dt-bindings/clock/sun8i-r-ccu.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 #include <dt-bindings/reset/sun8i-de2.h>
51 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 / {
54 interrupt-parent = <&gic>;
55 #address-cells = <1>;
56 #size-cells = <1>;
58 chosen {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
63 simplefb_lcd: framebuffer-lcd {
64 compatible = "allwinner,simple-framebuffer",
65 "simple-framebuffer";
66 allwinner,pipeline = "mixer0-lcd0";
67 clocks = <&ccu CLK_TCON0>,
68 <&display_clocks CLK_MIXER0>;
69 status = "disabled";
70 };
72 simplefb_hdmi: framebuffer-hdmi {
73 compatible = "allwinner,simple-framebuffer",
74 "simple-framebuffer";
75 allwinner,pipeline = "mixer1-lcd1-hdmi";
76 clocks = <&display_clocks CLK_MIXER1>,
77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
78 status = "disabled";
79 };
80 };
82 cpus {
83 #address-cells = <1>;
84 #size-cells = <0>;
86 cpu0: cpu@0 {
87 compatible = "arm,cortex-a53";
88 device_type = "cpu";
89 reg = <0>;
90 enable-method = "psci";
91 next-level-cache = <&L2>;
92 };
94 cpu1: cpu@1 {
95 compatible = "arm,cortex-a53";
96 device_type = "cpu";
97 reg = <1>;
98 enable-method = "psci";
99 next-level-cache = <&L2>;
100 };
102 cpu2: cpu@2 {
103 compatible = "arm,cortex-a53";
104 device_type = "cpu";
105 reg = <2>;
106 enable-method = "psci";
107 next-level-cache = <&L2>;
108 };
110 cpu3: cpu@3 {
111 compatible = "arm,cortex-a53";
112 device_type = "cpu";
113 reg = <3>;
114 enable-method = "psci";
115 next-level-cache = <&L2>;
116 };
118 L2: l2-cache {
119 compatible = "cache";
120 cache-level = <2>;
121 };
122 };
124 de: display-engine {
125 compatible = "allwinner,sun50i-a64-display-engine";
126 allwinner,pipelines = <&mixer0>,
127 <&mixer1>;
128 status = "disabled";
129 };
131 osc24M: osc24M_clk {
132 #clock-cells = <0>;
133 compatible = "fixed-clock";
134 clock-frequency = <24000000>;
135 clock-output-names = "osc24M";
136 };
138 osc32k: osc32k_clk {
139 #clock-cells = <0>;
140 compatible = "fixed-clock";
141 clock-frequency = <32768>;
142 clock-output-names = "ext-osc32k";
143 };
145 pmu {
146 compatible = "arm,cortex-a53-pmu";
147 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
152 };
154 psci {
155 compatible = "arm,psci-0.2";
156 method = "smc";
157 };
159 sound: sound {
160 compatible = "simple-audio-card";
161 simple-audio-card,name = "sun50i-a64-audio";
162 simple-audio-card,format = "i2s";
163 simple-audio-card,frame-master = <&cpudai>;
164 simple-audio-card,bitclock-master = <&cpudai>;
165 simple-audio-card,mclk-fs = <128>;
166 simple-audio-card,aux-devs = <&codec_analog>;
167 simple-audio-card,routing =
168 "Left DAC", "AIF1 Slot 0 Left",
169 "Right DAC", "AIF1 Slot 0 Right",
170 "AIF1 Slot 0 Left ADC", "Left ADC",
171 "AIF1 Slot 0 Right ADC", "Right ADC";
172 status = "disabled";
174 cpudai: simple-audio-card,cpu {
175 sound-dai = <&dai>;
176 };
178 link_codec: simple-audio-card,codec {
179 sound-dai = <&codec>;
180 };
181 };
183 sound_spdif {
184 compatible = "simple-audio-card";
185 simple-audio-card,name = "On-board SPDIF";
187 simple-audio-card,cpu {
188 sound-dai = <&spdif>;
189 };
191 simple-audio-card,codec {
192 sound-dai = <&spdif_out>;
193 };
194 };
196 spdif_out: spdif-out {
197 #sound-dai-cells = <0>;
198 compatible = "linux,spdif-dit";
199 };
201 timer {
202 compatible = "arm,armv8-timer";
203 allwinner,erratum-unknown1;
204 interrupts = <GIC_PPI 13
205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
206 <GIC_PPI 14
207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
208 <GIC_PPI 11
209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
210 <GIC_PPI 10
211 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
212 };
214 soc {
215 compatible = "simple-bus";
216 #address-cells = <1>;
217 #size-cells = <1>;
218 ranges;
220 bus@1000000 {
221 compatible = "allwinner,sun50i-a64-de2";
222 reg = <0x1000000 0x400000>;
223 allwinner,sram = <&de2_sram 1>;
224 #address-cells = <1>;
225 #size-cells = <1>;
226 ranges = <0 0x1000000 0x400000>;
228 display_clocks: clock@0 {
229 compatible = "allwinner,sun50i-a64-de2-clk";
230 reg = <0x0 0x100000>;
231 clocks = <&ccu CLK_BUS_DE>,
232 <&ccu CLK_DE>;
233 clock-names = "bus",
234 "mod";
235 resets = <&ccu RST_BUS_DE>;
236 #clock-cells = <1>;
237 #reset-cells = <1>;
238 };
240 mixer0: mixer@100000 {
241 compatible = "allwinner,sun50i-a64-de2-mixer-0";
242 reg = <0x100000 0x100000>;
243 clocks = <&display_clocks CLK_BUS_MIXER0>,
244 <&display_clocks CLK_MIXER0>;
245 clock-names = "bus",
246 "mod";
247 resets = <&display_clocks RST_MIXER0>;
249 ports {
250 #address-cells = <1>;
251 #size-cells = <0>;
253 mixer0_out: port@1 {
254 #address-cells = <1>;
255 #size-cells = <0>;
256 reg = <1>;
258 mixer0_out_tcon0: endpoint@0 {
259 reg = <0>;
260 remote-endpoint = <&tcon0_in_mixer0>;
261 };
263 mixer0_out_tcon1: endpoint@1 {
264 reg = <1>;
265 remote-endpoint = <&tcon1_in_mixer0>;
266 };
267 };
268 };
269 };
271 mixer1: mixer@200000 {
272 compatible = "allwinner,sun50i-a64-de2-mixer-1";
273 reg = <0x200000 0x100000>;
274 clocks = <&display_clocks CLK_BUS_MIXER1>,
275 <&display_clocks CLK_MIXER1>;
276 clock-names = "bus",
277 "mod";
278 resets = <&display_clocks RST_MIXER1>;
280 ports {
281 #address-cells = <1>;
282 #size-cells = <0>;
284 mixer1_out: port@1 {
285 #address-cells = <1>;
286 #size-cells = <0>;
287 reg = <1>;
289 mixer1_out_tcon0: endpoint@0 {
290 reg = <0>;
291 remote-endpoint = <&tcon0_in_mixer1>;
292 };
294 mixer1_out_tcon1: endpoint@1 {
295 reg = <1>;
296 remote-endpoint = <&tcon1_in_mixer1>;
297 };
298 };
299 };
300 };
301 };
303 syscon: syscon@1c00000 {
304 compatible = "allwinner,sun50i-a64-system-control";
305 reg = <0x01c00000 0x1000>;
306 #address-cells = <1>;
307 #size-cells = <1>;
308 ranges;
310 sram_c: sram@18000 {
311 compatible = "mmio-sram";
312 reg = <0x00018000 0x28000>;
313 #address-cells = <1>;
314 #size-cells = <1>;
315 ranges = <0 0x00018000 0x28000>;
317 de2_sram: sram-section@0 {
318 compatible = "allwinner,sun50i-a64-sram-c";
319 reg = <0x0000 0x28000>;
320 };
321 };
323 sram_c1: sram@1d00000 {
324 compatible = "mmio-sram";
325 reg = <0x01d00000 0x40000>;
326 #address-cells = <1>;
327 #size-cells = <1>;
328 ranges = <0 0x01d00000 0x40000>;
330 ve_sram: sram-section@0 {
331 compatible = "allwinner,sun50i-a64-sram-c1",
332 "allwinner,sun4i-a10-sram-c1";
333 reg = <0x000000 0x40000>;
334 };
335 };
336 };
338 dma: dma-controller@1c02000 {
339 compatible = "allwinner,sun50i-a64-dma";
340 reg = <0x01c02000 0x1000>;
341 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&ccu CLK_BUS_DMA>;
343 dma-channels = <8>;
344 dma-requests = <27>;
345 resets = <&ccu RST_BUS_DMA>;
346 #dma-cells = <1>;
347 };
349 tcon0: lcd-controller@1c0c000 {
350 compatible = "allwinner,sun50i-a64-tcon-lcd",
351 "allwinner,sun8i-a83t-tcon-lcd";
352 reg = <0x01c0c000 0x1000>;
353 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
355 clock-names = "ahb", "tcon-ch0";
356 clock-output-names = "tcon-pixel-clock";
357 #clock-cells = <0>;
358 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
359 reset-names = "lcd", "lvds";
361 ports {
362 #address-cells = <1>;
363 #size-cells = <0>;
365 tcon0_in: port@0 {
366 #address-cells = <1>;
367 #size-cells = <0>;
368 reg = <0>;
370 tcon0_in_mixer0: endpoint@0 {
371 reg = <0>;
372 remote-endpoint = <&mixer0_out_tcon0>;
373 };
375 tcon0_in_mixer1: endpoint@1 {
376 reg = <1>;
377 remote-endpoint = <&mixer1_out_tcon0>;
378 };
379 };
381 tcon0_out: port@1 {
382 #address-cells = <1>;
383 #size-cells = <0>;
384 reg = <1>;
385 };
386 };
387 };
389 tcon1: lcd-controller@1c0d000 {
390 compatible = "allwinner,sun50i-a64-tcon-tv",
391 "allwinner,sun8i-a83t-tcon-tv";
392 reg = <0x01c0d000 0x1000>;
393 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
395 clock-names = "ahb", "tcon-ch1";
396 resets = <&ccu RST_BUS_TCON1>;
397 reset-names = "lcd";
399 ports {
400 #address-cells = <1>;
401 #size-cells = <0>;
403 tcon1_in: port@0 {
404 #address-cells = <1>;
405 #size-cells = <0>;
406 reg = <0>;
408 tcon1_in_mixer0: endpoint@0 {
409 reg = <0>;
410 remote-endpoint = <&mixer0_out_tcon1>;
411 };
413 tcon1_in_mixer1: endpoint@1 {
414 reg = <1>;
415 remote-endpoint = <&mixer1_out_tcon1>;
416 };
417 };
419 tcon1_out: port@1 {
420 #address-cells = <1>;
421 #size-cells = <0>;
422 reg = <1>;
424 tcon1_out_hdmi: endpoint@1 {
425 reg = <1>;
426 remote-endpoint = <&hdmi_in_tcon1>;
427 };
428 };
429 };
430 };
432 video-codec@1c0e000 {
433 compatible = "allwinner,sun50i-a64-video-engine";
434 reg = <0x01c0e000 0x1000>;
435 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
436 <&ccu CLK_DRAM_VE>;
437 clock-names = "ahb", "mod", "ram";
438 resets = <&ccu RST_BUS_VE>;
439 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
440 allwinner,sram = <&ve_sram 1>;
441 };
443 mmc0: mmc@1c0f000 {
444 compatible = "allwinner,sun50i-a64-mmc";
445 reg = <0x01c0f000 0x1000>;
446 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
447 clock-names = "ahb", "mmc";
448 resets = <&ccu RST_BUS_MMC0>;
449 reset-names = "ahb";
450 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
451 max-frequency = <150000000>;
452 status = "disabled";
453 #address-cells = <1>;
454 #size-cells = <0>;
455 };
457 mmc1: mmc@1c10000 {
458 compatible = "allwinner,sun50i-a64-mmc";
459 reg = <0x01c10000 0x1000>;
460 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
461 clock-names = "ahb", "mmc";
462 resets = <&ccu RST_BUS_MMC1>;
463 reset-names = "ahb";
464 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
465 max-frequency = <150000000>;
466 status = "disabled";
467 #address-cells = <1>;
468 #size-cells = <0>;
469 };
471 mmc2: mmc@1c11000 {
472 compatible = "allwinner,sun50i-a64-emmc";
473 reg = <0x01c11000 0x1000>;
474 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
475 clock-names = "ahb", "mmc";
476 resets = <&ccu RST_BUS_MMC2>;
477 reset-names = "ahb";
478 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
479 max-frequency = <200000000>;
480 status = "disabled";
481 #address-cells = <1>;
482 #size-cells = <0>;
483 };
485 sid: eeprom@1c14000 {
486 compatible = "allwinner,sun50i-a64-sid";
487 reg = <0x1c14000 0x400>;
488 };
490 crypto: crypto@1c15000 {
491 compatible = "allwinner,sun50i-a64-crypto";
492 reg = <0x01c15000 0x1000>;
493 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
495 clock-names = "bus", "mod";
496 resets = <&ccu RST_BUS_CE>;
497 };
499 usb_otg: usb@1c19000 {
500 compatible = "allwinner,sun8i-a33-musb";
501 reg = <0x01c19000 0x0400>;
502 clocks = <&ccu CLK_BUS_OTG>;
503 resets = <&ccu RST_BUS_OTG>;
504 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
505 interrupt-names = "mc";
506 phys = <&usbphy 0>;
507 phy-names = "usb";
508 extcon = <&usbphy 0>;
509 dr_mode = "otg";
510 status = "disabled";
511 };
513 usbphy: phy@1c19400 {
514 compatible = "allwinner,sun50i-a64-usb-phy";
515 reg = <0x01c19400 0x14>,
516 <0x01c1a800 0x4>,
517 <0x01c1b800 0x4>;
518 reg-names = "phy_ctrl",
519 "pmu0",
520 "pmu1";
521 clocks = <&ccu CLK_USB_PHY0>,
522 <&ccu CLK_USB_PHY1>;
523 clock-names = "usb0_phy",
524 "usb1_phy";
525 resets = <&ccu RST_USB_PHY0>,
526 <&ccu RST_USB_PHY1>;
527 reset-names = "usb0_reset",
528 "usb1_reset";
529 status = "disabled";
530 #phy-cells = <1>;
531 };
533 ehci0: usb@1c1a000 {
534 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
535 reg = <0x01c1a000 0x100>;
536 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&ccu CLK_BUS_OHCI0>,
538 <&ccu CLK_BUS_EHCI0>,
539 <&ccu CLK_USB_OHCI0>;
540 resets = <&ccu RST_BUS_OHCI0>,
541 <&ccu RST_BUS_EHCI0>;
542 status = "disabled";
543 };
545 ohci0: usb@1c1a400 {
546 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
547 reg = <0x01c1a400 0x100>;
548 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&ccu CLK_BUS_OHCI0>,
550 <&ccu CLK_USB_OHCI0>;
551 resets = <&ccu RST_BUS_OHCI0>;
552 status = "disabled";
553 };
555 ehci1: usb@1c1b000 {
556 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
557 reg = <0x01c1b000 0x100>;
558 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&ccu CLK_BUS_OHCI1>,
560 <&ccu CLK_BUS_EHCI1>,
561 <&ccu CLK_USB_OHCI1>;
562 resets = <&ccu RST_BUS_OHCI1>,
563 <&ccu RST_BUS_EHCI1>;
564 phys = <&usbphy 1>;
565 phy-names = "usb";
566 status = "disabled";
567 };
569 ohci1: usb@1c1b400 {
570 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
571 reg = <0x01c1b400 0x100>;
572 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&ccu CLK_BUS_OHCI1>,
574 <&ccu CLK_USB_OHCI1>;
575 resets = <&ccu RST_BUS_OHCI1>;
576 phys = <&usbphy 1>;
577 phy-names = "usb";
578 status = "disabled";
579 };
581 ccu: clock@1c20000 {
582 compatible = "allwinner,sun50i-a64-ccu";
583 reg = <0x01c20000 0x400>;
584 clocks = <&osc24M>, <&rtc 0>;
585 clock-names = "hosc", "losc";
586 #clock-cells = <1>;
587 #reset-cells = <1>;
588 };
590 pio: pinctrl@1c20800 {
591 compatible = "allwinner,sun50i-a64-pinctrl";
592 reg = <0x01c20800 0x400>;
593 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>;
597 clock-names = "apb", "hosc", "losc";
598 gpio-controller;
599 #gpio-cells = <3>;
600 interrupt-controller;
601 #interrupt-cells = <3>;
603 csi_pins: csi-pins {
604 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
605 "PE7", "PE8", "PE9", "PE10", "PE11";
606 function = "csi";
607 };
609 /omit-if-no-ref/
610 csi_mclk_pin: csi-mclk-pin {
611 pins = "PE1";
612 function = "csi";
613 };
615 i2c0_pins: i2c0-pins {
616 pins = "PH0", "PH1";
617 function = "i2c0";
618 };
620 i2c1_pins: i2c1-pins {
621 pins = "PH2", "PH3";
622 function = "i2c1";
623 };
625 /omit-if-no-ref/
626 lcd_rgb666_pins: lcd-rgb666-pins {
627 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
628 "PD5", "PD6", "PD7", "PD8", "PD9",
629 "PD10", "PD11", "PD12", "PD13",
630 "PD14", "PD15", "PD16", "PD17",
631 "PD18", "PD19", "PD20", "PD21";
632 function = "lcd0";
633 };
635 mmc0_pins: mmc0-pins {
636 pins = "PF0", "PF1", "PF2", "PF3",
637 "PF4", "PF5";
638 function = "mmc0";
639 drive-strength = <30>;
640 bias-pull-up;
641 };
643 mmc1_pins: mmc1-pins {
644 pins = "PG0", "PG1", "PG2", "PG3",
645 "PG4", "PG5";
646 function = "mmc1";
647 drive-strength = <30>;
648 bias-pull-up;
649 };
651 mmc2_pins: mmc2-pins {
652 pins = "PC5", "PC6", "PC8", "PC9",
653 "PC10","PC11", "PC12", "PC13",
654 "PC14", "PC15", "PC16";
655 function = "mmc2";
656 drive-strength = <30>;
657 bias-pull-up;
658 };
660 mmc2_ds_pin: mmc2-ds-pin {
661 pins = "PC1";
662 function = "mmc2";
663 drive-strength = <30>;
664 bias-pull-up;
665 };
667 pwm_pin: pwm-pin {
668 pins = "PD22";
669 function = "pwm";
670 };
672 rmii_pins: rmii-pins {
673 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
674 "PD18", "PD19", "PD20", "PD22", "PD23";
675 function = "emac";
676 drive-strength = <40>;
677 };
679 rgmii_pins: rgmii-pins {
680 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
681 "PD13", "PD15", "PD16", "PD17", "PD18",
682 "PD19", "PD20", "PD21", "PD22", "PD23";
683 function = "emac";
684 drive-strength = <40>;
685 };
687 spdif_tx_pin: spdif-tx-pin {
688 pins = "PH8";
689 function = "spdif";
690 };
692 spi0_pins: spi0-pins {
693 pins = "PC0", "PC1", "PC2", "PC3";
694 function = "spi0";
695 };
697 spi1_pins: spi1-pins {
698 pins = "PD0", "PD1", "PD2", "PD3";
699 function = "spi1";
700 };
702 uart0_pb_pins: uart0-pb-pins {
703 pins = "PB8", "PB9";
704 function = "uart0";
705 };
707 uart1_pins: uart1-pins {
708 pins = "PG6", "PG7";
709 function = "uart1";
710 };
712 uart1_rts_cts_pins: uart1-rts-cts-pins {
713 pins = "PG8", "PG9";
714 function = "uart1";
715 };
717 uart2_pins: uart2-pins {
718 pins = "PB0", "PB1";
719 function = "uart2";
720 };
722 uart3_pins: uart3-pins {
723 pins = "PD0", "PD1";
724 function = "uart3";
725 };
727 uart4_pins: uart4-pins {
728 pins = "PD2", "PD3";
729 function = "uart4";
730 };
732 uart4_rts_cts_pins: uart4-rts-cts-pins {
733 pins = "PD4", "PD5";
734 function = "uart4";
735 };
736 };
738 spdif: spdif@1c21000 {
739 #sound-dai-cells = <0>;
740 compatible = "allwinner,sun50i-a64-spdif",
741 "allwinner,sun8i-h3-spdif";
742 reg = <0x01c21000 0x400>;
743 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
745 resets = <&ccu RST_BUS_SPDIF>;
746 clock-names = "apb", "spdif";
747 dmas = <&dma 2>;
748 dma-names = "tx";
749 pinctrl-names = "default";
750 pinctrl-0 = <&spdif_tx_pin>;
751 status = "disabled";
752 };
754 lradc: lradc@1c21800 {
755 compatible = "allwinner,sun50i-a64-lradc",
756 "allwinner,sun8i-a83t-r-lradc";
757 reg = <0x01c21800 0x400>;
758 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
759 status = "disabled";
760 };
762 i2s0: i2s@1c22000 {
763 #sound-dai-cells = <0>;
764 compatible = "allwinner,sun50i-a64-i2s",
765 "allwinner,sun8i-h3-i2s";
766 reg = <0x01c22000 0x400>;
767 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
769 clock-names = "apb", "mod";
770 resets = <&ccu RST_BUS_I2S0>;
771 dma-names = "rx", "tx";
772 dmas = <&dma 3>, <&dma 3>;
773 status = "disabled";
774 };
776 i2s1: i2s@1c22400 {
777 #sound-dai-cells = <0>;
778 compatible = "allwinner,sun50i-a64-i2s",
779 "allwinner,sun8i-h3-i2s";
780 reg = <0x01c22400 0x400>;
781 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
783 clock-names = "apb", "mod";
784 resets = <&ccu RST_BUS_I2S1>;
785 dma-names = "rx", "tx";
786 dmas = <&dma 4>, <&dma 4>;
787 status = "disabled";
788 };
790 dai: dai@1c22c00 {
791 #sound-dai-cells = <0>;
792 compatible = "allwinner,sun50i-a64-codec-i2s";
793 reg = <0x01c22c00 0x200>;
794 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
796 clock-names = "apb", "mod";
797 resets = <&ccu RST_BUS_CODEC>;
798 dmas = <&dma 15>, <&dma 15>;
799 dma-names = "rx", "tx";
800 status = "disabled";
801 };
803 codec: codec@1c22e00 {
804 #sound-dai-cells = <0>;
805 compatible = "allwinner,sun8i-a33-codec";
806 reg = <0x01c22e00 0x600>;
807 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
809 clock-names = "bus", "mod";
810 status = "disabled";
811 };
813 uart0: serial@1c28000 {
814 compatible = "snps,dw-apb-uart";
815 reg = <0x01c28000 0x400>;
816 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
817 reg-shift = <2>;
818 reg-io-width = <4>;
819 clocks = <&ccu CLK_BUS_UART0>;
820 resets = <&ccu RST_BUS_UART0>;
821 status = "disabled";
822 };
824 uart1: serial@1c28400 {
825 compatible = "snps,dw-apb-uart";
826 reg = <0x01c28400 0x400>;
827 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
828 reg-shift = <2>;
829 reg-io-width = <4>;
830 clocks = <&ccu CLK_BUS_UART1>;
831 resets = <&ccu RST_BUS_UART1>;
832 status = "disabled";
833 };
835 uart2: serial@1c28800 {
836 compatible = "snps,dw-apb-uart";
837 reg = <0x01c28800 0x400>;
838 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
839 reg-shift = <2>;
840 reg-io-width = <4>;
841 clocks = <&ccu CLK_BUS_UART2>;
842 resets = <&ccu RST_BUS_UART2>;
843 status = "disabled";
844 };
846 uart3: serial@1c28c00 {
847 compatible = "snps,dw-apb-uart";
848 reg = <0x01c28c00 0x400>;
849 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
850 reg-shift = <2>;
851 reg-io-width = <4>;
852 clocks = <&ccu CLK_BUS_UART3>;
853 resets = <&ccu RST_BUS_UART3>;
854 status = "disabled";
855 };
857 uart4: serial@1c29000 {
858 compatible = "snps,dw-apb-uart";
859 reg = <0x01c29000 0x400>;
860 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
861 reg-shift = <2>;
862 reg-io-width = <4>;
863 clocks = <&ccu CLK_BUS_UART4>;
864 resets = <&ccu RST_BUS_UART4>;
865 status = "disabled";
866 };
868 i2c0: i2c@1c2ac00 {
869 compatible = "allwinner,sun6i-a31-i2c";
870 reg = <0x01c2ac00 0x400>;
871 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&ccu CLK_BUS_I2C0>;
873 resets = <&ccu RST_BUS_I2C0>;
874 pinctrl-names = "default";
875 pinctrl-0 = <&i2c0_pins>;
876 status = "disabled";
877 #address-cells = <1>;
878 #size-cells = <0>;
879 };
881 i2c1: i2c@1c2b000 {
882 compatible = "allwinner,sun6i-a31-i2c";
883 reg = <0x01c2b000 0x400>;
884 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&ccu CLK_BUS_I2C1>;
886 resets = <&ccu RST_BUS_I2C1>;
887 pinctrl-names = "default";
888 pinctrl-0 = <&i2c1_pins>;
889 status = "disabled";
890 #address-cells = <1>;
891 #size-cells = <0>;
892 };
894 i2c2: i2c@1c2b400 {
895 compatible = "allwinner,sun6i-a31-i2c";
896 reg = <0x01c2b400 0x400>;
897 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&ccu CLK_BUS_I2C2>;
899 resets = <&ccu RST_BUS_I2C2>;
900 status = "disabled";
901 #address-cells = <1>;
902 #size-cells = <0>;
903 };
906 spi0: spi@1c68000 {
907 compatible = "allwinner,sun8i-h3-spi";
908 reg = <0x01c68000 0x1000>;
909 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
911 clock-names = "ahb", "mod";
912 dmas = <&dma 23>, <&dma 23>;
913 dma-names = "rx", "tx";
914 pinctrl-names = "default";
915 pinctrl-0 = <&spi0_pins>;
916 resets = <&ccu RST_BUS_SPI0>;
917 status = "disabled";
918 num-cs = <1>;
919 #address-cells = <1>;
920 #size-cells = <0>;
921 };
923 spi1: spi@1c69000 {
924 compatible = "allwinner,sun8i-h3-spi";
925 reg = <0x01c69000 0x1000>;
926 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
928 clock-names = "ahb", "mod";
929 dmas = <&dma 24>, <&dma 24>;
930 dma-names = "rx", "tx";
931 pinctrl-names = "default";
932 pinctrl-0 = <&spi1_pins>;
933 resets = <&ccu RST_BUS_SPI1>;
934 status = "disabled";
935 num-cs = <1>;
936 #address-cells = <1>;
937 #size-cells = <0>;
938 };
940 emac: ethernet@1c30000 {
941 compatible = "allwinner,sun50i-a64-emac";
942 syscon = <&syscon>;
943 reg = <0x01c30000 0x10000>;
944 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
945 interrupt-names = "macirq";
946 resets = <&ccu RST_BUS_EMAC>;
947 reset-names = "stmmaceth";
948 clocks = <&ccu CLK_BUS_EMAC>;
949 clock-names = "stmmaceth";
950 status = "disabled";
952 mdio: mdio {
953 compatible = "snps,dwmac-mdio";
954 #address-cells = <1>;
955 #size-cells = <0>;
956 };
957 };
959 mali: gpu@1c40000 {
960 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
961 reg = <0x01c40000 0x10000>;
962 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
969 interrupt-names = "gp",
970 "gpmmu",
971 "pp0",
972 "ppmmu0",
973 "pp1",
974 "ppmmu1",
975 "pmu";
976 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
977 clock-names = "bus", "core";
978 resets = <&ccu RST_BUS_GPU>;
979 };
981 gic: interrupt-controller@1c81000 {
982 compatible = "arm,gic-400";
983 reg = <0x01c81000 0x1000>,
984 <0x01c82000 0x2000>,
985 <0x01c84000 0x2000>,
986 <0x01c86000 0x2000>;
987 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
988 interrupt-controller;
989 #interrupt-cells = <3>;
990 };
992 pwm: pwm@1c21400 {
993 compatible = "allwinner,sun50i-a64-pwm",
994 "allwinner,sun5i-a13-pwm";
995 reg = <0x01c21400 0x400>;
996 clocks = <&osc24M>;
997 pinctrl-names = "default";
998 pinctrl-0 = <&pwm_pin>;
999 #pwm-cells = <3>;
1000 status = "disabled";
1001 };
1003 csi: csi@1cb0000 {
1004 compatible = "allwinner,sun50i-a64-csi";
1005 reg = <0x01cb0000 0x1000>;
1006 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&ccu CLK_BUS_CSI>,
1008 <&ccu CLK_CSI_SCLK>,
1009 <&ccu CLK_DRAM_CSI>;
1010 clock-names = "bus", "mod", "ram";
1011 resets = <&ccu RST_BUS_CSI>;
1012 pinctrl-names = "default";
1013 pinctrl-0 = <&csi_pins>;
1014 status = "disabled";
1015 };
1017 hdmi: hdmi@1ee0000 {
1018 compatible = "allwinner,sun50i-a64-dw-hdmi",
1019 "allwinner,sun8i-a83t-dw-hdmi";
1020 reg = <0x01ee0000 0x10000>;
1021 reg-io-width = <1>;
1022 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1024 <&ccu CLK_HDMI>;
1025 clock-names = "iahb", "isfr", "tmds";
1026 resets = <&ccu RST_BUS_HDMI1>;
1027 reset-names = "ctrl";
1028 phys = <&hdmi_phy>;
1029 phy-names = "phy";
1030 status = "disabled";
1032 ports {
1033 #address-cells = <1>;
1034 #size-cells = <0>;
1036 hdmi_in: port@0 {
1037 reg = <0>;
1039 hdmi_in_tcon1: endpoint {
1040 remote-endpoint = <&tcon1_out_hdmi>;
1041 };
1042 };
1044 hdmi_out: port@1 {
1045 reg = <1>;
1046 };
1047 };
1048 };
1050 hdmi_phy: hdmi-phy@1ef0000 {
1051 compatible = "allwinner,sun50i-a64-hdmi-phy";
1052 reg = <0x01ef0000 0x10000>;
1053 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1054 <&ccu 7>;
1055 clock-names = "bus", "mod", "pll-0";
1056 resets = <&ccu RST_BUS_HDMI0>;
1057 reset-names = "phy";
1058 #phy-cells = <0>;
1059 };
1061 rtc: rtc@1f00000 {
1062 compatible = "allwinner,sun50i-a64-rtc",
1063 "allwinner,sun8i-h3-rtc";
1064 reg = <0x01f00000 0x400>;
1065 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1066 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1067 clock-output-names = "osc32k", "osc32k-out", "iosc";
1068 clocks = <&osc32k>;
1069 #clock-cells = <1>;
1070 };
1072 r_intc: interrupt-controller@1f00c00 {
1073 compatible = "allwinner,sun50i-a64-r-intc",
1074 "allwinner,sun6i-a31-r-intc";
1075 interrupt-controller;
1076 #interrupt-cells = <2>;
1077 reg = <0x01f00c00 0x400>;
1078 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1079 };
1081 r_ccu: clock@1f01400 {
1082 compatible = "allwinner,sun50i-a64-r-ccu";
1083 reg = <0x01f01400 0x100>;
1084 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>;
1085 clock-names = "hosc", "losc", "iosc", "pll-periph";
1086 #clock-cells = <1>;
1087 #reset-cells = <1>;
1088 };
1090 codec_analog: codec-analog@1f015c0 {
1091 compatible = "allwinner,sun50i-a64-codec-analog";
1092 reg = <0x01f015c0 0x4>;
1093 status = "disabled";
1094 };
1096 r_i2c: i2c@1f02400 {
1097 compatible = "allwinner,sun50i-a64-i2c",
1098 "allwinner,sun6i-a31-i2c";
1099 reg = <0x01f02400 0x400>;
1100 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1101 clocks = <&r_ccu CLK_APB0_I2C>;
1102 resets = <&r_ccu RST_APB0_I2C>;
1103 status = "disabled";
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1106 };
1108 r_ir: ir@1f02000 {
1109 compatible = "allwinner,sun50i-a64-ir",
1110 "allwinner,sun6i-a31-ir";
1111 reg = <0x01f02000 0x400>;
1112 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1113 clock-names = "apb", "ir";
1114 resets = <&r_ccu RST_APB0_IR>;
1115 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&r_ir_rx_pin>;
1118 status = "disabled";
1119 };
1121 r_pwm: pwm@1f03800 {
1122 compatible = "allwinner,sun50i-a64-pwm",
1123 "allwinner,sun5i-a13-pwm";
1124 reg = <0x01f03800 0x400>;
1125 clocks = <&osc24M>;
1126 pinctrl-names = "default";
1127 pinctrl-0 = <&r_pwm_pin>;
1128 #pwm-cells = <3>;
1129 status = "disabled";
1130 };
1132 r_pio: pinctrl@1f02c00 {
1133 compatible = "allwinner,sun50i-a64-r-pinctrl";
1134 reg = <0x01f02c00 0x400>;
1135 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1137 clock-names = "apb", "hosc", "losc";
1138 gpio-controller;
1139 #gpio-cells = <3>;
1140 interrupt-controller;
1141 #interrupt-cells = <3>;
1143 r_i2c_pl89_pins: r-i2c-pl89-pins {
1144 pins = "PL8", "PL9";
1145 function = "s_i2c";
1146 };
1148 r_ir_rx_pin: r-ir-rx-pin {
1149 pins = "PL11";
1150 function = "s_cir_rx";
1151 };
1153 r_pwm_pin: r-pwm-pin {
1154 pins = "PL10";
1155 function = "s_pwm";
1156 };
1158 r_rsb_pins: r-rsb-pins {
1159 pins = "PL0", "PL1";
1160 function = "s_rsb";
1161 };
1162 };
1164 r_rsb: rsb@1f03400 {
1165 compatible = "allwinner,sun8i-a23-rsb";
1166 reg = <0x01f03400 0x400>;
1167 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&r_ccu 6>;
1169 clock-frequency = <3000000>;
1170 resets = <&r_ccu 2>;
1171 pinctrl-names = "default";
1172 pinctrl-0 = <&r_rsb_pins>;
1173 status = "disabled";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1176 };
1178 wdt0: watchdog@1c20ca0 {
1179 compatible = "allwinner,sun50i-a64-wdt",
1180 "allwinner,sun6i-a31-wdt";
1181 reg = <0x01c20ca0 0x20>;
1182 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&osc24M>;
1184 };
1185 };
1186 };