| blob | a6f9b7784e8fc8c98bcf90b152a136cc97691c7c |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
4 *
5 * Copyright 2018 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
8 *
9 */
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 / {
15 compatible = "fsl,ls1028a";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu0: cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a72";
27 reg = <0x0>;
28 enable-method = "psci";
29 clocks = <&clockgen 1 0>;
30 next-level-cache = <&l2>;
31 cpu-idle-states = <&CPU_PW20>;
32 #cooling-cells = <2>;
33 };
35 cpu1: cpu@1 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a72";
38 reg = <0x1>;
39 enable-method = "psci";
40 clocks = <&clockgen 1 0>;
41 next-level-cache = <&l2>;
42 cpu-idle-states = <&CPU_PW20>;
43 #cooling-cells = <2>;
44 };
46 l2: l2-cache {
47 compatible = "cache";
48 };
49 };
51 idle-states {
52 /*
53 * PSCI node is not added default, U-boot will add missing
54 * parts if it determines to use PSCI.
55 */
56 entry-method = "arm,psci";
58 CPU_PW20: cpu-pw20 {
59 compatible = "arm,idle-state";
60 idle-state-name = "PW20";
61 arm,psci-suspend-param = <0x0>;
62 entry-latency-us = <2000>;
63 exit-latency-us = <2000>;
64 min-residency-us = <6000>;
65 };
66 };
68 sysclk: clock-sysclk {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <100000000>;
72 clock-output-names = "sysclk";
73 };
75 osc_27m: clock-osc-27m {
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <27000000>;
79 clock-output-names = "phy_27m";
80 };
82 dpclk: clock-controller@f1f0000 {
83 compatible = "fsl,ls1028a-plldig";
84 reg = <0x0 0xf1f0000 0x0 0xffff>;
85 #clock-cells = <0>;
86 clocks = <&osc_27m>;
87 };
89 reboot {
90 compatible ="syscon-reboot";
91 regmap = <&rst>;
92 offset = <0xb0>;
93 mask = <0x02>;
94 };
96 timer {
97 compatible = "arm,armv8-timer";
98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
99 IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
101 IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
103 IRQ_TYPE_LEVEL_LOW)>,
104 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
105 IRQ_TYPE_LEVEL_LOW)>;
106 };
108 pmu {
109 compatible = "arm,cortex-a72-pmu";
110 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
111 };
113 gic: interrupt-controller@6000000 {
114 compatible= "arm,gic-v3";
115 #address-cells = <2>;
116 #size-cells = <2>;
117 ranges;
118 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
119 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
120 #interrupt-cells= <3>;
121 interrupt-controller;
122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
123 IRQ_TYPE_LEVEL_LOW)>;
124 its: gic-its@6020000 {
125 compatible = "arm,gic-v3-its";
126 msi-controller;
127 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
128 };
129 };
131 thermal-zones {
132 core-cluster {
133 polling-delay-passive = <1000>;
134 polling-delay = <5000>;
135 thermal-sensors = <&tmu 0>;
137 trips {
138 core_cluster_alert: core-cluster-alert {
139 temperature = <85000>;
140 hysteresis = <2000>;
141 type = "passive";
142 };
144 core_cluster_crit: core-cluster-crit {
145 temperature = <95000>;
146 hysteresis = <2000>;
147 type = "critical";
148 };
149 };
151 cooling-maps {
152 map0 {
153 trip = <&core_cluster_alert>;
154 cooling-device =
155 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
156 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
157 };
158 };
159 };
160 };
162 soc: soc {
163 compatible = "simple-bus";
164 #address-cells = <2>;
165 #size-cells = <2>;
166 ranges;
168 ddr: memory-controller@1080000 {
169 compatible = "fsl,qoriq-memory-controller";
170 reg = <0x0 0x1080000 0x0 0x1000>;
171 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
172 big-endian;
173 };
175 dcfg: syscon@1e00000 {
176 compatible = "fsl,ls1028a-dcfg", "syscon";
177 reg = <0x0 0x1e00000 0x0 0x10000>;
178 little-endian;
179 };
181 rst: syscon@1e60000 {
182 compatible = "syscon";
183 reg = <0x0 0x1e60000 0x0 0x10000>;
184 little-endian;
185 };
187 scfg: syscon@1fc0000 {
188 compatible = "fsl,ls1028a-scfg", "syscon";
189 reg = <0x0 0x1fc0000 0x0 0x10000>;
190 big-endian;
191 };
193 clockgen: clock-controller@1300000 {
194 compatible = "fsl,ls1028a-clockgen";
195 reg = <0x0 0x1300000 0x0 0xa0000>;
196 #clock-cells = <2>;
197 clocks = <&sysclk>;
198 };
200 i2c0: i2c@2000000 {
201 compatible = "fsl,vf610-i2c";
202 #address-cells = <1>;
203 #size-cells = <0>;
204 reg = <0x0 0x2000000 0x0 0x10000>;
205 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&clockgen 4 3>;
207 status = "disabled";
208 };
210 i2c1: i2c@2010000 {
211 compatible = "fsl,vf610-i2c";
212 #address-cells = <1>;
213 #size-cells = <0>;
214 reg = <0x0 0x2010000 0x0 0x10000>;
215 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clockgen 4 3>;
217 status = "disabled";
218 };
220 i2c2: i2c@2020000 {
221 compatible = "fsl,vf610-i2c";
222 #address-cells = <1>;
223 #size-cells = <0>;
224 reg = <0x0 0x2020000 0x0 0x10000>;
225 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clockgen 4 3>;
227 status = "disabled";
228 };
230 i2c3: i2c@2030000 {
231 compatible = "fsl,vf610-i2c";
232 #address-cells = <1>;
233 #size-cells = <0>;
234 reg = <0x0 0x2030000 0x0 0x10000>;
235 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&clockgen 4 3>;
237 status = "disabled";
238 };
240 i2c4: i2c@2040000 {
241 compatible = "fsl,vf610-i2c";
242 #address-cells = <1>;
243 #size-cells = <0>;
244 reg = <0x0 0x2040000 0x0 0x10000>;
245 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&clockgen 4 3>;
247 status = "disabled";
248 };
250 i2c5: i2c@2050000 {
251 compatible = "fsl,vf610-i2c";
252 #address-cells = <1>;
253 #size-cells = <0>;
254 reg = <0x0 0x2050000 0x0 0x10000>;
255 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&clockgen 4 3>;
257 status = "disabled";
258 };
260 i2c6: i2c@2060000 {
261 compatible = "fsl,vf610-i2c";
262 #address-cells = <1>;
263 #size-cells = <0>;
264 reg = <0x0 0x2060000 0x0 0x10000>;
265 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&clockgen 4 3>;
267 status = "disabled";
268 };
270 i2c7: i2c@2070000 {
271 compatible = "fsl,vf610-i2c";
272 #address-cells = <1>;
273 #size-cells = <0>;
274 reg = <0x0 0x2070000 0x0 0x10000>;
275 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&clockgen 4 3>;
277 status = "disabled";
278 };
280 esdhc: mmc@2140000 {
281 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
282 reg = <0x0 0x2140000 0x0 0x10000>;
283 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
284 clock-frequency = <0>; /* fixed up by bootloader */
285 clocks = <&clockgen 2 1>;
286 voltage-ranges = <1800 1800 3300 3300>;
287 sdhci,auto-cmd12;
288 little-endian;
289 bus-width = <4>;
290 status = "disabled";
291 };
293 esdhc1: mmc@2150000 {
294 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
295 reg = <0x0 0x2150000 0x0 0x10000>;
296 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
297 clock-frequency = <0>; /* fixed up by bootloader */
298 clocks = <&clockgen 2 1>;
299 voltage-ranges = <1800 1800 3300 3300>;
300 sdhci,auto-cmd12;
301 broken-cd;
302 little-endian;
303 bus-width = <4>;
304 status = "disabled";
305 };
307 duart0: serial@21c0500 {
308 compatible = "fsl,ns16550", "ns16550a";
309 reg = <0x00 0x21c0500 0x0 0x100>;
310 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clockgen 4 1>;
312 status = "disabled";
313 };
315 duart1: serial@21c0600 {
316 compatible = "fsl,ns16550", "ns16550a";
317 reg = <0x00 0x21c0600 0x0 0x100>;
318 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clockgen 4 1>;
320 status = "disabled";
321 };
323 edma0: dma-controller@22c0000 {
324 #dma-cells = <2>;
325 compatible = "fsl,vf610-edma";
326 reg = <0x0 0x22c0000 0x0 0x10000>,
327 <0x0 0x22d0000 0x0 0x10000>,
328 <0x0 0x22e0000 0x0 0x10000>;
329 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
331 interrupt-names = "edma-tx", "edma-err";
332 dma-channels = <32>;
333 clock-names = "dmamux0", "dmamux1";
334 clocks = <&clockgen 4 1>,
335 <&clockgen 4 1>;
336 };
338 gpio1: gpio@2300000 {
339 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
340 reg = <0x0 0x2300000 0x0 0x10000>;
341 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
342 gpio-controller;
343 #gpio-cells = <2>;
344 interrupt-controller;
345 #interrupt-cells = <2>;
346 little-endian;
347 };
349 gpio2: gpio@2310000 {
350 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
351 reg = <0x0 0x2310000 0x0 0x10000>;
352 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
353 gpio-controller;
354 #gpio-cells = <2>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 little-endian;
358 };
360 gpio3: gpio@2320000 {
361 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
362 reg = <0x0 0x2320000 0x0 0x10000>;
363 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 little-endian;
369 };
371 usb0: usb@3100000 {
372 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
373 reg = <0x0 0x3100000 0x0 0x10000>;
374 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
375 dr_mode = "host";
376 snps,dis_rxdet_inp3_quirk;
377 snps,quirk-frame-length-adjustment = <0x20>;
378 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
379 };
381 usb1: usb@3110000 {
382 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
383 reg = <0x0 0x3110000 0x0 0x10000>;
384 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
385 dr_mode = "host";
386 snps,dis_rxdet_inp3_quirk;
387 snps,quirk-frame-length-adjustment = <0x20>;
388 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
389 };
391 sata: sata@3200000 {
392 compatible = "fsl,ls1028a-ahci";
393 reg = <0x0 0x3200000 0x0 0x10000>,
394 <0x7 0x100520 0x0 0x4>;
395 reg-names = "ahci", "sata-ecc";
396 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clockgen 4 1>;
398 status = "disabled";
399 };
401 smmu: iommu@5000000 {
402 compatible = "arm,mmu-500";
403 reg = <0 0x5000000 0 0x800000>;
404 #global-interrupts = <8>;
405 #iommu-cells = <1>;
406 stream-match-mask = <0x7c00>;
407 /* global secure fault */
408 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
409 /* combined secure interrupt */
410 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
411 /* global non-secure fault */
412 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
413 /* combined non-secure interrupt */
414 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
415 /* performance counter interrupts 0-7 */
416 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
418 /* per context interrupt, 64 interrupts */
419 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
451 };
453 crypto: crypto@8000000 {
454 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
455 fsl,sec-era = <10>;
456 #address-cells = <1>;
457 #size-cells = <1>;
458 ranges = <0x0 0x00 0x8000000 0x100000>;
459 reg = <0x00 0x8000000 0x0 0x100000>;
460 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
461 dma-coherent;
463 sec_jr0: jr@10000 {
464 compatible = "fsl,sec-v5.0-job-ring",
465 "fsl,sec-v4.0-job-ring";
466 reg = <0x10000 0x10000>;
467 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
468 };
470 sec_jr1: jr@20000 {
471 compatible = "fsl,sec-v5.0-job-ring",
472 "fsl,sec-v4.0-job-ring";
473 reg = <0x20000 0x10000>;
474 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
475 };
477 sec_jr2: jr@30000 {
478 compatible = "fsl,sec-v5.0-job-ring",
479 "fsl,sec-v4.0-job-ring";
480 reg = <0x30000 0x10000>;
481 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
482 };
484 sec_jr3: jr@40000 {
485 compatible = "fsl,sec-v5.0-job-ring",
486 "fsl,sec-v4.0-job-ring";
487 reg = <0x40000 0x10000>;
488 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
489 };
490 };
492 qdma: dma-controller@8380000 {
493 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
494 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
495 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
496 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
497 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
502 interrupt-names = "qdma-error", "qdma-queue0",
503 "qdma-queue1", "qdma-queue2", "qdma-queue3";
504 dma-channels = <8>;
505 block-number = <1>;
506 block-offset = <0x10000>;
507 fsl,dma-queues = <2>;
508 status-sizes = <64>;
509 queue-sizes = <64 64>;
510 };
512 cluster1_core0_watchdog: watchdog@c000000 {
513 compatible = "arm,sp805", "arm,primecell";
514 reg = <0x0 0xc000000 0x0 0x1000>;
515 clocks = <&clockgen 4 15>, <&clockgen 4 15>;
516 clock-names = "apb_pclk", "wdog_clk";
517 };
519 cluster1_core1_watchdog: watchdog@c010000 {
520 compatible = "arm,sp805", "arm,primecell";
521 reg = <0x0 0xc010000 0x0 0x1000>;
522 clocks = <&clockgen 4 15>, <&clockgen 4 15>;
523 clock-names = "apb_pclk", "wdog_clk";
524 };
526 sai1: audio-controller@f100000 {
527 #sound-dai-cells = <0>;
528 compatible = "fsl,vf610-sai";
529 reg = <0x0 0xf100000 0x0 0x10000>;
530 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
532 <&clockgen 4 1>, <&clockgen 4 1>;
533 clock-names = "bus", "mclk1", "mclk2", "mclk3";
534 dma-names = "tx", "rx";
535 dmas = <&edma0 1 4>,
536 <&edma0 1 3>;
537 status = "disabled";
538 };
540 sai2: audio-controller@f110000 {
541 #sound-dai-cells = <0>;
542 compatible = "fsl,vf610-sai";
543 reg = <0x0 0xf110000 0x0 0x10000>;
544 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
546 <&clockgen 4 1>, <&clockgen 4 1>;
547 clock-names = "bus", "mclk1", "mclk2", "mclk3";
548 dma-names = "tx", "rx";
549 dmas = <&edma0 1 6>,
550 <&edma0 1 5>;
551 status = "disabled";
552 };
554 sai4: audio-controller@f130000 {
555 #sound-dai-cells = <0>;
556 compatible = "fsl,vf610-sai";
557 reg = <0x0 0xf130000 0x0 0x10000>;
558 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
560 <&clockgen 4 1>, <&clockgen 4 1>;
561 clock-names = "bus", "mclk1", "mclk2", "mclk3";
562 dma-names = "tx", "rx";
563 dmas = <&edma0 1 10>,
564 <&edma0 1 9>;
565 status = "disabled";
566 };
568 tmu: tmu@1f80000 {
569 compatible = "fsl,qoriq-tmu";
570 reg = <0x0 0x1f80000 0x0 0x10000>;
571 interrupts = <0 23 0x4>;
572 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
573 fsl,tmu-calibration = <0x00000000 0x00000024
574 0x00000001 0x0000002b
575 0x00000002 0x00000031
576 0x00000003 0x00000038
577 0x00000004 0x0000003f
578 0x00000005 0x00000045
579 0x00000006 0x0000004c
580 0x00000007 0x00000053
581 0x00000008 0x00000059
582 0x00000009 0x00000060
583 0x0000000a 0x00000066
584 0x0000000b 0x0000006d
586 0x00010000 0x0000001c
587 0x00010001 0x00000024
588 0x00010002 0x0000002c
589 0x00010003 0x00000035
590 0x00010004 0x0000003d
591 0x00010005 0x00000045
592 0x00010006 0x0000004d
593 0x00010007 0x00000055
594 0x00010008 0x0000005e
595 0x00010009 0x00000066
596 0x0001000a 0x0000006e
598 0x00020000 0x00000018
599 0x00020001 0x00000022
600 0x00020002 0x0000002d
601 0x00020003 0x00000038
602 0x00020004 0x00000043
603 0x00020005 0x0000004d
604 0x00020006 0x00000058
605 0x00020007 0x00000063
606 0x00020008 0x0000006e
608 0x00030000 0x00000010
609 0x00030001 0x0000001c
610 0x00030002 0x00000029
611 0x00030003 0x00000036
612 0x00030004 0x00000042
613 0x00030005 0x0000004f
614 0x00030006 0x0000005b
615 0x00030007 0x00000068>;
616 little-endian;
617 #thermal-sensor-cells = <1>;
618 };
620 pcie@1f0000000 { /* Integrated Endpoint Root Complex */
621 compatible = "pci-host-ecam-generic";
622 reg = <0x01 0xf0000000 0x0 0x100000>;
623 #address-cells = <3>;
624 #size-cells = <2>;
625 #interrupt-cells = <1>;
626 msi-parent = <&its>;
627 device_type = "pci";
628 bus-range = <0x0 0x0>;
629 dma-coherent;
630 msi-map = <0 &its 0x17 0xe>;
631 iommu-map = <0 &smmu 0x17 0xe>;
632 /* PF0-6 BAR0 - non-prefetchable memory */
633 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000
634 /* PF0-6 BAR2 - prefetchable memory */
635 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000
636 /* PF0: VF0-1 BAR0 - non-prefetchable memory */
637 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000
638 /* PF0: VF0-1 BAR2 - prefetchable memory */
639 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000
640 /* PF1: VF0-1 BAR0 - non-prefetchable memory */
641 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
642 /* PF1: VF0-1 BAR2 - prefetchable memory */
643 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>;
645 enetc_port0: ethernet@0,0 {
646 compatible = "fsl,enetc";
647 reg = <0x000000 0 0 0 0>;
648 };
649 enetc_port1: ethernet@0,1 {
650 compatible = "fsl,enetc";
651 reg = <0x000100 0 0 0 0>;
652 };
653 enetc_mdio_pf3: mdio@0,3 {
654 compatible = "fsl,enetc-mdio";
655 reg = <0x000300 0 0 0 0>;
656 #address-cells = <1>;
657 #size-cells = <0>;
658 };
659 ethernet@0,4 {
660 compatible = "fsl,enetc-ptp";
661 reg = <0x000400 0 0 0 0>;
662 clocks = <&clockgen 4 0>;
663 little-endian;
664 };
665 };
666 };
668 malidp0: display@f080000 {
669 compatible = "arm,mali-dp500";
670 reg = <0x0 0xf080000 0x0 0x10000>;
671 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
672 <0 223 IRQ_TYPE_LEVEL_HIGH>;
673 interrupt-names = "DE", "SE";
674 clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
675 <&clockgen 2 2>;
676 clock-names = "pxlclk", "mclk", "aclk", "pclk";
677 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
678 arm,malidp-arqos-value = <0xd000d000>;
680 port {
681 dp0_out: endpoint {
683 };
684 };
685 };
686 };