arch/arm64/include/asm/cache.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012 ARM Ltd.
   4  */
   5 #ifndef __ASM_CACHE_H
   6 #define __ASM_CACHE_H
   7
   8 #include <asm/cputype.h>
   9
  10 #define CTR_L1IP_SHIFT          14
  11 #define CTR_L1IP_MASK           3
  12 #define CTR_DMINLINE_SHIFT      16
  13 #define CTR_IMINLINE_SHIFT      0
  14 #define CTR_IMINLINE_MASK       0xf
  15 #define CTR_ERG_SHIFT           20
  16 #define CTR_CWG_SHIFT           24
  17 #define CTR_CWG_MASK            15
  18 #define CTR_IDC_SHIFT           28
  19 #define CTR_DIC_SHIFT           29
  20
  21 #define CTR_CACHE_MINLINE_MASK  \
  22         (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
  23
  24 #define CTR_L1IP(ctr)           (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
  25
  26 #define ICACHE_POLICY_VPIPT     0
  27 #define ICACHE_POLICY_VIPT      2
  28 #define ICACHE_POLICY_PIPT      3
  29
  30 #define L1_CACHE_SHIFT          (6)
  31 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
  32
  33
  34 #define CLIDR_LOUU_SHIFT        27
  35 #define CLIDR_LOC_SHIFT         24
  36 #define CLIDR_LOUIS_SHIFT       21
  37
  38 #define CLIDR_LOUU(clidr)       (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
  39 #define CLIDR_LOC(clidr)        (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
  40 #define CLIDR_LOUIS(clidr)      (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
  41
  42 /*
  43  * Memory returned by kmalloc() may be used for DMA, so we must make
  44  * sure that all such allocations are cache aligned. Otherwise,
  45  * unrelated code may cause parts of the buffer to be read into the
  46  * cache before the transfer is done, causing old data to be seen by
  47  * the CPU.
  48  */
  49 #define ARCH_DMA_MINALIGN       (128)
  50
  51 #ifdef CONFIG_KASAN_SW_TAGS
  52 #define ARCH_SLAB_MINALIGN      (1ULL << KASAN_SHADOW_SCALE_SHIFT)
  53 #endif
  54
  55 #ifndef __ASSEMBLY__
  56
  57 #include <linux/bitops.h>
  58
  59 #define ICACHEF_ALIASING        0
  60 #define ICACHEF_VPIPT           1
  61 extern unsigned long __icache_flags;
  62
  63 /*
  64  * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
  65  * permitted in the I-cache.
  66  */
  67 static inline int icache_is_aliasing(void)
  68 {
  69         return test_bit(ICACHEF_ALIASING, &__icache_flags);
  70 }
  71
  72 static inline int icache_is_vpipt(void)
  73 {
  74         return test_bit(ICACHEF_VPIPT, &__icache_flags);
  75 }
  76
  77 static inline u32 cache_type_cwg(void)
  78 {
  79         return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
  80 }
  81
  82 #define __read_mostly __section(.data..read_mostly)
  83
  84 static inline int cache_line_size_of_cpu(void)
  85 {
  86         u32 cwg = cache_type_cwg();
  87
  88         return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
  89 }
  90
  91 int cache_line_size(void);
  92
  93 /*
  94  * Read the effective value of CTR_EL0.
  95  *
  96  * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
  97  * section D10.2.33 "CTR_EL0, Cache Type Register" :
  98  *
  99  * CTR_EL0.IDC reports the data cache clean requirements for
 100  * instruction to data coherence.
 101  *
 102  *  0 - dcache clean to PoU is required unless :
 103  *     (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
 104  *  1 - dcache clean to PoU is not required for i-to-d coherence.
 105  *
 106  * This routine provides the CTR_EL0 with the IDC field updated to the
 107  * effective state.
 108  */
 109 static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
 110 {
 111         u32 ctr = read_cpuid_cachetype();
 112
 113         if (!(ctr & BIT(CTR_IDC_SHIFT))) {
 114                 u64 clidr = read_sysreg(clidr_el1);
 115
 116                 if (CLIDR_LOC(clidr) == 0 ||
 117                     (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
 118                         ctr |= BIT(CTR_IDC_SHIFT);
 119         }
 120
 121         return ctr;
 122 }
 123
 124 #endif  /* __ASSEMBLY__ */
 125
 126 #endif