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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / arch / x86 / events / intel / core.c
blob3be51aa06e67ec2e5b893af82096b43db5c3f23a
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17
18 #include <asm/cpufeature.h>
19 #include <asm/hardirq.h>
20 #include <asm/intel-family.h>
21 #include <asm/intel_pt.h>
22 #include <asm/apic.h>
23 #include <asm/cpu_device_id.h>
24
25 #include "../perf_event.h"
26
27 /*
28 * Intel PerfMon, used on Core and later.
29 */
30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
31 {
32 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
33 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
34 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
35 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
36 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
37 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
38 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
39 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
40 };
41
42 static struct event_constraint intel_core_event_constraints[] __read_mostly =
43 {
44 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
45 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
46 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
47 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
48 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
49 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
50 EVENT_CONSTRAINT_END
51 };
52
53 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
54 {
55 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
57 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
58 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
59 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
60 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
61 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
62 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
63 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
64 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
65 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
66 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
67 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
68 EVENT_CONSTRAINT_END
69 };
70
71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
72 {
73 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
75 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
76 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
77 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
78 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
79 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
80 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
81 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
82 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
83 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
84 EVENT_CONSTRAINT_END
85 };
86
87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
88 {
89 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
90 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
91 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
92 EVENT_EXTRA_END
93 };
94
95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
96 {
97 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
99 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
100 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
101 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
102 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
103 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
104 EVENT_CONSTRAINT_END
105 };
106
107 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
108 {
109 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
111 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
112 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
113 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
115 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
116 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
118 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
119 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
120 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
121
122 /*
123 * When HT is off these events can only run on the bottom 4 counters
124 * When HT is on, they are impacted by the HT bug and require EXCL access
125 */
126 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
127 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
128 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
129 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
130
131 EVENT_CONSTRAINT_END
132 };
133
134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
135 {
136 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
138 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
139 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
141 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
142 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
144 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
146 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
149
150 /*
151 * When HT is off these events can only run on the bottom 4 counters
152 * When HT is on, they are impacted by the HT bug and require EXCL access
153 */
154 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
155 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
156 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
157 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
158
159 EVENT_CONSTRAINT_END
160 };
161
162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
163 {
164 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
165 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
167 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
168 EVENT_EXTRA_END
169 };
170
171 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
172 {
173 EVENT_CONSTRAINT_END
174 };
175
176 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
177 {
178 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
180 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
181 EVENT_CONSTRAINT_END
182 };
183
184 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
185 {
186 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
188 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
189 EVENT_CONSTRAINT_END
190 };
191
192 static struct event_constraint intel_skl_event_constraints[] = {
193 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
194 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
195 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
196 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
197
198 /*
199 * when HT is off, these can only run on the bottom 4 counters
200 */
201 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
203 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
204 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
205 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
206
207 EVENT_CONSTRAINT_END
208 };
209
210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
211 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
212 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
213 EVENT_EXTRA_END
214 };
215
216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
217 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
218 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
219 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
220 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
221 EVENT_EXTRA_END
222 };
223
224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
225 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
226 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
227 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
228 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
229 EVENT_EXTRA_END
230 };
231
232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
234 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
235 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
236 /*
237 * Note the low 8 bits eventsel code is not a continuous field, containing
238 * some #GPing bits. These are masked out.
239 */
240 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
241 EVENT_EXTRA_END
242 };
243
244 static struct event_constraint intel_icl_event_constraints[] = {
245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
246 INTEL_UEVENT_CONSTRAINT(0x1c0, 0), /* INST_RETIRED.PREC_DIST */
247 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
248 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
249 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
250 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
251 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
252 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
253 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf),
254 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
255 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
256 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
257 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
258 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
259 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
260 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
261 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
262 EVENT_CONSTRAINT_END
263 };
264
265 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
266 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
267 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
268 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
269 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
270 EVENT_EXTRA_END
271 };
272
273 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
274 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
275 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
276
277 static struct attribute *nhm_mem_events_attrs[] = {
278 EVENT_PTR(mem_ld_nhm),
279 NULL,
280 };
281
282 /*
283 * topdown events for Intel Core CPUs.
284 *
285 * The events are all in slots, which is a free slot in a 4 wide
286 * pipeline. Some events are already reported in slots, for cycle
287 * events we multiply by the pipeline width (4).
288 *
289 * With Hyper Threading on, topdown metrics are either summed or averaged
290 * between the threads of a core: (count_t0 + count_t1).
291 *
292 * For the average case the metric is always scaled to pipeline width,
293 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
294 */
295
296 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
297 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
298 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
299 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
300 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
301 "event=0xe,umask=0x1"); /* uops_issued.any */
302 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
303 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
304 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
305 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
306 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
307 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
308 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
309 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
310 "4", "2");
311
312 static struct attribute *snb_events_attrs[] = {
313 EVENT_PTR(td_slots_issued),
314 EVENT_PTR(td_slots_retired),
315 EVENT_PTR(td_fetch_bubbles),
316 EVENT_PTR(td_total_slots),
317 EVENT_PTR(td_total_slots_scale),
318 EVENT_PTR(td_recovery_bubbles),
319 EVENT_PTR(td_recovery_bubbles_scale),
320 NULL,
321 };
322
323 static struct attribute *snb_mem_events_attrs[] = {
324 EVENT_PTR(mem_ld_snb),
325 EVENT_PTR(mem_st_snb),
326 NULL,
327 };
328
329 static struct event_constraint intel_hsw_event_constraints[] = {
330 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
331 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
332 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
333 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
334 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
335 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
336 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
337 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
338 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
339 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
340 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
341 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
342
343 /*
344 * When HT is off these events can only run on the bottom 4 counters
345 * When HT is on, they are impacted by the HT bug and require EXCL access
346 */
347 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
348 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
349 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
350 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
351
352 EVENT_CONSTRAINT_END
353 };
354
355 static struct event_constraint intel_bdw_event_constraints[] = {
356 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
357 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
358 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
359 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
360 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
361 /*
362 * when HT is off, these can only run on the bottom 4 counters
363 */
364 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
365 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
366 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
367 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
368 EVENT_CONSTRAINT_END
369 };
370
371 static u64 intel_pmu_event_map(int hw_event)
372 {
373 return intel_perfmon_event_map[hw_event];
374 }
375
376 /*
377 * Notes on the events:
378 * - data reads do not include code reads (comparable to earlier tables)
379 * - data counts include speculative execution (except L1 write, dtlb, bpu)
380 * - remote node access includes remote memory, remote cache, remote mmio.
381 * - prefetches are not included in the counts.
382 * - icache miss does not include decoded icache
383 */
384
385 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
386 #define SKL_DEMAND_RFO BIT_ULL(1)
387 #define SKL_ANY_RESPONSE BIT_ULL(16)
388 #define SKL_SUPPLIER_NONE BIT_ULL(17)
389 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
390 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
391 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
392 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
393 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
394 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
395 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
396 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
397 #define SKL_SPL_HIT BIT_ULL(30)
398 #define SKL_SNOOP_NONE BIT_ULL(31)
399 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
400 #define SKL_SNOOP_MISS BIT_ULL(33)
401 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
402 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
403 #define SKL_SNOOP_HITM BIT_ULL(36)
404 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
405 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
406 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
407 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
408 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
409 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
410 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
411 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
412 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
413 SKL_SNOOP_HITM|SKL_SPL_HIT)
414 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
415 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
416 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
417 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
418 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
419
420 static __initconst const u64 skl_hw_cache_event_ids
421 [PERF_COUNT_HW_CACHE_MAX]
422 [PERF_COUNT_HW_CACHE_OP_MAX]
423 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
424 {
425 [ C(L1D ) ] = {
426 [ C(OP_READ) ] = {
427 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
428 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
429 },
430 [ C(OP_WRITE) ] = {
431 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
432 [ C(RESULT_MISS) ] = 0x0,
433 },
434 [ C(OP_PREFETCH) ] = {
435 [ C(RESULT_ACCESS) ] = 0x0,
436 [ C(RESULT_MISS) ] = 0x0,
437 },
438 },
439 [ C(L1I ) ] = {
440 [ C(OP_READ) ] = {
441 [ C(RESULT_ACCESS) ] = 0x0,
442 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
443 },
444 [ C(OP_WRITE) ] = {
445 [ C(RESULT_ACCESS) ] = -1,
446 [ C(RESULT_MISS) ] = -1,
447 },
448 [ C(OP_PREFETCH) ] = {
449 [ C(RESULT_ACCESS) ] = 0x0,
450 [ C(RESULT_MISS) ] = 0x0,
451 },
452 },
453 [ C(LL ) ] = {
454 [ C(OP_READ) ] = {
455 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
456 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
457 },
458 [ C(OP_WRITE) ] = {
459 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
460 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
461 },
462 [ C(OP_PREFETCH) ] = {
463 [ C(RESULT_ACCESS) ] = 0x0,
464 [ C(RESULT_MISS) ] = 0x0,
465 },
466 },
467 [ C(DTLB) ] = {
468 [ C(OP_READ) ] = {
469 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
470 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
471 },
472 [ C(OP_WRITE) ] = {
473 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
474 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
475 },
476 [ C(OP_PREFETCH) ] = {
477 [ C(RESULT_ACCESS) ] = 0x0,
478 [ C(RESULT_MISS) ] = 0x0,
479 },
480 },
481 [ C(ITLB) ] = {
482 [ C(OP_READ) ] = {
483 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
484 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
485 },
486 [ C(OP_WRITE) ] = {
487 [ C(RESULT_ACCESS) ] = -1,
488 [ C(RESULT_MISS) ] = -1,
489 },
490 [ C(OP_PREFETCH) ] = {
491 [ C(RESULT_ACCESS) ] = -1,
492 [ C(RESULT_MISS) ] = -1,
493 },
494 },
495 [ C(BPU ) ] = {
496 [ C(OP_READ) ] = {
497 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
498 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
499 },
500 [ C(OP_WRITE) ] = {
501 [ C(RESULT_ACCESS) ] = -1,
502 [ C(RESULT_MISS) ] = -1,
503 },
504 [ C(OP_PREFETCH) ] = {
505 [ C(RESULT_ACCESS) ] = -1,
506 [ C(RESULT_MISS) ] = -1,
507 },
508 },
509 [ C(NODE) ] = {
510 [ C(OP_READ) ] = {
511 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
512 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
513 },
514 [ C(OP_WRITE) ] = {
515 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
516 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
517 },
518 [ C(OP_PREFETCH) ] = {
519 [ C(RESULT_ACCESS) ] = 0x0,
520 [ C(RESULT_MISS) ] = 0x0,
521 },
522 },
523 };
524
525 static __initconst const u64 skl_hw_cache_extra_regs
526 [PERF_COUNT_HW_CACHE_MAX]
527 [PERF_COUNT_HW_CACHE_OP_MAX]
528 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
529 {
530 [ C(LL ) ] = {
531 [ C(OP_READ) ] = {
532 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
533 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
534 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
535 SKL_L3_MISS|SKL_ANY_SNOOP|
536 SKL_SUPPLIER_NONE,
537 },
538 [ C(OP_WRITE) ] = {
539 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
540 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
541 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
542 SKL_L3_MISS|SKL_ANY_SNOOP|
543 SKL_SUPPLIER_NONE,
544 },
545 [ C(OP_PREFETCH) ] = {
546 [ C(RESULT_ACCESS) ] = 0x0,
547 [ C(RESULT_MISS) ] = 0x0,
548 },
549 },
550 [ C(NODE) ] = {
551 [ C(OP_READ) ] = {
552 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
553 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
554 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
555 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
556 },
557 [ C(OP_WRITE) ] = {
558 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
559 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
560 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
561 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
562 },
563 [ C(OP_PREFETCH) ] = {
564 [ C(RESULT_ACCESS) ] = 0x0,
565 [ C(RESULT_MISS) ] = 0x0,
566 },
567 },
568 };
569
570 #define SNB_DMND_DATA_RD (1ULL << 0)
571 #define SNB_DMND_RFO (1ULL << 1)
572 #define SNB_DMND_IFETCH (1ULL << 2)
573 #define SNB_DMND_WB (1ULL << 3)
574 #define SNB_PF_DATA_RD (1ULL << 4)
575 #define SNB_PF_RFO (1ULL << 5)
576 #define SNB_PF_IFETCH (1ULL << 6)
577 #define SNB_LLC_DATA_RD (1ULL << 7)
578 #define SNB_LLC_RFO (1ULL << 8)
579 #define SNB_LLC_IFETCH (1ULL << 9)
580 #define SNB_BUS_LOCKS (1ULL << 10)
581 #define SNB_STRM_ST (1ULL << 11)
582 #define SNB_OTHER (1ULL << 15)
583 #define SNB_RESP_ANY (1ULL << 16)
584 #define SNB_NO_SUPP (1ULL << 17)
585 #define SNB_LLC_HITM (1ULL << 18)
586 #define SNB_LLC_HITE (1ULL << 19)
587 #define SNB_LLC_HITS (1ULL << 20)
588 #define SNB_LLC_HITF (1ULL << 21)
589 #define SNB_LOCAL (1ULL << 22)
590 #define SNB_REMOTE (0xffULL << 23)
591 #define SNB_SNP_NONE (1ULL << 31)
592 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
593 #define SNB_SNP_MISS (1ULL << 33)
594 #define SNB_NO_FWD (1ULL << 34)
595 #define SNB_SNP_FWD (1ULL << 35)
596 #define SNB_HITM (1ULL << 36)
597 #define SNB_NON_DRAM (1ULL << 37)
598
599 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
600 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
601 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
602
603 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
604 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
605 SNB_HITM)
606
607 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
608 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
609
610 #define SNB_L3_ACCESS SNB_RESP_ANY
611 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
612
613 static __initconst const u64 snb_hw_cache_extra_regs
614 [PERF_COUNT_HW_CACHE_MAX]
615 [PERF_COUNT_HW_CACHE_OP_MAX]
616 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
617 {
618 [ C(LL ) ] = {
619 [ C(OP_READ) ] = {
620 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
621 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
622 },
623 [ C(OP_WRITE) ] = {
624 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
625 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
626 },
627 [ C(OP_PREFETCH) ] = {
628 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
629 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
630 },
631 },
632 [ C(NODE) ] = {
633 [ C(OP_READ) ] = {
634 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
635 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
636 },
637 [ C(OP_WRITE) ] = {
638 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
639 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
640 },
641 [ C(OP_PREFETCH) ] = {
642 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
643 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
644 },
645 },
646 };
647
648 static __initconst const u64 snb_hw_cache_event_ids
649 [PERF_COUNT_HW_CACHE_MAX]
650 [PERF_COUNT_HW_CACHE_OP_MAX]
651 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
652 {
653 [ C(L1D) ] = {
654 [ C(OP_READ) ] = {
655 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
656 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
657 },
658 [ C(OP_WRITE) ] = {
659 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
660 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
661 },
662 [ C(OP_PREFETCH) ] = {
663 [ C(RESULT_ACCESS) ] = 0x0,
664 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
665 },
666 },
667 [ C(L1I ) ] = {
668 [ C(OP_READ) ] = {
669 [ C(RESULT_ACCESS) ] = 0x0,
670 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
671 },
672 [ C(OP_WRITE) ] = {
673 [ C(RESULT_ACCESS) ] = -1,
674 [ C(RESULT_MISS) ] = -1,
675 },
676 [ C(OP_PREFETCH) ] = {
677 [ C(RESULT_ACCESS) ] = 0x0,
678 [ C(RESULT_MISS) ] = 0x0,
679 },
680 },
681 [ C(LL ) ] = {
682 [ C(OP_READ) ] = {
683 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
684 [ C(RESULT_ACCESS) ] = 0x01b7,
685 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
686 [ C(RESULT_MISS) ] = 0x01b7,
687 },
688 [ C(OP_WRITE) ] = {
689 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
690 [ C(RESULT_ACCESS) ] = 0x01b7,
691 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
692 [ C(RESULT_MISS) ] = 0x01b7,
693 },
694 [ C(OP_PREFETCH) ] = {
695 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
696 [ C(RESULT_ACCESS) ] = 0x01b7,
697 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
698 [ C(RESULT_MISS) ] = 0x01b7,
699 },
700 },
701 [ C(DTLB) ] = {
702 [ C(OP_READ) ] = {
703 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
704 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
705 },
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
708 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
709 },
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = 0x0,
712 [ C(RESULT_MISS) ] = 0x0,
713 },
714 },
715 [ C(ITLB) ] = {
716 [ C(OP_READ) ] = {
717 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
718 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
719 },
720 [ C(OP_WRITE) ] = {
721 [ C(RESULT_ACCESS) ] = -1,
722 [ C(RESULT_MISS) ] = -1,
723 },
724 [ C(OP_PREFETCH) ] = {
725 [ C(RESULT_ACCESS) ] = -1,
726 [ C(RESULT_MISS) ] = -1,
727 },
728 },
729 [ C(BPU ) ] = {
730 [ C(OP_READ) ] = {
731 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
732 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
733 },
734 [ C(OP_WRITE) ] = {
735 [ C(RESULT_ACCESS) ] = -1,
736 [ C(RESULT_MISS) ] = -1,
737 },
738 [ C(OP_PREFETCH) ] = {
739 [ C(RESULT_ACCESS) ] = -1,
740 [ C(RESULT_MISS) ] = -1,
741 },
742 },
743 [ C(NODE) ] = {
744 [ C(OP_READ) ] = {
745 [ C(RESULT_ACCESS) ] = 0x01b7,
746 [ C(RESULT_MISS) ] = 0x01b7,
747 },
748 [ C(OP_WRITE) ] = {
749 [ C(RESULT_ACCESS) ] = 0x01b7,
750 [ C(RESULT_MISS) ] = 0x01b7,
751 },
752 [ C(OP_PREFETCH) ] = {
753 [ C(RESULT_ACCESS) ] = 0x01b7,
754 [ C(RESULT_MISS) ] = 0x01b7,
755 },
756 },
757
758 };
759
760 /*
761 * Notes on the events:
762 * - data reads do not include code reads (comparable to earlier tables)
763 * - data counts include speculative execution (except L1 write, dtlb, bpu)
764 * - remote node access includes remote memory, remote cache, remote mmio.
765 * - prefetches are not included in the counts because they are not
766 * reliably counted.
767 */
768
769 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
770 #define HSW_DEMAND_RFO BIT_ULL(1)
771 #define HSW_ANY_RESPONSE BIT_ULL(16)
772 #define HSW_SUPPLIER_NONE BIT_ULL(17)
773 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
774 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
775 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
776 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
777 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
778 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
779 HSW_L3_MISS_REMOTE_HOP2P)
780 #define HSW_SNOOP_NONE BIT_ULL(31)
781 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
782 #define HSW_SNOOP_MISS BIT_ULL(33)
783 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
784 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
785 #define HSW_SNOOP_HITM BIT_ULL(36)
786 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
787 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
788 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
789 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
790 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
791 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
792 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
793 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
794 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
795 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
796 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
797
798 #define BDW_L3_MISS_LOCAL BIT(26)
799 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
800 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
801 HSW_L3_MISS_REMOTE_HOP2P)
802
803
804 static __initconst const u64 hsw_hw_cache_event_ids
805 [PERF_COUNT_HW_CACHE_MAX]
806 [PERF_COUNT_HW_CACHE_OP_MAX]
807 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
808 {
809 [ C(L1D ) ] = {
810 [ C(OP_READ) ] = {
811 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
812 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
813 },
814 [ C(OP_WRITE) ] = {
815 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
816 [ C(RESULT_MISS) ] = 0x0,
817 },
818 [ C(OP_PREFETCH) ] = {
819 [ C(RESULT_ACCESS) ] = 0x0,
820 [ C(RESULT_MISS) ] = 0x0,
821 },
822 },
823 [ C(L1I ) ] = {
824 [ C(OP_READ) ] = {
825 [ C(RESULT_ACCESS) ] = 0x0,
826 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
827 },
828 [ C(OP_WRITE) ] = {
829 [ C(RESULT_ACCESS) ] = -1,
830 [ C(RESULT_MISS) ] = -1,
831 },
832 [ C(OP_PREFETCH) ] = {
833 [ C(RESULT_ACCESS) ] = 0x0,
834 [ C(RESULT_MISS) ] = 0x0,
835 },
836 },
837 [ C(LL ) ] = {
838 [ C(OP_READ) ] = {
839 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
840 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
841 },
842 [ C(OP_WRITE) ] = {
843 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
844 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
845 },
846 [ C(OP_PREFETCH) ] = {
847 [ C(RESULT_ACCESS) ] = 0x0,
848 [ C(RESULT_MISS) ] = 0x0,
849 },
850 },
851 [ C(DTLB) ] = {
852 [ C(OP_READ) ] = {
853 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
854 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
855 },
856 [ C(OP_WRITE) ] = {
857 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
858 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
859 },
860 [ C(OP_PREFETCH) ] = {
861 [ C(RESULT_ACCESS) ] = 0x0,
862 [ C(RESULT_MISS) ] = 0x0,
863 },
864 },
865 [ C(ITLB) ] = {
866 [ C(OP_READ) ] = {
867 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
868 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
869 },
870 [ C(OP_WRITE) ] = {
871 [ C(RESULT_ACCESS) ] = -1,
872 [ C(RESULT_MISS) ] = -1,
873 },
874 [ C(OP_PREFETCH) ] = {
875 [ C(RESULT_ACCESS) ] = -1,
876 [ C(RESULT_MISS) ] = -1,
877 },
878 },
879 [ C(BPU ) ] = {
880 [ C(OP_READ) ] = {
881 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
882 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
883 },
884 [ C(OP_WRITE) ] = {
885 [ C(RESULT_ACCESS) ] = -1,
886 [ C(RESULT_MISS) ] = -1,
887 },
888 [ C(OP_PREFETCH) ] = {
889 [ C(RESULT_ACCESS) ] = -1,
890 [ C(RESULT_MISS) ] = -1,
891 },
892 },
893 [ C(NODE) ] = {
894 [ C(OP_READ) ] = {
895 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
896 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
897 },
898 [ C(OP_WRITE) ] = {
899 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
900 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
901 },
902 [ C(OP_PREFETCH) ] = {
903 [ C(RESULT_ACCESS) ] = 0x0,
904 [ C(RESULT_MISS) ] = 0x0,
905 },
906 },
907 };
908
909 static __initconst const u64 hsw_hw_cache_extra_regs
910 [PERF_COUNT_HW_CACHE_MAX]
911 [PERF_COUNT_HW_CACHE_OP_MAX]
912 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
913 {
914 [ C(LL ) ] = {
915 [ C(OP_READ) ] = {
916 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
917 HSW_LLC_ACCESS,
918 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
919 HSW_L3_MISS|HSW_ANY_SNOOP,
920 },
921 [ C(OP_WRITE) ] = {
922 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
923 HSW_LLC_ACCESS,
924 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
925 HSW_L3_MISS|HSW_ANY_SNOOP,
926 },
927 [ C(OP_PREFETCH) ] = {
928 [ C(RESULT_ACCESS) ] = 0x0,
929 [ C(RESULT_MISS) ] = 0x0,
930 },
931 },
932 [ C(NODE) ] = {
933 [ C(OP_READ) ] = {
934 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
935 HSW_L3_MISS_LOCAL_DRAM|
936 HSW_SNOOP_DRAM,
937 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
938 HSW_L3_MISS_REMOTE|
939 HSW_SNOOP_DRAM,
940 },
941 [ C(OP_WRITE) ] = {
942 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
943 HSW_L3_MISS_LOCAL_DRAM|
944 HSW_SNOOP_DRAM,
945 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
946 HSW_L3_MISS_REMOTE|
947 HSW_SNOOP_DRAM,
948 },
949 [ C(OP_PREFETCH) ] = {
950 [ C(RESULT_ACCESS) ] = 0x0,
951 [ C(RESULT_MISS) ] = 0x0,
952 },
953 },
954 };
955
956 static __initconst const u64 westmere_hw_cache_event_ids
957 [PERF_COUNT_HW_CACHE_MAX]
958 [PERF_COUNT_HW_CACHE_OP_MAX]
959 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
960 {
961 [ C(L1D) ] = {
962 [ C(OP_READ) ] = {
963 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
964 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
965 },
966 [ C(OP_WRITE) ] = {
967 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
968 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
969 },
970 [ C(OP_PREFETCH) ] = {
971 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
972 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
973 },
974 },
975 [ C(L1I ) ] = {
976 [ C(OP_READ) ] = {
977 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
978 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
979 },
980 [ C(OP_WRITE) ] = {
981 [ C(RESULT_ACCESS) ] = -1,
982 [ C(RESULT_MISS) ] = -1,
983 },
984 [ C(OP_PREFETCH) ] = {
985 [ C(RESULT_ACCESS) ] = 0x0,
986 [ C(RESULT_MISS) ] = 0x0,
987 },
988 },
989 [ C(LL ) ] = {
990 [ C(OP_READ) ] = {
991 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
992 [ C(RESULT_ACCESS) ] = 0x01b7,
993 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
994 [ C(RESULT_MISS) ] = 0x01b7,
995 },
996 /*
997 * Use RFO, not WRITEBACK, because a write miss would typically occur
998 * on RFO.
999 */
1000 [ C(OP_WRITE) ] = {
1001 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1002 [ C(RESULT_ACCESS) ] = 0x01b7,
1003 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1004 [ C(RESULT_MISS) ] = 0x01b7,
1005 },
1006 [ C(OP_PREFETCH) ] = {
1007 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1008 [ C(RESULT_ACCESS) ] = 0x01b7,
1009 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1010 [ C(RESULT_MISS) ] = 0x01b7,
1011 },
1012 },
1013 [ C(DTLB) ] = {
1014 [ C(OP_READ) ] = {
1015 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1016 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1017 },
1018 [ C(OP_WRITE) ] = {
1019 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1020 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1021 },
1022 [ C(OP_PREFETCH) ] = {
1023 [ C(RESULT_ACCESS) ] = 0x0,
1024 [ C(RESULT_MISS) ] = 0x0,
1025 },
1026 },
1027 [ C(ITLB) ] = {
1028 [ C(OP_READ) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1030 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1031 },
1032 [ C(OP_WRITE) ] = {
1033 [ C(RESULT_ACCESS) ] = -1,
1034 [ C(RESULT_MISS) ] = -1,
1035 },
1036 [ C(OP_PREFETCH) ] = {
1037 [ C(RESULT_ACCESS) ] = -1,
1038 [ C(RESULT_MISS) ] = -1,
1039 },
1040 },
1041 [ C(BPU ) ] = {
1042 [ C(OP_READ) ] = {
1043 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1044 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1045 },
1046 [ C(OP_WRITE) ] = {
1047 [ C(RESULT_ACCESS) ] = -1,
1048 [ C(RESULT_MISS) ] = -1,
1049 },
1050 [ C(OP_PREFETCH) ] = {
1051 [ C(RESULT_ACCESS) ] = -1,
1052 [ C(RESULT_MISS) ] = -1,
1053 },
1054 },
1055 [ C(NODE) ] = {
1056 [ C(OP_READ) ] = {
1057 [ C(RESULT_ACCESS) ] = 0x01b7,
1058 [ C(RESULT_MISS) ] = 0x01b7,
1059 },
1060 [ C(OP_WRITE) ] = {
1061 [ C(RESULT_ACCESS) ] = 0x01b7,
1062 [ C(RESULT_MISS) ] = 0x01b7,
1063 },
1064 [ C(OP_PREFETCH) ] = {
1065 [ C(RESULT_ACCESS) ] = 0x01b7,
1066 [ C(RESULT_MISS) ] = 0x01b7,
1067 },
1068 },
1069 };
1070
1071 /*
1072 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1073 * See IA32 SDM Vol 3B 30.6.1.3
1074 */
1075
1076 #define NHM_DMND_DATA_RD (1 << 0)
1077 #define NHM_DMND_RFO (1 << 1)
1078 #define NHM_DMND_IFETCH (1 << 2)
1079 #define NHM_DMND_WB (1 << 3)
1080 #define NHM_PF_DATA_RD (1 << 4)
1081 #define NHM_PF_DATA_RFO (1 << 5)
1082 #define NHM_PF_IFETCH (1 << 6)
1083 #define NHM_OFFCORE_OTHER (1 << 7)
1084 #define NHM_UNCORE_HIT (1 << 8)
1085 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1086 #define NHM_OTHER_CORE_HITM (1 << 10)
1087 /* reserved */
1088 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1089 #define NHM_REMOTE_DRAM (1 << 13)
1090 #define NHM_LOCAL_DRAM (1 << 14)
1091 #define NHM_NON_DRAM (1 << 15)
1092
1093 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1094 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1095
1096 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1097 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1098 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1099
1100 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1101 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1102 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1103
1104 static __initconst const u64 nehalem_hw_cache_extra_regs
1105 [PERF_COUNT_HW_CACHE_MAX]
1106 [PERF_COUNT_HW_CACHE_OP_MAX]
1107 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1108 {
1109 [ C(LL ) ] = {
1110 [ C(OP_READ) ] = {
1111 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1112 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1113 },
1114 [ C(OP_WRITE) ] = {
1115 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1116 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1117 },
1118 [ C(OP_PREFETCH) ] = {
1119 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1120 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1121 },
1122 },
1123 [ C(NODE) ] = {
1124 [ C(OP_READ) ] = {
1125 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1126 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1127 },
1128 [ C(OP_WRITE) ] = {
1129 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1130 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1131 },
1132 [ C(OP_PREFETCH) ] = {
1133 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1134 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1135 },
1136 },
1137 };
1138
1139 static __initconst const u64 nehalem_hw_cache_event_ids
1140 [PERF_COUNT_HW_CACHE_MAX]
1141 [PERF_COUNT_HW_CACHE_OP_MAX]
1142 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1143 {
1144 [ C(L1D) ] = {
1145 [ C(OP_READ) ] = {
1146 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1147 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1148 },
1149 [ C(OP_WRITE) ] = {
1150 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1151 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1152 },
1153 [ C(OP_PREFETCH) ] = {
1154 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1155 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1156 },
1157 },
1158 [ C(L1I ) ] = {
1159 [ C(OP_READ) ] = {
1160 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1161 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1162 },
1163 [ C(OP_WRITE) ] = {
1164 [ C(RESULT_ACCESS) ] = -1,
1165 [ C(RESULT_MISS) ] = -1,
1166 },
1167 [ C(OP_PREFETCH) ] = {
1168 [ C(RESULT_ACCESS) ] = 0x0,
1169 [ C(RESULT_MISS) ] = 0x0,
1170 },
1171 },
1172 [ C(LL ) ] = {
1173 [ C(OP_READ) ] = {
1174 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1175 [ C(RESULT_ACCESS) ] = 0x01b7,
1176 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1177 [ C(RESULT_MISS) ] = 0x01b7,
1178 },
1179 /*
1180 * Use RFO, not WRITEBACK, because a write miss would typically occur
1181 * on RFO.
1182 */
1183 [ C(OP_WRITE) ] = {
1184 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1185 [ C(RESULT_ACCESS) ] = 0x01b7,
1186 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1187 [ C(RESULT_MISS) ] = 0x01b7,
1188 },
1189 [ C(OP_PREFETCH) ] = {
1190 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1191 [ C(RESULT_ACCESS) ] = 0x01b7,
1192 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1193 [ C(RESULT_MISS) ] = 0x01b7,
1194 },
1195 },
1196 [ C(DTLB) ] = {
1197 [ C(OP_READ) ] = {
1198 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1199 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1200 },
1201 [ C(OP_WRITE) ] = {
1202 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1203 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1204 },
1205 [ C(OP_PREFETCH) ] = {
1206 [ C(RESULT_ACCESS) ] = 0x0,
1207 [ C(RESULT_MISS) ] = 0x0,
1208 },
1209 },
1210 [ C(ITLB) ] = {
1211 [ C(OP_READ) ] = {
1212 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1213 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1214 },
1215 [ C(OP_WRITE) ] = {
1216 [ C(RESULT_ACCESS) ] = -1,
1217 [ C(RESULT_MISS) ] = -1,
1218 },
1219 [ C(OP_PREFETCH) ] = {
1220 [ C(RESULT_ACCESS) ] = -1,
1221 [ C(RESULT_MISS) ] = -1,
1222 },
1223 },
1224 [ C(BPU ) ] = {
1225 [ C(OP_READ) ] = {
1226 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1227 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1228 },
1229 [ C(OP_WRITE) ] = {
1230 [ C(RESULT_ACCESS) ] = -1,
1231 [ C(RESULT_MISS) ] = -1,
1232 },
1233 [ C(OP_PREFETCH) ] = {
1234 [ C(RESULT_ACCESS) ] = -1,
1235 [ C(RESULT_MISS) ] = -1,
1236 },
1237 },
1238 [ C(NODE) ] = {
1239 [ C(OP_READ) ] = {
1240 [ C(RESULT_ACCESS) ] = 0x01b7,
1241 [ C(RESULT_MISS) ] = 0x01b7,
1242 },
1243 [ C(OP_WRITE) ] = {
1244 [ C(RESULT_ACCESS) ] = 0x01b7,
1245 [ C(RESULT_MISS) ] = 0x01b7,
1246 },
1247 [ C(OP_PREFETCH) ] = {
1248 [ C(RESULT_ACCESS) ] = 0x01b7,
1249 [ C(RESULT_MISS) ] = 0x01b7,
1250 },
1251 },
1252 };
1253
1254 static __initconst const u64 core2_hw_cache_event_ids
1255 [PERF_COUNT_HW_CACHE_MAX]
1256 [PERF_COUNT_HW_CACHE_OP_MAX]
1257 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1258 {
1259 [ C(L1D) ] = {
1260 [ C(OP_READ) ] = {
1261 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1262 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1263 },
1264 [ C(OP_WRITE) ] = {
1265 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1266 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1267 },
1268 [ C(OP_PREFETCH) ] = {
1269 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1270 [ C(RESULT_MISS) ] = 0,
1271 },
1272 },
1273 [ C(L1I ) ] = {
1274 [ C(OP_READ) ] = {
1275 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1276 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1277 },
1278 [ C(OP_WRITE) ] = {
1279 [ C(RESULT_ACCESS) ] = -1,
1280 [ C(RESULT_MISS) ] = -1,
1281 },
1282 [ C(OP_PREFETCH) ] = {
1283 [ C(RESULT_ACCESS) ] = 0,
1284 [ C(RESULT_MISS) ] = 0,
1285 },
1286 },
1287 [ C(LL ) ] = {
1288 [ C(OP_READ) ] = {
1289 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1290 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1291 },
1292 [ C(OP_WRITE) ] = {
1293 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1294 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1295 },
1296 [ C(OP_PREFETCH) ] = {
1297 [ C(RESULT_ACCESS) ] = 0,
1298 [ C(RESULT_MISS) ] = 0,
1299 },
1300 },
1301 [ C(DTLB) ] = {
1302 [ C(OP_READ) ] = {
1303 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1304 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1305 },
1306 [ C(OP_WRITE) ] = {
1307 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1308 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1309 },
1310 [ C(OP_PREFETCH) ] = {
1311 [ C(RESULT_ACCESS) ] = 0,
1312 [ C(RESULT_MISS) ] = 0,
1313 },
1314 },
1315 [ C(ITLB) ] = {
1316 [ C(OP_READ) ] = {
1317 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1318 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1319 },
1320 [ C(OP_WRITE) ] = {
1321 [ C(RESULT_ACCESS) ] = -1,
1322 [ C(RESULT_MISS) ] = -1,
1323 },
1324 [ C(OP_PREFETCH) ] = {
1325 [ C(RESULT_ACCESS) ] = -1,
1326 [ C(RESULT_MISS) ] = -1,
1327 },
1328 },
1329 [ C(BPU ) ] = {
1330 [ C(OP_READ) ] = {
1331 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1332 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1333 },
1334 [ C(OP_WRITE) ] = {
1335 [ C(RESULT_ACCESS) ] = -1,
1336 [ C(RESULT_MISS) ] = -1,
1337 },
1338 [ C(OP_PREFETCH) ] = {
1339 [ C(RESULT_ACCESS) ] = -1,
1340 [ C(RESULT_MISS) ] = -1,
1341 },
1342 },
1343 };
1344
1345 static __initconst const u64 atom_hw_cache_event_ids
1346 [PERF_COUNT_HW_CACHE_MAX]
1347 [PERF_COUNT_HW_CACHE_OP_MAX]
1348 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1349 {
1350 [ C(L1D) ] = {
1351 [ C(OP_READ) ] = {
1352 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1353 [ C(RESULT_MISS) ] = 0,
1354 },
1355 [ C(OP_WRITE) ] = {
1356 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1357 [ C(RESULT_MISS) ] = 0,
1358 },
1359 [ C(OP_PREFETCH) ] = {
1360 [ C(RESULT_ACCESS) ] = 0x0,
1361 [ C(RESULT_MISS) ] = 0,
1362 },
1363 },
1364 [ C(L1I ) ] = {
1365 [ C(OP_READ) ] = {
1366 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1367 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1368 },
1369 [ C(OP_WRITE) ] = {
1370 [ C(RESULT_ACCESS) ] = -1,
1371 [ C(RESULT_MISS) ] = -1,
1372 },
1373 [ C(OP_PREFETCH) ] = {
1374 [ C(RESULT_ACCESS) ] = 0,
1375 [ C(RESULT_MISS) ] = 0,
1376 },
1377 },
1378 [ C(LL ) ] = {
1379 [ C(OP_READ) ] = {
1380 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1381 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1382 },
1383 [ C(OP_WRITE) ] = {
1384 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1385 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1386 },
1387 [ C(OP_PREFETCH) ] = {
1388 [ C(RESULT_ACCESS) ] = 0,
1389 [ C(RESULT_MISS) ] = 0,
1390 },
1391 },
1392 [ C(DTLB) ] = {
1393 [ C(OP_READ) ] = {
1394 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1395 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1396 },
1397 [ C(OP_WRITE) ] = {
1398 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1399 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1400 },
1401 [ C(OP_PREFETCH) ] = {
1402 [ C(RESULT_ACCESS) ] = 0,
1403 [ C(RESULT_MISS) ] = 0,
1404 },
1405 },
1406 [ C(ITLB) ] = {
1407 [ C(OP_READ) ] = {
1408 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1409 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1410 },
1411 [ C(OP_WRITE) ] = {
1412 [ C(RESULT_ACCESS) ] = -1,
1413 [ C(RESULT_MISS) ] = -1,
1414 },
1415 [ C(OP_PREFETCH) ] = {
1416 [ C(RESULT_ACCESS) ] = -1,
1417 [ C(RESULT_MISS) ] = -1,
1418 },
1419 },
1420 [ C(BPU ) ] = {
1421 [ C(OP_READ) ] = {
1422 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1423 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1424 },
1425 [ C(OP_WRITE) ] = {
1426 [ C(RESULT_ACCESS) ] = -1,
1427 [ C(RESULT_MISS) ] = -1,
1428 },
1429 [ C(OP_PREFETCH) ] = {
1430 [ C(RESULT_ACCESS) ] = -1,
1431 [ C(RESULT_MISS) ] = -1,
1432 },
1433 },
1434 };
1435
1436 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1437 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1438 /* no_alloc_cycles.not_delivered */
1439 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1440 "event=0xca,umask=0x50");
1441 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1442 /* uops_retired.all */
1443 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1444 "event=0xc2,umask=0x10");
1445 /* uops_retired.all */
1446 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1447 "event=0xc2,umask=0x10");
1448
1449 static struct attribute *slm_events_attrs[] = {
1450 EVENT_PTR(td_total_slots_slm),
1451 EVENT_PTR(td_total_slots_scale_slm),
1452 EVENT_PTR(td_fetch_bubbles_slm),
1453 EVENT_PTR(td_fetch_bubbles_scale_slm),
1454 EVENT_PTR(td_slots_issued_slm),
1455 EVENT_PTR(td_slots_retired_slm),
1456 NULL
1457 };
1458
1459 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1460 {
1461 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1462 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1463 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1464 EVENT_EXTRA_END
1465 };
1466
1467 #define SLM_DMND_READ SNB_DMND_DATA_RD
1468 #define SLM_DMND_WRITE SNB_DMND_RFO
1469 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1470
1471 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1472 #define SLM_LLC_ACCESS SNB_RESP_ANY
1473 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1474
1475 static __initconst const u64 slm_hw_cache_extra_regs
1476 [PERF_COUNT_HW_CACHE_MAX]
1477 [PERF_COUNT_HW_CACHE_OP_MAX]
1478 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1479 {
1480 [ C(LL ) ] = {
1481 [ C(OP_READ) ] = {
1482 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1483 [ C(RESULT_MISS) ] = 0,
1484 },
1485 [ C(OP_WRITE) ] = {
1486 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1487 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1488 },
1489 [ C(OP_PREFETCH) ] = {
1490 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1491 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1492 },
1493 },
1494 };
1495
1496 static __initconst const u64 slm_hw_cache_event_ids
1497 [PERF_COUNT_HW_CACHE_MAX]
1498 [PERF_COUNT_HW_CACHE_OP_MAX]
1499 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1500 {
1501 [ C(L1D) ] = {
1502 [ C(OP_READ) ] = {
1503 [ C(RESULT_ACCESS) ] = 0,
1504 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1505 },
1506 [ C(OP_WRITE) ] = {
1507 [ C(RESULT_ACCESS) ] = 0,
1508 [ C(RESULT_MISS) ] = 0,
1509 },
1510 [ C(OP_PREFETCH) ] = {
1511 [ C(RESULT_ACCESS) ] = 0,
1512 [ C(RESULT_MISS) ] = 0,
1513 },
1514 },
1515 [ C(L1I ) ] = {
1516 [ C(OP_READ) ] = {
1517 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1518 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1519 },
1520 [ C(OP_WRITE) ] = {
1521 [ C(RESULT_ACCESS) ] = -1,
1522 [ C(RESULT_MISS) ] = -1,
1523 },
1524 [ C(OP_PREFETCH) ] = {
1525 [ C(RESULT_ACCESS) ] = 0,
1526 [ C(RESULT_MISS) ] = 0,
1527 },
1528 },
1529 [ C(LL ) ] = {
1530 [ C(OP_READ) ] = {
1531 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1532 [ C(RESULT_ACCESS) ] = 0x01b7,
1533 [ C(RESULT_MISS) ] = 0,
1534 },
1535 [ C(OP_WRITE) ] = {
1536 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1537 [ C(RESULT_ACCESS) ] = 0x01b7,
1538 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1539 [ C(RESULT_MISS) ] = 0x01b7,
1540 },
1541 [ C(OP_PREFETCH) ] = {
1542 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1543 [ C(RESULT_ACCESS) ] = 0x01b7,
1544 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1545 [ C(RESULT_MISS) ] = 0x01b7,
1546 },
1547 },
1548 [ C(DTLB) ] = {
1549 [ C(OP_READ) ] = {
1550 [ C(RESULT_ACCESS) ] = 0,
1551 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1552 },
1553 [ C(OP_WRITE) ] = {
1554 [ C(RESULT_ACCESS) ] = 0,
1555 [ C(RESULT_MISS) ] = 0,
1556 },
1557 [ C(OP_PREFETCH) ] = {
1558 [ C(RESULT_ACCESS) ] = 0,
1559 [ C(RESULT_MISS) ] = 0,
1560 },
1561 },
1562 [ C(ITLB) ] = {
1563 [ C(OP_READ) ] = {
1564 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1565 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1566 },
1567 [ C(OP_WRITE) ] = {
1568 [ C(RESULT_ACCESS) ] = -1,
1569 [ C(RESULT_MISS) ] = -1,
1570 },
1571 [ C(OP_PREFETCH) ] = {
1572 [ C(RESULT_ACCESS) ] = -1,
1573 [ C(RESULT_MISS) ] = -1,
1574 },
1575 },
1576 [ C(BPU ) ] = {
1577 [ C(OP_READ) ] = {
1578 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1579 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1580 },
1581 [ C(OP_WRITE) ] = {
1582 [ C(RESULT_ACCESS) ] = -1,
1583 [ C(RESULT_MISS) ] = -1,
1584 },
1585 [ C(OP_PREFETCH) ] = {
1586 [ C(RESULT_ACCESS) ] = -1,
1587 [ C(RESULT_MISS) ] = -1,
1588 },
1589 },
1590 };
1591
1592 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1593 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1594 /* UOPS_NOT_DELIVERED.ANY */
1595 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1596 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1597 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1598 /* UOPS_RETIRED.ANY */
1599 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1600 /* UOPS_ISSUED.ANY */
1601 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1602
1603 static struct attribute *glm_events_attrs[] = {
1604 EVENT_PTR(td_total_slots_glm),
1605 EVENT_PTR(td_total_slots_scale_glm),
1606 EVENT_PTR(td_fetch_bubbles_glm),
1607 EVENT_PTR(td_recovery_bubbles_glm),
1608 EVENT_PTR(td_slots_issued_glm),
1609 EVENT_PTR(td_slots_retired_glm),
1610 NULL
1611 };
1612
1613 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1614 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1615 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1616 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1617 EVENT_EXTRA_END
1618 };
1619
1620 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1621 #define GLM_DEMAND_RFO BIT_ULL(1)
1622 #define GLM_ANY_RESPONSE BIT_ULL(16)
1623 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1624 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1625 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1626 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1627 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1628 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1629 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1630
1631 static __initconst const u64 glm_hw_cache_event_ids
1632 [PERF_COUNT_HW_CACHE_MAX]
1633 [PERF_COUNT_HW_CACHE_OP_MAX]
1634 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1635 [C(L1D)] = {
1636 [C(OP_READ)] = {
1637 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1638 [C(RESULT_MISS)] = 0x0,
1639 },
1640 [C(OP_WRITE)] = {
1641 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1642 [C(RESULT_MISS)] = 0x0,
1643 },
1644 [C(OP_PREFETCH)] = {
1645 [C(RESULT_ACCESS)] = 0x0,
1646 [C(RESULT_MISS)] = 0x0,
1647 },
1648 },
1649 [C(L1I)] = {
1650 [C(OP_READ)] = {
1651 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1652 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1653 },
1654 [C(OP_WRITE)] = {
1655 [C(RESULT_ACCESS)] = -1,
1656 [C(RESULT_MISS)] = -1,
1657 },
1658 [C(OP_PREFETCH)] = {
1659 [C(RESULT_ACCESS)] = 0x0,
1660 [C(RESULT_MISS)] = 0x0,
1661 },
1662 },
1663 [C(LL)] = {
1664 [C(OP_READ)] = {
1665 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1666 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1667 },
1668 [C(OP_WRITE)] = {
1669 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1670 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1671 },
1672 [C(OP_PREFETCH)] = {
1673 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1674 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1675 },
1676 },
1677 [C(DTLB)] = {
1678 [C(OP_READ)] = {
1679 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1680 [C(RESULT_MISS)] = 0x0,
1681 },
1682 [C(OP_WRITE)] = {
1683 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1684 [C(RESULT_MISS)] = 0x0,
1685 },
1686 [C(OP_PREFETCH)] = {
1687 [C(RESULT_ACCESS)] = 0x0,
1688 [C(RESULT_MISS)] = 0x0,
1689 },
1690 },
1691 [C(ITLB)] = {
1692 [C(OP_READ)] = {
1693 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1694 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1695 },
1696 [C(OP_WRITE)] = {
1697 [C(RESULT_ACCESS)] = -1,
1698 [C(RESULT_MISS)] = -1,
1699 },
1700 [C(OP_PREFETCH)] = {
1701 [C(RESULT_ACCESS)] = -1,
1702 [C(RESULT_MISS)] = -1,
1703 },
1704 },
1705 [C(BPU)] = {
1706 [C(OP_READ)] = {
1707 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1708 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1709 },
1710 [C(OP_WRITE)] = {
1711 [C(RESULT_ACCESS)] = -1,
1712 [C(RESULT_MISS)] = -1,
1713 },
1714 [C(OP_PREFETCH)] = {
1715 [C(RESULT_ACCESS)] = -1,
1716 [C(RESULT_MISS)] = -1,
1717 },
1718 },
1719 };
1720
1721 static __initconst const u64 glm_hw_cache_extra_regs
1722 [PERF_COUNT_HW_CACHE_MAX]
1723 [PERF_COUNT_HW_CACHE_OP_MAX]
1724 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1725 [C(LL)] = {
1726 [C(OP_READ)] = {
1727 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1728 GLM_LLC_ACCESS,
1729 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1730 GLM_LLC_MISS,
1731 },
1732 [C(OP_WRITE)] = {
1733 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1734 GLM_LLC_ACCESS,
1735 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1736 GLM_LLC_MISS,
1737 },
1738 [C(OP_PREFETCH)] = {
1739 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1740 GLM_LLC_ACCESS,
1741 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1742 GLM_LLC_MISS,
1743 },
1744 },
1745 };
1746
1747 static __initconst const u64 glp_hw_cache_event_ids
1748 [PERF_COUNT_HW_CACHE_MAX]
1749 [PERF_COUNT_HW_CACHE_OP_MAX]
1750 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1751 [C(L1D)] = {
1752 [C(OP_READ)] = {
1753 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1754 [C(RESULT_MISS)] = 0x0,
1755 },
1756 [C(OP_WRITE)] = {
1757 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1758 [C(RESULT_MISS)] = 0x0,
1759 },
1760 [C(OP_PREFETCH)] = {
1761 [C(RESULT_ACCESS)] = 0x0,
1762 [C(RESULT_MISS)] = 0x0,
1763 },
1764 },
1765 [C(L1I)] = {
1766 [C(OP_READ)] = {
1767 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1768 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1769 },
1770 [C(OP_WRITE)] = {
1771 [C(RESULT_ACCESS)] = -1,
1772 [C(RESULT_MISS)] = -1,
1773 },
1774 [C(OP_PREFETCH)] = {
1775 [C(RESULT_ACCESS)] = 0x0,
1776 [C(RESULT_MISS)] = 0x0,
1777 },
1778 },
1779 [C(LL)] = {
1780 [C(OP_READ)] = {
1781 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1782 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1783 },
1784 [C(OP_WRITE)] = {
1785 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1786 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1787 },
1788 [C(OP_PREFETCH)] = {
1789 [C(RESULT_ACCESS)] = 0x0,
1790 [C(RESULT_MISS)] = 0x0,
1791 },
1792 },
1793 [C(DTLB)] = {
1794 [C(OP_READ)] = {
1795 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1796 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1797 },
1798 [C(OP_WRITE)] = {
1799 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1800 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1801 },
1802 [C(OP_PREFETCH)] = {
1803 [C(RESULT_ACCESS)] = 0x0,
1804 [C(RESULT_MISS)] = 0x0,
1805 },
1806 },
1807 [C(ITLB)] = {
1808 [C(OP_READ)] = {
1809 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1810 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1811 },
1812 [C(OP_WRITE)] = {
1813 [C(RESULT_ACCESS)] = -1,
1814 [C(RESULT_MISS)] = -1,
1815 },
1816 [C(OP_PREFETCH)] = {
1817 [C(RESULT_ACCESS)] = -1,
1818 [C(RESULT_MISS)] = -1,
1819 },
1820 },
1821 [C(BPU)] = {
1822 [C(OP_READ)] = {
1823 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1824 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1825 },
1826 [C(OP_WRITE)] = {
1827 [C(RESULT_ACCESS)] = -1,
1828 [C(RESULT_MISS)] = -1,
1829 },
1830 [C(OP_PREFETCH)] = {
1831 [C(RESULT_ACCESS)] = -1,
1832 [C(RESULT_MISS)] = -1,
1833 },
1834 },
1835 };
1836
1837 static __initconst const u64 glp_hw_cache_extra_regs
1838 [PERF_COUNT_HW_CACHE_MAX]
1839 [PERF_COUNT_HW_CACHE_OP_MAX]
1840 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1841 [C(LL)] = {
1842 [C(OP_READ)] = {
1843 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1844 GLM_LLC_ACCESS,
1845 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1846 GLM_LLC_MISS,
1847 },
1848 [C(OP_WRITE)] = {
1849 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1850 GLM_LLC_ACCESS,
1851 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1852 GLM_LLC_MISS,
1853 },
1854 [C(OP_PREFETCH)] = {
1855 [C(RESULT_ACCESS)] = 0x0,
1856 [C(RESULT_MISS)] = 0x0,
1857 },
1858 },
1859 };
1860
1861 #define TNT_LOCAL_DRAM BIT_ULL(26)
1862 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
1863 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
1864 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
1865 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
1866 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
1867 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
1868
1869 static __initconst const u64 tnt_hw_cache_extra_regs
1870 [PERF_COUNT_HW_CACHE_MAX]
1871 [PERF_COUNT_HW_CACHE_OP_MAX]
1872 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1873 [C(LL)] = {
1874 [C(OP_READ)] = {
1875 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
1876 TNT_LLC_ACCESS,
1877 [C(RESULT_MISS)] = TNT_DEMAND_READ|
1878 TNT_LLC_MISS,
1879 },
1880 [C(OP_WRITE)] = {
1881 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
1882 TNT_LLC_ACCESS,
1883 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
1884 TNT_LLC_MISS,
1885 },
1886 [C(OP_PREFETCH)] = {
1887 [C(RESULT_ACCESS)] = 0x0,
1888 [C(RESULT_MISS)] = 0x0,
1889 },
1890 },
1891 };
1892
1893 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
1894 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1895 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0),
1896 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1),
1897 EVENT_EXTRA_END
1898 };
1899
1900 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1901 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1902 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
1903 #define KNL_MCDRAM_FAR BIT_ULL(22)
1904 #define KNL_DDR_LOCAL BIT_ULL(23)
1905 #define KNL_DDR_FAR BIT_ULL(24)
1906 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1907 KNL_DDR_LOCAL | KNL_DDR_FAR)
1908 #define KNL_L2_READ SLM_DMND_READ
1909 #define KNL_L2_WRITE SLM_DMND_WRITE
1910 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1911 #define KNL_L2_ACCESS SLM_LLC_ACCESS
1912 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1913 KNL_DRAM_ANY | SNB_SNP_ANY | \
1914 SNB_NON_DRAM)
1915
1916 static __initconst const u64 knl_hw_cache_extra_regs
1917 [PERF_COUNT_HW_CACHE_MAX]
1918 [PERF_COUNT_HW_CACHE_OP_MAX]
1919 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1920 [C(LL)] = {
1921 [C(OP_READ)] = {
1922 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1923 [C(RESULT_MISS)] = 0,
1924 },
1925 [C(OP_WRITE)] = {
1926 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1927 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1928 },
1929 [C(OP_PREFETCH)] = {
1930 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1931 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1932 },
1933 },
1934 };
1935
1936 /*
1937 * Used from PMIs where the LBRs are already disabled.
1938 *
1939 * This function could be called consecutively. It is required to remain in
1940 * disabled state if called consecutively.
1941 *
1942 * During consecutive calls, the same disable value will be written to related
1943 * registers, so the PMU state remains unchanged.
1944 *
1945 * intel_bts events don't coexist with intel PMU's BTS events because of
1946 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
1947 * disabled around intel PMU's event batching etc, only inside the PMI handler.
1948 */
1949 static void __intel_pmu_disable_all(void)
1950 {
1951 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1952
1953 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1954
1955 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1956 intel_pmu_disable_bts();
1957
1958 intel_pmu_pebs_disable_all();
1959 }
1960
1961 static void intel_pmu_disable_all(void)
1962 {
1963 __intel_pmu_disable_all();
1964 intel_pmu_lbr_disable_all();
1965 }
1966
1967 static void __intel_pmu_enable_all(int added, bool pmi)
1968 {
1969 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1970
1971 intel_pmu_pebs_enable_all();
1972 intel_pmu_lbr_enable_all(pmi);
1973 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1974 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1975
1976 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1977 struct perf_event *event =
1978 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1979
1980 if (WARN_ON_ONCE(!event))
1981 return;
1982
1983 intel_pmu_enable_bts(event->hw.config);
1984 }
1985 }
1986
1987 static void intel_pmu_enable_all(int added)
1988 {
1989 __intel_pmu_enable_all(added, false);
1990 }
1991
1992 /*
1993 * Workaround for:
1994 * Intel Errata AAK100 (model 26)
1995 * Intel Errata AAP53 (model 30)
1996 * Intel Errata BD53 (model 44)
1997 *
1998 * The official story:
1999 * These chips need to be 'reset' when adding counters by programming the
2000 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2001 * in sequence on the same PMC or on different PMCs.
2002 *
2003 * In practise it appears some of these events do in fact count, and
2004 * we need to program all 4 events.
2005 */
2006 static void intel_pmu_nhm_workaround(void)
2007 {
2008 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2009 static const unsigned long nhm_magic[4] = {
2010 0x4300B5,
2011 0x4300D2,
2012 0x4300B1,
2013 0x4300B1
2014 };
2015 struct perf_event *event;
2016 int i;
2017
2018 /*
2019 * The Errata requires below steps:
2020 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2021 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2022 * the corresponding PMCx;
2023 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2024 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2025 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2026 */
2027
2028 /*
2029 * The real steps we choose are a little different from above.
2030 * A) To reduce MSR operations, we don't run step 1) as they
2031 * are already cleared before this function is called;
2032 * B) Call x86_perf_event_update to save PMCx before configuring
2033 * PERFEVTSELx with magic number;
2034 * C) With step 5), we do clear only when the PERFEVTSELx is
2035 * not used currently.
2036 * D) Call x86_perf_event_set_period to restore PMCx;
2037 */
2038
2039 /* We always operate 4 pairs of PERF Counters */
2040 for (i = 0; i < 4; i++) {
2041 event = cpuc->events[i];
2042 if (event)
2043 x86_perf_event_update(event);
2044 }
2045
2046 for (i = 0; i < 4; i++) {
2047 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2048 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2049 }
2050
2051 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2052 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2053
2054 for (i = 0; i < 4; i++) {
2055 event = cpuc->events[i];
2056
2057 if (event) {
2058 x86_perf_event_set_period(event);
2059 __x86_pmu_enable_event(&event->hw,
2060 ARCH_PERFMON_EVENTSEL_ENABLE);
2061 } else
2062 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2063 }
2064 }
2065
2066 static void intel_pmu_nhm_enable_all(int added)
2067 {
2068 if (added)
2069 intel_pmu_nhm_workaround();
2070 intel_pmu_enable_all(added);
2071 }
2072
2073 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2074 {
2075 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2076
2077 if (cpuc->tfa_shadow != val) {
2078 cpuc->tfa_shadow = val;
2079 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2080 }
2081 }
2082
2083 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2084 {
2085 /*
2086 * We're going to use PMC3, make sure TFA is set before we touch it.
2087 */
2088 if (cntr == 3)
2089 intel_set_tfa(cpuc, true);
2090 }
2091
2092 static void intel_tfa_pmu_enable_all(int added)
2093 {
2094 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2095
2096 /*
2097 * If we find PMC3 is no longer used when we enable the PMU, we can
2098 * clear TFA.
2099 */
2100 if (!test_bit(3, cpuc->active_mask))
2101 intel_set_tfa(cpuc, false);
2102
2103 intel_pmu_enable_all(added);
2104 }
2105
2106 static void enable_counter_freeze(void)
2107 {
2108 update_debugctlmsr(get_debugctlmsr() |
2109 DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2110 }
2111
2112 static void disable_counter_freeze(void)
2113 {
2114 update_debugctlmsr(get_debugctlmsr() &
2115 ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2116 }
2117
2118 static inline u64 intel_pmu_get_status(void)
2119 {
2120 u64 status;
2121
2122 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2123
2124 return status;
2125 }
2126
2127 static inline void intel_pmu_ack_status(u64 ack)
2128 {
2129 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2130 }
2131
2132 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
2133 {
2134 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
2135 u64 ctrl_val, mask;
2136
2137 mask = 0xfULL << (idx * 4);
2138
2139 rdmsrl(hwc->config_base, ctrl_val);
2140 ctrl_val &= ~mask;
2141 wrmsrl(hwc->config_base, ctrl_val);
2142 }
2143
2144 static inline bool event_is_checkpointed(struct perf_event *event)
2145 {
2146 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2147 }
2148
2149 static void intel_pmu_disable_event(struct perf_event *event)
2150 {
2151 struct hw_perf_event *hwc = &event->hw;
2152 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2153
2154 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
2155 intel_pmu_disable_bts();
2156 intel_pmu_drain_bts_buffer();
2157 return;
2158 }
2159
2160 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
2161 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2162 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
2163
2164 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL))
2165 intel_pmu_disable_fixed(hwc);
2166 else
2167 x86_pmu_disable_event(event);
2168
2169 /*
2170 * Needs to be called after x86_pmu_disable_event,
2171 * so we don't trigger the event without PEBS bit set.
2172 */
2173 if (unlikely(event->attr.precise_ip))
2174 intel_pmu_pebs_disable(event);
2175 }
2176
2177 static void intel_pmu_del_event(struct perf_event *event)
2178 {
2179 if (needs_branch_stack(event))
2180 intel_pmu_lbr_del(event);
2181 if (event->attr.precise_ip)
2182 intel_pmu_pebs_del(event);
2183 }
2184
2185 static void intel_pmu_read_event(struct perf_event *event)
2186 {
2187 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2188 intel_pmu_auto_reload_read(event);
2189 else
2190 x86_perf_event_update(event);
2191 }
2192
2193 static void intel_pmu_enable_fixed(struct perf_event *event)
2194 {
2195 struct hw_perf_event *hwc = &event->hw;
2196 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
2197 u64 ctrl_val, mask, bits = 0;
2198
2199 /*
2200 * Enable IRQ generation (0x8), if not PEBS,
2201 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2202 * if requested:
2203 */
2204 if (!event->attr.precise_ip)
2205 bits |= 0x8;
2206 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2207 bits |= 0x2;
2208 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2209 bits |= 0x1;
2210
2211 /*
2212 * ANY bit is supported in v3 and up
2213 */
2214 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2215 bits |= 0x4;
2216
2217 bits <<= (idx * 4);
2218 mask = 0xfULL << (idx * 4);
2219
2220 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2221 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2222 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2223 }
2224
2225 rdmsrl(hwc->config_base, ctrl_val);
2226 ctrl_val &= ~mask;
2227 ctrl_val |= bits;
2228 wrmsrl(hwc->config_base, ctrl_val);
2229 }
2230
2231 static void intel_pmu_enable_event(struct perf_event *event)
2232 {
2233 struct hw_perf_event *hwc = &event->hw;
2234 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2235
2236 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
2237 if (!__this_cpu_read(cpu_hw_events.enabled))
2238 return;
2239
2240 intel_pmu_enable_bts(hwc->config);
2241 return;
2242 }
2243
2244 if (event->attr.exclude_host)
2245 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
2246 if (event->attr.exclude_guest)
2247 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
2248
2249 if (unlikely(event_is_checkpointed(event)))
2250 cpuc->intel_cp_status |= (1ull << hwc->idx);
2251
2252 if (unlikely(event->attr.precise_ip))
2253 intel_pmu_pebs_enable(event);
2254
2255 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
2256 intel_pmu_enable_fixed(event);
2257 return;
2258 }
2259
2260 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2261 }
2262
2263 static void intel_pmu_add_event(struct perf_event *event)
2264 {
2265 if (event->attr.precise_ip)
2266 intel_pmu_pebs_add(event);
2267 if (needs_branch_stack(event))
2268 intel_pmu_lbr_add(event);
2269 }
2270
2271 /*
2272 * Save and restart an expired event. Called by NMI contexts,
2273 * so it has to be careful about preempting normal event ops:
2274 */
2275 int intel_pmu_save_and_restart(struct perf_event *event)
2276 {
2277 x86_perf_event_update(event);
2278 /*
2279 * For a checkpointed counter always reset back to 0. This
2280 * avoids a situation where the counter overflows, aborts the
2281 * transaction and is then set back to shortly before the
2282 * overflow, and overflows and aborts again.
2283 */
2284 if (unlikely(event_is_checkpointed(event))) {
2285 /* No race with NMIs because the counter should not be armed */
2286 wrmsrl(event->hw.event_base, 0);
2287 local64_set(&event->hw.prev_count, 0);
2288 }
2289 return x86_perf_event_set_period(event);
2290 }
2291
2292 static void intel_pmu_reset(void)
2293 {
2294 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2295 unsigned long flags;
2296 int idx;
2297
2298 if (!x86_pmu.num_counters)
2299 return;
2300
2301 local_irq_save(flags);
2302
2303 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2304
2305 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2306 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2307 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2308 }
2309 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
2310 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2311
2312 if (ds)
2313 ds->bts_index = ds->bts_buffer_base;
2314
2315 /* Ack all overflows and disable fixed counters */
2316 if (x86_pmu.version >= 2) {
2317 intel_pmu_ack_status(intel_pmu_get_status());
2318 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2319 }
2320
2321 /* Reset LBRs and LBR freezing */
2322 if (x86_pmu.lbr_nr) {
2323 update_debugctlmsr(get_debugctlmsr() &
2324 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2325 }
2326
2327 local_irq_restore(flags);
2328 }
2329
2330 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2331 {
2332 struct perf_sample_data data;
2333 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2334 int bit;
2335 int handled = 0;
2336
2337 inc_irq_stat(apic_perf_irqs);
2338
2339 /*
2340 * Ignore a range of extra bits in status that do not indicate
2341 * overflow by themselves.
2342 */
2343 status &= ~(GLOBAL_STATUS_COND_CHG |
2344 GLOBAL_STATUS_ASIF |
2345 GLOBAL_STATUS_LBRS_FROZEN);
2346 if (!status)
2347 return 0;
2348 /*
2349 * In case multiple PEBS events are sampled at the same time,
2350 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2351 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2352 * having their bits set in the status register. This is a sign
2353 * that there was at least one PEBS record pending at the time
2354 * of the PMU interrupt. PEBS counters must only be processed
2355 * via the drain_pebs() calls and not via the regular sample
2356 * processing loop coming after that the function, otherwise
2357 * phony regular samples may be generated in the sampling buffer
2358 * not marked with the EXACT tag. Another possibility is to have
2359 * one PEBS event and at least one non-PEBS event whic hoverflows
2360 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2361 * not be set, yet the overflow status bit for the PEBS counter will
2362 * be on Skylake.
2363 *
2364 * To avoid this problem, we systematically ignore the PEBS-enabled
2365 * counters from the GLOBAL_STATUS mask and we always process PEBS
2366 * events via drain_pebs().
2367 */
2368 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2369 status &= ~cpuc->pebs_enabled;
2370 else
2371 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2372
2373 /*
2374 * PEBS overflow sets bit 62 in the global status register
2375 */
2376 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
2377 handled++;
2378 x86_pmu.drain_pebs(regs);
2379 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2380 }
2381
2382 /*
2383 * Intel PT
2384 */
2385 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
2386 handled++;
2387 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() &&
2388 perf_guest_cbs->handle_intel_pt_intr))
2389 perf_guest_cbs->handle_intel_pt_intr();
2390 else
2391 intel_pt_interrupt();
2392 }
2393
2394 /*
2395 * Checkpointed counters can lead to 'spurious' PMIs because the
2396 * rollback caused by the PMI will have cleared the overflow status
2397 * bit. Therefore always force probe these counters.
2398 */
2399 status |= cpuc->intel_cp_status;
2400
2401 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2402 struct perf_event *event = cpuc->events[bit];
2403
2404 handled++;
2405
2406 if (!test_bit(bit, cpuc->active_mask))
2407 continue;
2408
2409 if (!intel_pmu_save_and_restart(event))
2410 continue;
2411
2412 perf_sample_data_init(&data, 0, event->hw.last_period);
2413
2414 if (has_branch_stack(event))
2415 data.br_stack = &cpuc->lbr_stack;
2416
2417 if (perf_event_overflow(event, &data, regs))
2418 x86_pmu_stop(event, 0);
2419 }
2420
2421 return handled;
2422 }
2423
2424 static bool disable_counter_freezing = true;
2425 static int __init intel_perf_counter_freezing_setup(char *s)
2426 {
2427 bool res;
2428
2429 if (kstrtobool(s, &res))
2430 return -EINVAL;
2431
2432 disable_counter_freezing = !res;
2433 return 1;
2434 }
2435 __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup);
2436
2437 /*
2438 * Simplified handler for Arch Perfmon v4:
2439 * - We rely on counter freezing/unfreezing to enable/disable the PMU.
2440 * This is done automatically on PMU ack.
2441 * - Ack the PMU only after the APIC.
2442 */
2443
2444 static int intel_pmu_handle_irq_v4(struct pt_regs *regs)
2445 {
2446 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2447 int handled = 0;
2448 bool bts = false;
2449 u64 status;
2450 int pmu_enabled = cpuc->enabled;
2451 int loops = 0;
2452
2453 /* PMU has been disabled because of counter freezing */
2454 cpuc->enabled = 0;
2455 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2456 bts = true;
2457 intel_bts_disable_local();
2458 handled = intel_pmu_drain_bts_buffer();
2459 handled += intel_bts_interrupt();
2460 }
2461 status = intel_pmu_get_status();
2462 if (!status)
2463 goto done;
2464 again:
2465 intel_pmu_lbr_read();
2466 if (++loops > 100) {
2467 static bool warned;
2468
2469 if (!warned) {
2470 WARN(1, "perfevents: irq loop stuck!\n");
2471 perf_event_print_debug();
2472 warned = true;
2473 }
2474 intel_pmu_reset();
2475 goto done;
2476 }
2477
2478
2479 handled += handle_pmi_common(regs, status);
2480 done:
2481 /* Ack the PMI in the APIC */
2482 apic_write(APIC_LVTPC, APIC_DM_NMI);
2483
2484 /*
2485 * The counters start counting immediately while ack the status.
2486 * Make it as close as possible to IRET. This avoids bogus
2487 * freezing on Skylake CPUs.
2488 */
2489 if (status) {
2490 intel_pmu_ack_status(status);
2491 } else {
2492 /*
2493 * CPU may issues two PMIs very close to each other.
2494 * When the PMI handler services the first one, the
2495 * GLOBAL_STATUS is already updated to reflect both.
2496 * When it IRETs, the second PMI is immediately
2497 * handled and it sees clear status. At the meantime,
2498 * there may be a third PMI, because the freezing bit
2499 * isn't set since the ack in first PMI handlers.
2500 * Double check if there is more work to be done.
2501 */
2502 status = intel_pmu_get_status();
2503 if (status)
2504 goto again;
2505 }
2506
2507 if (bts)
2508 intel_bts_enable_local();
2509 cpuc->enabled = pmu_enabled;
2510 return handled;
2511 }
2512
2513 /*
2514 * This handler is triggered by the local APIC, so the APIC IRQ handling
2515 * rules apply:
2516 */
2517 static int intel_pmu_handle_irq(struct pt_regs *regs)
2518 {
2519 struct cpu_hw_events *cpuc;
2520 int loops;
2521 u64 status;
2522 int handled;
2523 int pmu_enabled;
2524
2525 cpuc = this_cpu_ptr(&cpu_hw_events);
2526
2527 /*
2528 * Save the PMU state.
2529 * It needs to be restored when leaving the handler.
2530 */
2531 pmu_enabled = cpuc->enabled;
2532 /*
2533 * No known reason to not always do late ACK,
2534 * but just in case do it opt-in.
2535 */
2536 if (!x86_pmu.late_ack)
2537 apic_write(APIC_LVTPC, APIC_DM_NMI);
2538 intel_bts_disable_local();
2539 cpuc->enabled = 0;
2540 __intel_pmu_disable_all();
2541 handled = intel_pmu_drain_bts_buffer();
2542 handled += intel_bts_interrupt();
2543 status = intel_pmu_get_status();
2544 if (!status)
2545 goto done;
2546
2547 loops = 0;
2548 again:
2549 intel_pmu_lbr_read();
2550 intel_pmu_ack_status(status);
2551 if (++loops > 100) {
2552 static bool warned;
2553
2554 if (!warned) {
2555 WARN(1, "perfevents: irq loop stuck!\n");
2556 perf_event_print_debug();
2557 warned = true;
2558 }
2559 intel_pmu_reset();
2560 goto done;
2561 }
2562
2563 handled += handle_pmi_common(regs, status);
2564
2565 /*
2566 * Repeat if there is more work to be done:
2567 */
2568 status = intel_pmu_get_status();
2569 if (status)
2570 goto again;
2571
2572 done:
2573 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2574 cpuc->enabled = pmu_enabled;
2575 if (pmu_enabled)
2576 __intel_pmu_enable_all(0, true);
2577 intel_bts_enable_local();
2578
2579 /*
2580 * Only unmask the NMI after the overflow counters
2581 * have been reset. This avoids spurious NMIs on
2582 * Haswell CPUs.
2583 */
2584 if (x86_pmu.late_ack)
2585 apic_write(APIC_LVTPC, APIC_DM_NMI);
2586 return handled;
2587 }
2588
2589 static struct event_constraint *
2590 intel_bts_constraints(struct perf_event *event)
2591 {
2592 if (unlikely(intel_pmu_has_bts(event)))
2593 return &bts_constraint;
2594
2595 return NULL;
2596 }
2597
2598 static int intel_alt_er(int idx, u64 config)
2599 {
2600 int alt_idx = idx;
2601
2602 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
2603 return idx;
2604
2605 if (idx == EXTRA_REG_RSP_0)
2606 alt_idx = EXTRA_REG_RSP_1;
2607
2608 if (idx == EXTRA_REG_RSP_1)
2609 alt_idx = EXTRA_REG_RSP_0;
2610
2611 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2612 return idx;
2613
2614 return alt_idx;
2615 }
2616
2617 static void intel_fixup_er(struct perf_event *event, int idx)
2618 {
2619 event->hw.extra_reg.idx = idx;
2620
2621 if (idx == EXTRA_REG_RSP_0) {
2622 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2623 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
2624 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
2625 } else if (idx == EXTRA_REG_RSP_1) {
2626 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2627 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
2628 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
2629 }
2630 }
2631
2632 /*
2633 * manage allocation of shared extra msr for certain events
2634 *
2635 * sharing can be:
2636 * per-cpu: to be shared between the various events on a single PMU
2637 * per-core: per-cpu + shared by HT threads
2638 */
2639 static struct event_constraint *
2640 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
2641 struct perf_event *event,
2642 struct hw_perf_event_extra *reg)
2643 {
2644 struct event_constraint *c = &emptyconstraint;
2645 struct er_account *era;
2646 unsigned long flags;
2647 int idx = reg->idx;
2648
2649 /*
2650 * reg->alloc can be set due to existing state, so for fake cpuc we
2651 * need to ignore this, otherwise we might fail to allocate proper fake
2652 * state for this extra reg constraint. Also see the comment below.
2653 */
2654 if (reg->alloc && !cpuc->is_fake)
2655 return NULL; /* call x86_get_event_constraint() */
2656
2657 again:
2658 era = &cpuc->shared_regs->regs[idx];
2659 /*
2660 * we use spin_lock_irqsave() to avoid lockdep issues when
2661 * passing a fake cpuc
2662 */
2663 raw_spin_lock_irqsave(&era->lock, flags);
2664
2665 if (!atomic_read(&era->ref) || era->config == reg->config) {
2666
2667 /*
2668 * If its a fake cpuc -- as per validate_{group,event}() we
2669 * shouldn't touch event state and we can avoid doing so
2670 * since both will only call get_event_constraints() once
2671 * on each event, this avoids the need for reg->alloc.
2672 *
2673 * Not doing the ER fixup will only result in era->reg being
2674 * wrong, but since we won't actually try and program hardware
2675 * this isn't a problem either.
2676 */
2677 if (!cpuc->is_fake) {
2678 if (idx != reg->idx)
2679 intel_fixup_er(event, idx);
2680
2681 /*
2682 * x86_schedule_events() can call get_event_constraints()
2683 * multiple times on events in the case of incremental
2684 * scheduling(). reg->alloc ensures we only do the ER
2685 * allocation once.
2686 */
2687 reg->alloc = 1;
2688 }
2689
2690 /* lock in msr value */
2691 era->config = reg->config;
2692 era->reg = reg->reg;
2693
2694 /* one more user */
2695 atomic_inc(&era->ref);
2696
2697 /*
2698 * need to call x86_get_event_constraint()
2699 * to check if associated event has constraints
2700 */
2701 c = NULL;
2702 } else {
2703 idx = intel_alt_er(idx, reg->config);
2704 if (idx != reg->idx) {
2705 raw_spin_unlock_irqrestore(&era->lock, flags);
2706 goto again;
2707 }
2708 }
2709 raw_spin_unlock_irqrestore(&era->lock, flags);
2710
2711 return c;
2712 }
2713
2714 static void
2715 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2716 struct hw_perf_event_extra *reg)
2717 {
2718 struct er_account *era;
2719
2720 /*
2721 * Only put constraint if extra reg was actually allocated. Also takes
2722 * care of event which do not use an extra shared reg.
2723 *
2724 * Also, if this is a fake cpuc we shouldn't touch any event state
2725 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2726 * either since it'll be thrown out.
2727 */
2728 if (!reg->alloc || cpuc->is_fake)
2729 return;
2730
2731 era = &cpuc->shared_regs->regs[reg->idx];
2732
2733 /* one fewer user */
2734 atomic_dec(&era->ref);
2735
2736 /* allocate again next time */
2737 reg->alloc = 0;
2738 }
2739
2740 static struct event_constraint *
2741 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2742 struct perf_event *event)
2743 {
2744 struct event_constraint *c = NULL, *d;
2745 struct hw_perf_event_extra *xreg, *breg;
2746
2747 xreg = &event->hw.extra_reg;
2748 if (xreg->idx != EXTRA_REG_NONE) {
2749 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2750 if (c == &emptyconstraint)
2751 return c;
2752 }
2753 breg = &event->hw.branch_reg;
2754 if (breg->idx != EXTRA_REG_NONE) {
2755 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2756 if (d == &emptyconstraint) {
2757 __intel_shared_reg_put_constraints(cpuc, xreg);
2758 c = d;
2759 }
2760 }
2761 return c;
2762 }
2763
2764 struct event_constraint *
2765 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2766 struct perf_event *event)
2767 {
2768 struct event_constraint *c;
2769
2770 if (x86_pmu.event_constraints) {
2771 for_each_event_constraint(c, x86_pmu.event_constraints) {
2772 if (constraint_match(c, event->hw.config)) {
2773 event->hw.flags |= c->flags;
2774 return c;
2775 }
2776 }
2777 }
2778
2779 return &unconstrained;
2780 }
2781
2782 static struct event_constraint *
2783 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2784 struct perf_event *event)
2785 {
2786 struct event_constraint *c;
2787
2788 c = intel_bts_constraints(event);
2789 if (c)
2790 return c;
2791
2792 c = intel_shared_regs_constraints(cpuc, event);
2793 if (c)
2794 return c;
2795
2796 c = intel_pebs_constraints(event);
2797 if (c)
2798 return c;
2799
2800 return x86_get_event_constraints(cpuc, idx, event);
2801 }
2802
2803 static void
2804 intel_start_scheduling(struct cpu_hw_events *cpuc)
2805 {
2806 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2807 struct intel_excl_states *xl;
2808 int tid = cpuc->excl_thread_id;
2809
2810 /*
2811 * nothing needed if in group validation mode
2812 */
2813 if (cpuc->is_fake || !is_ht_workaround_enabled())
2814 return;
2815
2816 /*
2817 * no exclusion needed
2818 */
2819 if (WARN_ON_ONCE(!excl_cntrs))
2820 return;
2821
2822 xl = &excl_cntrs->states[tid];
2823
2824 xl->sched_started = true;
2825 /*
2826 * lock shared state until we are done scheduling
2827 * in stop_event_scheduling()
2828 * makes scheduling appear as a transaction
2829 */
2830 raw_spin_lock(&excl_cntrs->lock);
2831 }
2832
2833 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2834 {
2835 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2836 struct event_constraint *c = cpuc->event_constraint[idx];
2837 struct intel_excl_states *xl;
2838 int tid = cpuc->excl_thread_id;
2839
2840 if (cpuc->is_fake || !is_ht_workaround_enabled())
2841 return;
2842
2843 if (WARN_ON_ONCE(!excl_cntrs))
2844 return;
2845
2846 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2847 return;
2848
2849 xl = &excl_cntrs->states[tid];
2850
2851 lockdep_assert_held(&excl_cntrs->lock);
2852
2853 if (c->flags & PERF_X86_EVENT_EXCL)
2854 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
2855 else
2856 xl->state[cntr] = INTEL_EXCL_SHARED;
2857 }
2858
2859 static void
2860 intel_stop_scheduling(struct cpu_hw_events *cpuc)
2861 {
2862 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2863 struct intel_excl_states *xl;
2864 int tid = cpuc->excl_thread_id;
2865
2866 /*
2867 * nothing needed if in group validation mode
2868 */
2869 if (cpuc->is_fake || !is_ht_workaround_enabled())
2870 return;
2871 /*
2872 * no exclusion needed
2873 */
2874 if (WARN_ON_ONCE(!excl_cntrs))
2875 return;
2876
2877 xl = &excl_cntrs->states[tid];
2878
2879 xl->sched_started = false;
2880 /*
2881 * release shared state lock (acquired in intel_start_scheduling())
2882 */
2883 raw_spin_unlock(&excl_cntrs->lock);
2884 }
2885
2886 static struct event_constraint *
2887 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
2888 {
2889 WARN_ON_ONCE(!cpuc->constraint_list);
2890
2891 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2892 struct event_constraint *cx;
2893
2894 /*
2895 * grab pre-allocated constraint entry
2896 */
2897 cx = &cpuc->constraint_list[idx];
2898
2899 /*
2900 * initialize dynamic constraint
2901 * with static constraint
2902 */
2903 *cx = *c;
2904
2905 /*
2906 * mark constraint as dynamic
2907 */
2908 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2909 c = cx;
2910 }
2911
2912 return c;
2913 }
2914
2915 static struct event_constraint *
2916 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2917 int idx, struct event_constraint *c)
2918 {
2919 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2920 struct intel_excl_states *xlo;
2921 int tid = cpuc->excl_thread_id;
2922 int is_excl, i, w;
2923
2924 /*
2925 * validating a group does not require
2926 * enforcing cross-thread exclusion
2927 */
2928 if (cpuc->is_fake || !is_ht_workaround_enabled())
2929 return c;
2930
2931 /*
2932 * no exclusion needed
2933 */
2934 if (WARN_ON_ONCE(!excl_cntrs))
2935 return c;
2936
2937 /*
2938 * because we modify the constraint, we need
2939 * to make a copy. Static constraints come
2940 * from static const tables.
2941 *
2942 * only needed when constraint has not yet
2943 * been cloned (marked dynamic)
2944 */
2945 c = dyn_constraint(cpuc, c, idx);
2946
2947 /*
2948 * From here on, the constraint is dynamic.
2949 * Either it was just allocated above, or it
2950 * was allocated during a earlier invocation
2951 * of this function
2952 */
2953
2954 /*
2955 * state of sibling HT
2956 */
2957 xlo = &excl_cntrs->states[tid ^ 1];
2958
2959 /*
2960 * event requires exclusive counter access
2961 * across HT threads
2962 */
2963 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2964 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2965 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2966 if (!cpuc->n_excl++)
2967 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2968 }
2969
2970 /*
2971 * Modify static constraint with current dynamic
2972 * state of thread
2973 *
2974 * EXCLUSIVE: sibling counter measuring exclusive event
2975 * SHARED : sibling counter measuring non-exclusive event
2976 * UNUSED : sibling counter unused
2977 */
2978 w = c->weight;
2979 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
2980 /*
2981 * exclusive event in sibling counter
2982 * our corresponding counter cannot be used
2983 * regardless of our event
2984 */
2985 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
2986 __clear_bit(i, c->idxmsk);
2987 w--;
2988 continue;
2989 }
2990 /*
2991 * if measuring an exclusive event, sibling
2992 * measuring non-exclusive, then counter cannot
2993 * be used
2994 */
2995 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
2996 __clear_bit(i, c->idxmsk);
2997 w--;
2998 continue;
2999 }
3000 }
3001
3002 /*
3003 * if we return an empty mask, then switch
3004 * back to static empty constraint to avoid
3005 * the cost of freeing later on
3006 */
3007 if (!w)
3008 c = &emptyconstraint;
3009
3010 c->weight = w;
3011
3012 return c;
3013 }
3014
3015 static struct event_constraint *
3016 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3017 struct perf_event *event)
3018 {
3019 struct event_constraint *c1, *c2;
3020
3021 c1 = cpuc->event_constraint[idx];
3022
3023 /*
3024 * first time only
3025 * - static constraint: no change across incremental scheduling calls
3026 * - dynamic constraint: handled by intel_get_excl_constraints()
3027 */
3028 c2 = __intel_get_event_constraints(cpuc, idx, event);
3029 if (c1) {
3030 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3031 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3032 c1->weight = c2->weight;
3033 c2 = c1;
3034 }
3035
3036 if (cpuc->excl_cntrs)
3037 return intel_get_excl_constraints(cpuc, event, idx, c2);
3038
3039 return c2;
3040 }
3041
3042 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3043 struct perf_event *event)
3044 {
3045 struct hw_perf_event *hwc = &event->hw;
3046 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3047 int tid = cpuc->excl_thread_id;
3048 struct intel_excl_states *xl;
3049
3050 /*
3051 * nothing needed if in group validation mode
3052 */
3053 if (cpuc->is_fake)
3054 return;
3055
3056 if (WARN_ON_ONCE(!excl_cntrs))
3057 return;
3058
3059 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3060 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3061 if (!--cpuc->n_excl)
3062 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3063 }
3064
3065 /*
3066 * If event was actually assigned, then mark the counter state as
3067 * unused now.
3068 */
3069 if (hwc->idx >= 0) {
3070 xl = &excl_cntrs->states[tid];
3071
3072 /*
3073 * put_constraint may be called from x86_schedule_events()
3074 * which already has the lock held so here make locking
3075 * conditional.
3076 */
3077 if (!xl->sched_started)
3078 raw_spin_lock(&excl_cntrs->lock);
3079
3080 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3081
3082 if (!xl->sched_started)
3083 raw_spin_unlock(&excl_cntrs->lock);
3084 }
3085 }
3086
3087 static void
3088 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3089 struct perf_event *event)
3090 {
3091 struct hw_perf_event_extra *reg;
3092
3093 reg = &event->hw.extra_reg;
3094 if (reg->idx != EXTRA_REG_NONE)
3095 __intel_shared_reg_put_constraints(cpuc, reg);
3096
3097 reg = &event->hw.branch_reg;
3098 if (reg->idx != EXTRA_REG_NONE)
3099 __intel_shared_reg_put_constraints(cpuc, reg);
3100 }
3101
3102 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3103 struct perf_event *event)
3104 {
3105 intel_put_shared_regs_event_constraints(cpuc, event);
3106
3107 /*
3108 * is PMU has exclusive counter restrictions, then
3109 * all events are subject to and must call the
3110 * put_excl_constraints() routine
3111 */
3112 if (cpuc->excl_cntrs)
3113 intel_put_excl_constraints(cpuc, event);
3114 }
3115
3116 static void intel_pebs_aliases_core2(struct perf_event *event)
3117 {
3118 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3119 /*
3120 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3121 * (0x003c) so that we can use it with PEBS.
3122 *
3123 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3124 * PEBS capable. However we can use INST_RETIRED.ANY_P
3125 * (0x00c0), which is a PEBS capable event, to get the same
3126 * count.
3127 *
3128 * INST_RETIRED.ANY_P counts the number of cycles that retires
3129 * CNTMASK instructions. By setting CNTMASK to a value (16)
3130 * larger than the maximum number of instructions that can be
3131 * retired per cycle (4) and then inverting the condition, we
3132 * count all cycles that retire 16 or less instructions, which
3133 * is every cycle.
3134 *
3135 * Thereby we gain a PEBS capable cycle counter.
3136 */
3137 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3138
3139 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3140 event->hw.config = alt_config;
3141 }
3142 }
3143
3144 static void intel_pebs_aliases_snb(struct perf_event *event)
3145 {
3146 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3147 /*
3148 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3149 * (0x003c) so that we can use it with PEBS.
3150 *
3151 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3152 * PEBS capable. However we can use UOPS_RETIRED.ALL
3153 * (0x01c2), which is a PEBS capable event, to get the same
3154 * count.
3155 *
3156 * UOPS_RETIRED.ALL counts the number of cycles that retires
3157 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3158 * larger than the maximum number of micro-ops that can be
3159 * retired per cycle (4) and then inverting the condition, we
3160 * count all cycles that retire 16 or less micro-ops, which
3161 * is every cycle.
3162 *
3163 * Thereby we gain a PEBS capable cycle counter.
3164 */
3165 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3166
3167 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3168 event->hw.config = alt_config;
3169 }
3170 }
3171
3172 static void intel_pebs_aliases_precdist(struct perf_event *event)
3173 {
3174 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3175 /*
3176 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3177 * (0x003c) so that we can use it with PEBS.
3178 *
3179 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3180 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3181 * (0x01c0), which is a PEBS capable event, to get the same
3182 * count.
3183 *
3184 * The PREC_DIST event has special support to minimize sample
3185 * shadowing effects. One drawback is that it can be
3186 * only programmed on counter 1, but that seems like an
3187 * acceptable trade off.
3188 */
3189 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3190
3191 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3192 event->hw.config = alt_config;
3193 }
3194 }
3195
3196 static void intel_pebs_aliases_ivb(struct perf_event *event)
3197 {
3198 if (event->attr.precise_ip < 3)
3199 return intel_pebs_aliases_snb(event);
3200 return intel_pebs_aliases_precdist(event);
3201 }
3202
3203 static void intel_pebs_aliases_skl(struct perf_event *event)
3204 {
3205 if (event->attr.precise_ip < 3)
3206 return intel_pebs_aliases_core2(event);
3207 return intel_pebs_aliases_precdist(event);
3208 }
3209
3210 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3211 {
3212 unsigned long flags = x86_pmu.large_pebs_flags;
3213
3214 if (event->attr.use_clockid)
3215 flags &= ~PERF_SAMPLE_TIME;
3216 if (!event->attr.exclude_kernel)
3217 flags &= ~PERF_SAMPLE_REGS_USER;
3218 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3219 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3220 return flags;
3221 }
3222
3223 static int intel_pmu_bts_config(struct perf_event *event)
3224 {
3225 struct perf_event_attr *attr = &event->attr;
3226
3227 if (unlikely(intel_pmu_has_bts(event))) {
3228 /* BTS is not supported by this architecture. */
3229 if (!x86_pmu.bts_active)
3230 return -EOPNOTSUPP;
3231
3232 /* BTS is currently only allowed for user-mode. */
3233 if (!attr->exclude_kernel)
3234 return -EOPNOTSUPP;
3235
3236 /* BTS is not allowed for precise events. */
3237 if (attr->precise_ip)
3238 return -EOPNOTSUPP;
3239
3240 /* disallow bts if conflicting events are present */
3241 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3242 return -EBUSY;
3243
3244 event->destroy = hw_perf_lbr_event_destroy;
3245 }
3246
3247 return 0;
3248 }
3249
3250 static int core_pmu_hw_config(struct perf_event *event)
3251 {
3252 int ret = x86_pmu_hw_config(event);
3253
3254 if (ret)
3255 return ret;
3256
3257 return intel_pmu_bts_config(event);
3258 }
3259
3260 static int intel_pmu_hw_config(struct perf_event *event)
3261 {
3262 int ret = x86_pmu_hw_config(event);
3263
3264 if (ret)
3265 return ret;
3266
3267 ret = intel_pmu_bts_config(event);
3268 if (ret)
3269 return ret;
3270
3271 if (event->attr.precise_ip) {
3272 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3273 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3274 if (!(event->attr.sample_type &
3275 ~intel_pmu_large_pebs_flags(event)))
3276 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3277 }
3278 if (x86_pmu.pebs_aliases)
3279 x86_pmu.pebs_aliases(event);
3280
3281 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3282 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
3283 }
3284
3285 if (needs_branch_stack(event)) {
3286 ret = intel_pmu_setup_lbr_filter(event);
3287 if (ret)
3288 return ret;
3289
3290 /*
3291 * BTS is set up earlier in this path, so don't account twice
3292 */
3293 if (!unlikely(intel_pmu_has_bts(event))) {
3294 /* disallow lbr if conflicting events are present */
3295 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3296 return -EBUSY;
3297
3298 event->destroy = hw_perf_lbr_event_destroy;
3299 }
3300 }
3301
3302 if (event->attr.aux_output) {
3303 if (!event->attr.precise_ip)
3304 return -EINVAL;
3305
3306 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
3307 }
3308
3309 if (event->attr.type != PERF_TYPE_RAW)
3310 return 0;
3311
3312 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3313 return 0;
3314
3315 if (x86_pmu.version < 3)
3316 return -EINVAL;
3317
3318 ret = perf_allow_cpu(&event->attr);
3319 if (ret)
3320 return ret;
3321
3322 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3323
3324 return 0;
3325 }
3326
3327 #ifdef CONFIG_RETPOLINE
3328 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr);
3329 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr);
3330 #endif
3331
3332 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
3333 {
3334 #ifdef CONFIG_RETPOLINE
3335 if (x86_pmu.guest_get_msrs == intel_guest_get_msrs)
3336 return intel_guest_get_msrs(nr);
3337 else if (x86_pmu.guest_get_msrs == core_guest_get_msrs)
3338 return core_guest_get_msrs(nr);
3339 #endif
3340 if (x86_pmu.guest_get_msrs)
3341 return x86_pmu.guest_get_msrs(nr);
3342 *nr = 0;
3343 return NULL;
3344 }
3345 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
3346
3347 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3348 {
3349 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3350 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3351
3352 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3353 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3354 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3355 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
3356 arr[0].guest &= ~cpuc->pebs_enabled;
3357 else
3358 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
3359 *nr = 1;
3360
3361 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
3362 /*
3363 * If PMU counter has PEBS enabled it is not enough to
3364 * disable counter on a guest entry since PEBS memory
3365 * write can overshoot guest entry and corrupt guest
3366 * memory. Disabling PEBS solves the problem.
3367 *
3368 * Don't do this if the CPU already enforces it.
3369 */
3370 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3371 arr[1].host = cpuc->pebs_enabled;
3372 arr[1].guest = 0;
3373 *nr = 2;
3374 }
3375
3376 return arr;
3377 }
3378
3379 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3380 {
3381 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3382 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3383 int idx;
3384
3385 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3386 struct perf_event *event = cpuc->events[idx];
3387
3388 arr[idx].msr = x86_pmu_config_addr(idx);
3389 arr[idx].host = arr[idx].guest = 0;
3390
3391 if (!test_bit(idx, cpuc->active_mask))
3392 continue;
3393
3394 arr[idx].host = arr[idx].guest =
3395 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3396
3397 if (event->attr.exclude_host)
3398 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3399 else if (event->attr.exclude_guest)
3400 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3401 }
3402
3403 *nr = x86_pmu.num_counters;
3404 return arr;
3405 }
3406
3407 static void core_pmu_enable_event(struct perf_event *event)
3408 {
3409 if (!event->attr.exclude_host)
3410 x86_pmu_enable_event(event);
3411 }
3412
3413 static void core_pmu_enable_all(int added)
3414 {
3415 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3416 int idx;
3417
3418 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3419 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3420
3421 if (!test_bit(idx, cpuc->active_mask) ||
3422 cpuc->events[idx]->attr.exclude_host)
3423 continue;
3424
3425 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3426 }
3427 }
3428
3429 static int hsw_hw_config(struct perf_event *event)
3430 {
3431 int ret = intel_pmu_hw_config(event);
3432
3433 if (ret)
3434 return ret;
3435 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3436 return 0;
3437 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3438
3439 /*
3440 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3441 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3442 * this combination.
3443 */
3444 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3445 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3446 event->attr.precise_ip > 0))
3447 return -EOPNOTSUPP;
3448
3449 if (event_is_checkpointed(event)) {
3450 /*
3451 * Sampling of checkpointed events can cause situations where
3452 * the CPU constantly aborts because of a overflow, which is
3453 * then checkpointed back and ignored. Forbid checkpointing
3454 * for sampling.
3455 *
3456 * But still allow a long sampling period, so that perf stat
3457 * from KVM works.
3458 */
3459 if (event->attr.sample_period > 0 &&
3460 event->attr.sample_period < 0x7fffffff)
3461 return -EOPNOTSUPP;
3462 }
3463 return 0;
3464 }
3465
3466 static struct event_constraint counter0_constraint =
3467 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3468
3469 static struct event_constraint counter2_constraint =
3470 EVENT_CONSTRAINT(0, 0x4, 0);
3471
3472 static struct event_constraint fixed0_constraint =
3473 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
3474
3475 static struct event_constraint fixed0_counter0_constraint =
3476 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
3477
3478 static struct event_constraint *
3479 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3480 struct perf_event *event)
3481 {
3482 struct event_constraint *c;
3483
3484 c = intel_get_event_constraints(cpuc, idx, event);
3485
3486 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3487 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3488 if (c->idxmsk64 & (1U << 2))
3489 return &counter2_constraint;
3490 return &emptyconstraint;
3491 }
3492
3493 return c;
3494 }
3495
3496 static struct event_constraint *
3497 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3498 struct perf_event *event)
3499 {
3500 /*
3501 * Fixed counter 0 has less skid.
3502 * Force instruction:ppp in Fixed counter 0
3503 */
3504 if ((event->attr.precise_ip == 3) &&
3505 constraint_match(&fixed0_constraint, event->hw.config))
3506 return &fixed0_constraint;
3507
3508 return hsw_get_event_constraints(cpuc, idx, event);
3509 }
3510
3511 static struct event_constraint *
3512 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3513 struct perf_event *event)
3514 {
3515 struct event_constraint *c;
3516
3517 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
3518 if (event->attr.precise_ip == 3)
3519 return &counter0_constraint;
3520
3521 c = intel_get_event_constraints(cpuc, idx, event);
3522
3523 return c;
3524 }
3525
3526 static struct event_constraint *
3527 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3528 struct perf_event *event)
3529 {
3530 struct event_constraint *c;
3531
3532 /*
3533 * :ppp means to do reduced skid PEBS,
3534 * which is available on PMC0 and fixed counter 0.
3535 */
3536 if (event->attr.precise_ip == 3) {
3537 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
3538 if (constraint_match(&fixed0_constraint, event->hw.config))
3539 return &fixed0_counter0_constraint;
3540
3541 return &counter0_constraint;
3542 }
3543
3544 c = intel_get_event_constraints(cpuc, idx, event);
3545
3546 return c;
3547 }
3548
3549 static bool allow_tsx_force_abort = true;
3550
3551 static struct event_constraint *
3552 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3553 struct perf_event *event)
3554 {
3555 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
3556
3557 /*
3558 * Without TFA we must not use PMC3.
3559 */
3560 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
3561 c = dyn_constraint(cpuc, c, idx);
3562 c->idxmsk64 &= ~(1ULL << 3);
3563 c->weight--;
3564 }
3565
3566 return c;
3567 }
3568
3569 /*
3570 * Broadwell:
3571 *
3572 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
3573 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
3574 * the two to enforce a minimum period of 128 (the smallest value that has bits
3575 * 0-5 cleared and >= 100).
3576 *
3577 * Because of how the code in x86_perf_event_set_period() works, the truncation
3578 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
3579 * to make up for the 'lost' events due to carrying the 'error' in period_left.
3580 *
3581 * Therefore the effective (average) period matches the requested period,
3582 * despite coarser hardware granularity.
3583 */
3584 static u64 bdw_limit_period(struct perf_event *event, u64 left)
3585 {
3586 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
3587 X86_CONFIG(.event=0xc0, .umask=0x01)) {
3588 if (left < 128)
3589 left = 128;
3590 left &= ~0x3fULL;
3591 }
3592 return left;
3593 }
3594
3595 static u64 nhm_limit_period(struct perf_event *event, u64 left)
3596 {
3597 return max(left, 32ULL);
3598 }
3599
3600 PMU_FORMAT_ATTR(event, "config:0-7" );
3601 PMU_FORMAT_ATTR(umask, "config:8-15" );
3602 PMU_FORMAT_ATTR(edge, "config:18" );
3603 PMU_FORMAT_ATTR(pc, "config:19" );
3604 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
3605 PMU_FORMAT_ATTR(inv, "config:23" );
3606 PMU_FORMAT_ATTR(cmask, "config:24-31" );
3607 PMU_FORMAT_ATTR(in_tx, "config:32");
3608 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
3609
3610 static struct attribute *intel_arch_formats_attr[] = {
3611 &format_attr_event.attr,
3612 &format_attr_umask.attr,
3613 &format_attr_edge.attr,
3614 &format_attr_pc.attr,
3615 &format_attr_inv.attr,
3616 &format_attr_cmask.attr,
3617 NULL,
3618 };
3619
3620 ssize_t intel_event_sysfs_show(char *page, u64 config)
3621 {
3622 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
3623
3624 return x86_event_sysfs_show(page, config, event);
3625 }
3626
3627 static struct intel_shared_regs *allocate_shared_regs(int cpu)
3628 {
3629 struct intel_shared_regs *regs;
3630 int i;
3631
3632 regs = kzalloc_node(sizeof(struct intel_shared_regs),
3633 GFP_KERNEL, cpu_to_node(cpu));
3634 if (regs) {
3635 /*
3636 * initialize the locks to keep lockdep happy
3637 */
3638 for (i = 0; i < EXTRA_REG_MAX; i++)
3639 raw_spin_lock_init(&regs->regs[i].lock);
3640
3641 regs->core_id = -1;
3642 }
3643 return regs;
3644 }
3645
3646 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
3647 {
3648 struct intel_excl_cntrs *c;
3649
3650 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
3651 GFP_KERNEL, cpu_to_node(cpu));
3652 if (c) {
3653 raw_spin_lock_init(&c->lock);
3654 c->core_id = -1;
3655 }
3656 return c;
3657 }
3658
3659
3660 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
3661 {
3662 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
3663
3664 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
3665 cpuc->shared_regs = allocate_shared_regs(cpu);
3666 if (!cpuc->shared_regs)
3667 goto err;
3668 }
3669
3670 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
3671 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
3672
3673 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
3674 if (!cpuc->constraint_list)
3675 goto err_shared_regs;
3676 }
3677
3678 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3679 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
3680 if (!cpuc->excl_cntrs)
3681 goto err_constraint_list;
3682
3683 cpuc->excl_thread_id = 0;
3684 }
3685
3686 return 0;
3687
3688 err_constraint_list:
3689 kfree(cpuc->constraint_list);
3690 cpuc->constraint_list = NULL;
3691
3692 err_shared_regs:
3693 kfree(cpuc->shared_regs);
3694 cpuc->shared_regs = NULL;
3695
3696 err:
3697 return -ENOMEM;
3698 }
3699
3700 static int intel_pmu_cpu_prepare(int cpu)
3701 {
3702 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
3703 }
3704
3705 static void flip_smm_bit(void *data)
3706 {
3707 unsigned long set = *(unsigned long *)data;
3708
3709 if (set > 0) {
3710 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
3711 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3712 } else {
3713 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
3714 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3715 }
3716 }
3717
3718 static void intel_pmu_cpu_starting(int cpu)
3719 {
3720 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3721 int core_id = topology_core_id(cpu);
3722 int i;
3723
3724 init_debug_store_on_cpu(cpu);
3725 /*
3726 * Deal with CPUs that don't clear their LBRs on power-up.
3727 */
3728 intel_pmu_lbr_reset();
3729
3730 cpuc->lbr_sel = NULL;
3731
3732 if (x86_pmu.flags & PMU_FL_TFA) {
3733 WARN_ON_ONCE(cpuc->tfa_shadow);
3734 cpuc->tfa_shadow = ~0ULL;
3735 intel_set_tfa(cpuc, false);
3736 }
3737
3738 if (x86_pmu.version > 1)
3739 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
3740
3741 if (x86_pmu.counter_freezing)
3742 enable_counter_freeze();
3743
3744 if (!cpuc->shared_regs)
3745 return;
3746
3747 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
3748 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3749 struct intel_shared_regs *pc;
3750
3751 pc = per_cpu(cpu_hw_events, i).shared_regs;
3752 if (pc && pc->core_id == core_id) {
3753 cpuc->kfree_on_online[0] = cpuc->shared_regs;
3754 cpuc->shared_regs = pc;
3755 break;
3756 }
3757 }
3758 cpuc->shared_regs->core_id = core_id;
3759 cpuc->shared_regs->refcnt++;
3760 }
3761
3762 if (x86_pmu.lbr_sel_map)
3763 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
3764
3765 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3766 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3767 struct cpu_hw_events *sibling;
3768 struct intel_excl_cntrs *c;
3769
3770 sibling = &per_cpu(cpu_hw_events, i);
3771 c = sibling->excl_cntrs;
3772 if (c && c->core_id == core_id) {
3773 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
3774 cpuc->excl_cntrs = c;
3775 if (!sibling->excl_thread_id)
3776 cpuc->excl_thread_id = 1;
3777 break;
3778 }
3779 }
3780 cpuc->excl_cntrs->core_id = core_id;
3781 cpuc->excl_cntrs->refcnt++;
3782 }
3783 }
3784
3785 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
3786 {
3787 struct intel_excl_cntrs *c;
3788
3789 c = cpuc->excl_cntrs;
3790 if (c) {
3791 if (c->core_id == -1 || --c->refcnt == 0)
3792 kfree(c);
3793 cpuc->excl_cntrs = NULL;
3794 }
3795
3796 kfree(cpuc->constraint_list);
3797 cpuc->constraint_list = NULL;
3798 }
3799
3800 static void intel_pmu_cpu_dying(int cpu)
3801 {
3802 fini_debug_store_on_cpu(cpu);
3803
3804 if (x86_pmu.counter_freezing)
3805 disable_counter_freeze();
3806 }
3807
3808 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
3809 {
3810 struct intel_shared_regs *pc;
3811
3812 pc = cpuc->shared_regs;
3813 if (pc) {
3814 if (pc->core_id == -1 || --pc->refcnt == 0)
3815 kfree(pc);
3816 cpuc->shared_regs = NULL;
3817 }
3818
3819 free_excl_cntrs(cpuc);
3820 }
3821
3822 static void intel_pmu_cpu_dead(int cpu)
3823 {
3824 intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu));
3825 }
3826
3827 static void intel_pmu_sched_task(struct perf_event_context *ctx,
3828 bool sched_in)
3829 {
3830 intel_pmu_pebs_sched_task(ctx, sched_in);
3831 intel_pmu_lbr_sched_task(ctx, sched_in);
3832 }
3833
3834 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev,
3835 struct perf_event_context *next)
3836 {
3837 intel_pmu_lbr_swap_task_ctx(prev, next);
3838 }
3839
3840 static int intel_pmu_check_period(struct perf_event *event, u64 value)
3841 {
3842 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
3843 }
3844
3845 static int intel_pmu_aux_output_match(struct perf_event *event)
3846 {
3847 if (!x86_pmu.intel_cap.pebs_output_pt_available)
3848 return 0;
3849
3850 return is_intel_pt_event(event);
3851 }
3852
3853 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
3854
3855 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
3856
3857 PMU_FORMAT_ATTR(frontend, "config1:0-23");
3858
3859 static struct attribute *intel_arch3_formats_attr[] = {
3860 &format_attr_event.attr,
3861 &format_attr_umask.attr,
3862 &format_attr_edge.attr,
3863 &format_attr_pc.attr,
3864 &format_attr_any.attr,
3865 &format_attr_inv.attr,
3866 &format_attr_cmask.attr,
3867 NULL,
3868 };
3869
3870 static struct attribute *hsw_format_attr[] = {
3871 &format_attr_in_tx.attr,
3872 &format_attr_in_tx_cp.attr,
3873 &format_attr_offcore_rsp.attr,
3874 &format_attr_ldlat.attr,
3875 NULL
3876 };
3877
3878 static struct attribute *nhm_format_attr[] = {
3879 &format_attr_offcore_rsp.attr,
3880 &format_attr_ldlat.attr,
3881 NULL
3882 };
3883
3884 static struct attribute *slm_format_attr[] = {
3885 &format_attr_offcore_rsp.attr,
3886 NULL
3887 };
3888
3889 static struct attribute *skl_format_attr[] = {
3890 &format_attr_frontend.attr,
3891 NULL,
3892 };
3893
3894 static __initconst const struct x86_pmu core_pmu = {
3895 .name = "core",
3896 .handle_irq = x86_pmu_handle_irq,
3897 .disable_all = x86_pmu_disable_all,
3898 .enable_all = core_pmu_enable_all,
3899 .enable = core_pmu_enable_event,
3900 .disable = x86_pmu_disable_event,
3901 .hw_config = core_pmu_hw_config,
3902 .schedule_events = x86_schedule_events,
3903 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3904 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3905 .event_map = intel_pmu_event_map,
3906 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3907 .apic = 1,
3908 .large_pebs_flags = LARGE_PEBS_FLAGS,
3909
3910 /*
3911 * Intel PMCs cannot be accessed sanely above 32-bit width,
3912 * so we install an artificial 1<<31 period regardless of
3913 * the generic event period:
3914 */
3915 .max_period = (1ULL<<31) - 1,
3916 .get_event_constraints = intel_get_event_constraints,
3917 .put_event_constraints = intel_put_event_constraints,
3918 .event_constraints = intel_core_event_constraints,
3919 .guest_get_msrs = core_guest_get_msrs,
3920 .format_attrs = intel_arch_formats_attr,
3921 .events_sysfs_show = intel_event_sysfs_show,
3922
3923 /*
3924 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3925 * together with PMU version 1 and thus be using core_pmu with
3926 * shared_regs. We need following callbacks here to allocate
3927 * it properly.
3928 */
3929 .cpu_prepare = intel_pmu_cpu_prepare,
3930 .cpu_starting = intel_pmu_cpu_starting,
3931 .cpu_dying = intel_pmu_cpu_dying,
3932 .cpu_dead = intel_pmu_cpu_dead,
3933
3934 .check_period = intel_pmu_check_period,
3935 };
3936
3937 static __initconst const struct x86_pmu intel_pmu = {
3938 .name = "Intel",
3939 .handle_irq = intel_pmu_handle_irq,
3940 .disable_all = intel_pmu_disable_all,
3941 .enable_all = intel_pmu_enable_all,
3942 .enable = intel_pmu_enable_event,
3943 .disable = intel_pmu_disable_event,
3944 .add = intel_pmu_add_event,
3945 .del = intel_pmu_del_event,
3946 .read = intel_pmu_read_event,
3947 .hw_config = intel_pmu_hw_config,
3948 .schedule_events = x86_schedule_events,
3949 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3950 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3951 .event_map = intel_pmu_event_map,
3952 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3953 .apic = 1,
3954 .large_pebs_flags = LARGE_PEBS_FLAGS,
3955 /*
3956 * Intel PMCs cannot be accessed sanely above 32 bit width,
3957 * so we install an artificial 1<<31 period regardless of
3958 * the generic event period:
3959 */
3960 .max_period = (1ULL << 31) - 1,
3961 .get_event_constraints = intel_get_event_constraints,
3962 .put_event_constraints = intel_put_event_constraints,
3963 .pebs_aliases = intel_pebs_aliases_core2,
3964
3965 .format_attrs = intel_arch3_formats_attr,
3966 .events_sysfs_show = intel_event_sysfs_show,
3967
3968 .cpu_prepare = intel_pmu_cpu_prepare,
3969 .cpu_starting = intel_pmu_cpu_starting,
3970 .cpu_dying = intel_pmu_cpu_dying,
3971 .cpu_dead = intel_pmu_cpu_dead,
3972
3973 .guest_get_msrs = intel_guest_get_msrs,
3974 .sched_task = intel_pmu_sched_task,
3975 .swap_task_ctx = intel_pmu_swap_task_ctx,
3976
3977 .check_period = intel_pmu_check_period,
3978
3979 .aux_output_match = intel_pmu_aux_output_match,
3980 };
3981
3982 static __init void intel_clovertown_quirk(void)
3983 {
3984 /*
3985 * PEBS is unreliable due to:
3986 *
3987 * AJ67 - PEBS may experience CPL leaks
3988 * AJ68 - PEBS PMI may be delayed by one event
3989 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3990 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3991 *
3992 * AJ67 could be worked around by restricting the OS/USR flags.
3993 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3994 *
3995 * AJ106 could possibly be worked around by not allowing LBR
3996 * usage from PEBS, including the fixup.
3997 * AJ68 could possibly be worked around by always programming
3998 * a pebs_event_reset[0] value and coping with the lost events.
3999 *
4000 * But taken together it might just make sense to not enable PEBS on
4001 * these chips.
4002 */
4003 pr_warn("PEBS disabled due to CPU errata\n");
4004 x86_pmu.pebs = 0;
4005 x86_pmu.pebs_constraints = NULL;
4006 }
4007
4008 static const struct x86_cpu_desc isolation_ucodes[] = {
4009 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f),
4010 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e),
4011 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015),
4012 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037),
4013 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a),
4014 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023),
4015 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014),
4016 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010),
4017 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009),
4018 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009),
4019 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002),
4020 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 2, 0x0b000014),
4021 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021),
4022 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000),
4023 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c),
4024 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c),
4025 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e),
4026 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e),
4027 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e),
4028 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e),
4029 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e),
4030 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e),
4031 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e),
4032 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e),
4033 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e),
4034 {}
4035 };
4036
4037 static void intel_check_pebs_isolation(void)
4038 {
4039 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
4040 }
4041
4042 static __init void intel_pebs_isolation_quirk(void)
4043 {
4044 WARN_ON_ONCE(x86_pmu.check_microcode);
4045 x86_pmu.check_microcode = intel_check_pebs_isolation;
4046 intel_check_pebs_isolation();
4047 }
4048
4049 static const struct x86_cpu_desc pebs_ucodes[] = {
4050 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028),
4051 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618),
4052 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c),
4053 {}
4054 };
4055
4056 static bool intel_snb_pebs_broken(void)
4057 {
4058 return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
4059 }
4060
4061 static void intel_snb_check_microcode(void)
4062 {
4063 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
4064 return;
4065
4066 /*
4067 * Serialized by the microcode lock..
4068 */
4069 if (x86_pmu.pebs_broken) {
4070 pr_info("PEBS enabled due to microcode update\n");
4071 x86_pmu.pebs_broken = 0;
4072 } else {
4073 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
4074 x86_pmu.pebs_broken = 1;
4075 }
4076 }
4077
4078 static bool is_lbr_from(unsigned long msr)
4079 {
4080 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
4081
4082 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
4083 }
4084
4085 /*
4086 * Under certain circumstances, access certain MSR may cause #GP.
4087 * The function tests if the input MSR can be safely accessed.
4088 */
4089 static bool check_msr(unsigned long msr, u64 mask)
4090 {
4091 u64 val_old, val_new, val_tmp;
4092
4093 /*
4094 * Disable the check for real HW, so we don't
4095 * mess with potentionaly enabled registers:
4096 */
4097 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
4098 return true;
4099
4100 /*
4101 * Read the current value, change it and read it back to see if it
4102 * matches, this is needed to detect certain hardware emulators
4103 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
4104 */
4105 if (rdmsrl_safe(msr, &val_old))
4106 return false;
4107
4108 /*
4109 * Only change the bits which can be updated by wrmsrl.
4110 */
4111 val_tmp = val_old ^ mask;
4112
4113 if (is_lbr_from(msr))
4114 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
4115
4116 if (wrmsrl_safe(msr, val_tmp) ||
4117 rdmsrl_safe(msr, &val_new))
4118 return false;
4119
4120 /*
4121 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
4122 * should equal rdmsrl()'s even with the quirk.
4123 */
4124 if (val_new != val_tmp)
4125 return false;
4126
4127 if (is_lbr_from(msr))
4128 val_old = lbr_from_signext_quirk_wr(val_old);
4129
4130 /* Here it's sure that the MSR can be safely accessed.
4131 * Restore the old value and return.
4132 */
4133 wrmsrl(msr, val_old);
4134
4135 return true;
4136 }
4137
4138 static __init void intel_sandybridge_quirk(void)
4139 {
4140 x86_pmu.check_microcode = intel_snb_check_microcode;
4141 cpus_read_lock();
4142 intel_snb_check_microcode();
4143 cpus_read_unlock();
4144 }
4145
4146 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
4147 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
4148 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
4149 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
4150 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
4151 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
4152 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
4153 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
4154 };
4155
4156 static __init void intel_arch_events_quirk(void)
4157 {
4158 int bit;
4159
4160 /* disable event that reported as not presend by cpuid */
4161 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
4162 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
4163 pr_warn("CPUID marked event: \'%s\' unavailable\n",
4164 intel_arch_events_map[bit].name);
4165 }
4166 }
4167
4168 static __init void intel_nehalem_quirk(void)
4169 {
4170 union cpuid10_ebx ebx;
4171
4172 ebx.full = x86_pmu.events_maskl;
4173 if (ebx.split.no_branch_misses_retired) {
4174 /*
4175 * Erratum AAJ80 detected, we work it around by using
4176 * the BR_MISP_EXEC.ANY event. This will over-count
4177 * branch-misses, but it's still much better than the
4178 * architectural event which is often completely bogus:
4179 */
4180 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
4181 ebx.split.no_branch_misses_retired = 0;
4182 x86_pmu.events_maskl = ebx.full;
4183 pr_info("CPU erratum AAJ80 worked around\n");
4184 }
4185 }
4186
4187 static const struct x86_cpu_desc counter_freezing_ucodes[] = {
4188 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e),
4189 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e),
4190 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008),
4191 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_D, 1, 0x00000028),
4192 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028),
4193 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006),
4194 {}
4195 };
4196
4197 static bool intel_counter_freezing_broken(void)
4198 {
4199 return !x86_cpu_has_min_microcode_rev(counter_freezing_ucodes);
4200 }
4201
4202 static __init void intel_counter_freezing_quirk(void)
4203 {
4204 /* Check if it's already disabled */
4205 if (disable_counter_freezing)
4206 return;
4207
4208 /*
4209 * If the system starts with the wrong ucode, leave the
4210 * counter-freezing feature permanently disabled.
4211 */
4212 if (intel_counter_freezing_broken()) {
4213 pr_info("PMU counter freezing disabled due to CPU errata,"
4214 "please upgrade microcode\n");
4215 x86_pmu.counter_freezing = false;
4216 x86_pmu.handle_irq = intel_pmu_handle_irq;
4217 }
4218 }
4219
4220 /*
4221 * enable software workaround for errata:
4222 * SNB: BJ122
4223 * IVB: BV98
4224 * HSW: HSD29
4225 *
4226 * Only needed when HT is enabled. However detecting
4227 * if HT is enabled is difficult (model specific). So instead,
4228 * we enable the workaround in the early boot, and verify if
4229 * it is needed in a later initcall phase once we have valid
4230 * topology information to check if HT is actually enabled
4231 */
4232 static __init void intel_ht_bug(void)
4233 {
4234 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
4235
4236 x86_pmu.start_scheduling = intel_start_scheduling;
4237 x86_pmu.commit_scheduling = intel_commit_scheduling;
4238 x86_pmu.stop_scheduling = intel_stop_scheduling;
4239 }
4240
4241 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
4242 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
4243
4244 /* Haswell special events */
4245 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
4246 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
4247 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
4248 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
4249 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
4250 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
4251 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
4252 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
4253 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
4254 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
4255 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
4256 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4257
4258 static struct attribute *hsw_events_attrs[] = {
4259 EVENT_PTR(td_slots_issued),
4260 EVENT_PTR(td_slots_retired),
4261 EVENT_PTR(td_fetch_bubbles),
4262 EVENT_PTR(td_total_slots),
4263 EVENT_PTR(td_total_slots_scale),
4264 EVENT_PTR(td_recovery_bubbles),
4265 EVENT_PTR(td_recovery_bubbles_scale),
4266 NULL
4267 };
4268
4269 static struct attribute *hsw_mem_events_attrs[] = {
4270 EVENT_PTR(mem_ld_hsw),
4271 EVENT_PTR(mem_st_hsw),
4272 NULL,
4273 };
4274
4275 static struct attribute *hsw_tsx_events_attrs[] = {
4276 EVENT_PTR(tx_start),
4277 EVENT_PTR(tx_commit),
4278 EVENT_PTR(tx_abort),
4279 EVENT_PTR(tx_capacity),
4280 EVENT_PTR(tx_conflict),
4281 EVENT_PTR(el_start),
4282 EVENT_PTR(el_commit),
4283 EVENT_PTR(el_abort),
4284 EVENT_PTR(el_capacity),
4285 EVENT_PTR(el_conflict),
4286 EVENT_PTR(cycles_t),
4287 EVENT_PTR(cycles_ct),
4288 NULL
4289 };
4290
4291 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
4292 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
4293 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
4294 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
4295
4296 static struct attribute *icl_events_attrs[] = {
4297 EVENT_PTR(mem_ld_hsw),
4298 EVENT_PTR(mem_st_hsw),
4299 NULL,
4300 };
4301
4302 static struct attribute *icl_tsx_events_attrs[] = {
4303 EVENT_PTR(tx_start),
4304 EVENT_PTR(tx_abort),
4305 EVENT_PTR(tx_commit),
4306 EVENT_PTR(tx_capacity_read),
4307 EVENT_PTR(tx_capacity_write),
4308 EVENT_PTR(tx_conflict),
4309 EVENT_PTR(el_start),
4310 EVENT_PTR(el_abort),
4311 EVENT_PTR(el_commit),
4312 EVENT_PTR(el_capacity_read),
4313 EVENT_PTR(el_capacity_write),
4314 EVENT_PTR(el_conflict),
4315 EVENT_PTR(cycles_t),
4316 EVENT_PTR(cycles_ct),
4317 NULL,
4318 };
4319
4320 static ssize_t freeze_on_smi_show(struct device *cdev,
4321 struct device_attribute *attr,
4322 char *buf)
4323 {
4324 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
4325 }
4326
4327 static DEFINE_MUTEX(freeze_on_smi_mutex);
4328
4329 static ssize_t freeze_on_smi_store(struct device *cdev,
4330 struct device_attribute *attr,
4331 const char *buf, size_t count)
4332 {
4333 unsigned long val;
4334 ssize_t ret;
4335
4336 ret = kstrtoul(buf, 0, &val);
4337 if (ret)
4338 return ret;
4339
4340 if (val > 1)
4341 return -EINVAL;
4342
4343 mutex_lock(&freeze_on_smi_mutex);
4344
4345 if (x86_pmu.attr_freeze_on_smi == val)
4346 goto done;
4347
4348 x86_pmu.attr_freeze_on_smi = val;
4349
4350 get_online_cpus();
4351 on_each_cpu(flip_smm_bit, &val, 1);
4352 put_online_cpus();
4353 done:
4354 mutex_unlock(&freeze_on_smi_mutex);
4355
4356 return count;
4357 }
4358
4359 static void update_tfa_sched(void *ignored)
4360 {
4361 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4362
4363 /*
4364 * check if PMC3 is used
4365 * and if so force schedule out for all event types all contexts
4366 */
4367 if (test_bit(3, cpuc->active_mask))
4368 perf_pmu_resched(x86_get_pmu());
4369 }
4370
4371 static ssize_t show_sysctl_tfa(struct device *cdev,
4372 struct device_attribute *attr,
4373 char *buf)
4374 {
4375 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
4376 }
4377
4378 static ssize_t set_sysctl_tfa(struct device *cdev,
4379 struct device_attribute *attr,
4380 const char *buf, size_t count)
4381 {
4382 bool val;
4383 ssize_t ret;
4384
4385 ret = kstrtobool(buf, &val);
4386 if (ret)
4387 return ret;
4388
4389 /* no change */
4390 if (val == allow_tsx_force_abort)
4391 return count;
4392
4393 allow_tsx_force_abort = val;
4394
4395 get_online_cpus();
4396 on_each_cpu(update_tfa_sched, NULL, 1);
4397 put_online_cpus();
4398
4399 return count;
4400 }
4401
4402
4403 static DEVICE_ATTR_RW(freeze_on_smi);
4404
4405 static ssize_t branches_show(struct device *cdev,
4406 struct device_attribute *attr,
4407 char *buf)
4408 {
4409 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
4410 }
4411
4412 static DEVICE_ATTR_RO(branches);
4413
4414 static struct attribute *lbr_attrs[] = {
4415 &dev_attr_branches.attr,
4416 NULL
4417 };
4418
4419 static char pmu_name_str[30];
4420
4421 static ssize_t pmu_name_show(struct device *cdev,
4422 struct device_attribute *attr,
4423 char *buf)
4424 {
4425 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
4426 }
4427
4428 static DEVICE_ATTR_RO(pmu_name);
4429
4430 static struct attribute *intel_pmu_caps_attrs[] = {
4431 &dev_attr_pmu_name.attr,
4432 NULL
4433 };
4434
4435 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
4436 show_sysctl_tfa,
4437 set_sysctl_tfa);
4438
4439 static struct attribute *intel_pmu_attrs[] = {
4440 &dev_attr_freeze_on_smi.attr,
4441 &dev_attr_allow_tsx_force_abort.attr,
4442 NULL,
4443 };
4444
4445 static umode_t
4446 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4447 {
4448 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
4449 }
4450
4451 static umode_t
4452 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4453 {
4454 return x86_pmu.pebs ? attr->mode : 0;
4455 }
4456
4457 static umode_t
4458 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4459 {
4460 return x86_pmu.lbr_nr ? attr->mode : 0;
4461 }
4462
4463 static umode_t
4464 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4465 {
4466 return x86_pmu.version >= 2 ? attr->mode : 0;
4467 }
4468
4469 static umode_t
4470 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4471 {
4472 if (attr == &dev_attr_allow_tsx_force_abort.attr)
4473 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
4474
4475 return attr->mode;
4476 }
4477
4478 static struct attribute_group group_events_td = {
4479 .name = "events",
4480 };
4481
4482 static struct attribute_group group_events_mem = {
4483 .name = "events",
4484 .is_visible = pebs_is_visible,
4485 };
4486
4487 static struct attribute_group group_events_tsx = {
4488 .name = "events",
4489 .is_visible = tsx_is_visible,
4490 };
4491
4492 static struct attribute_group group_caps_gen = {
4493 .name = "caps",
4494 .attrs = intel_pmu_caps_attrs,
4495 };
4496
4497 static struct attribute_group group_caps_lbr = {
4498 .name = "caps",
4499 .attrs = lbr_attrs,
4500 .is_visible = lbr_is_visible,
4501 };
4502
4503 static struct attribute_group group_format_extra = {
4504 .name = "format",
4505 .is_visible = exra_is_visible,
4506 };
4507
4508 static struct attribute_group group_format_extra_skl = {
4509 .name = "format",
4510 .is_visible = exra_is_visible,
4511 };
4512
4513 static struct attribute_group group_default = {
4514 .attrs = intel_pmu_attrs,
4515 .is_visible = default_is_visible,
4516 };
4517
4518 static const struct attribute_group *attr_update[] = {
4519 &group_events_td,
4520 &group_events_mem,
4521 &group_events_tsx,
4522 &group_caps_gen,
4523 &group_caps_lbr,
4524 &group_format_extra,
4525 &group_format_extra_skl,
4526 &group_default,
4527 NULL,
4528 };
4529
4530 static struct attribute *empty_attrs;
4531
4532 __init int intel_pmu_init(void)
4533 {
4534 struct attribute **extra_skl_attr = &empty_attrs;
4535 struct attribute **extra_attr = &empty_attrs;
4536 struct attribute **td_attr = &empty_attrs;
4537 struct attribute **mem_attr = &empty_attrs;
4538 struct attribute **tsx_attr = &empty_attrs;
4539 union cpuid10_edx edx;
4540 union cpuid10_eax eax;
4541 union cpuid10_ebx ebx;
4542 struct event_constraint *c;
4543 unsigned int unused;
4544 struct extra_reg *er;
4545 bool pmem = false;
4546 int version, i;
4547 char *name;
4548
4549 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
4550 switch (boot_cpu_data.x86) {
4551 case 0x6:
4552 return p6_pmu_init();
4553 case 0xb:
4554 return knc_pmu_init();
4555 case 0xf:
4556 return p4_pmu_init();
4557 }
4558 return -ENODEV;
4559 }
4560
4561 /*
4562 * Check whether the Architectural PerfMon supports
4563 * Branch Misses Retired hw_event or not.
4564 */
4565 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
4566 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
4567 return -ENODEV;
4568
4569 version = eax.split.version_id;
4570 if (version < 2)
4571 x86_pmu = core_pmu;
4572 else
4573 x86_pmu = intel_pmu;
4574
4575 x86_pmu.version = version;
4576 x86_pmu.num_counters = eax.split.num_counters;
4577 x86_pmu.cntval_bits = eax.split.bit_width;
4578 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
4579
4580 x86_pmu.events_maskl = ebx.full;
4581 x86_pmu.events_mask_len = eax.split.mask_length;
4582
4583 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
4584
4585 /*
4586 * Quirk: v2 perfmon does not report fixed-purpose events, so
4587 * assume at least 3 events, when not running in a hypervisor:
4588 */
4589 if (version > 1) {
4590 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
4591
4592 x86_pmu.num_counters_fixed =
4593 max((int)edx.split.num_counters_fixed, assume);
4594 }
4595
4596 if (version >= 4)
4597 x86_pmu.counter_freezing = !disable_counter_freezing;
4598
4599 if (boot_cpu_has(X86_FEATURE_PDCM)) {
4600 u64 capabilities;
4601
4602 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
4603 x86_pmu.intel_cap.capabilities = capabilities;
4604 }
4605
4606 intel_ds_init();
4607
4608 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
4609
4610 /*
4611 * Install the hw-cache-events table:
4612 */
4613 switch (boot_cpu_data.x86_model) {
4614 case INTEL_FAM6_CORE_YONAH:
4615 pr_cont("Core events, ");
4616 name = "core";
4617 break;
4618
4619 case INTEL_FAM6_CORE2_MEROM:
4620 x86_add_quirk(intel_clovertown_quirk);
4621 /* fall through */
4622
4623 case INTEL_FAM6_CORE2_MEROM_L:
4624 case INTEL_FAM6_CORE2_PENRYN:
4625 case INTEL_FAM6_CORE2_DUNNINGTON:
4626 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
4627 sizeof(hw_cache_event_ids));
4628
4629 intel_pmu_lbr_init_core();
4630
4631 x86_pmu.event_constraints = intel_core2_event_constraints;
4632 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
4633 pr_cont("Core2 events, ");
4634 name = "core2";
4635 break;
4636
4637 case INTEL_FAM6_NEHALEM:
4638 case INTEL_FAM6_NEHALEM_EP:
4639 case INTEL_FAM6_NEHALEM_EX:
4640 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
4641 sizeof(hw_cache_event_ids));
4642 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
4643 sizeof(hw_cache_extra_regs));
4644
4645 intel_pmu_lbr_init_nhm();
4646
4647 x86_pmu.event_constraints = intel_nehalem_event_constraints;
4648 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
4649 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
4650 x86_pmu.extra_regs = intel_nehalem_extra_regs;
4651 x86_pmu.limit_period = nhm_limit_period;
4652
4653 mem_attr = nhm_mem_events_attrs;
4654
4655 /* UOPS_ISSUED.STALLED_CYCLES */
4656 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4657 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4658 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
4659 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4660 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
4661
4662 intel_pmu_pebs_data_source_nhm();
4663 x86_add_quirk(intel_nehalem_quirk);
4664 x86_pmu.pebs_no_tlb = 1;
4665 extra_attr = nhm_format_attr;
4666
4667 pr_cont("Nehalem events, ");
4668 name = "nehalem";
4669 break;
4670
4671 case INTEL_FAM6_ATOM_BONNELL:
4672 case INTEL_FAM6_ATOM_BONNELL_MID:
4673 case INTEL_FAM6_ATOM_SALTWELL:
4674 case INTEL_FAM6_ATOM_SALTWELL_MID:
4675 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
4676 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
4677 sizeof(hw_cache_event_ids));
4678
4679 intel_pmu_lbr_init_atom();
4680
4681 x86_pmu.event_constraints = intel_gen_event_constraints;
4682 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
4683 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
4684 pr_cont("Atom events, ");
4685 name = "bonnell";
4686 break;
4687
4688 case INTEL_FAM6_ATOM_SILVERMONT:
4689 case INTEL_FAM6_ATOM_SILVERMONT_D:
4690 case INTEL_FAM6_ATOM_SILVERMONT_MID:
4691 case INTEL_FAM6_ATOM_AIRMONT:
4692 case INTEL_FAM6_ATOM_AIRMONT_MID:
4693 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
4694 sizeof(hw_cache_event_ids));
4695 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
4696 sizeof(hw_cache_extra_regs));
4697
4698 intel_pmu_lbr_init_slm();
4699
4700 x86_pmu.event_constraints = intel_slm_event_constraints;
4701 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
4702 x86_pmu.extra_regs = intel_slm_extra_regs;
4703 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4704 td_attr = slm_events_attrs;
4705 extra_attr = slm_format_attr;
4706 pr_cont("Silvermont events, ");
4707 name = "silvermont";
4708 break;
4709
4710 case INTEL_FAM6_ATOM_GOLDMONT:
4711 case INTEL_FAM6_ATOM_GOLDMONT_D:
4712 x86_add_quirk(intel_counter_freezing_quirk);
4713 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
4714 sizeof(hw_cache_event_ids));
4715 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
4716 sizeof(hw_cache_extra_regs));
4717
4718 intel_pmu_lbr_init_skl();
4719
4720 x86_pmu.event_constraints = intel_slm_event_constraints;
4721 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
4722 x86_pmu.extra_regs = intel_glm_extra_regs;
4723 /*
4724 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4725 * for precise cycles.
4726 * :pp is identical to :ppp
4727 */
4728 x86_pmu.pebs_aliases = NULL;
4729 x86_pmu.pebs_prec_dist = true;
4730 x86_pmu.lbr_pt_coexist = true;
4731 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4732 td_attr = glm_events_attrs;
4733 extra_attr = slm_format_attr;
4734 pr_cont("Goldmont events, ");
4735 name = "goldmont";
4736 break;
4737
4738 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4739 x86_add_quirk(intel_counter_freezing_quirk);
4740 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
4741 sizeof(hw_cache_event_ids));
4742 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
4743 sizeof(hw_cache_extra_regs));
4744
4745 intel_pmu_lbr_init_skl();
4746
4747 x86_pmu.event_constraints = intel_slm_event_constraints;
4748 x86_pmu.extra_regs = intel_glm_extra_regs;
4749 /*
4750 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4751 * for precise cycles.
4752 */
4753 x86_pmu.pebs_aliases = NULL;
4754 x86_pmu.pebs_prec_dist = true;
4755 x86_pmu.lbr_pt_coexist = true;
4756 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4757 x86_pmu.flags |= PMU_FL_PEBS_ALL;
4758 x86_pmu.get_event_constraints = glp_get_event_constraints;
4759 td_attr = glm_events_attrs;
4760 /* Goldmont Plus has 4-wide pipeline */
4761 event_attr_td_total_slots_scale_glm.event_str = "4";
4762 extra_attr = slm_format_attr;
4763 pr_cont("Goldmont plus events, ");
4764 name = "goldmont_plus";
4765 break;
4766
4767 case INTEL_FAM6_ATOM_TREMONT_D:
4768 x86_pmu.late_ack = true;
4769 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
4770 sizeof(hw_cache_event_ids));
4771 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
4772 sizeof(hw_cache_extra_regs));
4773 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
4774
4775 intel_pmu_lbr_init_skl();
4776
4777 x86_pmu.event_constraints = intel_slm_event_constraints;
4778 x86_pmu.extra_regs = intel_tnt_extra_regs;
4779 /*
4780 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4781 * for precise cycles.
4782 */
4783 x86_pmu.pebs_aliases = NULL;
4784 x86_pmu.pebs_prec_dist = true;
4785 x86_pmu.lbr_pt_coexist = true;
4786 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4787 x86_pmu.get_event_constraints = tnt_get_event_constraints;
4788 extra_attr = slm_format_attr;
4789 pr_cont("Tremont events, ");
4790 name = "Tremont";
4791 break;
4792
4793 case INTEL_FAM6_WESTMERE:
4794 case INTEL_FAM6_WESTMERE_EP:
4795 case INTEL_FAM6_WESTMERE_EX:
4796 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
4797 sizeof(hw_cache_event_ids));
4798 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
4799 sizeof(hw_cache_extra_regs));
4800
4801 intel_pmu_lbr_init_nhm();
4802
4803 x86_pmu.event_constraints = intel_westmere_event_constraints;
4804 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
4805 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
4806 x86_pmu.extra_regs = intel_westmere_extra_regs;
4807 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4808
4809 mem_attr = nhm_mem_events_attrs;
4810
4811 /* UOPS_ISSUED.STALLED_CYCLES */
4812 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4813 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4814 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
4815 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4816 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
4817
4818 intel_pmu_pebs_data_source_nhm();
4819 extra_attr = nhm_format_attr;
4820 pr_cont("Westmere events, ");
4821 name = "westmere";
4822 break;
4823
4824 case INTEL_FAM6_SANDYBRIDGE:
4825 case INTEL_FAM6_SANDYBRIDGE_X:
4826 x86_add_quirk(intel_sandybridge_quirk);
4827 x86_add_quirk(intel_ht_bug);
4828 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4829 sizeof(hw_cache_event_ids));
4830 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4831 sizeof(hw_cache_extra_regs));
4832
4833 intel_pmu_lbr_init_snb();
4834
4835 x86_pmu.event_constraints = intel_snb_event_constraints;
4836 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
4837 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
4838 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
4839 x86_pmu.extra_regs = intel_snbep_extra_regs;
4840 else
4841 x86_pmu.extra_regs = intel_snb_extra_regs;
4842
4843
4844 /* all extra regs are per-cpu when HT is on */
4845 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4846 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4847
4848 td_attr = snb_events_attrs;
4849 mem_attr = snb_mem_events_attrs;
4850
4851 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
4852 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4853 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4854 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
4855 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4856 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
4857
4858 extra_attr = nhm_format_attr;
4859
4860 pr_cont("SandyBridge events, ");
4861 name = "sandybridge";
4862 break;
4863
4864 case INTEL_FAM6_IVYBRIDGE:
4865 case INTEL_FAM6_IVYBRIDGE_X:
4866 x86_add_quirk(intel_ht_bug);
4867 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4868 sizeof(hw_cache_event_ids));
4869 /* dTLB-load-misses on IVB is different than SNB */
4870 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
4871
4872 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4873 sizeof(hw_cache_extra_regs));
4874
4875 intel_pmu_lbr_init_snb();
4876
4877 x86_pmu.event_constraints = intel_ivb_event_constraints;
4878 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
4879 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4880 x86_pmu.pebs_prec_dist = true;
4881 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
4882 x86_pmu.extra_regs = intel_snbep_extra_regs;
4883 else
4884 x86_pmu.extra_regs = intel_snb_extra_regs;
4885 /* all extra regs are per-cpu when HT is on */
4886 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4887 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4888
4889 td_attr = snb_events_attrs;
4890 mem_attr = snb_mem_events_attrs;
4891
4892 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
4893 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4894 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4895
4896 extra_attr = nhm_format_attr;
4897
4898 pr_cont("IvyBridge events, ");
4899 name = "ivybridge";
4900 break;
4901
4902
4903 case INTEL_FAM6_HASWELL:
4904 case INTEL_FAM6_HASWELL_X:
4905 case INTEL_FAM6_HASWELL_L:
4906 case INTEL_FAM6_HASWELL_G:
4907 x86_add_quirk(intel_ht_bug);
4908 x86_add_quirk(intel_pebs_isolation_quirk);
4909 x86_pmu.late_ack = true;
4910 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4911 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4912
4913 intel_pmu_lbr_init_hsw();
4914
4915 x86_pmu.event_constraints = intel_hsw_event_constraints;
4916 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
4917 x86_pmu.extra_regs = intel_snbep_extra_regs;
4918 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4919 x86_pmu.pebs_prec_dist = true;
4920 /* all extra regs are per-cpu when HT is on */
4921 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4922 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4923
4924 x86_pmu.hw_config = hsw_hw_config;
4925 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4926 x86_pmu.lbr_double_abort = true;
4927 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4928 hsw_format_attr : nhm_format_attr;
4929 td_attr = hsw_events_attrs;
4930 mem_attr = hsw_mem_events_attrs;
4931 tsx_attr = hsw_tsx_events_attrs;
4932 pr_cont("Haswell events, ");
4933 name = "haswell";
4934 break;
4935
4936 case INTEL_FAM6_BROADWELL:
4937 case INTEL_FAM6_BROADWELL_D:
4938 case INTEL_FAM6_BROADWELL_G:
4939 case INTEL_FAM6_BROADWELL_X:
4940 x86_add_quirk(intel_pebs_isolation_quirk);
4941 x86_pmu.late_ack = true;
4942 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4943 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4944
4945 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
4946 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
4947 BDW_L3_MISS|HSW_SNOOP_DRAM;
4948 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
4949 HSW_SNOOP_DRAM;
4950 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
4951 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4952 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
4953 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4954
4955 intel_pmu_lbr_init_hsw();
4956
4957 x86_pmu.event_constraints = intel_bdw_event_constraints;
4958 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
4959 x86_pmu.extra_regs = intel_snbep_extra_regs;
4960 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4961 x86_pmu.pebs_prec_dist = true;
4962 /* all extra regs are per-cpu when HT is on */
4963 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4964 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4965
4966 x86_pmu.hw_config = hsw_hw_config;
4967 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4968 x86_pmu.limit_period = bdw_limit_period;
4969 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4970 hsw_format_attr : nhm_format_attr;
4971 td_attr = hsw_events_attrs;
4972 mem_attr = hsw_mem_events_attrs;
4973 tsx_attr = hsw_tsx_events_attrs;
4974 pr_cont("Broadwell events, ");
4975 name = "broadwell";
4976 break;
4977
4978 case INTEL_FAM6_XEON_PHI_KNL:
4979 case INTEL_FAM6_XEON_PHI_KNM:
4980 memcpy(hw_cache_event_ids,
4981 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4982 memcpy(hw_cache_extra_regs,
4983 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4984 intel_pmu_lbr_init_knl();
4985
4986 x86_pmu.event_constraints = intel_slm_event_constraints;
4987 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
4988 x86_pmu.extra_regs = intel_knl_extra_regs;
4989
4990 /* all extra regs are per-cpu when HT is on */
4991 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4992 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4993 extra_attr = slm_format_attr;
4994 pr_cont("Knights Landing/Mill events, ");
4995 name = "knights-landing";
4996 break;
4997
4998 case INTEL_FAM6_SKYLAKE_X:
4999 pmem = true;
5000 /* fall through */
5001 case INTEL_FAM6_SKYLAKE_L:
5002 case INTEL_FAM6_SKYLAKE:
5003 case INTEL_FAM6_KABYLAKE_L:
5004 case INTEL_FAM6_KABYLAKE:
5005 case INTEL_FAM6_COMETLAKE_L:
5006 case INTEL_FAM6_COMETLAKE:
5007 x86_add_quirk(intel_pebs_isolation_quirk);
5008 x86_pmu.late_ack = true;
5009 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5010 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5011 intel_pmu_lbr_init_skl();
5012
5013 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
5014 event_attr_td_recovery_bubbles.event_str_noht =
5015 "event=0xd,umask=0x1,cmask=1";
5016 event_attr_td_recovery_bubbles.event_str_ht =
5017 "event=0xd,umask=0x1,cmask=1,any=1";
5018
5019 x86_pmu.event_constraints = intel_skl_event_constraints;
5020 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
5021 x86_pmu.extra_regs = intel_skl_extra_regs;
5022 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
5023 x86_pmu.pebs_prec_dist = true;
5024 /* all extra regs are per-cpu when HT is on */
5025 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5026 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5027
5028 x86_pmu.hw_config = hsw_hw_config;
5029 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5030 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5031 hsw_format_attr : nhm_format_attr;
5032 extra_skl_attr = skl_format_attr;
5033 td_attr = hsw_events_attrs;
5034 mem_attr = hsw_mem_events_attrs;
5035 tsx_attr = hsw_tsx_events_attrs;
5036 intel_pmu_pebs_data_source_skl(pmem);
5037
5038 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
5039 x86_pmu.flags |= PMU_FL_TFA;
5040 x86_pmu.get_event_constraints = tfa_get_event_constraints;
5041 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
5042 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
5043 }
5044
5045 pr_cont("Skylake events, ");
5046 name = "skylake";
5047 break;
5048
5049 case INTEL_FAM6_ICELAKE_X:
5050 case INTEL_FAM6_ICELAKE_D:
5051 pmem = true;
5052 /* fall through */
5053 case INTEL_FAM6_ICELAKE_L:
5054 case INTEL_FAM6_ICELAKE:
5055 case INTEL_FAM6_TIGERLAKE_L:
5056 case INTEL_FAM6_TIGERLAKE:
5057 x86_pmu.late_ack = true;
5058 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5059 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5060 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5061 intel_pmu_lbr_init_skl();
5062
5063 x86_pmu.event_constraints = intel_icl_event_constraints;
5064 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
5065 x86_pmu.extra_regs = intel_icl_extra_regs;
5066 x86_pmu.pebs_aliases = NULL;
5067 x86_pmu.pebs_prec_dist = true;
5068 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5069 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5070
5071 x86_pmu.hw_config = hsw_hw_config;
5072 x86_pmu.get_event_constraints = icl_get_event_constraints;
5073 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5074 hsw_format_attr : nhm_format_attr;
5075 extra_skl_attr = skl_format_attr;
5076 mem_attr = icl_events_attrs;
5077 tsx_attr = icl_tsx_events_attrs;
5078 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xca, .umask=0x02);
5079 x86_pmu.lbr_pt_coexist = true;
5080 intel_pmu_pebs_data_source_skl(pmem);
5081 pr_cont("Icelake events, ");
5082 name = "icelake";
5083 break;
5084
5085 default:
5086 switch (x86_pmu.version) {
5087 case 1:
5088 x86_pmu.event_constraints = intel_v1_event_constraints;
5089 pr_cont("generic architected perfmon v1, ");
5090 name = "generic_arch_v1";
5091 break;
5092 default:
5093 /*
5094 * default constraints for v2 and up
5095 */
5096 x86_pmu.event_constraints = intel_gen_event_constraints;
5097 pr_cont("generic architected perfmon, ");
5098 name = "generic_arch_v2+";
5099 break;
5100 }
5101 }
5102
5103 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
5104
5105
5106 group_events_td.attrs = td_attr;
5107 group_events_mem.attrs = mem_attr;
5108 group_events_tsx.attrs = tsx_attr;
5109 group_format_extra.attrs = extra_attr;
5110 group_format_extra_skl.attrs = extra_skl_attr;
5111
5112 x86_pmu.attr_update = attr_update;
5113
5114 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
5115 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5116 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
5117 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
5118 }
5119 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1;
5120
5121 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5122 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5123 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
5124 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
5125 }
5126
5127 x86_pmu.intel_ctrl |=
5128 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
5129
5130 if (x86_pmu.event_constraints) {
5131 /*
5132 * event on fixed counter2 (REF_CYCLES) only works on this
5133 * counter, so do not extend mask to generic counters
5134 */
5135 for_each_event_constraint(c, x86_pmu.event_constraints) {
5136 if (c->cmask == FIXED_EVENT_FLAGS
5137 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
5138 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
5139 }
5140 c->idxmsk64 &=
5141 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
5142 c->weight = hweight64(c->idxmsk64);
5143 }
5144 }
5145
5146 /*
5147 * Access LBR MSR may cause #GP under certain circumstances.
5148 * E.g. KVM doesn't support LBR MSR
5149 * Check all LBT MSR here.
5150 * Disable LBR access if any LBR MSRs can not be accessed.
5151 */
5152 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
5153 x86_pmu.lbr_nr = 0;
5154 for (i = 0; i < x86_pmu.lbr_nr; i++) {
5155 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
5156 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
5157 x86_pmu.lbr_nr = 0;
5158 }
5159
5160 if (x86_pmu.lbr_nr)
5161 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
5162
5163 /*
5164 * Access extra MSR may cause #GP under certain circumstances.
5165 * E.g. KVM doesn't support offcore event
5166 * Check all extra_regs here.
5167 */
5168 if (x86_pmu.extra_regs) {
5169 for (er = x86_pmu.extra_regs; er->msr; er++) {
5170 er->extra_msr_access = check_msr(er->msr, 0x11UL);
5171 /* Disable LBR select mapping */
5172 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5173 x86_pmu.lbr_sel_map = NULL;
5174 }
5175 }
5176
5177 /* Support full width counters using alternative MSR range */
5178 if (x86_pmu.intel_cap.full_width_write) {
5179 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
5180 x86_pmu.perfctr = MSR_IA32_PMC0;
5181 pr_cont("full-width counters, ");
5182 }
5183
5184 /*
5185 * For arch perfmon 4 use counter freezing to avoid
5186 * several MSR accesses in the PMI.
5187 */
5188 if (x86_pmu.counter_freezing)
5189 x86_pmu.handle_irq = intel_pmu_handle_irq_v4;
5190
5191 return 0;
5192 }
5193
5194 /*
5195 * HT bug: phase 2 init
5196 * Called once we have valid topology information to check
5197 * whether or not HT is enabled
5198 * If HT is off, then we disable the workaround
5199 */
5200 static __init int fixup_ht_bug(void)
5201 {
5202 int c;
5203 /*
5204 * problem not present on this CPU model, nothing to do
5205 */
5206 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
5207 return 0;
5208
5209 if (topology_max_smt_threads() > 1) {
5210 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
5211 return 0;
5212 }
5213
5214 cpus_read_lock();
5215
5216 hardlockup_detector_perf_stop();
5217
5218 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
5219
5220 x86_pmu.start_scheduling = NULL;
5221 x86_pmu.commit_scheduling = NULL;
5222 x86_pmu.stop_scheduling = NULL;
5223
5224 hardlockup_detector_perf_restart();
5225
5226 for_each_online_cpu(c)
5227 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
5228
5229 cpus_read_unlock();
5230 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
5231 return 0;
5232 }
5233 subsys_initcall(fixup_ht_bug)
Linux with added FPC-III support