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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / amd / display / dc / bios / bios_parser2.c
blob2f1c9584ac32d5c03cd999a50fdf69cc52dffc4b
1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "ObjectID.h"
31 #include "atomfirmware.h"
32
33 #include "dc_bios_types.h"
34 #include "include/grph_object_ctrl_defs.h"
35 #include "include/bios_parser_interface.h"
36 #include "include/i2caux_interface.h"
37 #include "include/logger_interface.h"
38
39 #include "command_table2.h"
40
41 #include "bios_parser_helper.h"
42 #include "command_table_helper2.h"
43 #include "bios_parser2.h"
44 #include "bios_parser_types_internal2.h"
45 #include "bios_parser_interface.h"
46
47 #include "bios_parser_common.h"
48
49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */
50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT
51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05
52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */
53
54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1
55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \
56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */
60
61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2
62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \
63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */
67
68 #define DC_LOGGER \
69 bp->base.ctx->logger
70
71 #define LAST_RECORD_TYPE 0xff
72 #define SMU9_SYSPLL0_ID 0
73
74 struct i2c_id_config_access {
75 uint8_t bfI2C_LineMux:4;
76 uint8_t bfHW_EngineID:3;
77 uint8_t bfHW_Capable:1;
78 uint8_t ucAccess;
79 };
80
81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
82 struct atom_i2c_record *record,
83 struct graphics_object_i2c_info *info);
84
85 static enum bp_result bios_parser_get_firmware_info(
86 struct dc_bios *dcb,
87 struct dc_firmware_info *info);
88
89 static enum bp_result bios_parser_get_encoder_cap_info(
90 struct dc_bios *dcb,
91 struct graphics_object_id object_id,
92 struct bp_encoder_cap_info *info);
93
94 static enum bp_result get_firmware_info_v3_1(
95 struct bios_parser *bp,
96 struct dc_firmware_info *info);
97
98 static enum bp_result get_firmware_info_v3_2(
99 struct bios_parser *bp,
100 struct dc_firmware_info *info);
101
102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
103 struct atom_display_object_path_v2 *object);
104
105 static struct atom_encoder_caps_record *get_encoder_cap_record(
106 struct bios_parser *bp,
107 struct atom_display_object_path_v2 *object);
108
109 #define BIOS_IMAGE_SIZE_OFFSET 2
110 #define BIOS_IMAGE_SIZE_UNIT 512
111
112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
113
114 static void bios_parser2_destruct(struct bios_parser *bp)
115 {
116 kfree(bp->base.bios_local_image);
117 kfree(bp->base.integrated_info);
118 }
119
120 static void firmware_parser_destroy(struct dc_bios **dcb)
121 {
122 struct bios_parser *bp = BP_FROM_DCB(*dcb);
123
124 if (!bp) {
125 BREAK_TO_DEBUGGER();
126 return;
127 }
128
129 bios_parser2_destruct(bp);
130
131 kfree(bp);
132 *dcb = NULL;
133 }
134
135 static void get_atom_data_table_revision(
136 struct atom_common_table_header *atom_data_tbl,
137 struct atom_data_revision *tbl_revision)
138 {
139 if (!tbl_revision)
140 return;
141
142 /* initialize the revision to 0 which is invalid revision */
143 tbl_revision->major = 0;
144 tbl_revision->minor = 0;
145
146 if (!atom_data_tbl)
147 return;
148
149 tbl_revision->major =
150 (uint32_t) atom_data_tbl->format_revision & 0x3f;
151 tbl_revision->minor =
152 (uint32_t) atom_data_tbl->content_revision & 0x3f;
153 }
154
155 /* BIOS oject table displaypath is per connector.
156 * There is extra path not for connector. BIOS fill its encoderid as 0
157 */
158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
159 {
160 struct bios_parser *bp = BP_FROM_DCB(dcb);
161 unsigned int count = 0;
162 unsigned int i;
163
164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
166 count++;
167 }
168 return count;
169 }
170
171 static struct graphics_object_id bios_parser_get_connector_id(
172 struct dc_bios *dcb,
173 uint8_t i)
174 {
175 struct bios_parser *bp = BP_FROM_DCB(dcb);
176 struct graphics_object_id object_id = dal_graphics_object_id_init(
177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
178 struct object_info_table *tbl = &bp->object_info_tbl;
179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
180
181 if (v1_4->number_of_path > i) {
182 /* If display_objid is generic object id, the encoderObj
183 * /extencoderobjId should be 0
184 */
185 if (v1_4->display_path[i].encoderobjid != 0 &&
186 v1_4->display_path[i].display_objid != 0)
187 object_id = object_id_from_bios_object_id(
188 v1_4->display_path[i].display_objid);
189 }
190
191 return object_id;
192 }
193
194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
195 struct graphics_object_id object_id, uint32_t index,
196 struct graphics_object_id *src_object_id)
197 {
198 struct bios_parser *bp = BP_FROM_DCB(dcb);
199 unsigned int i;
200 enum bp_result bp_result = BP_RESULT_BADINPUT;
201 struct graphics_object_id obj_id = {0};
202 struct object_info_table *tbl = &bp->object_info_tbl;
203
204 if (!src_object_id)
205 return bp_result;
206
207 switch (object_id.type) {
208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
210 */
211 case OBJECT_TYPE_ENCODER:
212 /* TODO: since num of src must be less than 2.
213 * If found in for loop, should break.
214 * DAL2 implementation may be changed too
215 */
216 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
217 obj_id = object_id_from_bios_object_id(
218 tbl->v1_4->display_path[i].encoderobjid);
219 if (object_id.type == obj_id.type &&
220 object_id.id == obj_id.id &&
221 object_id.enum_id ==
222 obj_id.enum_id) {
223 *src_object_id =
224 object_id_from_bios_object_id(0x1100);
225 /* break; */
226 }
227 }
228 bp_result = BP_RESULT_OK;
229 break;
230 case OBJECT_TYPE_CONNECTOR:
231 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
232 obj_id = object_id_from_bios_object_id(
233 tbl->v1_4->display_path[i].display_objid);
234
235 if (object_id.type == obj_id.type &&
236 object_id.id == obj_id.id &&
237 object_id.enum_id == obj_id.enum_id) {
238 *src_object_id =
239 object_id_from_bios_object_id(
240 tbl->v1_4->display_path[i].encoderobjid);
241 /* break; */
242 }
243 }
244 bp_result = BP_RESULT_OK;
245 break;
246 default:
247 break;
248 }
249
250 return bp_result;
251 }
252
253 /* from graphics_object_id, find display path which includes the object_id */
254 static struct atom_display_object_path_v2 *get_bios_object(
255 struct bios_parser *bp,
256 struct graphics_object_id id)
257 {
258 unsigned int i;
259 struct graphics_object_id obj_id = {0};
260
261 switch (id.type) {
262 case OBJECT_TYPE_ENCODER:
263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
264 obj_id = object_id_from_bios_object_id(
265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
266 if (id.type == obj_id.type && id.id == obj_id.id
267 && id.enum_id == obj_id.enum_id)
268 return &bp->object_info_tbl.v1_4->display_path[i];
269 }
270 /* fall through */
271 case OBJECT_TYPE_CONNECTOR:
272 case OBJECT_TYPE_GENERIC:
273 /* Both Generic and Connector Object ID
274 * will be stored on display_objid
275 */
276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
277 obj_id = object_id_from_bios_object_id(
278 bp->object_info_tbl.v1_4->display_path[i].display_objid);
279 if (id.type == obj_id.type && id.id == obj_id.id
280 && id.enum_id == obj_id.enum_id)
281 return &bp->object_info_tbl.v1_4->display_path[i];
282 }
283 /* fall through */
284 default:
285 return NULL;
286 }
287 }
288
289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
290 struct graphics_object_id id,
291 struct graphics_object_i2c_info *info)
292 {
293 uint32_t offset;
294 struct atom_display_object_path_v2 *object;
295 struct atom_common_record_header *header;
296 struct atom_i2c_record *record;
297 struct atom_i2c_record dummy_record = {0};
298 struct bios_parser *bp = BP_FROM_DCB(dcb);
299
300 if (!info)
301 return BP_RESULT_BADINPUT;
302
303 if (id.type == OBJECT_TYPE_GENERIC) {
304 dummy_record.i2c_id = id.id;
305
306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
307 return BP_RESULT_OK;
308 else
309 return BP_RESULT_NORECORD;
310 }
311
312 object = get_bios_object(bp, id);
313
314 if (!object)
315 return BP_RESULT_BADINPUT;
316
317 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
318
319 for (;;) {
320 header = GET_IMAGE(struct atom_common_record_header, offset);
321
322 if (!header)
323 return BP_RESULT_BADBIOSTABLE;
324
325 if (header->record_type == LAST_RECORD_TYPE ||
326 !header->record_size)
327 break;
328
329 if (header->record_type == ATOM_I2C_RECORD_TYPE
330 && sizeof(struct atom_i2c_record) <=
331 header->record_size) {
332 /* get the I2C info */
333 record = (struct atom_i2c_record *) header;
334
335 if (get_gpio_i2c_info(bp, record, info) ==
336 BP_RESULT_OK)
337 return BP_RESULT_OK;
338 }
339
340 offset += header->record_size;
341 }
342
343 return BP_RESULT_NORECORD;
344 }
345
346 static enum bp_result get_gpio_i2c_info(
347 struct bios_parser *bp,
348 struct atom_i2c_record *record,
349 struct graphics_object_i2c_info *info)
350 {
351 struct atom_gpio_pin_lut_v2_1 *header;
352 uint32_t count = 0;
353 unsigned int table_index = 0;
354 bool find_valid = false;
355
356 if (!info)
357 return BP_RESULT_BADINPUT;
358
359 /* get the GPIO_I2C info */
360 if (!DATA_TABLES(gpio_pin_lut))
361 return BP_RESULT_BADBIOSTABLE;
362
363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
364 DATA_TABLES(gpio_pin_lut));
365 if (!header)
366 return BP_RESULT_BADBIOSTABLE;
367
368 if (sizeof(struct atom_common_table_header) +
369 sizeof(struct atom_gpio_pin_assignment) >
370 le16_to_cpu(header->table_header.structuresize))
371 return BP_RESULT_BADBIOSTABLE;
372
373 /* TODO: is version change? */
374 if (header->table_header.content_revision != 1)
375 return BP_RESULT_UNSUPPORTED;
376
377 /* get data count */
378 count = (le16_to_cpu(header->table_header.structuresize)
379 - sizeof(struct atom_common_table_header))
380 / sizeof(struct atom_gpio_pin_assignment);
381
382 for (table_index = 0; table_index < count; table_index++) {
383 if (((record->i2c_id & I2C_HW_CAP) == (
384 header->gpio_pin[table_index].gpio_id &
385 I2C_HW_CAP)) &&
386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) ==
387 (header->gpio_pin[table_index].gpio_id &
388 I2C_HW_ENGINE_ID_MASK)) &&
389 ((record->i2c_id & I2C_HW_LANE_MUX) ==
390 (header->gpio_pin[table_index].gpio_id &
391 I2C_HW_LANE_MUX))) {
392 /* still valid */
393 find_valid = true;
394 break;
395 }
396 }
397
398 /* If we don't find the entry that we are looking for then
399 * we will return BP_Result_BadBiosTable.
400 */
401 if (find_valid == false)
402 return BP_RESULT_BADBIOSTABLE;
403
404 /* get the GPIO_I2C_INFO */
405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
408 info->i2c_slave_address = record->i2c_slave_addr;
409
410 /* TODO: check how to get register offset for en, Y, etc. */
411 info->gpio_info.clk_a_register_index =
412 le16_to_cpu(
413 header->gpio_pin[table_index].data_a_reg_index);
414 info->gpio_info.clk_a_shift =
415 header->gpio_pin[table_index].gpio_bitshift;
416
417 return BP_RESULT_OK;
418 }
419
420 static enum bp_result bios_parser_get_hpd_info(
421 struct dc_bios *dcb,
422 struct graphics_object_id id,
423 struct graphics_object_hpd_info *info)
424 {
425 struct bios_parser *bp = BP_FROM_DCB(dcb);
426 struct atom_display_object_path_v2 *object;
427 struct atom_hpd_int_record *record = NULL;
428
429 if (!info)
430 return BP_RESULT_BADINPUT;
431
432 object = get_bios_object(bp, id);
433
434 if (!object)
435 return BP_RESULT_BADINPUT;
436
437 record = get_hpd_record(bp, object);
438
439 if (record != NULL) {
440 info->hpd_int_gpio_uid = record->pin_id;
441 info->hpd_active = record->plugin_pin_state;
442 return BP_RESULT_OK;
443 }
444
445 return BP_RESULT_NORECORD;
446 }
447
448 static struct atom_hpd_int_record *get_hpd_record(
449 struct bios_parser *bp,
450 struct atom_display_object_path_v2 *object)
451 {
452 struct atom_common_record_header *header;
453 uint32_t offset;
454
455 if (!object) {
456 BREAK_TO_DEBUGGER(); /* Invalid object */
457 return NULL;
458 }
459
460 offset = le16_to_cpu(object->disp_recordoffset)
461 + bp->object_info_tbl_offset;
462
463 for (;;) {
464 header = GET_IMAGE(struct atom_common_record_header, offset);
465
466 if (!header)
467 return NULL;
468
469 if (header->record_type == LAST_RECORD_TYPE ||
470 !header->record_size)
471 break;
472
473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
474 && sizeof(struct atom_hpd_int_record) <=
475 header->record_size)
476 return (struct atom_hpd_int_record *) header;
477
478 offset += header->record_size;
479 }
480
481 return NULL;
482 }
483
484 /**
485 * bios_parser_get_gpio_pin_info
486 * Get GpioPin information of input gpio id
487 *
488 * @param gpio_id, GPIO ID
489 * @param info, GpioPin information structure
490 * @return Bios parser result code
491 * @note
492 * to get the GPIO PIN INFO, we need:
493 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
494 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
495 * to get the registerA offset/mask
496 */
497 static enum bp_result bios_parser_get_gpio_pin_info(
498 struct dc_bios *dcb,
499 uint32_t gpio_id,
500 struct gpio_pin_info *info)
501 {
502 struct bios_parser *bp = BP_FROM_DCB(dcb);
503 struct atom_gpio_pin_lut_v2_1 *header;
504 uint32_t count = 0;
505 uint32_t i = 0;
506
507 if (!DATA_TABLES(gpio_pin_lut))
508 return BP_RESULT_BADBIOSTABLE;
509
510 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
511 DATA_TABLES(gpio_pin_lut));
512 if (!header)
513 return BP_RESULT_BADBIOSTABLE;
514
515 if (sizeof(struct atom_common_table_header) +
516 sizeof(struct atom_gpio_pin_assignment)
517 > le16_to_cpu(header->table_header.structuresize))
518 return BP_RESULT_BADBIOSTABLE;
519
520 if (header->table_header.content_revision != 1)
521 return BP_RESULT_UNSUPPORTED;
522
523 /* Temporary hard code gpio pin info */
524 #if defined(FOR_SIMNOW_BOOT)
525 {
526 struct atom_gpio_pin_assignment gpio_pin[8] = {
527 {0x5db5, 0, 0, 1, 0},
528 {0x5db5, 8, 8, 2, 0},
529 {0x5db5, 0x10, 0x10, 3, 0},
530 {0x5db5, 0x18, 0x14, 4, 0},
531 {0x5db5, 0x1A, 0x18, 5, 0},
532 {0x5db5, 0x1C, 0x1C, 6, 0},
533 };
534
535 count = 6;
536 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin));
537 }
538 #else
539 count = (le16_to_cpu(header->table_header.structuresize)
540 - sizeof(struct atom_common_table_header))
541 / sizeof(struct atom_gpio_pin_assignment);
542 #endif
543 for (i = 0; i < count; ++i) {
544 if (header->gpio_pin[i].gpio_id != gpio_id)
545 continue;
546
547 info->offset =
548 (uint32_t) le16_to_cpu(
549 header->gpio_pin[i].data_a_reg_index);
550 info->offset_y = info->offset + 2;
551 info->offset_en = info->offset + 1;
552 info->offset_mask = info->offset - 1;
553
554 info->mask = (uint32_t) (1 <<
555 header->gpio_pin[i].gpio_bitshift);
556 info->mask_y = info->mask + 2;
557 info->mask_en = info->mask + 1;
558 info->mask_mask = info->mask - 1;
559
560 return BP_RESULT_OK;
561 }
562
563 return BP_RESULT_NORECORD;
564 }
565
566 static struct device_id device_type_from_device_id(uint16_t device_id)
567 {
568
569 struct device_id result_device_id;
570
571 result_device_id.raw_device_tag = device_id;
572
573 switch (device_id) {
574 case ATOM_DISPLAY_LCD1_SUPPORT:
575 result_device_id.device_type = DEVICE_TYPE_LCD;
576 result_device_id.enum_id = 1;
577 break;
578
579 case ATOM_DISPLAY_DFP1_SUPPORT:
580 result_device_id.device_type = DEVICE_TYPE_DFP;
581 result_device_id.enum_id = 1;
582 break;
583
584 case ATOM_DISPLAY_DFP2_SUPPORT:
585 result_device_id.device_type = DEVICE_TYPE_DFP;
586 result_device_id.enum_id = 2;
587 break;
588
589 case ATOM_DISPLAY_DFP3_SUPPORT:
590 result_device_id.device_type = DEVICE_TYPE_DFP;
591 result_device_id.enum_id = 3;
592 break;
593
594 case ATOM_DISPLAY_DFP4_SUPPORT:
595 result_device_id.device_type = DEVICE_TYPE_DFP;
596 result_device_id.enum_id = 4;
597 break;
598
599 case ATOM_DISPLAY_DFP5_SUPPORT:
600 result_device_id.device_type = DEVICE_TYPE_DFP;
601 result_device_id.enum_id = 5;
602 break;
603
604 case ATOM_DISPLAY_DFP6_SUPPORT:
605 result_device_id.device_type = DEVICE_TYPE_DFP;
606 result_device_id.enum_id = 6;
607 break;
608
609 default:
610 BREAK_TO_DEBUGGER(); /* Invalid device Id */
611 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
612 result_device_id.enum_id = 0;
613 }
614 return result_device_id;
615 }
616
617 static enum bp_result bios_parser_get_device_tag(
618 struct dc_bios *dcb,
619 struct graphics_object_id connector_object_id,
620 uint32_t device_tag_index,
621 struct connector_device_tag_info *info)
622 {
623 struct bios_parser *bp = BP_FROM_DCB(dcb);
624 struct atom_display_object_path_v2 *object;
625
626 if (!info)
627 return BP_RESULT_BADINPUT;
628
629 /* getBiosObject will return MXM object */
630 object = get_bios_object(bp, connector_object_id);
631
632 if (!object) {
633 BREAK_TO_DEBUGGER(); /* Invalid object id */
634 return BP_RESULT_BADINPUT;
635 }
636
637 info->acpi_device = 0; /* BIOS no longer provides this */
638 info->dev_id = device_type_from_device_id(object->device_tag);
639
640 return BP_RESULT_OK;
641 }
642
643 static enum bp_result get_ss_info_v4_1(
644 struct bios_parser *bp,
645 uint32_t id,
646 uint32_t index,
647 struct spread_spectrum_info *ss_info)
648 {
649 enum bp_result result = BP_RESULT_OK;
650 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
651 struct atom_smu_info_v3_3 *smu_info = NULL;
652
653 if (!ss_info)
654 return BP_RESULT_BADINPUT;
655
656 if (!DATA_TABLES(dce_info))
657 return BP_RESULT_BADBIOSTABLE;
658
659 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
660 DATA_TABLES(dce_info));
661 if (!disp_cntl_tbl)
662 return BP_RESULT_BADBIOSTABLE;
663
664
665 ss_info->type.STEP_AND_DELAY_INFO = false;
666 ss_info->spread_percentage_divider = 1000;
667 /* BIOS no longer uses target clock. Always enable for now */
668 ss_info->target_clock_range = 0xffffffff;
669
670 switch (id) {
671 case AS_SIGNAL_TYPE_DVI:
672 ss_info->spread_spectrum_percentage =
673 disp_cntl_tbl->dvi_ss_percentage;
674 ss_info->spread_spectrum_range =
675 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
676 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
677 ss_info->type.CENTER_MODE = true;
678 break;
679 case AS_SIGNAL_TYPE_HDMI:
680 ss_info->spread_spectrum_percentage =
681 disp_cntl_tbl->hdmi_ss_percentage;
682 ss_info->spread_spectrum_range =
683 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
684 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
685 ss_info->type.CENTER_MODE = true;
686 break;
687 /* TODO LVDS not support anymore? */
688 case AS_SIGNAL_TYPE_DISPLAY_PORT:
689 ss_info->spread_spectrum_percentage =
690 disp_cntl_tbl->dp_ss_percentage;
691 ss_info->spread_spectrum_range =
692 disp_cntl_tbl->dp_ss_rate_10hz * 10;
693 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
694 ss_info->type.CENTER_MODE = true;
695 break;
696 case AS_SIGNAL_TYPE_GPU_PLL:
697 /* atom_firmware: DAL only get data from dce_info table.
698 * if data within smu_info is needed for DAL, VBIOS should
699 * copy it into dce_info
700 */
701 result = BP_RESULT_UNSUPPORTED;
702 break;
703 case AS_SIGNAL_TYPE_XGMI:
704 smu_info = GET_IMAGE(struct atom_smu_info_v3_3,
705 DATA_TABLES(smu_info));
706 if (!smu_info)
707 return BP_RESULT_BADBIOSTABLE;
708
709 ss_info->spread_spectrum_percentage =
710 smu_info->waflclk_ss_percentage;
711 ss_info->spread_spectrum_range =
712 smu_info->gpuclk_ss_rate_10hz * 10;
713 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
714 ss_info->type.CENTER_MODE = true;
715 break;
716 default:
717 result = BP_RESULT_UNSUPPORTED;
718 }
719
720 return result;
721 }
722
723 static enum bp_result get_ss_info_v4_2(
724 struct bios_parser *bp,
725 uint32_t id,
726 uint32_t index,
727 struct spread_spectrum_info *ss_info)
728 {
729 enum bp_result result = BP_RESULT_OK;
730 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
731 struct atom_smu_info_v3_1 *smu_info = NULL;
732
733 if (!ss_info)
734 return BP_RESULT_BADINPUT;
735
736 if (!DATA_TABLES(dce_info))
737 return BP_RESULT_BADBIOSTABLE;
738
739 if (!DATA_TABLES(smu_info))
740 return BP_RESULT_BADBIOSTABLE;
741
742 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
743 DATA_TABLES(dce_info));
744 if (!disp_cntl_tbl)
745 return BP_RESULT_BADBIOSTABLE;
746
747 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
748 if (!smu_info)
749 return BP_RESULT_BADBIOSTABLE;
750
751 ss_info->type.STEP_AND_DELAY_INFO = false;
752 ss_info->spread_percentage_divider = 1000;
753 /* BIOS no longer uses target clock. Always enable for now */
754 ss_info->target_clock_range = 0xffffffff;
755
756 switch (id) {
757 case AS_SIGNAL_TYPE_DVI:
758 ss_info->spread_spectrum_percentage =
759 disp_cntl_tbl->dvi_ss_percentage;
760 ss_info->spread_spectrum_range =
761 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
762 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
763 ss_info->type.CENTER_MODE = true;
764 break;
765 case AS_SIGNAL_TYPE_HDMI:
766 ss_info->spread_spectrum_percentage =
767 disp_cntl_tbl->hdmi_ss_percentage;
768 ss_info->spread_spectrum_range =
769 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
770 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
771 ss_info->type.CENTER_MODE = true;
772 break;
773 /* TODO LVDS not support anymore? */
774 case AS_SIGNAL_TYPE_DISPLAY_PORT:
775 ss_info->spread_spectrum_percentage =
776 smu_info->gpuclk_ss_percentage;
777 ss_info->spread_spectrum_range =
778 smu_info->gpuclk_ss_rate_10hz * 10;
779 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
780 ss_info->type.CENTER_MODE = true;
781 break;
782 case AS_SIGNAL_TYPE_GPU_PLL:
783 /* atom_firmware: DAL only get data from dce_info table.
784 * if data within smu_info is needed for DAL, VBIOS should
785 * copy it into dce_info
786 */
787 result = BP_RESULT_UNSUPPORTED;
788 break;
789 default:
790 result = BP_RESULT_UNSUPPORTED;
791 }
792
793 return result;
794 }
795
796 /**
797 * bios_parser_get_spread_spectrum_info
798 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
799 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
800 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
801 * ver 3.1,
802 * there is only one entry for each signal /ss id. However, there is
803 * no planning of supporting multiple spread Sprectum entry for EverGreen
804 * @param [in] this
805 * @param [in] signal, ASSignalType to be converted to info index
806 * @param [in] index, number of entries that match the converted info index
807 * @param [out] ss_info, sprectrum information structure,
808 * @return Bios parser result code
809 */
810 static enum bp_result bios_parser_get_spread_spectrum_info(
811 struct dc_bios *dcb,
812 enum as_signal_type signal,
813 uint32_t index,
814 struct spread_spectrum_info *ss_info)
815 {
816 struct bios_parser *bp = BP_FROM_DCB(dcb);
817 enum bp_result result = BP_RESULT_UNSUPPORTED;
818 struct atom_common_table_header *header;
819 struct atom_data_revision tbl_revision;
820
821 if (!ss_info) /* check for bad input */
822 return BP_RESULT_BADINPUT;
823
824 if (!DATA_TABLES(dce_info))
825 return BP_RESULT_UNSUPPORTED;
826
827 header = GET_IMAGE(struct atom_common_table_header,
828 DATA_TABLES(dce_info));
829 get_atom_data_table_revision(header, &tbl_revision);
830
831 switch (tbl_revision.major) {
832 case 4:
833 switch (tbl_revision.minor) {
834 case 1:
835 return get_ss_info_v4_1(bp, signal, index, ss_info);
836 case 2:
837 case 3:
838 return get_ss_info_v4_2(bp, signal, index, ss_info);
839 default:
840 break;
841 }
842 break;
843 default:
844 break;
845 }
846 /* there can not be more then one entry for SS Info table */
847 return result;
848 }
849
850 static enum bp_result get_embedded_panel_info_v2_1(
851 struct bios_parser *bp,
852 struct embedded_panel_info *info)
853 {
854 struct lcd_info_v2_1 *lvds;
855
856 if (!info)
857 return BP_RESULT_BADINPUT;
858
859 if (!DATA_TABLES(lcd_info))
860 return BP_RESULT_UNSUPPORTED;
861
862 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
863
864 if (!lvds)
865 return BP_RESULT_BADBIOSTABLE;
866
867 /* TODO: previous vv1_3, should v2_1 */
868 if (!((lvds->table_header.format_revision == 2)
869 && (lvds->table_header.content_revision >= 1)))
870 return BP_RESULT_UNSUPPORTED;
871
872 memset(info, 0, sizeof(struct embedded_panel_info));
873
874 /* We need to convert from 10KHz units into KHz units */
875 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
876 /* usHActive does not include borders, according to VBIOS team */
877 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
878 /* usHBlanking_Time includes borders, so we should really be
879 * subtractingborders duing this translation, but LVDS generally
880 * doesn't have borders, so we should be okay leaving this as is for
881 * now. May need to revisit if we ever have LVDS with borders
882 */
883 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
884 /* usVActive does not include borders, according to VBIOS team*/
885 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
886 /* usVBlanking_Time includes borders, so we should really be
887 * subtracting borders duing this translation, but LVDS generally
888 * doesn't have borders, so we should be okay leaving this as is for
889 * now. May need to revisit if we ever have LVDS with borders
890 */
891 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
892 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
893 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
894 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
895 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
896 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
897 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
898
899 /* not provided by VBIOS */
900 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
901
902 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
903 & ATOM_HSYNC_POLARITY);
904 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
905 & ATOM_VSYNC_POLARITY);
906
907 /* not provided by VBIOS */
908 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
909
910 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
911 & ATOM_H_REPLICATIONBY2);
912 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
913 & ATOM_V_REPLICATIONBY2);
914 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
915 & ATOM_COMPOSITESYNC);
916 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
917
918 /* not provided by VBIOS*/
919 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
920 /* not provided by VBIOS*/
921 info->ss_id = 0;
922
923 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
924
925 return BP_RESULT_OK;
926 }
927
928 static enum bp_result bios_parser_get_embedded_panel_info(
929 struct dc_bios *dcb,
930 struct embedded_panel_info *info)
931 {
932 struct bios_parser
933 *bp = BP_FROM_DCB(dcb);
934 struct atom_common_table_header *header;
935 struct atom_data_revision tbl_revision;
936
937 if (!DATA_TABLES(lcd_info))
938 return BP_RESULT_FAILURE;
939
940 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
941
942 if (!header)
943 return BP_RESULT_BADBIOSTABLE;
944
945 get_atom_data_table_revision(header, &tbl_revision);
946
947 switch (tbl_revision.major) {
948 case 2:
949 switch (tbl_revision.minor) {
950 case 1:
951 return get_embedded_panel_info_v2_1(bp, info);
952 default:
953 break;
954 }
955 default:
956 break;
957 }
958
959 return BP_RESULT_FAILURE;
960 }
961
962 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
963 {
964 enum dal_device_type device_type = device_id.device_type;
965 uint32_t enum_id = device_id.enum_id;
966
967 switch (device_type) {
968 case DEVICE_TYPE_LCD:
969 switch (enum_id) {
970 case 1:
971 return ATOM_DISPLAY_LCD1_SUPPORT;
972 default:
973 break;
974 }
975 break;
976 case DEVICE_TYPE_DFP:
977 switch (enum_id) {
978 case 1:
979 return ATOM_DISPLAY_DFP1_SUPPORT;
980 case 2:
981 return ATOM_DISPLAY_DFP2_SUPPORT;
982 case 3:
983 return ATOM_DISPLAY_DFP3_SUPPORT;
984 case 4:
985 return ATOM_DISPLAY_DFP4_SUPPORT;
986 case 5:
987 return ATOM_DISPLAY_DFP5_SUPPORT;
988 case 6:
989 return ATOM_DISPLAY_DFP6_SUPPORT;
990 default:
991 break;
992 }
993 break;
994 default:
995 break;
996 }
997
998 /* Unidentified device ID, return empty support mask. */
999 return 0;
1000 }
1001
1002 static bool bios_parser_is_device_id_supported(
1003 struct dc_bios *dcb,
1004 struct device_id id)
1005 {
1006 struct bios_parser *bp = BP_FROM_DCB(dcb);
1007
1008 uint32_t mask = get_support_mask_for_device_id(id);
1009
1010 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) &
1011 mask) != 0;
1012 }
1013
1014 static uint32_t bios_parser_get_ss_entry_number(
1015 struct dc_bios *dcb,
1016 enum as_signal_type signal)
1017 {
1018 /* TODO: DAL2 atomfirmware implementation does not need this.
1019 * why DAL3 need this?
1020 */
1021 return 1;
1022 }
1023
1024 static enum bp_result bios_parser_transmitter_control(
1025 struct dc_bios *dcb,
1026 struct bp_transmitter_control *cntl)
1027 {
1028 struct bios_parser *bp = BP_FROM_DCB(dcb);
1029
1030 if (!bp->cmd_tbl.transmitter_control)
1031 return BP_RESULT_FAILURE;
1032
1033 return bp->cmd_tbl.transmitter_control(bp, cntl);
1034 }
1035
1036 static enum bp_result bios_parser_encoder_control(
1037 struct dc_bios *dcb,
1038 struct bp_encoder_control *cntl)
1039 {
1040 struct bios_parser *bp = BP_FROM_DCB(dcb);
1041
1042 if (!bp->cmd_tbl.dig_encoder_control)
1043 return BP_RESULT_FAILURE;
1044
1045 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1046 }
1047
1048 static enum bp_result bios_parser_set_pixel_clock(
1049 struct dc_bios *dcb,
1050 struct bp_pixel_clock_parameters *bp_params)
1051 {
1052 struct bios_parser *bp = BP_FROM_DCB(dcb);
1053
1054 if (!bp->cmd_tbl.set_pixel_clock)
1055 return BP_RESULT_FAILURE;
1056
1057 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1058 }
1059
1060 static enum bp_result bios_parser_set_dce_clock(
1061 struct dc_bios *dcb,
1062 struct bp_set_dce_clock_parameters *bp_params)
1063 {
1064 struct bios_parser *bp = BP_FROM_DCB(dcb);
1065
1066 if (!bp->cmd_tbl.set_dce_clock)
1067 return BP_RESULT_FAILURE;
1068
1069 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1070 }
1071
1072 static enum bp_result bios_parser_program_crtc_timing(
1073 struct dc_bios *dcb,
1074 struct bp_hw_crtc_timing_parameters *bp_params)
1075 {
1076 struct bios_parser *bp = BP_FROM_DCB(dcb);
1077
1078 if (!bp->cmd_tbl.set_crtc_timing)
1079 return BP_RESULT_FAILURE;
1080
1081 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1082 }
1083
1084 static enum bp_result bios_parser_enable_crtc(
1085 struct dc_bios *dcb,
1086 enum controller_id id,
1087 bool enable)
1088 {
1089 struct bios_parser *bp = BP_FROM_DCB(dcb);
1090
1091 if (!bp->cmd_tbl.enable_crtc)
1092 return BP_RESULT_FAILURE;
1093
1094 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1095 }
1096
1097 static enum bp_result bios_parser_enable_disp_power_gating(
1098 struct dc_bios *dcb,
1099 enum controller_id controller_id,
1100 enum bp_pipe_control_action action)
1101 {
1102 struct bios_parser *bp = BP_FROM_DCB(dcb);
1103
1104 if (!bp->cmd_tbl.enable_disp_power_gating)
1105 return BP_RESULT_FAILURE;
1106
1107 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1108 action);
1109 }
1110
1111 static bool bios_parser_is_accelerated_mode(
1112 struct dc_bios *dcb)
1113 {
1114 return bios_is_accelerated_mode(dcb);
1115 }
1116
1117 /**
1118 * bios_parser_set_scratch_critical_state
1119 *
1120 * @brief
1121 * update critical state bit in VBIOS scratch register
1122 *
1123 * @param
1124 * bool - to set or reset state
1125 */
1126 static void bios_parser_set_scratch_critical_state(
1127 struct dc_bios *dcb,
1128 bool state)
1129 {
1130 bios_set_scratch_critical_state(dcb, state);
1131 }
1132
1133 static enum bp_result bios_parser_get_firmware_info(
1134 struct dc_bios *dcb,
1135 struct dc_firmware_info *info)
1136 {
1137 struct bios_parser *bp = BP_FROM_DCB(dcb);
1138 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1139 struct atom_common_table_header *header;
1140
1141 struct atom_data_revision revision;
1142
1143 if (info && DATA_TABLES(firmwareinfo)) {
1144 header = GET_IMAGE(struct atom_common_table_header,
1145 DATA_TABLES(firmwareinfo));
1146 get_atom_data_table_revision(header, &revision);
1147 switch (revision.major) {
1148 case 3:
1149 switch (revision.minor) {
1150 case 1:
1151 result = get_firmware_info_v3_1(bp, info);
1152 break;
1153 case 2:
1154 result = get_firmware_info_v3_2(bp, info);
1155 break;
1156 case 3:
1157 result = get_firmware_info_v3_2(bp, info);
1158 break;
1159 default:
1160 break;
1161 }
1162 break;
1163 default:
1164 break;
1165 }
1166 }
1167
1168 return result;
1169 }
1170
1171 static enum bp_result get_firmware_info_v3_1(
1172 struct bios_parser *bp,
1173 struct dc_firmware_info *info)
1174 {
1175 struct atom_firmware_info_v3_1 *firmware_info;
1176 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1177
1178 if (!info)
1179 return BP_RESULT_BADINPUT;
1180
1181 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1182 DATA_TABLES(firmwareinfo));
1183
1184 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1185 DATA_TABLES(dce_info));
1186
1187 if (!firmware_info || !dce_info)
1188 return BP_RESULT_BADBIOSTABLE;
1189
1190 memset(info, 0, sizeof(*info));
1191
1192 /* Pixel clock pll information. */
1193 /* We need to convert from 10KHz units into KHz units */
1194 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1195 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1196
1197 /* 27MHz for Vega10: */
1198 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1199
1200 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1201 if (info->pll_info.crystal_frequency == 0)
1202 info->pll_info.crystal_frequency = 27000;
1203 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1204 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1205 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1206
1207 /* Get GPU PLL VCO Clock */
1208
1209 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1210 /* VBIOS gives in 10KHz */
1211 info->smu_gpu_pll_output_freq =
1212 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1213 }
1214
1215 info->oem_i2c_present = false;
1216
1217 return BP_RESULT_OK;
1218 }
1219
1220 static enum bp_result get_firmware_info_v3_2(
1221 struct bios_parser *bp,
1222 struct dc_firmware_info *info)
1223 {
1224 struct atom_firmware_info_v3_2 *firmware_info;
1225 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1226 struct atom_common_table_header *header;
1227 struct atom_data_revision revision;
1228 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1229 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1230
1231 if (!info)
1232 return BP_RESULT_BADINPUT;
1233
1234 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1235 DATA_TABLES(firmwareinfo));
1236
1237 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1238 DATA_TABLES(dce_info));
1239
1240 if (!firmware_info || !dce_info)
1241 return BP_RESULT_BADBIOSTABLE;
1242
1243 memset(info, 0, sizeof(*info));
1244
1245 header = GET_IMAGE(struct atom_common_table_header,
1246 DATA_TABLES(smu_info));
1247 get_atom_data_table_revision(header, &revision);
1248
1249 if (revision.minor == 2) {
1250 /* Vega12 */
1251 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1252 DATA_TABLES(smu_info));
1253
1254 if (!smu_info_v3_2)
1255 return BP_RESULT_BADBIOSTABLE;
1256
1257 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1258 } else if (revision.minor == 3) {
1259 /* Vega20 */
1260 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1261 DATA_TABLES(smu_info));
1262
1263 if (!smu_info_v3_3)
1264 return BP_RESULT_BADBIOSTABLE;
1265
1266 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1267 }
1268
1269 // We need to convert from 10KHz units into KHz units.
1270 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1271
1272 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1273 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1274 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1275 if (info->pll_info.crystal_frequency == 0) {
1276 if (revision.minor == 2)
1277 info->pll_info.crystal_frequency = 27000;
1278 else if (revision.minor == 3)
1279 info->pll_info.crystal_frequency = 100000;
1280 }
1281 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1282 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1283 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1284
1285 /* Get GPU PLL VCO Clock */
1286 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1287 if (revision.minor == 2)
1288 info->smu_gpu_pll_output_freq =
1289 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1290 else if (revision.minor == 3)
1291 info->smu_gpu_pll_output_freq =
1292 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1293 }
1294
1295 if (firmware_info->board_i2c_feature_id == 0x2) {
1296 info->oem_i2c_present = true;
1297 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1298 } else {
1299 info->oem_i2c_present = false;
1300 }
1301
1302 return BP_RESULT_OK;
1303 }
1304
1305 static enum bp_result bios_parser_get_encoder_cap_info(
1306 struct dc_bios *dcb,
1307 struct graphics_object_id object_id,
1308 struct bp_encoder_cap_info *info)
1309 {
1310 struct bios_parser *bp = BP_FROM_DCB(dcb);
1311 struct atom_display_object_path_v2 *object;
1312 struct atom_encoder_caps_record *record = NULL;
1313
1314 if (!info)
1315 return BP_RESULT_BADINPUT;
1316
1317 object = get_bios_object(bp, object_id);
1318
1319 if (!object)
1320 return BP_RESULT_BADINPUT;
1321
1322 record = get_encoder_cap_record(bp, object);
1323 if (!record)
1324 return BP_RESULT_NORECORD;
1325
1326 info->DP_HBR2_CAP = (record->encodercaps &
1327 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
1328 info->DP_HBR2_EN = (record->encodercaps &
1329 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
1330 info->DP_HBR3_EN = (record->encodercaps &
1331 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
1332 info->HDMI_6GB_EN = (record->encodercaps &
1333 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
1334 info->DP_IS_USB_C = (record->encodercaps &
1335 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
1336
1337 return BP_RESULT_OK;
1338 }
1339
1340
1341 static struct atom_encoder_caps_record *get_encoder_cap_record(
1342 struct bios_parser *bp,
1343 struct atom_display_object_path_v2 *object)
1344 {
1345 struct atom_common_record_header *header;
1346 uint32_t offset;
1347
1348 if (!object) {
1349 BREAK_TO_DEBUGGER(); /* Invalid object */
1350 return NULL;
1351 }
1352
1353 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
1354
1355 for (;;) {
1356 header = GET_IMAGE(struct atom_common_record_header, offset);
1357
1358 if (!header)
1359 return NULL;
1360
1361 offset += header->record_size;
1362
1363 if (header->record_type == LAST_RECORD_TYPE ||
1364 !header->record_size)
1365 break;
1366
1367 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
1368 continue;
1369
1370 if (sizeof(struct atom_encoder_caps_record) <=
1371 header->record_size)
1372 return (struct atom_encoder_caps_record *)header;
1373 }
1374
1375 return NULL;
1376 }
1377
1378 /*
1379 * get_integrated_info_v11
1380 *
1381 * @brief
1382 * Get V8 integrated BIOS information
1383 *
1384 * @param
1385 * bios_parser *bp - [in]BIOS parser handler to get master data table
1386 * integrated_info *info - [out] store and output integrated info
1387 *
1388 * @return
1389 * enum bp_result - BP_RESULT_OK if information is available,
1390 * BP_RESULT_BADBIOSTABLE otherwise.
1391 */
1392 static enum bp_result get_integrated_info_v11(
1393 struct bios_parser *bp,
1394 struct integrated_info *info)
1395 {
1396 struct atom_integrated_system_info_v1_11 *info_v11;
1397 uint32_t i;
1398
1399 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
1400 DATA_TABLES(integratedsysteminfo));
1401
1402 if (info_v11 == NULL)
1403 return BP_RESULT_BADBIOSTABLE;
1404
1405 info->gpu_cap_info =
1406 le32_to_cpu(info_v11->gpucapinfo);
1407 /*
1408 * system_config: Bit[0] = 0 : PCIE power gating disabled
1409 * = 1 : PCIE power gating enabled
1410 * Bit[1] = 0 : DDR-PLL shut down disabled
1411 * = 1 : DDR-PLL shut down enabled
1412 * Bit[2] = 0 : DDR-PLL power down disabled
1413 * = 1 : DDR-PLL power down enabled
1414 */
1415 info->system_config = le32_to_cpu(info_v11->system_config);
1416 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
1417 info->memory_type = info_v11->memorytype;
1418 info->ma_channel_number = info_v11->umachannelnumber;
1419 info->lvds_ss_percentage =
1420 le16_to_cpu(info_v11->lvds_ss_percentage);
1421 info->dp_ss_control =
1422 le16_to_cpu(info_v11->reserved1);
1423 info->lvds_sspread_rate_in_10hz =
1424 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
1425 info->hdmi_ss_percentage =
1426 le16_to_cpu(info_v11->hdmi_ss_percentage);
1427 info->hdmi_sspread_rate_in_10hz =
1428 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
1429 info->dvi_ss_percentage =
1430 le16_to_cpu(info_v11->dvi_ss_percentage);
1431 info->dvi_sspread_rate_in_10_hz =
1432 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
1433 info->lvds_misc = info_v11->lvds_misc;
1434 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
1435 info->ext_disp_conn_info.gu_id[i] =
1436 info_v11->extdispconninfo.guid[i];
1437 }
1438
1439 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
1440 info->ext_disp_conn_info.path[i].device_connector_id =
1441 object_id_from_bios_object_id(
1442 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
1443
1444 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
1445 object_id_from_bios_object_id(
1446 le16_to_cpu(
1447 info_v11->extdispconninfo.path[i].ext_encoder_objid));
1448
1449 info->ext_disp_conn_info.path[i].device_tag =
1450 le16_to_cpu(
1451 info_v11->extdispconninfo.path[i].device_tag);
1452 info->ext_disp_conn_info.path[i].device_acpi_enum =
1453 le16_to_cpu(
1454 info_v11->extdispconninfo.path[i].device_acpi_enum);
1455 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
1456 info_v11->extdispconninfo.path[i].auxddclut_index;
1457 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
1458 info_v11->extdispconninfo.path[i].hpdlut_index;
1459 info->ext_disp_conn_info.path[i].channel_mapping.raw =
1460 info_v11->extdispconninfo.path[i].channelmapping;
1461 info->ext_disp_conn_info.path[i].caps =
1462 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
1463 }
1464 info->ext_disp_conn_info.checksum =
1465 info_v11->extdispconninfo.checksum;
1466
1467 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
1468 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
1469 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
1470 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
1471 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1472 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
1473 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1474 }
1475 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
1476 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
1477 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1478 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1479 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1480 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1481 }
1482
1483 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
1484 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
1485 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
1486 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
1487 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1488 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
1489 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1490 }
1491 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
1492 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
1493 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1494 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1495 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1496 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1497 }
1498
1499 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
1500 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
1501 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
1502 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
1503 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1504 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
1505 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1506 }
1507 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
1508 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
1509 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1510 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1511 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1512 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1513 }
1514
1515 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
1516 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
1517 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
1518 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
1519 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1520 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
1521 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1522 }
1523 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
1524 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
1525 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1526 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1527 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1528 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1529 }
1530
1531
1532 /** TODO - review **/
1533 #if 0
1534 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
1535 * 10;
1536 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
1537 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
1538
1539 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1540 /* Convert [10KHz] into [KHz] */
1541 info->disp_clk_voltage[i].max_supported_clk =
1542 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
1543 ulMaximumSupportedCLK) * 10;
1544 info->disp_clk_voltage[i].voltage_index =
1545 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
1546 }
1547
1548 info->boot_up_req_display_vector =
1549 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
1550 info->boot_up_nb_voltage =
1551 le16_to_cpu(info_v11->usBootUpNBVoltage);
1552 info->ext_disp_conn_info_offset =
1553 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
1554 info->gmc_restore_reset_time =
1555 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
1556 info->minimum_n_clk =
1557 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
1558 for (i = 1; i < 4; ++i)
1559 info->minimum_n_clk =
1560 info->minimum_n_clk <
1561 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
1562 info->minimum_n_clk : le32_to_cpu(
1563 info_v11->ulNbpStateNClkFreq[i]);
1564
1565 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
1566 info->ddr_dll_power_up_time =
1567 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
1568 info->ddr_pll_power_up_time =
1569 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
1570 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
1571 info->max_lvds_pclk_freq_in_single_link =
1572 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1573 info->max_lvds_pclk_freq_in_single_link =
1574 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1575 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
1576 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
1577 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
1578 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
1579 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
1580 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
1581 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
1582 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
1583 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
1584 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
1585 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
1586 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
1587 info->lvds_off_to_on_delay_in_4ms =
1588 info_v11->ucLVDSOffToOnDelay_in4Ms;
1589 info->lvds_bit_depth_control_val =
1590 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
1591
1592 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
1593 /* Convert [10KHz] into [KHz] */
1594 info->avail_s_clk[i].supported_s_clk =
1595 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
1596 * 10;
1597 info->avail_s_clk[i].voltage_index =
1598 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
1599 info->avail_s_clk[i].voltage_id =
1600 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
1601 }
1602 #endif /* TODO*/
1603
1604 return BP_RESULT_OK;
1605 }
1606
1607
1608 /*
1609 * construct_integrated_info
1610 *
1611 * @brief
1612 * Get integrated BIOS information based on table revision
1613 *
1614 * @param
1615 * bios_parser *bp - [in]BIOS parser handler to get master data table
1616 * integrated_info *info - [out] store and output integrated info
1617 *
1618 * @return
1619 * enum bp_result - BP_RESULT_OK if information is available,
1620 * BP_RESULT_BADBIOSTABLE otherwise.
1621 */
1622 static enum bp_result construct_integrated_info(
1623 struct bios_parser *bp,
1624 struct integrated_info *info)
1625 {
1626 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1627
1628 struct atom_common_table_header *header;
1629 struct atom_data_revision revision;
1630 uint32_t i;
1631 uint32_t j;
1632
1633 if (info && DATA_TABLES(integratedsysteminfo)) {
1634 header = GET_IMAGE(struct atom_common_table_header,
1635 DATA_TABLES(integratedsysteminfo));
1636
1637 get_atom_data_table_revision(header, &revision);
1638
1639 /* Don't need to check major revision as they are all 1 */
1640 switch (revision.minor) {
1641 case 11:
1642 case 12:
1643 result = get_integrated_info_v11(bp, info);
1644 break;
1645 default:
1646 return result;
1647 }
1648 }
1649
1650 if (result != BP_RESULT_OK)
1651 return result;
1652
1653 /* Sort voltage table from low to high*/
1654 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1655 for (j = i; j > 0; --j) {
1656 if (info->disp_clk_voltage[j].max_supported_clk <
1657 info->disp_clk_voltage[j-1].max_supported_clk
1658 ) {
1659 /* swap j and j - 1*/
1660 swap(info->disp_clk_voltage[j - 1],
1661 info->disp_clk_voltage[j]);
1662 }
1663 }
1664 }
1665
1666 return result;
1667 }
1668
1669 static struct integrated_info *bios_parser_create_integrated_info(
1670 struct dc_bios *dcb)
1671 {
1672 struct bios_parser *bp = BP_FROM_DCB(dcb);
1673 struct integrated_info *info = NULL;
1674
1675 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
1676
1677 if (info == NULL) {
1678 ASSERT_CRITICAL(0);
1679 return NULL;
1680 }
1681
1682 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
1683 return info;
1684
1685 kfree(info);
1686
1687 return NULL;
1688 }
1689
1690 static enum bp_result update_slot_layout_info(
1691 struct dc_bios *dcb,
1692 unsigned int i,
1693 struct slot_layout_info *slot_layout_info)
1694 {
1695 unsigned int record_offset;
1696 unsigned int j;
1697 struct atom_display_object_path_v2 *object;
1698 struct atom_bracket_layout_record *record;
1699 struct atom_common_record_header *record_header;
1700 enum bp_result result;
1701 struct bios_parser *bp;
1702 struct object_info_table *tbl;
1703 struct display_object_info_table_v1_4 *v1_4;
1704
1705 record = NULL;
1706 record_header = NULL;
1707 result = BP_RESULT_NORECORD;
1708
1709 bp = BP_FROM_DCB(dcb);
1710 tbl = &bp->object_info_tbl;
1711 v1_4 = tbl->v1_4;
1712
1713 object = &v1_4->display_path[i];
1714 record_offset = (unsigned int)
1715 (object->disp_recordoffset) +
1716 (unsigned int)(bp->object_info_tbl_offset);
1717
1718 for (;;) {
1719
1720 record_header = (struct atom_common_record_header *)
1721 GET_IMAGE(struct atom_common_record_header,
1722 record_offset);
1723 if (record_header == NULL) {
1724 result = BP_RESULT_BADBIOSTABLE;
1725 break;
1726 }
1727
1728 /* the end of the list */
1729 if (record_header->record_type == 0xff ||
1730 record_header->record_size == 0) {
1731 break;
1732 }
1733
1734 if (record_header->record_type ==
1735 ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
1736 sizeof(struct atom_bracket_layout_record)
1737 <= record_header->record_size) {
1738 record = (struct atom_bracket_layout_record *)
1739 (record_header);
1740 result = BP_RESULT_OK;
1741 break;
1742 }
1743
1744 record_offset += record_header->record_size;
1745 }
1746
1747 /* return if the record not found */
1748 if (result != BP_RESULT_OK)
1749 return result;
1750
1751 /* get slot sizes */
1752 slot_layout_info->length = record->bracketlen;
1753 slot_layout_info->width = record->bracketwidth;
1754
1755 /* get info for each connector in the slot */
1756 slot_layout_info->num_of_connectors = record->conn_num;
1757 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
1758 slot_layout_info->connectors[j].connector_type =
1759 (enum connector_layout_type)
1760 (record->conn_info[j].connector_type);
1761 switch (record->conn_info[j].connector_type) {
1762 case CONNECTOR_TYPE_DVI_D:
1763 slot_layout_info->connectors[j].connector_type =
1764 CONNECTOR_LAYOUT_TYPE_DVI_D;
1765 slot_layout_info->connectors[j].length =
1766 CONNECTOR_SIZE_DVI;
1767 break;
1768
1769 case CONNECTOR_TYPE_HDMI:
1770 slot_layout_info->connectors[j].connector_type =
1771 CONNECTOR_LAYOUT_TYPE_HDMI;
1772 slot_layout_info->connectors[j].length =
1773 CONNECTOR_SIZE_HDMI;
1774 break;
1775
1776 case CONNECTOR_TYPE_DISPLAY_PORT:
1777 slot_layout_info->connectors[j].connector_type =
1778 CONNECTOR_LAYOUT_TYPE_DP;
1779 slot_layout_info->connectors[j].length =
1780 CONNECTOR_SIZE_DP;
1781 break;
1782
1783 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
1784 slot_layout_info->connectors[j].connector_type =
1785 CONNECTOR_LAYOUT_TYPE_MINI_DP;
1786 slot_layout_info->connectors[j].length =
1787 CONNECTOR_SIZE_MINI_DP;
1788 break;
1789
1790 default:
1791 slot_layout_info->connectors[j].connector_type =
1792 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
1793 slot_layout_info->connectors[j].length =
1794 CONNECTOR_SIZE_UNKNOWN;
1795 }
1796
1797 slot_layout_info->connectors[j].position =
1798 record->conn_info[j].position;
1799 slot_layout_info->connectors[j].connector_id =
1800 object_id_from_bios_object_id(
1801 record->conn_info[j].connectorobjid);
1802 }
1803 return result;
1804 }
1805
1806
1807 static enum bp_result get_bracket_layout_record(
1808 struct dc_bios *dcb,
1809 unsigned int bracket_layout_id,
1810 struct slot_layout_info *slot_layout_info)
1811 {
1812 unsigned int i;
1813 struct bios_parser *bp = BP_FROM_DCB(dcb);
1814 enum bp_result result;
1815 struct object_info_table *tbl;
1816 struct display_object_info_table_v1_4 *v1_4;
1817
1818 if (slot_layout_info == NULL) {
1819 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
1820 return BP_RESULT_BADINPUT;
1821 }
1822 tbl = &bp->object_info_tbl;
1823 v1_4 = tbl->v1_4;
1824
1825 result = BP_RESULT_NORECORD;
1826 for (i = 0; i < v1_4->number_of_path; ++i) {
1827
1828 if (bracket_layout_id ==
1829 v1_4->display_path[i].display_objid) {
1830 result = update_slot_layout_info(dcb, i,
1831 slot_layout_info);
1832 break;
1833 }
1834 }
1835 return result;
1836 }
1837
1838 static enum bp_result bios_get_board_layout_info(
1839 struct dc_bios *dcb,
1840 struct board_layout_info *board_layout_info)
1841 {
1842 unsigned int i;
1843 enum bp_result record_result;
1844
1845 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
1846 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
1847 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
1848 0, 0
1849 };
1850
1851 if (board_layout_info == NULL) {
1852 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
1853 return BP_RESULT_BADINPUT;
1854 }
1855
1856 board_layout_info->num_of_slots = 0;
1857
1858 for (i = 0; i < MAX_BOARD_SLOTS; ++i) {
1859 record_result = get_bracket_layout_record(dcb,
1860 slot_index_to_vbios_id[i],
1861 &board_layout_info->slots[i]);
1862
1863 if (record_result == BP_RESULT_NORECORD && i > 0)
1864 break; /* no more slots present in bios */
1865 else if (record_result != BP_RESULT_OK)
1866 return record_result; /* fail */
1867
1868 ++board_layout_info->num_of_slots;
1869 }
1870
1871 /* all data is valid */
1872 board_layout_info->is_number_of_slots_valid = 1;
1873 board_layout_info->is_slots_size_valid = 1;
1874 board_layout_info->is_connector_offsets_valid = 1;
1875 board_layout_info->is_connector_lengths_valid = 1;
1876
1877 return BP_RESULT_OK;
1878 }
1879
1880 static const struct dc_vbios_funcs vbios_funcs = {
1881 .get_connectors_number = bios_parser_get_connectors_number,
1882
1883 .get_connector_id = bios_parser_get_connector_id,
1884
1885 .get_src_obj = bios_parser_get_src_obj,
1886
1887 .get_i2c_info = bios_parser_get_i2c_info,
1888
1889 .get_hpd_info = bios_parser_get_hpd_info,
1890
1891 .get_device_tag = bios_parser_get_device_tag,
1892
1893 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
1894
1895 .get_ss_entry_number = bios_parser_get_ss_entry_number,
1896
1897 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
1898
1899 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
1900
1901 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
1902
1903 .is_device_id_supported = bios_parser_is_device_id_supported,
1904
1905 .is_accelerated_mode = bios_parser_is_accelerated_mode,
1906
1907 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
1908
1909
1910 /* COMMANDS */
1911 .encoder_control = bios_parser_encoder_control,
1912
1913 .transmitter_control = bios_parser_transmitter_control,
1914
1915 .enable_crtc = bios_parser_enable_crtc,
1916
1917 .set_pixel_clock = bios_parser_set_pixel_clock,
1918
1919 .set_dce_clock = bios_parser_set_dce_clock,
1920
1921 .program_crtc_timing = bios_parser_program_crtc_timing,
1922
1923 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
1924
1925 .bios_parser_destroy = firmware_parser_destroy,
1926
1927 .get_board_layout_info = bios_get_board_layout_info,
1928 };
1929
1930 static bool bios_parser2_construct(
1931 struct bios_parser *bp,
1932 struct bp_init_data *init,
1933 enum dce_version dce_version)
1934 {
1935 uint16_t *rom_header_offset = NULL;
1936 struct atom_rom_header_v2_2 *rom_header = NULL;
1937 struct display_object_info_table_v1_4 *object_info_tbl;
1938 struct atom_data_revision tbl_rev = {0};
1939
1940 if (!init)
1941 return false;
1942
1943 if (!init->bios)
1944 return false;
1945
1946 bp->base.funcs = &vbios_funcs;
1947 bp->base.bios = init->bios;
1948 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
1949
1950 bp->base.ctx = init->ctx;
1951
1952 bp->base.bios_local_image = NULL;
1953
1954 rom_header_offset =
1955 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
1956
1957 if (!rom_header_offset)
1958 return false;
1959
1960 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
1961
1962 if (!rom_header)
1963 return false;
1964
1965 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
1966 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
1967 return false;
1968
1969 bp->master_data_tbl =
1970 GET_IMAGE(struct atom_master_data_table_v2_1,
1971 rom_header->masterdatatable_offset);
1972
1973 if (!bp->master_data_tbl)
1974 return false;
1975
1976 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
1977
1978 if (!bp->object_info_tbl_offset)
1979 return false;
1980
1981 object_info_tbl =
1982 GET_IMAGE(struct display_object_info_table_v1_4,
1983 bp->object_info_tbl_offset);
1984
1985 if (!object_info_tbl)
1986 return false;
1987
1988 get_atom_data_table_revision(&object_info_tbl->table_header,
1989 &bp->object_info_tbl.revision);
1990
1991 if (bp->object_info_tbl.revision.major == 1
1992 && bp->object_info_tbl.revision.minor >= 4) {
1993 struct display_object_info_table_v1_4 *tbl_v1_4;
1994
1995 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
1996 bp->object_info_tbl_offset);
1997 if (!tbl_v1_4)
1998 return false;
1999
2000 bp->object_info_tbl.v1_4 = tbl_v1_4;
2001 } else
2002 return false;
2003
2004 dal_firmware_parser_init_cmd_tbl(bp);
2005 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
2006
2007 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
2008 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
2009
2010 return true;
2011 }
2012
2013 struct dc_bios *firmware_parser_create(
2014 struct bp_init_data *init,
2015 enum dce_version dce_version)
2016 {
2017 struct bios_parser *bp = NULL;
2018
2019 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
2020 if (!bp)
2021 return NULL;
2022
2023 if (bios_parser2_construct(bp, init, dce_version))
2024 return &bp->base;
2025
2026 kfree(bp);
2027 return NULL;
2028 }
2029
2030
Linux with added FPC-III support