1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __DC_CLOCK_SOURCE_DCE_H__
26 #define __DC_CLOCK_SOURCE_DCE_H__
28 #include "../inc/clock_source.h"
30 #define TO_DCE110_CLK_SRC(clk_src)\
31 container_of(clk_src, struct dce110_clk_src, base)
33 #define CS_COMMON_REG_LIST_DCE_100_110(id) \
34 SRI(RESYNC_CNTL, PIXCLK, id), \
35 SRI(PLL_CNTL, BPHYC_PLL, id)
37 #define CS_COMMON_REG_LIST_DCE_80(id) \
38 SRI(RESYNC_CNTL, PIXCLK, id), \
39 SRI(PLL_CNTL, DCCG_PLL, id)
41 #define CS_COMMON_REG_LIST_DCE_112(id) \
42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
45 #define CS_SF(reg_name, field_name, post_fix)\
46 .field_name = reg_name ## __ ## field_name ## post_fix
48 #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
49 CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
50 CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\
51 CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\
52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
54 #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
55 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
56 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
58 #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \
59 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
66 SRII(MODULO, DP_DTO, 0),\
67 SRII(MODULO, DP_DTO, 1),\
68 SRII(MODULO, DP_DTO, 2),\
69 SRII(MODULO, DP_DTO, 3),\
70 SRII(MODULO, DP_DTO, 4),\
71 SRII(MODULO, DP_DTO, 5),\
72 SRII(PIXEL_RATE_CNTL, OTG, 0),\
73 SRII(PIXEL_RATE_CNTL, OTG, 1),\
74 SRII(PIXEL_RATE_CNTL, OTG, 2),\
75 SRII(PIXEL_RATE_CNTL, OTG, 3),\
76 SRII(PIXEL_RATE_CNTL, OTG, 4),\
77 SRII(PIXEL_RATE_CNTL, OTG, 5)
79 #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
80 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
83 SRII(PHASE, DP_DTO, 2),\
84 SRII(PHASE, DP_DTO, 3),\
85 SRII(MODULO, DP_DTO, 0),\
86 SRII(MODULO, DP_DTO, 1),\
87 SRII(MODULO, DP_DTO, 2),\
88 SRII(MODULO, DP_DTO, 3),\
89 SRII(PIXEL_RATE_CNTL, OTG, 0),\
90 SRII(PIXEL_RATE_CNTL, OTG, 1),\
91 SRII(PIXEL_RATE_CNTL, OTG, 2),\
92 SRII(PIXEL_RATE_CNTL, OTG, 3)
94 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
95 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
96 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
97 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
98 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
100 #if defined(CONFIG_DRM_AMD_DC_DCN)
102 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
103 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
104 SRII(PHASE, DP_DTO, 0),\
105 SRII(PHASE, DP_DTO, 1),\
106 SRII(PHASE, DP_DTO, 2),\
107 SRII(PHASE, DP_DTO, 3),\
108 SRII(MODULO, DP_DTO, 0),\
109 SRII(MODULO, DP_DTO, 1),\
110 SRII(MODULO, DP_DTO, 2),\
111 SRII(MODULO, DP_DTO, 3),\
112 SRII(PIXEL_RATE_CNTL, OTG, 0), \
113 SRII(PIXEL_RATE_CNTL, OTG, 1), \
114 SRII(PIXEL_RATE_CNTL, OTG, 2), \
115 SRII(PIXEL_RATE_CNTL, OTG, 3)
117 #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
118 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
119 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
120 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
121 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
125 #define CS_REG_FIELD_LIST(type) \
126 type PLL_REF_DIV_SRC; \
127 type DCCG_DEEP_COLOR_CNTL1; \
128 type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \
129 type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \
130 type PLL_POST_DIV_PIXCLK; \
132 type DP_DTO0_PHASE; \
133 type DP_DTO0_MODULO; \
136 struct dce110_clk_src_shift
{
137 CS_REG_FIELD_LIST(uint8_t)
140 struct dce110_clk_src_mask
{
141 CS_REG_FIELD_LIST(uint32_t)
144 struct dce110_clk_src_regs
{
145 uint32_t RESYNC_CNTL
;
146 uint32_t PIXCLK_RESYNC_CNTL
;
149 /* below are for DTO.
150 * todo: should probably use different struct to not waste space
152 uint32_t PHASE
[MAX_PIPES
];
153 uint32_t MODULO
[MAX_PIPES
];
154 uint32_t PIXEL_RATE_CNTL
[MAX_PIPES
];
157 struct dce110_clk_src
{
158 struct clock_source base
;
159 const struct dce110_clk_src_regs
*regs
;
160 const struct dce110_clk_src_mask
*cs_mask
;
161 const struct dce110_clk_src_shift
*cs_shift
;
162 struct dc_bios
*bios
;
164 struct spread_spectrum_data
*dp_ss_params
;
165 uint32_t dp_ss_params_cnt
;
166 struct spread_spectrum_data
*hdmi_ss_params
;
167 uint32_t hdmi_ss_params_cnt
;
168 struct spread_spectrum_data
*dvi_ss_params
;
169 uint32_t dvi_ss_params_cnt
;
170 struct spread_spectrum_data
*lvds_ss_params
;
171 uint32_t lvds_ss_params_cnt
;
173 uint32_t ext_clk_khz
;
174 uint32_t ref_freq_khz
;
176 struct calc_pll_clock_source calc_pll
;
177 struct calc_pll_clock_source calc_pll_hdmi
;
180 bool dce110_clk_src_construct(
181 struct dce110_clk_src
*clk_src
,
182 struct dc_context
*ctx
,
183 struct dc_bios
*bios
,
184 enum clock_source_id
,
185 const struct dce110_clk_src_regs
*regs
,
186 const struct dce110_clk_src_shift
*cs_shift
,
187 const struct dce110_clk_src_mask
*cs_mask
);
189 bool dce112_clk_src_construct(
190 struct dce110_clk_src
*clk_src
,
191 struct dc_context
*ctx
,
192 struct dc_bios
*bios
,
193 enum clock_source_id id
,
194 const struct dce110_clk_src_regs
*regs
,
195 const struct dce110_clk_src_shift
*cs_shift
,
196 const struct dce110_clk_src_mask
*cs_mask
);
198 bool dcn20_clk_src_construct(
199 struct dce110_clk_src
*clk_src
,
200 struct dc_context
*ctx
,
201 struct dc_bios
*bios
,
202 enum clock_source_id id
,
203 const struct dce110_clk_src_regs
*regs
,
204 const struct dce110_clk_src_shift
*cs_shift
,
205 const struct dce110_clk_src_mask
*cs_mask
);