drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_STREAM_ENCODER_DCN10_H__
  27 #define __DC_STREAM_ENCODER_DCN10_H__
  28
  29 #include "stream_encoder.h"
  30
  31 #define DCN10STRENC_FROM_STRENC(stream_encoder)\
  32         container_of(stream_encoder, struct dcn10_stream_encoder, base)
  33
  34 #define SE_COMMON_DCN_REG_LIST(id) \
  35         SRI(AFMT_CNTL, DIG, id), \
  36         SRI(AFMT_GENERIC_0, DIG, id), \
  37         SRI(AFMT_GENERIC_1, DIG, id), \
  38         SRI(AFMT_GENERIC_2, DIG, id), \
  39         SRI(AFMT_GENERIC_3, DIG, id), \
  40         SRI(AFMT_GENERIC_4, DIG, id), \
  41         SRI(AFMT_GENERIC_5, DIG, id), \
  42         SRI(AFMT_GENERIC_6, DIG, id), \
  43         SRI(AFMT_GENERIC_7, DIG, id), \
  44         SRI(AFMT_GENERIC_HDR, DIG, id), \
  45         SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
  46         SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
  47         SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \
  48         SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
  49         SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
  50         SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
  51         SRI(AFMT_60958_0, DIG, id), \
  52         SRI(AFMT_60958_1, DIG, id), \
  53         SRI(AFMT_60958_2, DIG, id), \
  54         SRI(DIG_FE_CNTL, DIG, id), \
  55         SRI(HDMI_CONTROL, DIG, id), \
  56         SRI(HDMI_DB_CONTROL, DIG, id), \
  57         SRI(HDMI_GC, DIG, id), \
  58         SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
  59         SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
  60         SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
  61         SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
  62         SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
  63         SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
  64         SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
  65         SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
  66         SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
  67         SRI(HDMI_ACR_32_0, DIG, id),\
  68         SRI(HDMI_ACR_32_1, DIG, id),\
  69         SRI(HDMI_ACR_44_0, DIG, id),\
  70         SRI(HDMI_ACR_44_1, DIG, id),\
  71         SRI(HDMI_ACR_48_0, DIG, id),\
  72         SRI(HDMI_ACR_48_1, DIG, id),\
  73         SRI(DP_DB_CNTL, DP, id), \
  74         SRI(DP_MSA_MISC, DP, id), \
  75         SRI(DP_MSA_COLORIMETRY, DP, id), \
  76         SRI(DP_MSA_TIMING_PARAM1, DP, id), \
  77         SRI(DP_MSA_TIMING_PARAM2, DP, id), \
  78         SRI(DP_MSA_TIMING_PARAM3, DP, id), \
  79         SRI(DP_MSA_TIMING_PARAM4, DP, id), \
  80         SRI(DP_MSE_RATE_CNTL, DP, id), \
  81         SRI(DP_MSE_RATE_UPDATE, DP, id), \
  82         SRI(DP_PIXEL_FORMAT, DP, id), \
  83         SRI(DP_SEC_CNTL, DP, id), \
  84         SRI(DP_SEC_CNTL2, DP, id), \
  85         SRI(DP_SEC_CNTL6, DP, id), \
  86         SRI(DP_STEER_FIFO, DP, id), \
  87         SRI(DP_VID_M, DP, id), \
  88         SRI(DP_VID_N, DP, id), \
  89         SRI(DP_VID_STREAM_CNTL, DP, id), \
  90         SRI(DP_VID_TIMING, DP, id), \
  91         SRI(DP_SEC_AUD_N, DP, id), \
  92         SRI(DP_SEC_TIMESTAMP, DP, id), \
  93         SRI(DIG_CLOCK_PATTERN, DIG, id)
  94
  95 #define SE_DCN_REG_LIST(id)\
  96         SE_COMMON_DCN_REG_LIST(id)
  97
  98
  99 struct dcn10_stream_enc_registers {
 100         uint32_t AFMT_CNTL;
 101         uint32_t AFMT_AVI_INFO0;
 102         uint32_t AFMT_AVI_INFO1;
 103         uint32_t AFMT_AVI_INFO2;
 104         uint32_t AFMT_AVI_INFO3;
 105         uint32_t AFMT_GENERIC_0;
 106         uint32_t AFMT_GENERIC_1;
 107         uint32_t AFMT_GENERIC_2;
 108         uint32_t AFMT_GENERIC_3;
 109         uint32_t AFMT_GENERIC_4;
 110         uint32_t AFMT_GENERIC_5;
 111         uint32_t AFMT_GENERIC_6;
 112         uint32_t AFMT_GENERIC_7;
 113         uint32_t AFMT_GENERIC_HDR;
 114         uint32_t AFMT_INFOFRAME_CONTROL0;
 115         uint32_t AFMT_VBI_PACKET_CONTROL;
 116         uint32_t AFMT_VBI_PACKET_CONTROL1;
 117         uint32_t AFMT_AUDIO_PACKET_CONTROL;
 118         uint32_t AFMT_AUDIO_PACKET_CONTROL2;
 119         uint32_t AFMT_AUDIO_SRC_CONTROL;
 120         uint32_t AFMT_60958_0;
 121         uint32_t AFMT_60958_1;
 122         uint32_t AFMT_60958_2;
 123         uint32_t DIG_FE_CNTL;
 124         uint32_t DIG_FE_CNTL2;
 125         uint32_t DP_MSE_RATE_CNTL;
 126         uint32_t DP_MSE_RATE_UPDATE;
 127         uint32_t DP_PIXEL_FORMAT;
 128         uint32_t DP_SEC_CNTL;
 129         uint32_t DP_SEC_CNTL2;
 130         uint32_t DP_SEC_CNTL6;
 131         uint32_t DP_STEER_FIFO;
 132         uint32_t DP_VID_M;
 133         uint32_t DP_VID_N;
 134         uint32_t DP_VID_STREAM_CNTL;
 135         uint32_t DP_VID_TIMING;
 136         uint32_t DP_SEC_AUD_N;
 137         uint32_t DP_SEC_TIMESTAMP;
 138         uint32_t HDMI_CONTROL;
 139         uint32_t HDMI_GC;
 140         uint32_t HDMI_GENERIC_PACKET_CONTROL0;
 141         uint32_t HDMI_GENERIC_PACKET_CONTROL1;
 142         uint32_t HDMI_GENERIC_PACKET_CONTROL2;
 143         uint32_t HDMI_GENERIC_PACKET_CONTROL3;
 144         uint32_t HDMI_GENERIC_PACKET_CONTROL4;
 145         uint32_t HDMI_GENERIC_PACKET_CONTROL5;
 146         uint32_t HDMI_INFOFRAME_CONTROL0;
 147         uint32_t HDMI_INFOFRAME_CONTROL1;
 148         uint32_t HDMI_VBI_PACKET_CONTROL;
 149         uint32_t HDMI_AUDIO_PACKET_CONTROL;
 150         uint32_t HDMI_ACR_PACKET_CONTROL;
 151         uint32_t HDMI_ACR_32_0;
 152         uint32_t HDMI_ACR_32_1;
 153         uint32_t HDMI_ACR_44_0;
 154         uint32_t HDMI_ACR_44_1;
 155         uint32_t HDMI_ACR_48_0;
 156         uint32_t HDMI_ACR_48_1;
 157         uint32_t DP_DB_CNTL;
 158         uint32_t DP_MSA_MISC;
 159         uint32_t DP_MSA_VBID_MISC;
 160         uint32_t DP_MSA_COLORIMETRY;
 161         uint32_t DP_MSA_TIMING_PARAM1;
 162         uint32_t DP_MSA_TIMING_PARAM2;
 163         uint32_t DP_MSA_TIMING_PARAM3;
 164         uint32_t DP_MSA_TIMING_PARAM4;
 165         uint32_t HDMI_DB_CONTROL;
 166         uint32_t DP_DSC_CNTL;
 167         uint32_t DP_DSC_BYTES_PER_PIXEL;
 168         uint32_t DME_CONTROL;
 169         uint32_t DP_SEC_METADATA_TRANSMISSION;
 170         uint32_t HDMI_METADATA_PACKET_CONTROL;
 171         uint32_t DP_SEC_FRAMING4;
 172         uint32_t DIG_CLOCK_PATTERN;
 173 };
 174
 175
 176 #define SE_SF(reg_name, field_name, post_fix)\
 177         .field_name = reg_name ## __ ## field_name ## post_fix
 178
 179 #define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\
 180         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
 181         SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
 182         SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
 183         SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
 184         SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
 185         SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
 186         SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
 187         SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
 188         SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
 189         SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
 190         SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
 191         SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
 192         SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\
 193         SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
 194         SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
 195         SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
 196         SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
 197         SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
 198         SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
 199         SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
 200         SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
 201         SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
 202         SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
 203         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
 204         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
 205         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
 206         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
 207         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
 208         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
 209         SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\
 210         SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\
 211         SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\
 212         SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\
 213         SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
 214         SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
 215         SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
 216         SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
 217         SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
 218         SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
 219         SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
 220         SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
 221         SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
 222         SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
 223         SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
 224         SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
 225         SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
 226         SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
 227         SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
 228         SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
 229         SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
 230         SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
 231         SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
 232         SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
 233         SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
 234         SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
 235         SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
 236         SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
 237         SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
 238         SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
 239         SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
 240         SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
 241         SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
 242         SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
 243         SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
 244         SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
 245         SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
 246         SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
 247         SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
 248         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
 249         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
 250         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
 251         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
 252         SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
 253         SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
 254         SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
 255         SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
 256         SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
 257         SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
 258         SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
 259         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
 260         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
 261         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
 262         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
 263         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
 264         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
 265         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
 266         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
 267         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, mask_sh),\
 268         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
 269         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
 270         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
 271         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
 272         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
 273         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
 274         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
 275         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
 276         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\
 277         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
 278         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
 279         SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
 280         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
 281         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
 282         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
 283         SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
 284         SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_PPS, mask_sh),\
 285         SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\
 286         SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\
 287         SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
 288         SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
 289         SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
 290         SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
 291         SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
 292         SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
 293         SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
 294         SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
 295         SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
 296         SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
 297         SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
 298         SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
 299         SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
 300         SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
 301         SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\
 302         SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)
 303
 304 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
 305         SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
 306
 307 #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
 308         SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
 309         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
 310         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
 311         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
 312         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
 313         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
 314         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh)
 315
 316
 317 #define SE_REG_FIELD_LIST_DCN1_0(type) \
 318         type AFMT_GENERIC_INDEX;\
 319         type AFMT_GENERIC_HB0;\
 320         type AFMT_GENERIC_HB1;\
 321         type AFMT_GENERIC_HB2;\
 322         type AFMT_GENERIC_HB3;\
 323         type AFMT_GENERIC_LOCK_STATUS;\
 324         type AFMT_GENERIC_CONFLICT;\
 325         type AFMT_GENERIC_CONFLICT_CLR;\
 326         type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\
 327         type AFMT_GENERIC1_FRAME_UPDATE_PENDING;\
 328         type AFMT_GENERIC2_FRAME_UPDATE_PENDING;\
 329         type AFMT_GENERIC3_FRAME_UPDATE_PENDING;\
 330         type AFMT_GENERIC4_FRAME_UPDATE_PENDING;\
 331         type AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING;\
 332         type AFMT_GENERIC5_FRAME_UPDATE_PENDING;\
 333         type AFMT_GENERIC6_FRAME_UPDATE_PENDING;\
 334         type AFMT_GENERIC7_FRAME_UPDATE_PENDING;\
 335         type AFMT_GENERIC0_FRAME_UPDATE;\
 336         type AFMT_GENERIC1_FRAME_UPDATE;\
 337         type AFMT_GENERIC2_FRAME_UPDATE;\
 338         type AFMT_GENERIC3_FRAME_UPDATE;\
 339         type AFMT_GENERIC4_FRAME_UPDATE;\
 340         type AFMT_GENERIC4_IMMEDIATE_UPDATE;\
 341         type AFMT_GENERIC5_FRAME_UPDATE;\
 342         type AFMT_GENERIC6_FRAME_UPDATE;\
 343         type AFMT_GENERIC7_FRAME_UPDATE;\
 344         type HDMI_GENERIC0_CONT;\
 345         type HDMI_GENERIC0_SEND;\
 346         type HDMI_GENERIC0_LINE;\
 347         type HDMI_GENERIC1_CONT;\
 348         type HDMI_GENERIC1_SEND;\
 349         type HDMI_GENERIC1_LINE;\
 350         type HDMI_GENERIC2_CONT;\
 351         type HDMI_GENERIC2_SEND;\
 352         type HDMI_GENERIC2_LINE;\
 353         type HDMI_GENERIC3_CONT;\
 354         type HDMI_GENERIC3_SEND;\
 355         type HDMI_GENERIC3_LINE;\
 356         type HDMI_GENERIC4_CONT;\
 357         type HDMI_GENERIC4_SEND;\
 358         type HDMI_GENERIC4_LINE;\
 359         type HDMI_GENERIC5_CONT;\
 360         type HDMI_GENERIC5_SEND;\
 361         type HDMI_GENERIC5_LINE;\
 362         type HDMI_GENERIC6_CONT;\
 363         type HDMI_GENERIC6_SEND;\
 364         type HDMI_GENERIC6_LINE;\
 365         type HDMI_GENERIC7_CONT;\
 366         type HDMI_GENERIC7_SEND;\
 367         type HDMI_GENERIC7_LINE;\
 368         type DP_PIXEL_ENCODING;\
 369         type DP_COMPONENT_DEPTH;\
 370         type HDMI_PACKET_GEN_VERSION;\
 371         type HDMI_KEEPOUT_MODE;\
 372         type HDMI_DEEP_COLOR_ENABLE;\
 373         type HDMI_CLOCK_CHANNEL_RATE;\
 374         type HDMI_DEEP_COLOR_DEPTH;\
 375         type HDMI_GC_CONT;\
 376         type HDMI_GC_SEND;\
 377         type HDMI_NULL_SEND;\
 378         type HDMI_DATA_SCRAMBLE_EN;\
 379         type HDMI_NO_EXTRA_NULL_PACKET_FILLED;\
 380         type HDMI_AUDIO_INFO_SEND;\
 381         type AFMT_AUDIO_INFO_UPDATE;\
 382         type HDMI_AUDIO_INFO_LINE;\
 383         type HDMI_GC_AVMUTE;\
 384         type DP_MSE_RATE_X;\
 385         type DP_MSE_RATE_Y;\
 386         type DP_MSE_RATE_UPDATE_PENDING;\
 387         type DP_SEC_GSP0_ENABLE;\
 388         type DP_SEC_STREAM_ENABLE;\
 389         type DP_SEC_GSP1_ENABLE;\
 390         type DP_SEC_GSP2_ENABLE;\
 391         type DP_SEC_GSP3_ENABLE;\
 392         type DP_SEC_GSP4_ENABLE;\
 393         type DP_SEC_GSP5_ENABLE;\
 394         type DP_SEC_GSP6_ENABLE;\
 395         type DP_SEC_GSP7_ENABLE;\
 396         type DP_SEC_GSP7_PPS;\
 397         type DP_SEC_GSP7_SEND;\
 398         type DP_SEC_GSP4_SEND;\
 399         type DP_SEC_GSP4_SEND_PENDING;\
 400         type DP_SEC_GSP4_LINE_NUM;\
 401         type DP_SEC_GSP4_SEND_ANY_LINE;\
 402         type DP_SEC_MPG_ENABLE;\
 403         type DP_VID_STREAM_DIS_DEFER;\
 404         type DP_VID_STREAM_ENABLE;\
 405         type DP_VID_STREAM_STATUS;\
 406         type DP_STEER_FIFO_RESET;\
 407         type DP_VID_M_N_GEN_EN;\
 408         type DP_VID_N;\
 409         type DP_VID_M;\
 410         type DIG_START;\
 411         type AFMT_AUDIO_SRC_SELECT;\
 412         type AFMT_AUDIO_CHANNEL_ENABLE;\
 413         type HDMI_AUDIO_PACKETS_PER_LINE;\
 414         type HDMI_AUDIO_DELAY_EN;\
 415         type AFMT_60958_CS_UPDATE;\
 416         type AFMT_AUDIO_LAYOUT_OVRD;\
 417         type AFMT_60958_OSF_OVRD;\
 418         type HDMI_ACR_AUTO_SEND;\
 419         type HDMI_ACR_SOURCE;\
 420         type HDMI_ACR_AUDIO_PRIORITY;\
 421         type HDMI_ACR_CTS_32;\
 422         type HDMI_ACR_N_32;\
 423         type HDMI_ACR_CTS_44;\
 424         type HDMI_ACR_N_44;\
 425         type HDMI_ACR_CTS_48;\
 426         type HDMI_ACR_N_48;\
 427         type AFMT_60958_CS_CHANNEL_NUMBER_L;\
 428         type AFMT_60958_CS_CLOCK_ACCURACY;\
 429         type AFMT_60958_CS_CHANNEL_NUMBER_R;\
 430         type AFMT_60958_CS_CHANNEL_NUMBER_2;\
 431         type AFMT_60958_CS_CHANNEL_NUMBER_3;\
 432         type AFMT_60958_CS_CHANNEL_NUMBER_4;\
 433         type AFMT_60958_CS_CHANNEL_NUMBER_5;\
 434         type AFMT_60958_CS_CHANNEL_NUMBER_6;\
 435         type AFMT_60958_CS_CHANNEL_NUMBER_7;\
 436         type DP_SEC_AUD_N;\
 437         type DP_SEC_TIMESTAMP_MODE;\
 438         type DP_SEC_ASP_ENABLE;\
 439         type DP_SEC_ATP_ENABLE;\
 440         type DP_SEC_AIP_ENABLE;\
 441         type DP_SEC_ACM_ENABLE;\
 442         type DP_SEC_GSP7_LINE_NUM;\
 443         type AFMT_AUDIO_SAMPLE_SEND;\
 444         type AFMT_AUDIO_CLOCK_EN;\
 445         type TMDS_PIXEL_ENCODING;\
 446         type TMDS_COLOR_FORMAT;\
 447         type DIG_STEREOSYNC_SELECT;\
 448         type DIG_STEREOSYNC_GATE_EN;\
 449         type DP_DB_DISABLE;\
 450         type DP_MSA_MISC0;\
 451         type DP_MSA_HTOTAL;\
 452         type DP_MSA_VTOTAL;\
 453         type DP_MSA_HSTART;\
 454         type DP_MSA_VSTART;\
 455         type DP_MSA_HSYNCWIDTH;\
 456         type DP_MSA_HSYNCPOLARITY;\
 457         type DP_MSA_VSYNCWIDTH;\
 458         type DP_MSA_VSYNCPOLARITY;\
 459         type DP_MSA_HWIDTH;\
 460         type DP_MSA_VHEIGHT;\
 461         type HDMI_DB_DISABLE;\
 462         type DP_VID_N_MUL;\
 463         type DP_VID_M_DOUBLE_VALUE_EN;\
 464         type DIG_SOURCE_SELECT;\
 465         type DIG_CLOCK_PATTERN
 466
 467 #define SE_REG_FIELD_LIST_DCN2_0(type) \
 468         type DP_DSC_MODE;\
 469         type DP_DSC_SLICE_WIDTH;\
 470         type DP_DSC_BYTES_PER_PIXEL;\
 471         type DP_VBID6_LINE_REFERENCE;\
 472         type DP_VBID6_LINE_NUM;\
 473         type METADATA_ENGINE_EN;\
 474         type METADATA_HUBP_REQUESTOR_ID;\
 475         type METADATA_STREAM_TYPE;\
 476         type DP_SEC_METADATA_PACKET_ENABLE;\
 477         type DP_SEC_METADATA_PACKET_LINE_REFERENCE;\
 478         type DP_SEC_METADATA_PACKET_LINE;\
 479         type HDMI_METADATA_PACKET_ENABLE;\
 480         type HDMI_METADATA_PACKET_LINE_REFERENCE;\
 481         type HDMI_METADATA_PACKET_LINE;\
 482         type DOLBY_VISION_EN;\
 483         type DP_PIXEL_COMBINE;\
 484         type DP_SST_SDP_SPLITTING
 485
 486 struct dcn10_stream_encoder_shift {
 487         SE_REG_FIELD_LIST_DCN1_0(uint8_t);
 488         SE_REG_FIELD_LIST_DCN2_0(uint8_t);
 489 };
 490
 491 struct dcn10_stream_encoder_mask {
 492         SE_REG_FIELD_LIST_DCN1_0(uint32_t);
 493         SE_REG_FIELD_LIST_DCN2_0(uint32_t);
 494 };
 495
 496 struct dcn10_stream_encoder {
 497         struct stream_encoder base;
 498         const struct dcn10_stream_enc_registers *regs;
 499         const struct dcn10_stream_encoder_shift *se_shift;
 500         const struct dcn10_stream_encoder_mask *se_mask;
 501 };
 502
 503 void dcn10_stream_encoder_construct(
 504         struct dcn10_stream_encoder *enc1,
 505         struct dc_context *ctx,
 506         struct dc_bios *bp,
 507         enum engine_id eng_id,
 508         const struct dcn10_stream_enc_registers *regs,
 509         const struct dcn10_stream_encoder_shift *se_shift,
 510         const struct dcn10_stream_encoder_mask *se_mask);
 511
 512 void enc1_update_generic_info_packet(
 513         struct dcn10_stream_encoder *enc1,
 514         uint32_t packet_index,
 515         const struct dc_info_packet *info_packet);
 516
 517 void enc1_stream_encoder_dp_set_stream_attribute(
 518         struct stream_encoder *enc,
 519         struct dc_crtc_timing *crtc_timing,
 520         enum dc_color_space output_color_space,
 521         bool use_vsc_sdp_for_colorimetry,
 522         uint32_t enable_sdp_splitting);
 523
 524 void enc1_stream_encoder_hdmi_set_stream_attribute(
 525         struct stream_encoder *enc,
 526         struct dc_crtc_timing *crtc_timing,
 527         int actual_pix_clk_khz,
 528         bool enable_audio);
 529
 530 void enc1_stream_encoder_dvi_set_stream_attribute(
 531         struct stream_encoder *enc,
 532         struct dc_crtc_timing *crtc_timing,
 533         bool is_dual_link);
 534
 535 void enc1_stream_encoder_set_mst_bandwidth(
 536         struct stream_encoder *enc,
 537         struct fixed31_32 avg_time_slots_per_mtp);
 538
 539 void enc1_stream_encoder_update_dp_info_packets(
 540         struct stream_encoder *enc,
 541         const struct encoder_info_frame *info_frame);
 542
 543 void enc1_stream_encoder_send_immediate_sdp_message(
 544         struct stream_encoder *enc,
 545         const uint8_t *custom_sdp_message,
 546                                 unsigned int sdp_message_size);
 547
 548 void enc1_stream_encoder_stop_dp_info_packets(
 549         struct stream_encoder *enc);
 550
 551 void enc1_stream_encoder_dp_blank(
 552         struct stream_encoder *enc);
 553
 554 void enc1_stream_encoder_dp_unblank(
 555         struct stream_encoder *enc,
 556         const struct encoder_unblank_param *param);
 557
 558 void enc1_setup_stereo_sync(
 559         struct stream_encoder *enc,
 560         int tg_inst, bool enable);
 561
 562 void enc1_stream_encoder_set_avmute(
 563         struct stream_encoder *enc,
 564         bool enable);
 565
 566 void enc1_se_audio_mute_control(
 567         struct stream_encoder *enc,
 568         bool mute);
 569
 570 void enc1_se_dp_audio_setup(
 571         struct stream_encoder *enc,
 572         unsigned int az_inst,
 573         struct audio_info *info);
 574
 575 void enc1_se_dp_audio_enable(
 576         struct stream_encoder *enc);
 577
 578 void enc1_se_dp_audio_disable(
 579         struct stream_encoder *enc);
 580
 581 void enc1_se_hdmi_audio_setup(
 582         struct stream_encoder *enc,
 583         unsigned int az_inst,
 584         struct audio_info *info,
 585         struct audio_crtc_info *audio_crtc_info);
 586
 587 void enc1_se_hdmi_audio_disable(
 588         struct stream_encoder *enc);
 589
 590 void enc1_dig_connect_to_otg(
 591         struct stream_encoder *enc,
 592         int tg_inst);
 593
 594 unsigned int enc1_dig_source_otg(
 595         struct stream_encoder *enc);
 596
 597 void enc1_stream_encoder_set_stream_attribute_helper(
 598         struct dcn10_stream_encoder *enc1,
 599         struct dc_crtc_timing *crtc_timing);
 600
 601 void enc1_se_enable_audio_clock(
 602         struct stream_encoder *enc,
 603         bool enable);
 604
 605 void enc1_se_enable_dp_audio(
 606         struct stream_encoder *enc);
 607
 608 void get_audio_clock_info(
 609         enum dc_color_depth color_depth,
 610         uint32_t crtc_pixel_clock_100Hz,
 611         uint32_t actual_pixel_clock_100Hz,
 612         struct audio_clock_info *audio_clock_info);
 613
 614 void enc1_reset_hdmi_stream_attribute(
 615         struct stream_encoder *enc);
 616
 617 bool enc1_stream_encoder_dp_get_pixel_format(
 618         struct stream_encoder *enc,
 619         enum dc_pixel_encoding *encoding,
 620         enum dc_color_depth *depth);
 621
 622 #endif /* __DC_STREAM_ENCODER_DCN10_H__ */