drivers/gpu/drm/amd/include/amd_shared.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef __AMD_SHARED_H__
  24 #define __AMD_SHARED_H__
  25
  26 #include <drm/amd_asic_type.h>
  27
  28
  29 #define AMD_MAX_USEC_TIMEOUT            1000000  /* 1000 ms */
  30
  31 /*
  32  * Chip flags
  33  */
  34 enum amd_chip_flags {
  35         AMD_ASIC_MASK = 0x0000ffffUL,
  36         AMD_FLAGS_MASK  = 0xffff0000UL,
  37         AMD_IS_MOBILITY = 0x00010000UL,
  38         AMD_IS_APU      = 0x00020000UL,
  39         AMD_IS_PX       = 0x00040000UL,
  40         AMD_EXP_HW_SUPPORT = 0x00080000UL,
  41 };
  42
  43 enum amd_ip_block_type {
  44         AMD_IP_BLOCK_TYPE_COMMON,
  45         AMD_IP_BLOCK_TYPE_GMC,
  46         AMD_IP_BLOCK_TYPE_IH,
  47         AMD_IP_BLOCK_TYPE_SMC,
  48         AMD_IP_BLOCK_TYPE_PSP,
  49         AMD_IP_BLOCK_TYPE_DCE,
  50         AMD_IP_BLOCK_TYPE_GFX,
  51         AMD_IP_BLOCK_TYPE_SDMA,
  52         AMD_IP_BLOCK_TYPE_UVD,
  53         AMD_IP_BLOCK_TYPE_VCE,
  54         AMD_IP_BLOCK_TYPE_ACP,
  55         AMD_IP_BLOCK_TYPE_VCN,
  56         AMD_IP_BLOCK_TYPE_MES,
  57         AMD_IP_BLOCK_TYPE_JPEG
  58 };
  59
  60 enum amd_clockgating_state {
  61         AMD_CG_STATE_GATE = 0,
  62         AMD_CG_STATE_UNGATE,
  63 };
  64
  65
  66 enum amd_powergating_state {
  67         AMD_PG_STATE_GATE = 0,
  68         AMD_PG_STATE_UNGATE,
  69 };
  70
  71
  72 /* CG flags */
  73 #define AMD_CG_SUPPORT_GFX_MGCG                 (1 << 0)
  74 #define AMD_CG_SUPPORT_GFX_MGLS                 (1 << 1)
  75 #define AMD_CG_SUPPORT_GFX_CGCG                 (1 << 2)
  76 #define AMD_CG_SUPPORT_GFX_CGLS                 (1 << 3)
  77 #define AMD_CG_SUPPORT_GFX_CGTS                 (1 << 4)
  78 #define AMD_CG_SUPPORT_GFX_CGTS_LS              (1 << 5)
  79 #define AMD_CG_SUPPORT_GFX_CP_LS                (1 << 6)
  80 #define AMD_CG_SUPPORT_GFX_RLC_LS               (1 << 7)
  81 #define AMD_CG_SUPPORT_MC_LS                    (1 << 8)
  82 #define AMD_CG_SUPPORT_MC_MGCG                  (1 << 9)
  83 #define AMD_CG_SUPPORT_SDMA_LS                  (1 << 10)
  84 #define AMD_CG_SUPPORT_SDMA_MGCG                (1 << 11)
  85 #define AMD_CG_SUPPORT_BIF_LS                   (1 << 12)
  86 #define AMD_CG_SUPPORT_UVD_MGCG                 (1 << 13)
  87 #define AMD_CG_SUPPORT_VCE_MGCG                 (1 << 14)
  88 #define AMD_CG_SUPPORT_HDP_LS                   (1 << 15)
  89 #define AMD_CG_SUPPORT_HDP_MGCG                 (1 << 16)
  90 #define AMD_CG_SUPPORT_ROM_MGCG                 (1 << 17)
  91 #define AMD_CG_SUPPORT_DRM_LS                   (1 << 18)
  92 #define AMD_CG_SUPPORT_BIF_MGCG                 (1 << 19)
  93 #define AMD_CG_SUPPORT_GFX_3D_CGCG              (1 << 20)
  94 #define AMD_CG_SUPPORT_GFX_3D_CGLS              (1 << 21)
  95 #define AMD_CG_SUPPORT_DRM_MGCG                 (1 << 22)
  96 #define AMD_CG_SUPPORT_DF_MGCG                  (1 << 23)
  97 #define AMD_CG_SUPPORT_VCN_MGCG                 (1 << 24)
  98 #define AMD_CG_SUPPORT_HDP_DS                   (1 << 25)
  99 #define AMD_CG_SUPPORT_HDP_SD                   (1 << 26)
 100 #define AMD_CG_SUPPORT_IH_CG                    (1 << 27)
 101 #define AMD_CG_SUPPORT_ATHUB_LS                 (1 << 28)
 102 #define AMD_CG_SUPPORT_ATHUB_MGCG               (1 << 29)
 103 #define AMD_CG_SUPPORT_JPEG_MGCG                (1 << 30)
 104 /* PG flags */
 105 #define AMD_PG_SUPPORT_GFX_PG                   (1 << 0)
 106 #define AMD_PG_SUPPORT_GFX_SMG                  (1 << 1)
 107 #define AMD_PG_SUPPORT_GFX_DMG                  (1 << 2)
 108 #define AMD_PG_SUPPORT_UVD                      (1 << 3)
 109 #define AMD_PG_SUPPORT_VCE                      (1 << 4)
 110 #define AMD_PG_SUPPORT_CP                       (1 << 5)
 111 #define AMD_PG_SUPPORT_GDS                      (1 << 6)
 112 #define AMD_PG_SUPPORT_RLC_SMU_HS               (1 << 7)
 113 #define AMD_PG_SUPPORT_SDMA                     (1 << 8)
 114 #define AMD_PG_SUPPORT_ACP                      (1 << 9)
 115 #define AMD_PG_SUPPORT_SAMU                     (1 << 10)
 116 #define AMD_PG_SUPPORT_GFX_QUICK_MG             (1 << 11)
 117 #define AMD_PG_SUPPORT_GFX_PIPELINE             (1 << 12)
 118 #define AMD_PG_SUPPORT_MMHUB                    (1 << 13)
 119 #define AMD_PG_SUPPORT_VCN                      (1 << 14)
 120 #define AMD_PG_SUPPORT_VCN_DPG                  (1 << 15)
 121 #define AMD_PG_SUPPORT_ATHUB                    (1 << 16)
 122 #define AMD_PG_SUPPORT_JPEG                     (1 << 17)
 123
 124 enum PP_FEATURE_MASK {
 125         PP_SCLK_DPM_MASK = 0x1,
 126         PP_MCLK_DPM_MASK = 0x2,
 127         PP_PCIE_DPM_MASK = 0x4,
 128         PP_SCLK_DEEP_SLEEP_MASK = 0x8,
 129         PP_POWER_CONTAINMENT_MASK = 0x10,
 130         PP_UVD_HANDSHAKE_MASK = 0x20,
 131         PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
 132         PP_VBI_TIME_SUPPORT_MASK = 0x80,
 133         PP_ULV_MASK = 0x100,
 134         PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
 135         PP_CLOCK_STRETCH_MASK = 0x400,
 136         PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
 137         PP_SOCCLK_DPM_MASK = 0x1000,
 138         PP_DCEFCLK_DPM_MASK = 0x2000,
 139         PP_OVERDRIVE_MASK = 0x4000,
 140         PP_GFXOFF_MASK = 0x8000,
 141         PP_ACG_MASK = 0x10000,
 142         PP_STUTTER_MODE = 0x20000,
 143         PP_AVFS_MASK = 0x40000,
 144 };
 145
 146 enum DC_FEATURE_MASK {
 147         DC_FBC_MASK = 0x1,
 148         DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
 149         DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
 150         DC_PSR_MASK = 0x8,
 151 };
 152
 153 enum amd_dpm_forced_level;
 154 /**
 155  * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
 156  */
 157 struct amd_ip_funcs {
 158         /** @name: Name of IP block */
 159         char *name;
 160         /**
 161          * @early_init:
 162          *
 163          * sets up early driver state (pre sw_init),
 164          * does not configure hw - Optional
 165          */
 166         int (*early_init)(void *handle);
 167         /** @late_init: sets up late driver/hw state (post hw_init) - Optional */
 168         int (*late_init)(void *handle);
 169         /** @sw_init: sets up driver state, does not configure hw */
 170         int (*sw_init)(void *handle);
 171         /** @sw_fini: tears down driver state, does not configure hw */
 172         int (*sw_fini)(void *handle);
 173         /** @hw_init: sets up the hw state */
 174         int (*hw_init)(void *handle);
 175         /** @hw_fini: tears down the hw state */
 176         int (*hw_fini)(void *handle);
 177         /** @late_fini: final cleanup */
 178         void (*late_fini)(void *handle);
 179         /** @suspend: handles IP specific hw/sw changes for suspend */
 180         int (*suspend)(void *handle);
 181         /** @resume: handles IP specific hw/sw changes for resume */
 182         int (*resume)(void *handle);
 183         /** @is_idle: returns current IP block idle status */
 184         bool (*is_idle)(void *handle);
 185         /** @wait_for_idle: poll for idle */
 186         int (*wait_for_idle)(void *handle);
 187         /** @check_soft_reset: check soft reset the IP block */
 188         bool (*check_soft_reset)(void *handle);
 189         /** @pre_soft_reset: pre soft reset the IP block */
 190         int (*pre_soft_reset)(void *handle);
 191         /** @soft_reset: soft reset the IP block */
 192         int (*soft_reset)(void *handle);
 193         /** @post_soft_reset: post soft reset the IP block */
 194         int (*post_soft_reset)(void *handle);
 195         /** @set_clockgating_state: enable/disable cg for the IP block */
 196         int (*set_clockgating_state)(void *handle,
 197                                      enum amd_clockgating_state state);
 198         /** @set_powergating_state: enable/disable pg for the IP block */
 199         int (*set_powergating_state)(void *handle,
 200                                      enum amd_powergating_state state);
 201         /** @get_clockgating_state: get current clockgating status */
 202         void (*get_clockgating_state)(void *handle, u32 *flags);
 203         /** @enable_umd_pstate: enable UMD powerstate */
 204         int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level);
 205 };
 206
 207
 208 #endif /* __AMD_SHARED_H__ */