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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / display / intel_vdsc.c
blob9e6aaa302e40a6b12ebcdc3c49921e32b3e34276
1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
6 * Manasi Navare <manasi.d.navare@intel.com>
7 */
8
9 #include <drm/i915_drm.h>
10
11 #include "i915_drv.h"
12 #include "intel_display_types.h"
13 #include "intel_dsi.h"
14 #include "intel_vdsc.h"
15
16 enum ROW_INDEX_BPP {
17 ROW_INDEX_6BPP = 0,
18 ROW_INDEX_8BPP,
19 ROW_INDEX_10BPP,
20 ROW_INDEX_12BPP,
21 ROW_INDEX_15BPP,
22 MAX_ROW_INDEX
23 };
24
25 enum COLUMN_INDEX_BPC {
26 COLUMN_INDEX_8BPC = 0,
27 COLUMN_INDEX_10BPC,
28 COLUMN_INDEX_12BPC,
29 COLUMN_INDEX_14BPC,
30 COLUMN_INDEX_16BPC,
31 MAX_COLUMN_INDEX
32 };
33
34 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
35 static const u16 rc_buf_thresh[] = {
36 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
37 7744, 7872, 8000, 8064
38 };
39
40 struct rc_parameters {
41 u16 initial_xmit_delay;
42 u8 first_line_bpg_offset;
43 u16 initial_offset;
44 u8 flatness_min_qp;
45 u8 flatness_max_qp;
46 u8 rc_quant_incr_limit0;
47 u8 rc_quant_incr_limit1;
48 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
49 };
50
51 /*
52 * Selected Rate Control Related Parameter Recommended Values
53 * from DSC_v1.11 spec & C Model release: DSC_model_20161212
54 */
55 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
56 {
57 /* 6BPP/8BPC */
58 { 768, 15, 6144, 3, 13, 11, 11, {
59 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
60 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
61 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
62 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
63 }
64 },
65 /* 6BPP/10BPC */
66 { 768, 15, 6144, 7, 17, 15, 15, {
67 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
68 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
69 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
70 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
71 { 17, 18, -12 }
72 }
73 },
74 /* 6BPP/12BPC */
75 { 768, 15, 6144, 11, 21, 19, 19, {
76 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
77 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
78 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
79 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
80 { 21, 22, -12 }
81 }
82 },
83 /* 6BPP/14BPC */
84 { 768, 15, 6144, 15, 25, 23, 27, {
85 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
86 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
87 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
88 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
89 { 25, 26, -12 }
90 }
91 },
92 /* 6BPP/16BPC */
93 { 768, 15, 6144, 19, 29, 27, 27, {
94 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
95 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
96 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
97 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
98 { 29, 30, -12 }
99 }
100 },
101 },
102 {
103 /* 8BPP/8BPC */
104 { 512, 12, 6144, 3, 12, 11, 11, {
105 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
106 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
107 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
108 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
109 }
110 },
111 /* 8BPP/10BPC */
112 { 512, 12, 6144, 7, 16, 15, 15, {
113 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
114 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
115 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
116 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
117 }
118 },
119 /* 8BPP/12BPC */
120 { 512, 12, 6144, 11, 20, 19, 19, {
121 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
122 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
123 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
124 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
125 { 21, 23, -12 }
126 }
127 },
128 /* 8BPP/14BPC */
129 { 512, 12, 6144, 15, 24, 23, 23, {
130 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
131 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
132 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
133 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
134 { 24, 25, -12 }
135 }
136 },
137 /* 8BPP/16BPC */
138 { 512, 12, 6144, 19, 28, 27, 27, {
139 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
140 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
141 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
142 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
143 { 28, 29, -12 }
144 }
145 },
146 },
147 {
148 /* 10BPP/8BPC */
149 { 410, 15, 5632, 3, 12, 11, 11, {
150 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
151 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
152 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
153 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
154 }
155 },
156 /* 10BPP/10BPC */
157 { 410, 15, 5632, 7, 16, 15, 15, {
158 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
159 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
160 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
161 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
162 }
163 },
164 /* 10BPP/12BPC */
165 { 410, 15, 5632, 11, 20, 19, 19, {
166 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
167 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
168 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
169 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
170 { 19, 20, -12 }
171 }
172 },
173 /* 10BPP/14BPC */
174 { 410, 15, 5632, 15, 24, 23, 23, {
175 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
176 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
177 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
178 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
179 { 23, 24, -12 }
180 }
181 },
182 /* 10BPP/16BPC */
183 { 410, 15, 5632, 19, 28, 27, 27, {
184 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
185 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
186 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
187 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
188 { 27, 28, -12 }
189 }
190 },
191 },
192 {
193 /* 12BPP/8BPC */
194 { 341, 15, 2048, 3, 12, 11, 11, {
195 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
196 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
197 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
198 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
199 }
200 },
201 /* 12BPP/10BPC */
202 { 341, 15, 2048, 7, 16, 15, 15, {
203 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
204 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
205 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
206 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
207 }
208 },
209 /* 12BPP/12BPC */
210 { 341, 15, 2048, 11, 20, 19, 19, {
211 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
212 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
213 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
214 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
215 { 21, 23, -12 }
216 }
217 },
218 /* 12BPP/14BPC */
219 { 341, 15, 2048, 15, 24, 23, 23, {
220 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
221 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
222 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
223 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
224 { 22, 23, -12 }
225 }
226 },
227 /* 12BPP/16BPC */
228 { 341, 15, 2048, 19, 28, 27, 27, {
229 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
230 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
231 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
232 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
233 { 26, 27, -12 }
234 }
235 },
236 },
237 {
238 /* 15BPP/8BPC */
239 { 273, 15, 2048, 3, 12, 11, 11, {
240 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
241 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
242 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
243 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
244 }
245 },
246 /* 15BPP/10BPC */
247 { 273, 15, 2048, 7, 16, 15, 15, {
248 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
249 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
250 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
251 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
252 }
253 },
254 /* 15BPP/12BPC */
255 { 273, 15, 2048, 11, 20, 19, 19, {
256 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
257 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
258 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
259 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
260 { 16, 17, -12 }
261 }
262 },
263 /* 15BPP/14BPC */
264 { 273, 15, 2048, 15, 24, 23, 23, {
265 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
266 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
267 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
268 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
269 { 20, 21, -12 }
270 }
271 },
272 /* 15BPP/16BPC */
273 { 273, 15, 2048, 19, 28, 27, 27, {
274 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
275 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
276 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
277 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
278 { 24, 25, -12 }
279 }
280 }
281 }
282
283 };
284
285 static int get_row_index_for_rc_params(u16 compressed_bpp)
286 {
287 switch (compressed_bpp) {
288 case 6:
289 return ROW_INDEX_6BPP;
290 case 8:
291 return ROW_INDEX_8BPP;
292 case 10:
293 return ROW_INDEX_10BPP;
294 case 12:
295 return ROW_INDEX_12BPP;
296 case 15:
297 return ROW_INDEX_15BPP;
298 default:
299 return -EINVAL;
300 }
301 }
302
303 static int get_column_index_for_rc_params(u8 bits_per_component)
304 {
305 switch (bits_per_component) {
306 case 8:
307 return COLUMN_INDEX_8BPC;
308 case 10:
309 return COLUMN_INDEX_10BPC;
310 case 12:
311 return COLUMN_INDEX_12BPC;
312 case 14:
313 return COLUMN_INDEX_14BPC;
314 case 16:
315 return COLUMN_INDEX_16BPC;
316 default:
317 return -EINVAL;
318 }
319 }
320
321 static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
322 u8 bits_per_component)
323 {
324 int row_index, column_index;
325
326 row_index = get_row_index_for_rc_params(compressed_bpp);
327 if (row_index < 0)
328 return NULL;
329
330 column_index = get_column_index_for_rc_params(bits_per_component);
331 if (column_index < 0)
332 return NULL;
333
334 return &rc_parameters[row_index][column_index];
335 }
336
337 bool intel_dsc_source_support(struct intel_encoder *encoder,
338 const struct intel_crtc_state *crtc_state)
339 {
340 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
341 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
342 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
343 enum pipe pipe = crtc->pipe;
344
345 if (!INTEL_INFO(i915)->display.has_dsc)
346 return false;
347
348 /* On TGL, DSC is supported on all Pipes */
349 if (INTEL_GEN(i915) >= 12)
350 return true;
351
352 if (INTEL_GEN(i915) >= 10 &&
353 (pipe != PIPE_A ||
354 (cpu_transcoder == TRANSCODER_EDP ||
355 cpu_transcoder == TRANSCODER_DSI_0 ||
356 cpu_transcoder == TRANSCODER_DSI_1)))
357 return true;
358
359 return false;
360 }
361
362 static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state)
363 {
364 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
365 const struct drm_i915_private *i915 = to_i915(crtc->base.dev);
366 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
367
368 if (INTEL_GEN(i915) >= 12)
369 return true;
370
371 if (cpu_transcoder == TRANSCODER_EDP ||
372 cpu_transcoder == TRANSCODER_DSI_0 ||
373 cpu_transcoder == TRANSCODER_DSI_1)
374 return false;
375
376 /* There's no pipe A DSC engine on ICL */
377 WARN_ON(crtc->pipe == PIPE_A);
378
379 return true;
380 }
381
382 int intel_dsc_compute_params(struct intel_encoder *encoder,
383 struct intel_crtc_state *pipe_config)
384 {
385 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
386 u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
387 const struct rc_parameters *rc_params;
388 u8 i = 0;
389
390 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
391 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
392 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
393 pipe_config->dsc.slice_count);
394
395 /* Gen 11 does not support YCbCr */
396 vdsc_cfg->simple_422 = false;
397 /* Gen 11 does not support VBR */
398 vdsc_cfg->vbr_enable = false;
399
400 /* Gen 11 only supports integral values of bpp */
401 vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
402 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
403
404 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
405 /*
406 * six 0s are appended to the lsb of each threshold value
407 * internally in h/w.
408 * Only 8 bits are allowed for programming RcBufThreshold
409 */
410 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
411 }
412
413 /*
414 * For 6bpp, RC Buffer threshold 12 and 13 need a different value
415 * as per C Model
416 */
417 if (compressed_bpp == 6) {
418 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
419 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
420 }
421
422 rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component);
423 if (!rc_params)
424 return -EINVAL;
425
426 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
427 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
428 vdsc_cfg->initial_offset = rc_params->initial_offset;
429 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
430 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
431 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
432 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
433
434 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
435 vdsc_cfg->rc_range_params[i].range_min_qp =
436 rc_params->rc_range_params[i].range_min_qp;
437 vdsc_cfg->rc_range_params[i].range_max_qp =
438 rc_params->rc_range_params[i].range_max_qp;
439 /*
440 * Range BPG Offset uses 2's complement and is only a 6 bits. So
441 * mask it to get only 6 bits.
442 */
443 vdsc_cfg->rc_range_params[i].range_bpg_offset =
444 rc_params->rc_range_params[i].range_bpg_offset &
445 DSC_RANGE_BPG_OFFSET_MASK;
446 }
447
448 /*
449 * BitsPerComponent value determines mux_word_size:
450 * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
451 * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
452 * 48 bits
453 */
454 if (vdsc_cfg->bits_per_component == 8 ||
455 vdsc_cfg->bits_per_component == 10)
456 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
457 else if (vdsc_cfg->bits_per_component == 12)
458 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
459
460 /* RC_MODEL_SIZE is a constant across all configurations */
461 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
462 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
463 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
464 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
465
466 return 0;
467 }
468
469 enum intel_display_power_domain
470 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
471 {
472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
473 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
474 enum pipe pipe = crtc->pipe;
475
476 /*
477 * VDSC/joining uses a separate power well, PW2, and requires
478 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
479 *
480 * - ICL eDP/DSI transcoder
481 * - TGL pipe A
482 *
483 * For any other pipe, VDSC/joining uses the power well associated with
484 * the pipe in use. Hence another reference on the pipe power domain
485 * will suffice. (Except no VDSC/joining on ICL pipe A.)
486 */
487 if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A)
488 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
489 else if (is_pipe_dsc(crtc_state))
490 return POWER_DOMAIN_PIPE(pipe);
491 else
492 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
493 }
494
495 static void intel_dsc_pps_configure(struct intel_encoder *encoder,
496 const struct intel_crtc_state *crtc_state)
497 {
498 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
500 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
501 enum pipe pipe = crtc->pipe;
502 u32 pps_val = 0;
503 u32 rc_buf_thresh_dword[4];
504 u32 rc_range_params_dword[8];
505 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
506 int i = 0;
507
508 /* Populate PICTURE_PARAMETER_SET_0 registers */
509 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
510 DSC_VER_MIN_SHIFT |
511 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
512 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
513 if (vdsc_cfg->block_pred_enable)
514 pps_val |= DSC_BLOCK_PREDICTION;
515 if (vdsc_cfg->convert_rgb)
516 pps_val |= DSC_COLOR_SPACE_CONVERSION;
517 if (vdsc_cfg->simple_422)
518 pps_val |= DSC_422_ENABLE;
519 if (vdsc_cfg->vbr_enable)
520 pps_val |= DSC_VBR_ENABLE;
521 DRM_INFO("PPS0 = 0x%08x\n", pps_val);
522 if (!is_pipe_dsc(crtc_state)) {
523 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
524 /*
525 * If 2 VDSC instances are needed, configure PPS for second
526 * VDSC
527 */
528 if (crtc_state->dsc.dsc_split)
529 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
530 } else {
531 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
532 if (crtc_state->dsc.dsc_split)
533 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
534 pps_val);
535 }
536
537 /* Populate PICTURE_PARAMETER_SET_1 registers */
538 pps_val = 0;
539 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
540 DRM_INFO("PPS1 = 0x%08x\n", pps_val);
541 if (!is_pipe_dsc(crtc_state)) {
542 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
543 /*
544 * If 2 VDSC instances are needed, configure PPS for second
545 * VDSC
546 */
547 if (crtc_state->dsc.dsc_split)
548 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
549 } else {
550 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
551 if (crtc_state->dsc.dsc_split)
552 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
553 pps_val);
554 }
555
556 /* Populate PICTURE_PARAMETER_SET_2 registers */
557 pps_val = 0;
558 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
559 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
560 DRM_INFO("PPS2 = 0x%08x\n", pps_val);
561 if (!is_pipe_dsc(crtc_state)) {
562 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
563 /*
564 * If 2 VDSC instances are needed, configure PPS for second
565 * VDSC
566 */
567 if (crtc_state->dsc.dsc_split)
568 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
569 } else {
570 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
571 if (crtc_state->dsc.dsc_split)
572 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
573 pps_val);
574 }
575
576 /* Populate PICTURE_PARAMETER_SET_3 registers */
577 pps_val = 0;
578 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
579 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
580 DRM_INFO("PPS3 = 0x%08x\n", pps_val);
581 if (!is_pipe_dsc(crtc_state)) {
582 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val);
583 /*
584 * If 2 VDSC instances are needed, configure PPS for second
585 * VDSC
586 */
587 if (crtc_state->dsc.dsc_split)
588 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
589 } else {
590 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
591 if (crtc_state->dsc.dsc_split)
592 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
593 pps_val);
594 }
595
596 /* Populate PICTURE_PARAMETER_SET_4 registers */
597 pps_val = 0;
598 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
599 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
600 DRM_INFO("PPS4 = 0x%08x\n", pps_val);
601 if (!is_pipe_dsc(crtc_state)) {
602 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val);
603 /*
604 * If 2 VDSC instances are needed, configure PPS for second
605 * VDSC
606 */
607 if (crtc_state->dsc.dsc_split)
608 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
609 } else {
610 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
611 if (crtc_state->dsc.dsc_split)
612 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
613 pps_val);
614 }
615
616 /* Populate PICTURE_PARAMETER_SET_5 registers */
617 pps_val = 0;
618 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
619 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
620 DRM_INFO("PPS5 = 0x%08x\n", pps_val);
621 if (!is_pipe_dsc(crtc_state)) {
622 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val);
623 /*
624 * If 2 VDSC instances are needed, configure PPS for second
625 * VDSC
626 */
627 if (crtc_state->dsc.dsc_split)
628 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
629 } else {
630 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
631 if (crtc_state->dsc.dsc_split)
632 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
633 pps_val);
634 }
635
636 /* Populate PICTURE_PARAMETER_SET_6 registers */
637 pps_val = 0;
638 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
639 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
640 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
641 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
642 DRM_INFO("PPS6 = 0x%08x\n", pps_val);
643 if (!is_pipe_dsc(crtc_state)) {
644 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val);
645 /*
646 * If 2 VDSC instances are needed, configure PPS for second
647 * VDSC
648 */
649 if (crtc_state->dsc.dsc_split)
650 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
651 } else {
652 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
653 if (crtc_state->dsc.dsc_split)
654 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
655 pps_val);
656 }
657
658 /* Populate PICTURE_PARAMETER_SET_7 registers */
659 pps_val = 0;
660 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
661 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
662 DRM_INFO("PPS7 = 0x%08x\n", pps_val);
663 if (!is_pipe_dsc(crtc_state)) {
664 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val);
665 /*
666 * If 2 VDSC instances are needed, configure PPS for second
667 * VDSC
668 */
669 if (crtc_state->dsc.dsc_split)
670 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
671 } else {
672 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
673 if (crtc_state->dsc.dsc_split)
674 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
675 pps_val);
676 }
677
678 /* Populate PICTURE_PARAMETER_SET_8 registers */
679 pps_val = 0;
680 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
681 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
682 DRM_INFO("PPS8 = 0x%08x\n", pps_val);
683 if (!is_pipe_dsc(crtc_state)) {
684 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val);
685 /*
686 * If 2 VDSC instances are needed, configure PPS for second
687 * VDSC
688 */
689 if (crtc_state->dsc.dsc_split)
690 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
691 } else {
692 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
693 if (crtc_state->dsc.dsc_split)
694 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
695 pps_val);
696 }
697
698 /* Populate PICTURE_PARAMETER_SET_9 registers */
699 pps_val = 0;
700 pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
701 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
702 DRM_INFO("PPS9 = 0x%08x\n", pps_val);
703 if (!is_pipe_dsc(crtc_state)) {
704 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val);
705 /*
706 * If 2 VDSC instances are needed, configure PPS for second
707 * VDSC
708 */
709 if (crtc_state->dsc.dsc_split)
710 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
711 } else {
712 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
713 if (crtc_state->dsc.dsc_split)
714 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
715 pps_val);
716 }
717
718 /* Populate PICTURE_PARAMETER_SET_10 registers */
719 pps_val = 0;
720 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
721 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
722 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
723 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
724 DRM_INFO("PPS10 = 0x%08x\n", pps_val);
725 if (!is_pipe_dsc(crtc_state)) {
726 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val);
727 /*
728 * If 2 VDSC instances are needed, configure PPS for second
729 * VDSC
730 */
731 if (crtc_state->dsc.dsc_split)
732 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
733 } else {
734 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
735 if (crtc_state->dsc.dsc_split)
736 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
737 pps_val);
738 }
739
740 /* Populate Picture parameter set 16 */
741 pps_val = 0;
742 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
743 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
744 vdsc_cfg->slice_width) |
745 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
746 vdsc_cfg->slice_height);
747 DRM_INFO("PPS16 = 0x%08x\n", pps_val);
748 if (!is_pipe_dsc(crtc_state)) {
749 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val);
750 /*
751 * If 2 VDSC instances are needed, configure PPS for second
752 * VDSC
753 */
754 if (crtc_state->dsc.dsc_split)
755 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
756 } else {
757 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
758 if (crtc_state->dsc.dsc_split)
759 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
760 pps_val);
761 }
762
763 /* Populate the RC_BUF_THRESH registers */
764 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
765 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
766 rc_buf_thresh_dword[i / 4] |=
767 (u32)(vdsc_cfg->rc_buf_thresh[i] <<
768 BITS_PER_BYTE * (i % 4));
769 DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i,
770 rc_buf_thresh_dword[i / 4]);
771 }
772 if (!is_pipe_dsc(crtc_state)) {
773 I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]);
774 I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
775 I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
776 I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
777 if (crtc_state->dsc.dsc_split) {
778 I915_WRITE(DSCC_RC_BUF_THRESH_0,
779 rc_buf_thresh_dword[0]);
780 I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
781 rc_buf_thresh_dword[1]);
782 I915_WRITE(DSCC_RC_BUF_THRESH_1,
783 rc_buf_thresh_dword[2]);
784 I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW,
785 rc_buf_thresh_dword[3]);
786 }
787 } else {
788 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe),
789 rc_buf_thresh_dword[0]);
790 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
791 rc_buf_thresh_dword[1]);
792 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe),
793 rc_buf_thresh_dword[2]);
794 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
795 rc_buf_thresh_dword[3]);
796 if (crtc_state->dsc.dsc_split) {
797 I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
798 rc_buf_thresh_dword[0]);
799 I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
800 rc_buf_thresh_dword[1]);
801 I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe),
802 rc_buf_thresh_dword[2]);
803 I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
804 rc_buf_thresh_dword[3]);
805 }
806 }
807
808 /* Populate the RC_RANGE_PARAMETERS registers */
809 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
810 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
811 rc_range_params_dword[i / 2] |=
812 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
813 RC_BPG_OFFSET_SHIFT) |
814 (vdsc_cfg->rc_range_params[i].range_max_qp <<
815 RC_MAX_QP_SHIFT) |
816 (vdsc_cfg->rc_range_params[i].range_min_qp <<
817 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
818 DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i,
819 rc_range_params_dword[i / 2]);
820 }
821 if (!is_pipe_dsc(crtc_state)) {
822 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0,
823 rc_range_params_dword[0]);
824 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW,
825 rc_range_params_dword[1]);
826 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1,
827 rc_range_params_dword[2]);
828 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW,
829 rc_range_params_dword[3]);
830 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2,
831 rc_range_params_dword[4]);
832 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW,
833 rc_range_params_dword[5]);
834 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3,
835 rc_range_params_dword[6]);
836 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
837 rc_range_params_dword[7]);
838 if (crtc_state->dsc.dsc_split) {
839 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
840 rc_range_params_dword[0]);
841 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
842 rc_range_params_dword[1]);
843 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1,
844 rc_range_params_dword[2]);
845 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW,
846 rc_range_params_dword[3]);
847 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2,
848 rc_range_params_dword[4]);
849 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW,
850 rc_range_params_dword[5]);
851 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3,
852 rc_range_params_dword[6]);
853 I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW,
854 rc_range_params_dword[7]);
855 }
856 } else {
857 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
858 rc_range_params_dword[0]);
859 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
860 rc_range_params_dword[1]);
861 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
862 rc_range_params_dword[2]);
863 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
864 rc_range_params_dword[3]);
865 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
866 rc_range_params_dword[4]);
867 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
868 rc_range_params_dword[5]);
869 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
870 rc_range_params_dword[6]);
871 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
872 rc_range_params_dword[7]);
873 if (crtc_state->dsc.dsc_split) {
874 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
875 rc_range_params_dword[0]);
876 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
877 rc_range_params_dword[1]);
878 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
879 rc_range_params_dword[2]);
880 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
881 rc_range_params_dword[3]);
882 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
883 rc_range_params_dword[4]);
884 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
885 rc_range_params_dword[5]);
886 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
887 rc_range_params_dword[6]);
888 I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
889 rc_range_params_dword[7]);
890 }
891 }
892 }
893
894 void intel_dsc_get_config(struct intel_encoder *encoder,
895 struct intel_crtc_state *crtc_state)
896 {
897 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
898 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
899 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
900 enum pipe pipe = crtc->pipe;
901 enum intel_display_power_domain power_domain;
902 intel_wakeref_t wakeref;
903 u32 dss_ctl1, dss_ctl2, val;
904
905 if (!intel_dsc_source_support(encoder, crtc_state))
906 return;
907
908 power_domain = intel_dsc_power_domain(crtc_state);
909
910 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
911 if (!wakeref)
912 return;
913
914 if (!is_pipe_dsc(crtc_state)) {
915 dss_ctl1 = I915_READ(DSS_CTL1);
916 dss_ctl2 = I915_READ(DSS_CTL2);
917 } else {
918 dss_ctl1 = I915_READ(ICL_PIPE_DSS_CTL1(pipe));
919 dss_ctl2 = I915_READ(ICL_PIPE_DSS_CTL2(pipe));
920 }
921
922 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
923 if (!crtc_state->dsc.compression_enable)
924 goto out;
925
926 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
927 (dss_ctl1 & JOINER_ENABLE);
928
929 /* FIXME: add more state readout as needed */
930
931 /* PPS1 */
932 if (!is_pipe_dsc(crtc_state))
933 val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1);
934 else
935 val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
936 vdsc_cfg->bits_per_pixel = val;
937 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
938 out:
939 intel_display_power_put(dev_priv, power_domain, wakeref);
940 }
941
942 static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
943 const struct intel_crtc_state *crtc_state)
944 {
945 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
946 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
947 struct mipi_dsi_device *dsi;
948 struct drm_dsc_picture_parameter_set pps;
949 enum port port;
950
951 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
952
953 for_each_dsi_port(port, intel_dsi->ports) {
954 dsi = intel_dsi->dsi_hosts[port]->device;
955
956 mipi_dsi_picture_parameter_set(dsi, &pps);
957 mipi_dsi_compression_mode(dsi, true);
958 }
959 }
960
961 static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
962 const struct intel_crtc_state *crtc_state)
963 {
964 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
965 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
966 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
967 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
968
969 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
970 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
971
972 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
973 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
974
975 intel_dig_port->write_infoframe(encoder, crtc_state,
976 DP_SDP_PPS, &dp_dsc_pps_sdp,
977 sizeof(dp_dsc_pps_sdp));
978 }
979
980 void intel_dsc_enable(struct intel_encoder *encoder,
981 const struct intel_crtc_state *crtc_state)
982 {
983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
984 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
985 enum pipe pipe = crtc->pipe;
986 i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
987 u32 dss_ctl1_val = 0;
988 u32 dss_ctl2_val = 0;
989
990 if (!crtc_state->dsc.compression_enable)
991 return;
992
993 /* Enable Power wells for VDSC/joining */
994 intel_display_power_get(dev_priv,
995 intel_dsc_power_domain(crtc_state));
996
997 intel_dsc_pps_configure(encoder, crtc_state);
998
999 if (encoder->type == INTEL_OUTPUT_DSI)
1000 intel_dsc_dsi_pps_write(encoder, crtc_state);
1001 else
1002 intel_dsc_dp_pps_write(encoder, crtc_state);
1003
1004 if (!is_pipe_dsc(crtc_state)) {
1005 dss_ctl1_reg = DSS_CTL1;
1006 dss_ctl2_reg = DSS_CTL2;
1007 } else {
1008 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
1009 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
1010 }
1011 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
1012 if (crtc_state->dsc.dsc_split) {
1013 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
1014 dss_ctl1_val |= JOINER_ENABLE;
1015 }
1016 I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
1017 I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
1018 }
1019
1020 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
1021 {
1022 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1023 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1024 enum pipe pipe = crtc->pipe;
1025 i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
1026 u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
1027
1028 if (!old_crtc_state->dsc.compression_enable)
1029 return;
1030
1031 if (!is_pipe_dsc(old_crtc_state)) {
1032 dss_ctl1_reg = DSS_CTL1;
1033 dss_ctl2_reg = DSS_CTL2;
1034 } else {
1035 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
1036 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
1037 }
1038 dss_ctl1_val = I915_READ(dss_ctl1_reg);
1039 if (dss_ctl1_val & JOINER_ENABLE)
1040 dss_ctl1_val &= ~JOINER_ENABLE;
1041 I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
1042
1043 dss_ctl2_val = I915_READ(dss_ctl2_reg);
1044 if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
1045 dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
1046 dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
1047 RIGHT_BRANCH_VDSC_ENABLE);
1048 I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
1049
1050 /* Disable Power wells for VDSC/joining */
1051 intel_display_power_put_unchecked(dev_priv,
1052 intel_dsc_power_domain(old_crtc_state));
1053 }
Linux with added FPC-III support