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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / gvt / handlers.c
blob6d28d72e6c7e4d3a8c2119bd413a7b63ee13fa67
1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39 #include "i915_drv.h"
40 #include "gvt.h"
41 #include "i915_pvinfo.h"
42
43 /* XXX FIXME i915 has changed PP_XXX definition */
44 #define PCH_PP_STATUS _MMIO(0xc7200)
45 #define PCH_PP_CONTROL _MMIO(0xc7204)
46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48 #define PCH_PP_DIVISOR _MMIO(0xc7210)
49
50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51 {
52 if (IS_BROADWELL(gvt->dev_priv))
53 return D_BDW;
54 else if (IS_SKYLAKE(gvt->dev_priv))
55 return D_SKL;
56 else if (IS_KABYLAKE(gvt->dev_priv))
57 return D_KBL;
58 else if (IS_BROXTON(gvt->dev_priv))
59 return D_BXT;
60 else if (IS_COFFEELAKE(gvt->dev_priv))
61 return D_CFL;
62
63 return 0;
64 }
65
66 bool intel_gvt_match_device(struct intel_gvt *gvt,
67 unsigned long device)
68 {
69 return intel_gvt_get_device_type(gvt) & device;
70 }
71
72 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
73 void *p_data, unsigned int bytes)
74 {
75 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
76 }
77
78 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
79 void *p_data, unsigned int bytes)
80 {
81 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
82 }
83
84 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
85 unsigned int offset)
86 {
87 struct intel_gvt_mmio_info *e;
88
89 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
90 if (e->offset == offset)
91 return e;
92 }
93 return NULL;
94 }
95
96 static int new_mmio_info(struct intel_gvt *gvt,
97 u32 offset, u8 flags, u32 size,
98 u32 addr_mask, u32 ro_mask, u32 device,
99 gvt_mmio_func read, gvt_mmio_func write)
100 {
101 struct intel_gvt_mmio_info *info, *p;
102 u32 start, end, i;
103
104 if (!intel_gvt_match_device(gvt, device))
105 return 0;
106
107 if (WARN_ON(!IS_ALIGNED(offset, 4)))
108 return -EINVAL;
109
110 start = offset;
111 end = offset + size;
112
113 for (i = start; i < end; i += 4) {
114 info = kzalloc(sizeof(*info), GFP_KERNEL);
115 if (!info)
116 return -ENOMEM;
117
118 info->offset = i;
119 p = find_mmio_info(gvt, info->offset);
120 if (p) {
121 WARN(1, "dup mmio definition offset %x\n",
122 info->offset);
123 kfree(info);
124
125 /* We return -EEXIST here to make GVT-g load fail.
126 * So duplicated MMIO can be found as soon as
127 * possible.
128 */
129 return -EEXIST;
130 }
131
132 info->ro_mask = ro_mask;
133 info->device = device;
134 info->read = read ? read : intel_vgpu_default_mmio_read;
135 info->write = write ? write : intel_vgpu_default_mmio_write;
136 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
137 INIT_HLIST_NODE(&info->node);
138 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
139 gvt->mmio.num_tracked_mmio++;
140 }
141 return 0;
142 }
143
144 /**
145 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id
146 * @gvt: a GVT device
147 * @offset: register offset
148 *
149 * Returns:
150 * Ring ID on success, negative error code if failed.
151 */
152 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
153 unsigned int offset)
154 {
155 enum intel_engine_id id;
156 struct intel_engine_cs *engine;
157
158 offset &= ~GENMASK(11, 0);
159 for_each_engine(engine, gvt->dev_priv, id) {
160 if (engine->mmio_base == offset)
161 return id;
162 }
163 return -ENODEV;
164 }
165
166 #define offset_to_fence_num(offset) \
167 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
168
169 #define fence_num_to_offset(num) \
170 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
171
172
173 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
174 {
175 switch (reason) {
176 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
177 pr_err("Detected your guest driver doesn't support GVT-g.\n");
178 break;
179 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
180 pr_err("Graphics resource is not enough for the guest\n");
181 break;
182 case GVT_FAILSAFE_GUEST_ERR:
183 pr_err("GVT Internal error for the guest\n");
184 break;
185 default:
186 break;
187 }
188 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
189 vgpu->failsafe = true;
190 }
191
192 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
193 unsigned int fence_num, void *p_data, unsigned int bytes)
194 {
195 unsigned int max_fence = vgpu_fence_sz(vgpu);
196
197 if (fence_num >= max_fence) {
198 gvt_vgpu_err("access oob fence reg %d/%d\n",
199 fence_num, max_fence);
200
201 /* When guest access oob fence regs without access
202 * pv_info first, we treat guest not supporting GVT,
203 * and we will let vgpu enter failsafe mode.
204 */
205 if (!vgpu->pv_notified)
206 enter_failsafe_mode(vgpu,
207 GVT_FAILSAFE_UNSUPPORTED_GUEST);
208
209 memset(p_data, 0, bytes);
210 return -EINVAL;
211 }
212 return 0;
213 }
214
215 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
216 unsigned int offset, void *p_data, unsigned int bytes)
217 {
218 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
219
220 if (INTEL_GEN(vgpu->gvt->dev_priv) <= 10) {
221 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
222 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
223 else if (!ips)
224 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
225 else {
226 /* All engines must be enabled together for vGPU,
227 * since we don't know which engine the ppgtt will
228 * bind to when shadowing.
229 */
230 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
231 ips);
232 return -EINVAL;
233 }
234 }
235
236 write_vreg(vgpu, offset, p_data, bytes);
237 return 0;
238 }
239
240 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
241 void *p_data, unsigned int bytes)
242 {
243 int ret;
244
245 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
246 p_data, bytes);
247 if (ret)
248 return ret;
249 read_vreg(vgpu, off, p_data, bytes);
250 return 0;
251 }
252
253 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
254 void *p_data, unsigned int bytes)
255 {
256 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
257 unsigned int fence_num = offset_to_fence_num(off);
258 int ret;
259
260 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
261 if (ret)
262 return ret;
263 write_vreg(vgpu, off, p_data, bytes);
264
265 mmio_hw_access_pre(dev_priv);
266 intel_vgpu_write_fence(vgpu, fence_num,
267 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
268 mmio_hw_access_post(dev_priv);
269 return 0;
270 }
271
272 #define CALC_MODE_MASK_REG(old, new) \
273 (((new) & GENMASK(31, 16)) \
274 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
275 | ((new) & ((new) >> 16))))
276
277 static int mul_force_wake_write(struct intel_vgpu *vgpu,
278 unsigned int offset, void *p_data, unsigned int bytes)
279 {
280 u32 old, new;
281 u32 ack_reg_offset;
282
283 old = vgpu_vreg(vgpu, offset);
284 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
285
286 if (INTEL_GEN(vgpu->gvt->dev_priv) >= 9) {
287 switch (offset) {
288 case FORCEWAKE_RENDER_GEN9_REG:
289 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
290 break;
291 case FORCEWAKE_BLITTER_GEN9_REG:
292 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
293 break;
294 case FORCEWAKE_MEDIA_GEN9_REG:
295 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
296 break;
297 default:
298 /*should not hit here*/
299 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
300 return -EINVAL;
301 }
302 } else {
303 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
304 }
305
306 vgpu_vreg(vgpu, offset) = new;
307 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
308 return 0;
309 }
310
311 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
312 void *p_data, unsigned int bytes)
313 {
314 intel_engine_mask_t engine_mask = 0;
315 u32 data;
316
317 write_vreg(vgpu, offset, p_data, bytes);
318 data = vgpu_vreg(vgpu, offset);
319
320 if (data & GEN6_GRDOM_FULL) {
321 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
322 engine_mask = ALL_ENGINES;
323 } else {
324 if (data & GEN6_GRDOM_RENDER) {
325 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
326 engine_mask |= BIT(RCS0);
327 }
328 if (data & GEN6_GRDOM_MEDIA) {
329 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
330 engine_mask |= BIT(VCS0);
331 }
332 if (data & GEN6_GRDOM_BLT) {
333 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
334 engine_mask |= BIT(BCS0);
335 }
336 if (data & GEN6_GRDOM_VECS) {
337 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
338 engine_mask |= BIT(VECS0);
339 }
340 if (data & GEN8_GRDOM_MEDIA2) {
341 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
342 engine_mask |= BIT(VCS1);
343 }
344 if (data & GEN9_GRDOM_GUC) {
345 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
346 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
347 }
348 engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;
349 }
350
351 /* vgpu_lock already hold by emulate mmio r/w */
352 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
353
354 /* sw will wait for the device to ack the reset request */
355 vgpu_vreg(vgpu, offset) = 0;
356
357 return 0;
358 }
359
360 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
361 void *p_data, unsigned int bytes)
362 {
363 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
364 }
365
366 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
367 void *p_data, unsigned int bytes)
368 {
369 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
370 }
371
372 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
373 unsigned int offset, void *p_data, unsigned int bytes)
374 {
375 write_vreg(vgpu, offset, p_data, bytes);
376
377 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
378 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
379 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
381 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
382
383 } else
384 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
385 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
386 | PP_CYCLE_DELAY_ACTIVE);
387 return 0;
388 }
389
390 static int transconf_mmio_write(struct intel_vgpu *vgpu,
391 unsigned int offset, void *p_data, unsigned int bytes)
392 {
393 write_vreg(vgpu, offset, p_data, bytes);
394
395 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
396 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
397 else
398 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
399 return 0;
400 }
401
402 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
403 void *p_data, unsigned int bytes)
404 {
405 write_vreg(vgpu, offset, p_data, bytes);
406
407 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
408 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
409 else
410 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
411
412 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
413 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
414 else
415 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
416
417 return 0;
418 }
419
420 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
421 void *p_data, unsigned int bytes)
422 {
423 switch (offset) {
424 case 0xe651c:
425 case 0xe661c:
426 case 0xe671c:
427 case 0xe681c:
428 vgpu_vreg(vgpu, offset) = 1 << 17;
429 break;
430 case 0xe6c04:
431 vgpu_vreg(vgpu, offset) = 0x3;
432 break;
433 case 0xe6e1c:
434 vgpu_vreg(vgpu, offset) = 0x2f << 16;
435 break;
436 default:
437 return -EINVAL;
438 }
439
440 read_vreg(vgpu, offset, p_data, bytes);
441 return 0;
442 }
443
444 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
445 void *p_data, unsigned int bytes)
446 {
447 u32 data;
448
449 write_vreg(vgpu, offset, p_data, bytes);
450 data = vgpu_vreg(vgpu, offset);
451
452 if (data & PIPECONF_ENABLE)
453 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
454 else
455 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
456 /* vgpu_lock already hold by emulate mmio r/w */
457 mutex_unlock(&vgpu->vgpu_lock);
458 intel_gvt_check_vblank_emulation(vgpu->gvt);
459 mutex_lock(&vgpu->vgpu_lock);
460 return 0;
461 }
462
463 /* ascendingly sorted */
464 static i915_reg_t force_nonpriv_white_list[] = {
465 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
466 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
467 PS_INVOCATION_COUNT,//_MMIO(0x2348)
468 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
469 _MMIO(0x2690),
470 _MMIO(0x2694),
471 _MMIO(0x2698),
472 _MMIO(0x2754),
473 _MMIO(0x28a0),
474 _MMIO(0x4de0),
475 _MMIO(0x4de4),
476 _MMIO(0x4dfc),
477 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
478 _MMIO(0x7014),
479 HDC_CHICKEN0,//_MMIO(0x7300)
480 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
481 _MMIO(0x7700),
482 _MMIO(0x7704),
483 _MMIO(0x7708),
484 _MMIO(0x770c),
485 _MMIO(0x83a8),
486 _MMIO(0xb110),
487 GEN8_L3SQCREG4,//_MMIO(0xb118)
488 _MMIO(0xe100),
489 _MMIO(0xe18c),
490 _MMIO(0xe48c),
491 _MMIO(0xe5f4),
492 };
493
494 /* a simple bsearch */
495 static inline bool in_whitelist(unsigned int reg)
496 {
497 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
498 i915_reg_t *array = force_nonpriv_white_list;
499
500 while (left < right) {
501 int mid = (left + right)/2;
502
503 if (reg > array[mid].reg)
504 left = mid + 1;
505 else if (reg < array[mid].reg)
506 right = mid;
507 else
508 return true;
509 }
510 return false;
511 }
512
513 static int force_nonpriv_write(struct intel_vgpu *vgpu,
514 unsigned int offset, void *p_data, unsigned int bytes)
515 {
516 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
517 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
518 u32 ring_base;
519 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
520 int ret = -EINVAL;
521
522 if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) {
523 gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n",
524 vgpu->id, ring_id, offset, bytes);
525 return ret;
526 }
527
528 ring_base = dev_priv->engine[ring_id]->mmio_base;
529
530 if (in_whitelist(reg_nonpriv) ||
531 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {
532 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
533 bytes);
534 } else
535 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
536 vgpu->id, *(u32 *)p_data, offset);
537
538 return 0;
539 }
540
541 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
542 void *p_data, unsigned int bytes)
543 {
544 write_vreg(vgpu, offset, p_data, bytes);
545
546 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
547 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
548 } else {
549 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
550 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
551 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
552 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
553 }
554 return 0;
555 }
556
557 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
558 unsigned int offset, void *p_data, unsigned int bytes)
559 {
560 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
561 return 0;
562 }
563
564 #define FDI_LINK_TRAIN_PATTERN1 0
565 #define FDI_LINK_TRAIN_PATTERN2 1
566
567 static int fdi_auto_training_started(struct intel_vgpu *vgpu)
568 {
569 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
570 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
571 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
572
573 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
574 (rx_ctl & FDI_RX_ENABLE) &&
575 (rx_ctl & FDI_AUTO_TRAINING) &&
576 (tx_ctl & DP_TP_CTL_ENABLE) &&
577 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
578 return 1;
579 else
580 return 0;
581 }
582
583 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
584 enum pipe pipe, unsigned int train_pattern)
585 {
586 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
587 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
588 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
589 unsigned int fdi_iir_check_bits;
590
591 fdi_rx_imr = FDI_RX_IMR(pipe);
592 fdi_tx_ctl = FDI_TX_CTL(pipe);
593 fdi_rx_ctl = FDI_RX_CTL(pipe);
594
595 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
596 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
597 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
598 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
599 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
600 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
601 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
602 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
603 } else {
604 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
605 return -EINVAL;
606 }
607
608 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
609 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
610
611 /* If imr bit has been masked */
612 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
613 return 0;
614
615 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
616 == fdi_tx_check_bits)
617 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
618 == fdi_rx_check_bits))
619 return 1;
620 else
621 return 0;
622 }
623
624 #define INVALID_INDEX (~0U)
625
626 static unsigned int calc_index(unsigned int offset, unsigned int start,
627 unsigned int next, unsigned int end, i915_reg_t i915_end)
628 {
629 unsigned int range = next - start;
630
631 if (!end)
632 end = i915_mmio_reg_offset(i915_end);
633 if (offset < start || offset > end)
634 return INVALID_INDEX;
635 offset -= start;
636 return offset / range;
637 }
638
639 #define FDI_RX_CTL_TO_PIPE(offset) \
640 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
641
642 #define FDI_TX_CTL_TO_PIPE(offset) \
643 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
644
645 #define FDI_RX_IMR_TO_PIPE(offset) \
646 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
647
648 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
649 unsigned int offset, void *p_data, unsigned int bytes)
650 {
651 i915_reg_t fdi_rx_iir;
652 unsigned int index;
653 int ret;
654
655 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
656 index = FDI_RX_CTL_TO_PIPE(offset);
657 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
658 index = FDI_TX_CTL_TO_PIPE(offset);
659 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
660 index = FDI_RX_IMR_TO_PIPE(offset);
661 else {
662 gvt_vgpu_err("Unsupport registers %x\n", offset);
663 return -EINVAL;
664 }
665
666 write_vreg(vgpu, offset, p_data, bytes);
667
668 fdi_rx_iir = FDI_RX_IIR(index);
669
670 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
671 if (ret < 0)
672 return ret;
673 if (ret)
674 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
675
676 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
677 if (ret < 0)
678 return ret;
679 if (ret)
680 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
681
682 if (offset == _FDI_RXA_CTL)
683 if (fdi_auto_training_started(vgpu))
684 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
685 DP_TP_STATUS_AUTOTRAIN_DONE;
686 return 0;
687 }
688
689 #define DP_TP_CTL_TO_PORT(offset) \
690 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
691
692 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
693 void *p_data, unsigned int bytes)
694 {
695 i915_reg_t status_reg;
696 unsigned int index;
697 u32 data;
698
699 write_vreg(vgpu, offset, p_data, bytes);
700
701 index = DP_TP_CTL_TO_PORT(offset);
702 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
703 if (data == 0x2) {
704 status_reg = DP_TP_STATUS(index);
705 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
706 }
707 return 0;
708 }
709
710 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
711 unsigned int offset, void *p_data, unsigned int bytes)
712 {
713 u32 reg_val;
714 u32 sticky_mask;
715
716 reg_val = *((u32 *)p_data);
717 sticky_mask = GENMASK(27, 26) | (1 << 24);
718
719 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
720 (vgpu_vreg(vgpu, offset) & sticky_mask);
721 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
722 return 0;
723 }
724
725 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
726 unsigned int offset, void *p_data, unsigned int bytes)
727 {
728 u32 data;
729
730 write_vreg(vgpu, offset, p_data, bytes);
731 data = vgpu_vreg(vgpu, offset);
732
733 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
734 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
735 return 0;
736 }
737
738 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
739 unsigned int offset, void *p_data, unsigned int bytes)
740 {
741 u32 data;
742
743 write_vreg(vgpu, offset, p_data, bytes);
744 data = vgpu_vreg(vgpu, offset);
745
746 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
747 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
748 else
749 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
750 return 0;
751 }
752
753 #define DSPSURF_TO_PIPE(offset) \
754 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
755
756 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
757 void *p_data, unsigned int bytes)
758 {
759 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
760 u32 pipe = DSPSURF_TO_PIPE(offset);
761 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
762
763 write_vreg(vgpu, offset, p_data, bytes);
764 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
765
766 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
767
768 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP)
769 intel_vgpu_trigger_virtual_event(vgpu, event);
770 else
771 set_bit(event, vgpu->irq.flip_done_event[pipe]);
772
773 return 0;
774 }
775
776 #define SPRSURF_TO_PIPE(offset) \
777 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
778
779 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
780 void *p_data, unsigned int bytes)
781 {
782 u32 pipe = SPRSURF_TO_PIPE(offset);
783 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
784
785 write_vreg(vgpu, offset, p_data, bytes);
786 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
787
788 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
789 intel_vgpu_trigger_virtual_event(vgpu, event);
790 else
791 set_bit(event, vgpu->irq.flip_done_event[pipe]);
792
793 return 0;
794 }
795
796 static int reg50080_mmio_write(struct intel_vgpu *vgpu,
797 unsigned int offset, void *p_data,
798 unsigned int bytes)
799 {
800 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
801 enum pipe pipe = REG_50080_TO_PIPE(offset);
802 enum plane_id plane = REG_50080_TO_PLANE(offset);
803 int event = SKL_FLIP_EVENT(pipe, plane);
804
805 write_vreg(vgpu, offset, p_data, bytes);
806 if (plane == PLANE_PRIMARY) {
807 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
808 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
809 } else {
810 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
811 }
812
813 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
814 intel_vgpu_trigger_virtual_event(vgpu, event);
815 else
816 set_bit(event, vgpu->irq.flip_done_event[pipe]);
817
818 return 0;
819 }
820
821 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
822 unsigned int reg)
823 {
824 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
825 enum intel_gvt_event_type event;
826
827 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))
828 event = AUX_CHANNEL_A;
829 else if (reg == _PCH_DPB_AUX_CH_CTL ||
830 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))
831 event = AUX_CHANNEL_B;
832 else if (reg == _PCH_DPC_AUX_CH_CTL ||
833 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))
834 event = AUX_CHANNEL_C;
835 else if (reg == _PCH_DPD_AUX_CH_CTL ||
836 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
837 event = AUX_CHANNEL_D;
838 else {
839 WARN_ON(true);
840 return -EINVAL;
841 }
842
843 intel_vgpu_trigger_virtual_event(vgpu, event);
844 return 0;
845 }
846
847 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
848 unsigned int reg, int len, bool data_valid)
849 {
850 /* mark transaction done */
851 value |= DP_AUX_CH_CTL_DONE;
852 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
853 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
854
855 if (data_valid)
856 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
857 else
858 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
859
860 /* message size */
861 value &= ~(0xf << 20);
862 value |= (len << 20);
863 vgpu_vreg(vgpu, reg) = value;
864
865 if (value & DP_AUX_CH_CTL_INTERRUPT)
866 return trigger_aux_channel_interrupt(vgpu, reg);
867 return 0;
868 }
869
870 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
871 u8 t)
872 {
873 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
874 /* training pattern 1 for CR */
875 /* set LANE0_CR_DONE, LANE1_CR_DONE */
876 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
877 /* set LANE2_CR_DONE, LANE3_CR_DONE */
878 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
879 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
880 DPCD_TRAINING_PATTERN_2) {
881 /* training pattern 2 for EQ */
882 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
883 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
884 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
885 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
886 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
887 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
888 /* set INTERLANE_ALIGN_DONE */
889 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
890 DPCD_INTERLANE_ALIGN_DONE;
891 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
892 DPCD_LINK_TRAINING_DISABLED) {
893 /* finish link training */
894 /* set sink status as synchronized */
895 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
896 }
897 }
898
899 #define _REG_HSW_DP_AUX_CH_CTL(dp) \
900 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
901
902 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
903
904 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
905
906 #define dpy_is_valid_port(port) \
907 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
908
909 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
910 unsigned int offset, void *p_data, unsigned int bytes)
911 {
912 struct intel_vgpu_display *display = &vgpu->display;
913 int msg, addr, ctrl, op, len;
914 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
915 struct intel_vgpu_dpcd_data *dpcd = NULL;
916 struct intel_vgpu_port *port = NULL;
917 u32 data;
918
919 if (!dpy_is_valid_port(port_index)) {
920 gvt_vgpu_err("Unsupported DP port access!\n");
921 return 0;
922 }
923
924 write_vreg(vgpu, offset, p_data, bytes);
925 data = vgpu_vreg(vgpu, offset);
926
927 if ((INTEL_GEN(vgpu->gvt->dev_priv) >= 9)
928 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
929 /* SKL DPB/C/D aux ctl register changed */
930 return 0;
931 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
932 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
933 /* write to the data registers */
934 return 0;
935 }
936
937 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
938 /* just want to clear the sticky bits */
939 vgpu_vreg(vgpu, offset) = 0;
940 return 0;
941 }
942
943 port = &display->ports[port_index];
944 dpcd = port->dpcd;
945
946 /* read out message from DATA1 register */
947 msg = vgpu_vreg(vgpu, offset + 4);
948 addr = (msg >> 8) & 0xffff;
949 ctrl = (msg >> 24) & 0xff;
950 len = msg & 0xff;
951 op = ctrl >> 4;
952
953 if (op == GVT_AUX_NATIVE_WRITE) {
954 int t;
955 u8 buf[16];
956
957 if ((addr + len + 1) >= DPCD_SIZE) {
958 /*
959 * Write request exceeds what we supported,
960 * DCPD spec: When a Source Device is writing a DPCD
961 * address not supported by the Sink Device, the Sink
962 * Device shall reply with AUX NACK and “M” equal to
963 * zero.
964 */
965
966 /* NAK the write */
967 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
968 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
969 return 0;
970 }
971
972 /*
973 * Write request format: Headr (command + address + size) occupies
974 * 4 bytes, followed by (len + 1) bytes of data. See details at
975 * intel_dp_aux_transfer().
976 */
977 if ((len + 1 + 4) > AUX_BURST_SIZE) {
978 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
979 return -EINVAL;
980 }
981
982 /* unpack data from vreg to buf */
983 for (t = 0; t < 4; t++) {
984 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
985
986 buf[t * 4] = (r >> 24) & 0xff;
987 buf[t * 4 + 1] = (r >> 16) & 0xff;
988 buf[t * 4 + 2] = (r >> 8) & 0xff;
989 buf[t * 4 + 3] = r & 0xff;
990 }
991
992 /* write to virtual DPCD */
993 if (dpcd && dpcd->data_valid) {
994 for (t = 0; t <= len; t++) {
995 int p = addr + t;
996
997 dpcd->data[p] = buf[t];
998 /* check for link training */
999 if (p == DPCD_TRAINING_PATTERN_SET)
1000 dp_aux_ch_ctl_link_training(dpcd,
1001 buf[t]);
1002 }
1003 }
1004
1005 /* ACK the write */
1006 vgpu_vreg(vgpu, offset + 4) = 0;
1007 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
1008 dpcd && dpcd->data_valid);
1009 return 0;
1010 }
1011
1012 if (op == GVT_AUX_NATIVE_READ) {
1013 int idx, i, ret = 0;
1014
1015 if ((addr + len + 1) >= DPCD_SIZE) {
1016 /*
1017 * read request exceeds what we supported
1018 * DPCD spec: A Sink Device receiving a Native AUX CH
1019 * read request for an unsupported DPCD address must
1020 * reply with an AUX ACK and read data set equal to
1021 * zero instead of replying with AUX NACK.
1022 */
1023
1024 /* ACK the READ*/
1025 vgpu_vreg(vgpu, offset + 4) = 0;
1026 vgpu_vreg(vgpu, offset + 8) = 0;
1027 vgpu_vreg(vgpu, offset + 12) = 0;
1028 vgpu_vreg(vgpu, offset + 16) = 0;
1029 vgpu_vreg(vgpu, offset + 20) = 0;
1030
1031 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1032 true);
1033 return 0;
1034 }
1035
1036 for (idx = 1; idx <= 5; idx++) {
1037 /* clear the data registers */
1038 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1039 }
1040
1041 /*
1042 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1043 */
1044 if ((len + 2) > AUX_BURST_SIZE) {
1045 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1046 return -EINVAL;
1047 }
1048
1049 /* read from virtual DPCD to vreg */
1050 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
1051 if (dpcd && dpcd->data_valid) {
1052 for (i = 1; i <= (len + 1); i++) {
1053 int t;
1054
1055 t = dpcd->data[addr + i - 1];
1056 t <<= (24 - 8 * (i % 4));
1057 ret |= t;
1058
1059 if ((i % 4 == 3) || (i == (len + 1))) {
1060 vgpu_vreg(vgpu, offset +
1061 (i / 4 + 1) * 4) = ret;
1062 ret = 0;
1063 }
1064 }
1065 }
1066 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1067 dpcd && dpcd->data_valid);
1068 return 0;
1069 }
1070
1071 /* i2c transaction starts */
1072 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1073
1074 if (data & DP_AUX_CH_CTL_INTERRUPT)
1075 trigger_aux_channel_interrupt(vgpu, offset);
1076 return 0;
1077 }
1078
1079 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1080 void *p_data, unsigned int bytes)
1081 {
1082 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1083 write_vreg(vgpu, offset, p_data, bytes);
1084 return 0;
1085 }
1086
1087 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1088 void *p_data, unsigned int bytes)
1089 {
1090 bool vga_disable;
1091
1092 write_vreg(vgpu, offset, p_data, bytes);
1093 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1094
1095 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1096 vga_disable ? "Disable" : "Enable");
1097 return 0;
1098 }
1099
1100 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1101 unsigned int sbi_offset)
1102 {
1103 struct intel_vgpu_display *display = &vgpu->display;
1104 int num = display->sbi.number;
1105 int i;
1106
1107 for (i = 0; i < num; ++i)
1108 if (display->sbi.registers[i].offset == sbi_offset)
1109 break;
1110
1111 if (i == num)
1112 return 0;
1113
1114 return display->sbi.registers[i].value;
1115 }
1116
1117 static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1118 unsigned int offset, u32 value)
1119 {
1120 struct intel_vgpu_display *display = &vgpu->display;
1121 int num = display->sbi.number;
1122 int i;
1123
1124 for (i = 0; i < num; ++i) {
1125 if (display->sbi.registers[i].offset == offset)
1126 break;
1127 }
1128
1129 if (i == num) {
1130 if (num == SBI_REG_MAX) {
1131 gvt_vgpu_err("SBI caching meets maximum limits\n");
1132 return;
1133 }
1134 display->sbi.number++;
1135 }
1136
1137 display->sbi.registers[i].offset = offset;
1138 display->sbi.registers[i].value = value;
1139 }
1140
1141 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1142 void *p_data, unsigned int bytes)
1143 {
1144 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1145 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1146 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1147 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1148 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1149 sbi_offset);
1150 }
1151 read_vreg(vgpu, offset, p_data, bytes);
1152 return 0;
1153 }
1154
1155 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1156 void *p_data, unsigned int bytes)
1157 {
1158 u32 data;
1159
1160 write_vreg(vgpu, offset, p_data, bytes);
1161 data = vgpu_vreg(vgpu, offset);
1162
1163 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1164 data |= SBI_READY;
1165
1166 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1167 data |= SBI_RESPONSE_SUCCESS;
1168
1169 vgpu_vreg(vgpu, offset) = data;
1170
1171 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1172 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1173 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1174 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1175
1176 write_virtual_sbi_register(vgpu, sbi_offset,
1177 vgpu_vreg_t(vgpu, SBI_DATA));
1178 }
1179 return 0;
1180 }
1181
1182 #define _vgtif_reg(x) \
1183 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1184
1185 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1186 void *p_data, unsigned int bytes)
1187 {
1188 bool invalid_read = false;
1189
1190 read_vreg(vgpu, offset, p_data, bytes);
1191
1192 switch (offset) {
1193 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1194 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1195 invalid_read = true;
1196 break;
1197 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1198 _vgtif_reg(avail_rs.fence_num):
1199 if (offset + bytes >
1200 _vgtif_reg(avail_rs.fence_num) + 4)
1201 invalid_read = true;
1202 break;
1203 case 0x78010: /* vgt_caps */
1204 case 0x7881c:
1205 break;
1206 default:
1207 invalid_read = true;
1208 break;
1209 }
1210 if (invalid_read)
1211 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1212 offset, bytes, *(u32 *)p_data);
1213 vgpu->pv_notified = true;
1214 return 0;
1215 }
1216
1217 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1218 {
1219 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1220 struct intel_vgpu_mm *mm;
1221 u64 *pdps;
1222
1223 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1224
1225 switch (notification) {
1226 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1227 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1228 /* fall through */
1229 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1230 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1231 return PTR_ERR_OR_ZERO(mm);
1232 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1233 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1234 return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
1235 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1236 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1237 case 1: /* Remove this in guest driver. */
1238 break;
1239 default:
1240 gvt_vgpu_err("Invalid PV notification %d\n", notification);
1241 }
1242 return 0;
1243 }
1244
1245 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1246 {
1247 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1248 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1249 char *env[3] = {NULL, NULL, NULL};
1250 char vmid_str[20];
1251 char display_ready_str[20];
1252
1253 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1254 env[0] = display_ready_str;
1255
1256 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1257 env[1] = vmid_str;
1258
1259 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1260 }
1261
1262 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1263 void *p_data, unsigned int bytes)
1264 {
1265 u32 data = *(u32 *)p_data;
1266 bool invalid_write = false;
1267
1268 switch (offset) {
1269 case _vgtif_reg(display_ready):
1270 send_display_ready_uevent(vgpu, data ? 1 : 0);
1271 break;
1272 case _vgtif_reg(g2v_notify):
1273 handle_g2v_notification(vgpu, data);
1274 break;
1275 /* add xhot and yhot to handled list to avoid error log */
1276 case _vgtif_reg(cursor_x_hot):
1277 case _vgtif_reg(cursor_y_hot):
1278 case _vgtif_reg(pdp[0].lo):
1279 case _vgtif_reg(pdp[0].hi):
1280 case _vgtif_reg(pdp[1].lo):
1281 case _vgtif_reg(pdp[1].hi):
1282 case _vgtif_reg(pdp[2].lo):
1283 case _vgtif_reg(pdp[2].hi):
1284 case _vgtif_reg(pdp[3].lo):
1285 case _vgtif_reg(pdp[3].hi):
1286 case _vgtif_reg(execlist_context_descriptor_lo):
1287 case _vgtif_reg(execlist_context_descriptor_hi):
1288 break;
1289 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1290 invalid_write = true;
1291 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1292 break;
1293 default:
1294 invalid_write = true;
1295 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1296 offset, bytes, data);
1297 break;
1298 }
1299
1300 if (!invalid_write)
1301 write_vreg(vgpu, offset, p_data, bytes);
1302
1303 return 0;
1304 }
1305
1306 static int pf_write(struct intel_vgpu *vgpu,
1307 unsigned int offset, void *p_data, unsigned int bytes)
1308 {
1309 u32 val = *(u32 *)p_data;
1310
1311 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1312 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1313 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1314 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1315 vgpu->id);
1316 return 0;
1317 }
1318
1319 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1320 }
1321
1322 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1323 unsigned int offset, void *p_data, unsigned int bytes)
1324 {
1325 write_vreg(vgpu, offset, p_data, bytes);
1326
1327 if (vgpu_vreg(vgpu, offset) &
1328 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1329 vgpu_vreg(vgpu, offset) |=
1330 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1331 else
1332 vgpu_vreg(vgpu, offset) &=
1333 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1334 return 0;
1335 }
1336
1337 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,
1338 unsigned int offset, void *p_data, unsigned int bytes)
1339 {
1340 write_vreg(vgpu, offset, p_data, bytes);
1341
1342 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
1343 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
1344 else
1345 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
1346
1347 return 0;
1348 }
1349
1350 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1351 unsigned int offset, void *p_data, unsigned int bytes)
1352 {
1353 write_vreg(vgpu, offset, p_data, bytes);
1354
1355 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1356 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1357 return 0;
1358 }
1359
1360 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1361 void *p_data, unsigned int bytes)
1362 {
1363 u32 mode;
1364
1365 write_vreg(vgpu, offset, p_data, bytes);
1366 mode = vgpu_vreg(vgpu, offset);
1367
1368 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1369 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
1370 vgpu->id);
1371 return 0;
1372 }
1373
1374 return 0;
1375 }
1376
1377 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1378 void *p_data, unsigned int bytes)
1379 {
1380 u32 trtte = *(u32 *)p_data;
1381
1382 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1383 WARN(1, "VM(%d): Use physical address for TRTT!\n",
1384 vgpu->id);
1385 return -EINVAL;
1386 }
1387 write_vreg(vgpu, offset, p_data, bytes);
1388
1389 return 0;
1390 }
1391
1392 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1393 void *p_data, unsigned int bytes)
1394 {
1395 write_vreg(vgpu, offset, p_data, bytes);
1396 return 0;
1397 }
1398
1399 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1400 void *p_data, unsigned int bytes)
1401 {
1402 u32 v = 0;
1403
1404 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1405 v |= (1 << 0);
1406
1407 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1408 v |= (1 << 8);
1409
1410 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1411 v |= (1 << 16);
1412
1413 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1414 v |= (1 << 24);
1415
1416 vgpu_vreg(vgpu, offset) = v;
1417
1418 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1419 }
1420
1421 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1422 void *p_data, unsigned int bytes)
1423 {
1424 u32 value = *(u32 *)p_data;
1425 u32 cmd = value & 0xff;
1426 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
1427
1428 switch (cmd) {
1429 case GEN9_PCODE_READ_MEM_LATENCY:
1430 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1431 || IS_KABYLAKE(vgpu->gvt->dev_priv)
1432 || IS_COFFEELAKE(vgpu->gvt->dev_priv)) {
1433 /**
1434 * "Read memory latency" command on gen9.
1435 * Below memory latency values are read
1436 * from skylake platform.
1437 */
1438 if (!*data0)
1439 *data0 = 0x1e1a1100;
1440 else
1441 *data0 = 0x61514b3d;
1442 } else if (IS_BROXTON(vgpu->gvt->dev_priv)) {
1443 /**
1444 * "Read memory latency" command on gen9.
1445 * Below memory latency values are read
1446 * from Broxton MRB.
1447 */
1448 if (!*data0)
1449 *data0 = 0x16080707;
1450 else
1451 *data0 = 0x16161616;
1452 }
1453 break;
1454 case SKL_PCODE_CDCLK_CONTROL:
1455 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1456 || IS_KABYLAKE(vgpu->gvt->dev_priv)
1457 || IS_COFFEELAKE(vgpu->gvt->dev_priv))
1458 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
1459 break;
1460 case GEN6_PCODE_READ_RC6VIDS:
1461 *data0 |= 0x1;
1462 break;
1463 }
1464
1465 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1466 vgpu->id, value, *data0);
1467 /**
1468 * PCODE_READY clear means ready for pcode read/write,
1469 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1470 * always emulate as pcode read/write success and ready for access
1471 * anytime, since we don't touch real physical registers here.
1472 */
1473 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1474 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1475 }
1476
1477 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1478 void *p_data, unsigned int bytes)
1479 {
1480 u32 value = *(u32 *)p_data;
1481 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1482
1483 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1484 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1485 offset, value);
1486 return -EINVAL;
1487 }
1488 /*
1489 * Need to emulate all the HWSP register write to ensure host can
1490 * update the VM CSB status correctly. Here listed registers can
1491 * support BDW, SKL or other platforms with same HWSP registers.
1492 */
1493 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) {
1494 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1495 offset);
1496 return -EINVAL;
1497 }
1498 vgpu->hws_pga[ring_id] = value;
1499 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1500 vgpu->id, value, offset);
1501
1502 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1503 }
1504
1505 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1506 unsigned int offset, void *p_data, unsigned int bytes)
1507 {
1508 u32 v = *(u32 *)p_data;
1509
1510 if (IS_BROXTON(vgpu->gvt->dev_priv))
1511 v &= (1 << 31) | (1 << 29);
1512 else
1513 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1514 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1515 v |= (v >> 1);
1516
1517 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1518 }
1519
1520 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1521 void *p_data, unsigned int bytes)
1522 {
1523 u32 v = *(u32 *)p_data;
1524
1525 /* other bits are MBZ. */
1526 v &= (1 << 31) | (1 << 30);
1527 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1528
1529 vgpu_vreg(vgpu, offset) = v;
1530
1531 return 0;
1532 }
1533
1534 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
1535 unsigned int offset, void *p_data, unsigned int bytes)
1536 {
1537 u32 v = *(u32 *)p_data;
1538
1539 if (v & BXT_DE_PLL_PLL_ENABLE)
1540 v |= BXT_DE_PLL_LOCK;
1541
1542 vgpu_vreg(vgpu, offset) = v;
1543
1544 return 0;
1545 }
1546
1547 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
1548 unsigned int offset, void *p_data, unsigned int bytes)
1549 {
1550 u32 v = *(u32 *)p_data;
1551
1552 if (v & PORT_PLL_ENABLE)
1553 v |= PORT_PLL_LOCK;
1554
1555 vgpu_vreg(vgpu, offset) = v;
1556
1557 return 0;
1558 }
1559
1560 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
1561 unsigned int offset, void *p_data, unsigned int bytes)
1562 {
1563 u32 v = *(u32 *)p_data;
1564 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1565
1566 switch (offset) {
1567 case _PHY_CTL_FAMILY_EDP:
1568 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1569 break;
1570 case _PHY_CTL_FAMILY_DDI:
1571 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1572 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1573 break;
1574 }
1575
1576 vgpu_vreg(vgpu, offset) = v;
1577
1578 return 0;
1579 }
1580
1581 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
1582 unsigned int offset, void *p_data, unsigned int bytes)
1583 {
1584 u32 v = vgpu_vreg(vgpu, offset);
1585
1586 v &= ~UNIQUE_TRANGE_EN_METHOD;
1587
1588 vgpu_vreg(vgpu, offset) = v;
1589
1590 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1591 }
1592
1593 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
1594 unsigned int offset, void *p_data, unsigned int bytes)
1595 {
1596 u32 v = *(u32 *)p_data;
1597
1598 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
1599 vgpu_vreg(vgpu, offset - 0x600) = v;
1600 vgpu_vreg(vgpu, offset - 0x800) = v;
1601 } else {
1602 vgpu_vreg(vgpu, offset - 0x400) = v;
1603 vgpu_vreg(vgpu, offset - 0x600) = v;
1604 }
1605
1606 vgpu_vreg(vgpu, offset) = v;
1607
1608 return 0;
1609 }
1610
1611 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1612 unsigned int offset, void *p_data, unsigned int bytes)
1613 {
1614 u32 v = *(u32 *)p_data;
1615
1616 if (v & BIT(0)) {
1617 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
1618 ~PHY_RESERVED;
1619 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
1620 PHY_POWER_GOOD;
1621 }
1622
1623 if (v & BIT(1)) {
1624 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
1625 ~PHY_RESERVED;
1626 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
1627 PHY_POWER_GOOD;
1628 }
1629
1630
1631 vgpu_vreg(vgpu, offset) = v;
1632
1633 return 0;
1634 }
1635
1636 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1637 unsigned int offset, void *p_data, unsigned int bytes)
1638 {
1639 vgpu_vreg(vgpu, offset) = 0;
1640 return 0;
1641 }
1642
1643 static int guc_status_read(struct intel_vgpu *vgpu,
1644 unsigned int offset, void *p_data,
1645 unsigned int bytes)
1646 {
1647 /* keep MIA_IN_RESET before clearing */
1648 read_vreg(vgpu, offset, p_data, bytes);
1649 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;
1650 return 0;
1651 }
1652
1653 static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1654 unsigned int offset, void *p_data, unsigned int bytes)
1655 {
1656 struct intel_gvt *gvt = vgpu->gvt;
1657 struct drm_i915_private *dev_priv = gvt->dev_priv;
1658 int ring_id;
1659 u32 ring_base;
1660
1661 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset);
1662 /**
1663 * Read HW reg in following case
1664 * a. the offset isn't a ring mmio
1665 * b. the offset's ring is running on hw.
1666 * c. the offset is ring time stamp mmio
1667 */
1668 if (ring_id >= 0)
1669 ring_base = dev_priv->engine[ring_id]->mmio_base;
1670
1671 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] ||
1672 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) ||
1673 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) {
1674 mmio_hw_access_pre(dev_priv);
1675 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1676 mmio_hw_access_post(dev_priv);
1677 }
1678
1679 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1680 }
1681
1682 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1683 void *p_data, unsigned int bytes)
1684 {
1685 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1686 struct intel_vgpu_execlist *execlist;
1687 u32 data = *(u32 *)p_data;
1688 int ret = 0;
1689
1690 if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
1691 return -EINVAL;
1692
1693 execlist = &vgpu->submission.execlist[ring_id];
1694
1695 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
1696 if (execlist->elsp_dwords.index == 3) {
1697 ret = intel_vgpu_submit_execlist(vgpu, ring_id);
1698 if(ret)
1699 gvt_vgpu_err("fail submit workload on ring %d\n",
1700 ring_id);
1701 }
1702
1703 ++execlist->elsp_dwords.index;
1704 execlist->elsp_dwords.index &= 0x3;
1705 return ret;
1706 }
1707
1708 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1709 void *p_data, unsigned int bytes)
1710 {
1711 u32 data = *(u32 *)p_data;
1712 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1713 bool enable_execlist;
1714 int ret;
1715
1716 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
1717 if (IS_COFFEELAKE(vgpu->gvt->dev_priv))
1718 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
1719 write_vreg(vgpu, offset, p_data, bytes);
1720
1721 if (data & _MASKED_BIT_ENABLE(1)) {
1722 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1723 return 0;
1724 }
1725
1726 if (IS_COFFEELAKE(vgpu->gvt->dev_priv) &&
1727 data & _MASKED_BIT_ENABLE(2)) {
1728 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1729 return 0;
1730 }
1731
1732 /* when PPGTT mode enabled, we will check if guest has called
1733 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1734 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1735 */
1736 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1737 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1738 && !vgpu->pv_notified) {
1739 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1740 return 0;
1741 }
1742 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1743 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1744 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1745
1746 gvt_dbg_core("EXECLIST %s on ring %d\n",
1747 (enable_execlist ? "enabling" : "disabling"),
1748 ring_id);
1749
1750 if (!enable_execlist)
1751 return 0;
1752
1753 ret = intel_vgpu_select_submission_ops(vgpu,
1754 BIT(ring_id),
1755 INTEL_VGPU_EXECLIST_SUBMISSION);
1756 if (ret)
1757 return ret;
1758
1759 intel_vgpu_start_schedule(vgpu);
1760 }
1761 return 0;
1762 }
1763
1764 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1765 unsigned int offset, void *p_data, unsigned int bytes)
1766 {
1767 unsigned int id = 0;
1768
1769 write_vreg(vgpu, offset, p_data, bytes);
1770 vgpu_vreg(vgpu, offset) = 0;
1771
1772 switch (offset) {
1773 case 0x4260:
1774 id = RCS0;
1775 break;
1776 case 0x4264:
1777 id = VCS0;
1778 break;
1779 case 0x4268:
1780 id = VCS1;
1781 break;
1782 case 0x426c:
1783 id = BCS0;
1784 break;
1785 case 0x4270:
1786 id = VECS0;
1787 break;
1788 default:
1789 return -EINVAL;
1790 }
1791 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
1792
1793 return 0;
1794 }
1795
1796 static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1797 unsigned int offset, void *p_data, unsigned int bytes)
1798 {
1799 u32 data;
1800
1801 write_vreg(vgpu, offset, p_data, bytes);
1802 data = vgpu_vreg(vgpu, offset);
1803
1804 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1805 data |= RESET_CTL_READY_TO_RESET;
1806 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1807 data &= ~RESET_CTL_READY_TO_RESET;
1808
1809 vgpu_vreg(vgpu, offset) = data;
1810 return 0;
1811 }
1812
1813 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
1814 unsigned int offset, void *p_data,
1815 unsigned int bytes)
1816 {
1817 u32 data = *(u32 *)p_data;
1818
1819 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
1820 write_vreg(vgpu, offset, p_data, bytes);
1821
1822 if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8))
1823 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1824
1825 return 0;
1826 }
1827
1828 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1829 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
1830 f, s, am, rm, d, r, w); \
1831 if (ret) \
1832 return ret; \
1833 } while (0)
1834
1835 #define MMIO_D(reg, d) \
1836 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1837
1838 #define MMIO_DH(reg, d, r, w) \
1839 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1840
1841 #define MMIO_DFH(reg, d, f, r, w) \
1842 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1843
1844 #define MMIO_GM(reg, d, r, w) \
1845 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1846
1847 #define MMIO_GM_RDR(reg, d, r, w) \
1848 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1849
1850 #define MMIO_RO(reg, d, f, rm, r, w) \
1851 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1852
1853 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1854 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1855 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1856 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1857 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1858 if (HAS_ENGINE(dev_priv, VCS1)) \
1859 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
1860 } while (0)
1861
1862 #define MMIO_RING_D(prefix, d) \
1863 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1864
1865 #define MMIO_RING_DFH(prefix, d, f, r, w) \
1866 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1867
1868 #define MMIO_RING_GM(prefix, d, r, w) \
1869 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1870
1871 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
1872 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1873
1874 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1875 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1876
1877 static int init_generic_mmio_info(struct intel_gvt *gvt)
1878 {
1879 struct drm_i915_private *dev_priv = gvt->dev_priv;
1880 int ret;
1881
1882 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1883 intel_vgpu_reg_imr_handler);
1884
1885 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1886 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1887 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1888 MMIO_D(SDEISR, D_ALL);
1889
1890 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
1891
1892 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
1893 gamw_echo_dev_rw_ia_write);
1894
1895 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1896 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1897 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1898
1899 #define RING_REG(base) _MMIO((base) + 0x28)
1900 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1901 #undef RING_REG
1902
1903 #define RING_REG(base) _MMIO((base) + 0x134)
1904 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1905 #undef RING_REG
1906
1907 #define RING_REG(base) _MMIO((base) + 0x6c)
1908 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
1909 #undef RING_REG
1910 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
1911
1912 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
1913 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
1914 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
1915 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1916
1917 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1918 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1919 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1920 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
1921 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
1922
1923 /* RING MODE */
1924 #define RING_REG(base) _MMIO((base) + 0x29c)
1925 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1926 ring_mode_mmio_write);
1927 #undef RING_REG
1928
1929 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1930 NULL, NULL);
1931 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1932 NULL, NULL);
1933 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1934 mmio_read_from_hw, NULL);
1935 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1936 mmio_read_from_hw, NULL);
1937
1938 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1939 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1940 NULL, NULL);
1941 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1942 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1943 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1944
1945 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1946 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1947 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1948 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
1949 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1950 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1951 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1952 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1953 NULL, NULL);
1954 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1955 NULL, NULL);
1956 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
1957 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
1958 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
1959 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
1960 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
1961 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
1962 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
1963 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1964 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1965 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1966
1967 /* display */
1968 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1969 MMIO_D(_MMIO(0x602a0), D_ALL);
1970
1971 MMIO_D(_MMIO(0x65050), D_ALL);
1972 MMIO_D(_MMIO(0x650b4), D_ALL);
1973
1974 MMIO_D(_MMIO(0xc4040), D_ALL);
1975 MMIO_D(DERRMR, D_ALL);
1976
1977 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1978 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1979 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1980 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1981
1982 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1983 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1984 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1985 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
1986
1987 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1988 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1989 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1990 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1991
1992 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1993 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1994 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1995 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1996
1997 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
1998 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
1999 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
2000 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
2001
2002 MMIO_D(CURCNTR(PIPE_A), D_ALL);
2003 MMIO_D(CURCNTR(PIPE_B), D_ALL);
2004 MMIO_D(CURCNTR(PIPE_C), D_ALL);
2005
2006 MMIO_D(CURPOS(PIPE_A), D_ALL);
2007 MMIO_D(CURPOS(PIPE_B), D_ALL);
2008 MMIO_D(CURPOS(PIPE_C), D_ALL);
2009
2010 MMIO_D(CURBASE(PIPE_A), D_ALL);
2011 MMIO_D(CURBASE(PIPE_B), D_ALL);
2012 MMIO_D(CURBASE(PIPE_C), D_ALL);
2013
2014 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
2015 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
2016 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
2017
2018 MMIO_D(_MMIO(0x700ac), D_ALL);
2019 MMIO_D(_MMIO(0x710ac), D_ALL);
2020 MMIO_D(_MMIO(0x720ac), D_ALL);
2021
2022 MMIO_D(_MMIO(0x70090), D_ALL);
2023 MMIO_D(_MMIO(0x70094), D_ALL);
2024 MMIO_D(_MMIO(0x70098), D_ALL);
2025 MMIO_D(_MMIO(0x7009c), D_ALL);
2026
2027 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
2028 MMIO_D(DSPADDR(PIPE_A), D_ALL);
2029 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
2030 MMIO_D(DSPPOS(PIPE_A), D_ALL);
2031 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
2032 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
2033 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
2034 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
2035 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
2036 reg50080_mmio_write);
2037
2038 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
2039 MMIO_D(DSPADDR(PIPE_B), D_ALL);
2040 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
2041 MMIO_D(DSPPOS(PIPE_B), D_ALL);
2042 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
2043 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
2044 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
2045 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
2046 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
2047 reg50080_mmio_write);
2048
2049 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
2050 MMIO_D(DSPADDR(PIPE_C), D_ALL);
2051 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
2052 MMIO_D(DSPPOS(PIPE_C), D_ALL);
2053 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
2054 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
2055 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
2056 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
2057 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2058 reg50080_mmio_write);
2059
2060 MMIO_D(SPRCTL(PIPE_A), D_ALL);
2061 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
2062 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
2063 MMIO_D(SPRPOS(PIPE_A), D_ALL);
2064 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
2065 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
2066 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
2067 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
2068 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
2069 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
2070 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
2071 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
2072 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
2073 reg50080_mmio_write);
2074
2075 MMIO_D(SPRCTL(PIPE_B), D_ALL);
2076 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
2077 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
2078 MMIO_D(SPRPOS(PIPE_B), D_ALL);
2079 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
2080 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
2081 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
2082 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
2083 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
2084 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
2085 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
2086 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
2087 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
2088 reg50080_mmio_write);
2089
2090 MMIO_D(SPRCTL(PIPE_C), D_ALL);
2091 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
2092 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
2093 MMIO_D(SPRPOS(PIPE_C), D_ALL);
2094 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
2095 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
2096 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
2097 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
2098 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
2099 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
2100 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
2101 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
2102 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
2103 reg50080_mmio_write);
2104
2105 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
2106 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
2107 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
2108 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
2109 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
2110 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
2111 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
2112 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
2113 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
2114
2115 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
2116 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
2117 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
2118 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
2119 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
2120 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
2121 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
2122 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
2123 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
2124
2125 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
2126 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
2127 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
2128 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
2129 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
2130 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
2131 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
2132 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
2133 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
2134
2135 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
2136 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
2137 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
2138 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
2139 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
2140 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
2141 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
2142 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
2143
2144 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
2145 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
2146 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
2147 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
2148 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
2149 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
2150 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
2151 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
2152
2153 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
2154 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
2155 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
2156 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
2157 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
2158 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
2159 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
2160 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
2161
2162 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
2163 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
2164 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
2165 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
2166 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
2167 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
2168 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
2169 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
2170
2171 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
2172 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
2173 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
2174 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
2175 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
2176 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
2177 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
2178 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
2179
2180 MMIO_D(PF_CTL(PIPE_A), D_ALL);
2181 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
2182 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
2183 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
2184 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
2185
2186 MMIO_D(PF_CTL(PIPE_B), D_ALL);
2187 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
2188 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
2189 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
2190 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
2191
2192 MMIO_D(PF_CTL(PIPE_C), D_ALL);
2193 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
2194 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
2195 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
2196 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
2197
2198 MMIO_D(WM0_PIPEA_ILK, D_ALL);
2199 MMIO_D(WM0_PIPEB_ILK, D_ALL);
2200 MMIO_D(WM0_PIPEC_IVB, D_ALL);
2201 MMIO_D(WM1_LP_ILK, D_ALL);
2202 MMIO_D(WM2_LP_ILK, D_ALL);
2203 MMIO_D(WM3_LP_ILK, D_ALL);
2204 MMIO_D(WM1S_LP_ILK, D_ALL);
2205 MMIO_D(WM2S_LP_IVB, D_ALL);
2206 MMIO_D(WM3S_LP_IVB, D_ALL);
2207
2208 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
2209 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
2210 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
2211 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
2212
2213 MMIO_D(_MMIO(0x48268), D_ALL);
2214
2215 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2216 gmbus_mmio_write);
2217 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2218 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
2219
2220 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2221 dp_aux_ch_ctl_mmio_write);
2222 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2223 dp_aux_ch_ctl_mmio_write);
2224 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2225 dp_aux_ch_ctl_mmio_write);
2226
2227 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
2228
2229 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
2230 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
2231
2232 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2233 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2234 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2235 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2236 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2237 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2238 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2239 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2240 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2241
2242 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
2243 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
2244 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
2245 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
2246 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
2247 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
2248 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
2249
2250 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
2251 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
2252 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
2253 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
2254 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
2255 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
2256 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
2257
2258 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
2259 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
2260 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
2261 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
2262 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
2263 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
2264 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
2265 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
2266
2267 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
2268 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
2269 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
2270
2271 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
2272 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
2273 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
2274
2275 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
2276 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
2277 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
2278
2279 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
2280 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
2281 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
2282
2283 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
2284 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
2285 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
2286 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
2287 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
2288 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
2289
2290 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
2291 MMIO_D(PCH_PP_DIVISOR, D_ALL);
2292 MMIO_D(PCH_PP_STATUS, D_ALL);
2293 MMIO_D(PCH_LVDS, D_ALL);
2294 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
2295 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
2296 MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
2297 MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
2298 MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
2299 MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
2300 MMIO_D(PCH_DREF_CONTROL, D_ALL);
2301 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2302 MMIO_D(PCH_DPLL_SEL, D_ALL);
2303
2304 MMIO_D(_MMIO(0x61208), D_ALL);
2305 MMIO_D(_MMIO(0x6120c), D_ALL);
2306 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2307 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2308
2309 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2310 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2311 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2312 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2313 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2314 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2315
2316 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2317 PORTA_HOTPLUG_STATUS_MASK
2318 | PORTB_HOTPLUG_STATUS_MASK
2319 | PORTC_HOTPLUG_STATUS_MASK
2320 | PORTD_HOTPLUG_STATUS_MASK,
2321 NULL, NULL);
2322
2323 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2324 MMIO_D(FUSE_STRAP, D_ALL);
2325 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2326
2327 MMIO_D(DISP_ARB_CTL, D_ALL);
2328 MMIO_D(DISP_ARB_CTL2, D_ALL);
2329
2330 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2331 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2332 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2333
2334 MMIO_D(SOUTH_CHICKEN1, D_ALL);
2335 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2336 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
2337 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
2338 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2339 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
2340 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
2341
2342 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2343 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2344 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2345 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2346 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2347 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2348 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2349
2350 MMIO_D(IPS_CTL, D_ALL);
2351
2352 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2353 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2354 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2355 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2356 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2357 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2358 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2359 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2360 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2361 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2362 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2363 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2364 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2365
2366 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2367 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2368 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2369 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2370 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2371 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2372 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2373 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2374 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2375 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2376 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2377 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2378 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2379
2380 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2381 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2382 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2383 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2384 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2385 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2386 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2387 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2388 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2389 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2390 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2391 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2392 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2393
2394 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2395 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2396 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2397
2398 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2399 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2400 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2401
2402 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2403 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2404 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2405
2406 MMIO_D(_MMIO(0x60110), D_ALL);
2407 MMIO_D(_MMIO(0x61110), D_ALL);
2408 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2409 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2410 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2411 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2412 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2413 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2414 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2415 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2416 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2417
2418 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2419 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2420 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2421 MMIO_D(SPLL_CTL, D_ALL);
2422 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
2423 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
2424 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2425 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2426 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2427 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2428 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2429 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2430 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2431 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2432
2433 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2434 MMIO_D(_MMIO(0x46508), D_ALL);
2435
2436 MMIO_D(_MMIO(0x49080), D_ALL);
2437 MMIO_D(_MMIO(0x49180), D_ALL);
2438 MMIO_D(_MMIO(0x49280), D_ALL);
2439
2440 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2441 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2442 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2443
2444 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2445 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2446 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2447
2448 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2449 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2450 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2451
2452 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2453 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2454 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2455
2456 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2457 MMIO_D(SBI_ADDR, D_ALL);
2458 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2459 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2460 MMIO_D(PIXCLK_GATE, D_ALL);
2461
2462 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
2463 dp_aux_ch_ctl_mmio_write);
2464
2465 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2466 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2467 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2468 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2469 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2470
2471 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2472 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2473 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2474 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2475 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2476
2477 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2478 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2479 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2480 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2481 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2482
2483 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2484 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2485 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2486 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2487 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2488
2489 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2490 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2491 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
2492
2493 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2494 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2495 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2496 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
2497
2498 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
2499 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
2500 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
2501 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
2502
2503 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2504 MMIO_D(FORCEWAKE_ACK, D_ALL);
2505 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2506 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
2507 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2508 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2509 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2510 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2511 MMIO_D(ECOBUS, D_ALL);
2512 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2513 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2514 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2515 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2516 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2517 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2518 MMIO_D(GEN6_RPSTAT1, D_ALL);
2519 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2520 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2521 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2522 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2523 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2524 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2525 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2526 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2527 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2528 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2529 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2530 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2531 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2532 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2533 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2534 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2535 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2536 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2537 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2538 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2539 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2540 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2541 MMIO_D(GEN6_PMINTRMSK, D_ALL);
2542 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2543 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2544 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2545 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
2546 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2547 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2548
2549 MMIO_D(RSTDBYCTL, D_ALL);
2550
2551 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2552 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2553 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2554
2555 MMIO_D(TILECTL, D_ALL);
2556
2557 MMIO_D(GEN6_UCGCTL1, D_ALL);
2558 MMIO_D(GEN6_UCGCTL2, D_ALL);
2559
2560 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2561
2562 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2563 MMIO_D(_MMIO(0x13812c), D_ALL);
2564 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2565 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2566 MMIO_D(HSW_IDICR, D_ALL);
2567 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2568
2569 MMIO_D(_MMIO(0x3c), D_ALL);
2570 MMIO_D(_MMIO(0x860), D_ALL);
2571 MMIO_D(ECOSKPD, D_ALL);
2572 MMIO_D(_MMIO(0x121d0), D_ALL);
2573 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2574 MMIO_D(_MMIO(0x41d0), D_ALL);
2575 MMIO_D(GAC_ECO_BITS, D_ALL);
2576 MMIO_D(_MMIO(0x6200), D_ALL);
2577 MMIO_D(_MMIO(0x6204), D_ALL);
2578 MMIO_D(_MMIO(0x6208), D_ALL);
2579 MMIO_D(_MMIO(0x7118), D_ALL);
2580 MMIO_D(_MMIO(0x7180), D_ALL);
2581 MMIO_D(_MMIO(0x7408), D_ALL);
2582 MMIO_D(_MMIO(0x7c00), D_ALL);
2583 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2584 MMIO_D(_MMIO(0x911c), D_ALL);
2585 MMIO_D(_MMIO(0x9120), D_ALL);
2586 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2587
2588 MMIO_D(GAB_CTL, D_ALL);
2589 MMIO_D(_MMIO(0x48800), D_ALL);
2590 MMIO_D(_MMIO(0xce044), D_ALL);
2591 MMIO_D(_MMIO(0xe6500), D_ALL);
2592 MMIO_D(_MMIO(0xe6504), D_ALL);
2593 MMIO_D(_MMIO(0xe6600), D_ALL);
2594 MMIO_D(_MMIO(0xe6604), D_ALL);
2595 MMIO_D(_MMIO(0xe6700), D_ALL);
2596 MMIO_D(_MMIO(0xe6704), D_ALL);
2597 MMIO_D(_MMIO(0xe6800), D_ALL);
2598 MMIO_D(_MMIO(0xe6804), D_ALL);
2599 MMIO_D(PCH_GMBUS4, D_ALL);
2600 MMIO_D(PCH_GMBUS5, D_ALL);
2601
2602 MMIO_D(_MMIO(0x902c), D_ALL);
2603 MMIO_D(_MMIO(0xec008), D_ALL);
2604 MMIO_D(_MMIO(0xec00c), D_ALL);
2605 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
2606 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
2607 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
2608 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
2609 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
2610 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
2611 MMIO_D(_MMIO(0xec408), D_ALL);
2612 MMIO_D(_MMIO(0xec40c), D_ALL);
2613 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
2614 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
2615 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
2616 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
2617 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
2618 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
2619 MMIO_D(_MMIO(0xfc810), D_ALL);
2620 MMIO_D(_MMIO(0xfc81c), D_ALL);
2621 MMIO_D(_MMIO(0xfc828), D_ALL);
2622 MMIO_D(_MMIO(0xfc834), D_ALL);
2623 MMIO_D(_MMIO(0xfcc00), D_ALL);
2624 MMIO_D(_MMIO(0xfcc0c), D_ALL);
2625 MMIO_D(_MMIO(0xfcc18), D_ALL);
2626 MMIO_D(_MMIO(0xfcc24), D_ALL);
2627 MMIO_D(_MMIO(0xfd000), D_ALL);
2628 MMIO_D(_MMIO(0xfd00c), D_ALL);
2629 MMIO_D(_MMIO(0xfd018), D_ALL);
2630 MMIO_D(_MMIO(0xfd024), D_ALL);
2631 MMIO_D(_MMIO(0xfd034), D_ALL);
2632
2633 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2634 MMIO_D(_MMIO(0x2054), D_ALL);
2635 MMIO_D(_MMIO(0x12054), D_ALL);
2636 MMIO_D(_MMIO(0x22054), D_ALL);
2637 MMIO_D(_MMIO(0x1a054), D_ALL);
2638
2639 MMIO_D(_MMIO(0x44070), D_ALL);
2640 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2641 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2642 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2643 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2644 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2645
2646 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2647 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
2648 MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
2649 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2650 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2651 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2652
2653 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2654 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2655 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2656
2657 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2658 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2659 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2660 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2661 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2662 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2663 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2664 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2665 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2666 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2667 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2668 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2669 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2670 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2671 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2672 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2673 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2674
2675 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2676 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2677 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2678 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2679 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2680 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2681 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2682 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2683 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2684 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2685 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2686
2687 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2688 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2689 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
2690
2691 return 0;
2692 }
2693
2694 static int init_bdw_mmio_info(struct intel_gvt *gvt)
2695 {
2696 struct drm_i915_private *dev_priv = gvt->dev_priv;
2697 int ret;
2698
2699 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2700 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2701 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2702 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2703
2704 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2705 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2706 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2707 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2708
2709 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2710 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2711 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2712 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2713
2714 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2715 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2716 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2717 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2718
2719 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2720 intel_vgpu_reg_imr_handler);
2721 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2722 intel_vgpu_reg_ier_handler);
2723 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2724 intel_vgpu_reg_iir_handler);
2725 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2726
2727 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2728 intel_vgpu_reg_imr_handler);
2729 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2730 intel_vgpu_reg_ier_handler);
2731 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2732 intel_vgpu_reg_iir_handler);
2733 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2734
2735 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2736 intel_vgpu_reg_imr_handler);
2737 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2738 intel_vgpu_reg_ier_handler);
2739 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2740 intel_vgpu_reg_iir_handler);
2741 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2742
2743 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2744 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2745 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2746 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2747
2748 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2749 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2750 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2751 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2752
2753 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2754 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2755 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2756 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2757
2758 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2759 intel_vgpu_reg_master_irq_handler);
2760
2761 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2762 mmio_read_from_hw, NULL);
2763
2764 #define RING_REG(base) _MMIO((base) + 0xd0)
2765 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2766 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2767 ring_reset_ctl_write);
2768 #undef RING_REG
2769
2770 #define RING_REG(base) _MMIO((base) + 0x230)
2771 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2772 #undef RING_REG
2773
2774 #define RING_REG(base) _MMIO((base) + 0x234)
2775 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2776 NULL, NULL);
2777 #undef RING_REG
2778
2779 #define RING_REG(base) _MMIO((base) + 0x244)
2780 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2781 #undef RING_REG
2782
2783 #define RING_REG(base) _MMIO((base) + 0x370)
2784 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2785 #undef RING_REG
2786
2787 #define RING_REG(base) _MMIO((base) + 0x3a0)
2788 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2789 #undef RING_REG
2790
2791 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2792 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2793 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2794 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
2795 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2796 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2797 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
2798
2799 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2800
2801 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2802 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2803
2804 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2805
2806 #define RING_REG(base) _MMIO((base) + 0x270)
2807 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2808 #undef RING_REG
2809
2810 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
2811
2812 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2813
2814 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2815 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2816 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
2817
2818 MMIO_D(WM_MISC, D_BDW);
2819 MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
2820
2821 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
2822 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
2823 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
2824
2825 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2826
2827 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2828 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2829 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2830
2831 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
2832 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2833 NULL, NULL);
2834 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2835 NULL, NULL);
2836 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2837
2838 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2839 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2840 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2841 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2842 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2843 MMIO_D(_MMIO(0xb110), D_BDW);
2844
2845 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2846 NULL, force_nonpriv_write);
2847
2848 MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
2849 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
2850
2851 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2852 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2853
2854 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2855
2856 MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
2857
2858 MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
2859
2860 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
2861 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
2862
2863 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2864 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2865 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2866 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2867
2868 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2869
2870 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2871 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2872 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2873 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2874 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2875 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2876 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2877 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2878 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2879 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2880 return 0;
2881 }
2882
2883 static int init_skl_mmio_info(struct intel_gvt *gvt)
2884 {
2885 struct drm_i915_private *dev_priv = gvt->dev_priv;
2886 int ret;
2887
2888 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2889 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2890 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2891 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2892 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2893 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2894
2895 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2896 dp_aux_ch_ctl_mmio_write);
2897 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2898 dp_aux_ch_ctl_mmio_write);
2899 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2900 dp_aux_ch_ctl_mmio_write);
2901
2902 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
2903 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
2904
2905 MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
2906
2907 MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
2908 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2909 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2910 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2911 MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL);
2912 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
2913 MMIO_D(DC_STATE_EN, D_SKL_PLUS);
2914 MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
2915 MMIO_D(CDCLK_CTL, D_SKL_PLUS);
2916 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2917 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2918 MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
2919 MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
2920 MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
2921 MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
2922 MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
2923 MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
2924 MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
2925 MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
2926 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
2927
2928 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2929 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2930 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2931 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2932 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2933 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2934
2935 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2936 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2937 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2938 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2939 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2940 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2941
2942 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2943 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2944 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2945 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2946 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2947 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2948
2949 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2950 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2951 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2952 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2953
2954 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2955 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2956 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2957 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2958
2959 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2960 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2961 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2962 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2963
2964 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2965 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2966 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2967
2968 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2969 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2970 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2971
2972 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2973 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2974 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2975
2976 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2977 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2978 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2979
2980 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2981 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2982 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2983
2984 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2985 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2986 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2987
2988 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2989 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2990 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2991
2992 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2993 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2994 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2995
2996 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2997 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2998 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
2999
3000 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
3001 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
3002 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
3003 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
3004
3005 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
3006 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
3007 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
3008 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
3009
3010 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
3011 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
3012 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
3013 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
3014
3015 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
3016 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
3017 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
3018 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
3019
3020 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
3021 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
3022 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
3023 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
3024
3025 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
3026 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
3027 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
3028 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
3029
3030 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
3031 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
3032 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
3033 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
3034
3035 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
3036 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
3037 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
3038 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
3039
3040 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
3041 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
3042 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
3043 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
3044
3045 MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
3046 MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
3047 MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
3048 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
3049 MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
3050
3051 MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
3052 MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
3053 MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
3054
3055 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3056
3057 MMIO_D(SKL_DFSM, D_SKL_PLUS);
3058 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
3059
3060 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
3061 NULL, NULL);
3062 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
3063 NULL, NULL);
3064
3065 MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
3066 MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
3067 MMIO_D(RC6_LOCATION, D_SKL_PLUS);
3068 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
3069 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
3070 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3071 NULL, NULL);
3072
3073 /* TRTT */
3074 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3075 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3076 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3077 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3078 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3079 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS,
3080 NULL, gen9_trtte_write);
3081 MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);
3082
3083 MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
3084
3085 MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
3086
3087 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
3088 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3089 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
3090
3091 MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
3092 MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
3093 MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
3094 MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
3095 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
3096 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
3097 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
3098 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
3099 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
3100 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
3101
3102 MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
3103 MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
3104 MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
3105
3106 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
3107 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
3108 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
3109 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
3110 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
3111 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
3112 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
3113 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
3114 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
3115
3116 MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
3117 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
3118 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3119 NULL, csfe_chicken1_mmio_write);
3120 #undef CSFE_CHICKEN1_REG
3121 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3122 NULL, NULL);
3123 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3124 NULL, NULL);
3125
3126 MMIO_D(GAMT_CHKN_BIT_REG, D_KBL);
3127 MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL);
3128
3129 return 0;
3130 }
3131
3132 static int init_bxt_mmio_info(struct intel_gvt *gvt)
3133 {
3134 struct drm_i915_private *dev_priv = gvt->dev_priv;
3135 int ret;
3136
3137 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
3138
3139 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
3140 MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
3141 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
3142 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
3143 MMIO_D(ERROR_GEN6, D_BXT);
3144 MMIO_D(DONE_REG, D_BXT);
3145 MMIO_D(EIR, D_BXT);
3146 MMIO_D(PGTBL_ER, D_BXT);
3147 MMIO_D(_MMIO(0x4194), D_BXT);
3148 MMIO_D(_MMIO(0x4294), D_BXT);
3149 MMIO_D(_MMIO(0x4494), D_BXT);
3150
3151 MMIO_RING_D(RING_PSMI_CTL, D_BXT);
3152 MMIO_RING_D(RING_DMA_FADD, D_BXT);
3153 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
3154 MMIO_RING_D(RING_IPEHR, D_BXT);
3155 MMIO_RING_D(RING_INSTPS, D_BXT);
3156 MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
3157 MMIO_RING_D(RING_BBSTATE, D_BXT);
3158 MMIO_RING_D(RING_IPEIR, D_BXT);
3159
3160 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
3161
3162 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
3163 MMIO_D(BXT_RP_STATE_CAP, D_BXT);
3164 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
3165 NULL, bxt_phy_ctl_family_write);
3166 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
3167 NULL, bxt_phy_ctl_family_write);
3168 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
3169 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
3170 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
3171 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
3172 NULL, bxt_port_pll_enable_write);
3173 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
3174 NULL, bxt_port_pll_enable_write);
3175 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
3176 bxt_port_pll_enable_write);
3177
3178 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
3179 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
3180 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
3181 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
3182 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
3183 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
3184 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
3185 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
3186 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
3187
3188 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
3189 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
3190 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
3191 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
3192 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
3193 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
3194 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
3195 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
3196 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
3197
3198 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
3199 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
3200 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3201 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3202 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3203 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
3204 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
3205 NULL, bxt_pcs_dw12_grp_write);
3206 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3207 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3208 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
3209 bxt_port_tx_dw3_read, NULL);
3210 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3211 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3212 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3213 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3214 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3215 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3216 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3217 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3218 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3219 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3220 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3221 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
3222 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
3223 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
3224 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
3225
3226 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
3227 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
3228 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3229 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3230 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3231 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
3232 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
3233 NULL, bxt_pcs_dw12_grp_write);
3234 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3235 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3236 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
3237 bxt_port_tx_dw3_read, NULL);
3238 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3239 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3240 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3241 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3242 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3243 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3244 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3245 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3246 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3247 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3248 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3249 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
3250 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
3251 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
3252 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
3253
3254 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
3255 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
3256 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3257 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3258 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3259 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
3260 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
3261 NULL, bxt_pcs_dw12_grp_write);
3262 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3263 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3264 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
3265 bxt_port_tx_dw3_read, NULL);
3266 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3267 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3268 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3269 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3270 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3271 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3272 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3273 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3274 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3275 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3276 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3277 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
3278 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
3279 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
3280 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
3281
3282 MMIO_D(BXT_DE_PLL_CTL, D_BXT);
3283 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
3284 MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
3285 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
3286
3287 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
3288 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
3289
3290 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
3291 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
3292 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
3293
3294 MMIO_D(RC6_CTX_BASE, D_BXT);
3295
3296 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
3297 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
3298 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
3299 MMIO_D(GEN6_GFXPAUSE, D_BXT);
3300 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
3301
3302 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
3303
3304 return 0;
3305 }
3306
3307 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
3308 unsigned int offset)
3309 {
3310 unsigned long device = intel_gvt_get_device_type(gvt);
3311 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3312 int num = gvt->mmio.num_mmio_block;
3313 int i;
3314
3315 for (i = 0; i < num; i++, block++) {
3316 if (!(device & block->device))
3317 continue;
3318 if (offset >= i915_mmio_reg_offset(block->offset) &&
3319 offset < i915_mmio_reg_offset(block->offset) + block->size)
3320 return block;
3321 }
3322 return NULL;
3323 }
3324
3325 /**
3326 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
3327 * @gvt: GVT device
3328 *
3329 * This function is called at the driver unloading stage, to clean up the MMIO
3330 * information table of GVT device
3331 *
3332 */
3333 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
3334 {
3335 struct hlist_node *tmp;
3336 struct intel_gvt_mmio_info *e;
3337 int i;
3338
3339 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
3340 kfree(e);
3341
3342 vfree(gvt->mmio.mmio_attribute);
3343 gvt->mmio.mmio_attribute = NULL;
3344 }
3345
3346 /* Special MMIO blocks. */
3347 static struct gvt_mmio_block mmio_blocks[] = {
3348 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
3349 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
3350 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
3351 pvinfo_mmio_read, pvinfo_mmio_write},
3352 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
3353 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
3354 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
3355 };
3356
3357 /**
3358 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
3359 * @gvt: GVT device
3360 *
3361 * This function is called at the initialization stage, to setup the MMIO
3362 * information table for GVT device
3363 *
3364 * Returns:
3365 * zero on success, negative if failed.
3366 */
3367 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
3368 {
3369 struct intel_gvt_device_info *info = &gvt->device_info;
3370 struct drm_i915_private *dev_priv = gvt->dev_priv;
3371 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
3372 int ret;
3373
3374 gvt->mmio.mmio_attribute = vzalloc(size);
3375 if (!gvt->mmio.mmio_attribute)
3376 return -ENOMEM;
3377
3378 ret = init_generic_mmio_info(gvt);
3379 if (ret)
3380 goto err;
3381
3382 if (IS_BROADWELL(dev_priv)) {
3383 ret = init_bdw_mmio_info(gvt);
3384 if (ret)
3385 goto err;
3386 } else if (IS_SKYLAKE(dev_priv)
3387 || IS_KABYLAKE(dev_priv)
3388 || IS_COFFEELAKE(dev_priv)) {
3389 ret = init_bdw_mmio_info(gvt);
3390 if (ret)
3391 goto err;
3392 ret = init_skl_mmio_info(gvt);
3393 if (ret)
3394 goto err;
3395 } else if (IS_BROXTON(dev_priv)) {
3396 ret = init_bdw_mmio_info(gvt);
3397 if (ret)
3398 goto err;
3399 ret = init_skl_mmio_info(gvt);
3400 if (ret)
3401 goto err;
3402 ret = init_bxt_mmio_info(gvt);
3403 if (ret)
3404 goto err;
3405 }
3406
3407 gvt->mmio.mmio_block = mmio_blocks;
3408 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
3409
3410 return 0;
3411 err:
3412 intel_gvt_clean_mmio_info(gvt);
3413 return ret;
3414 }
3415
3416 /**
3417 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
3418 * @gvt: a GVT device
3419 * @handler: the handler
3420 * @data: private data given to handler
3421 *
3422 * Returns:
3423 * Zero on success, negative error code if failed.
3424 */
3425 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3426 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3427 void *data)
3428 {
3429 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3430 struct intel_gvt_mmio_info *e;
3431 int i, j, ret;
3432
3433 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3434 ret = handler(gvt, e->offset, data);
3435 if (ret)
3436 return ret;
3437 }
3438
3439 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3440 /* pvinfo data doesn't come from hw mmio */
3441 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE)
3442 continue;
3443
3444 for (j = 0; j < block->size; j += 4) {
3445 ret = handler(gvt,
3446 i915_mmio_reg_offset(block->offset) + j,
3447 data);
3448 if (ret)
3449 return ret;
3450 }
3451 }
3452 return 0;
3453 }
3454
3455 /**
3456 * intel_vgpu_default_mmio_read - default MMIO read handler
3457 * @vgpu: a vGPU
3458 * @offset: access offset
3459 * @p_data: data return buffer
3460 * @bytes: access data length
3461 *
3462 * Returns:
3463 * Zero on success, negative error code if failed.
3464 */
3465 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3466 void *p_data, unsigned int bytes)
3467 {
3468 read_vreg(vgpu, offset, p_data, bytes);
3469 return 0;
3470 }
3471
3472 /**
3473 * intel_t_default_mmio_write - default MMIO write handler
3474 * @vgpu: a vGPU
3475 * @offset: access offset
3476 * @p_data: write data buffer
3477 * @bytes: access data length
3478 *
3479 * Returns:
3480 * Zero on success, negative error code if failed.
3481 */
3482 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3483 void *p_data, unsigned int bytes)
3484 {
3485 write_vreg(vgpu, offset, p_data, bytes);
3486 return 0;
3487 }
3488
3489 /**
3490 * intel_vgpu_mask_mmio_write - write mask register
3491 * @vgpu: a vGPU
3492 * @offset: access offset
3493 * @p_data: write data buffer
3494 * @bytes: access data length
3495 *
3496 * Returns:
3497 * Zero on success, negative error code if failed.
3498 */
3499 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3500 void *p_data, unsigned int bytes)
3501 {
3502 u32 mask, old_vreg;
3503
3504 old_vreg = vgpu_vreg(vgpu, offset);
3505 write_vreg(vgpu, offset, p_data, bytes);
3506 mask = vgpu_vreg(vgpu, offset) >> 16;
3507 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
3508 (vgpu_vreg(vgpu, offset) & mask);
3509
3510 return 0;
3511 }
3512
3513 /**
3514 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3515 * force-nopriv register
3516 *
3517 * @gvt: a GVT device
3518 * @offset: register offset
3519 *
3520 * Returns:
3521 * True if the register is in force-nonpriv whitelist;
3522 * False if outside;
3523 */
3524 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3525 unsigned int offset)
3526 {
3527 return in_whitelist(offset);
3528 }
3529
3530 /**
3531 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3532 * @vgpu: a vGPU
3533 * @offset: register offset
3534 * @pdata: data buffer
3535 * @bytes: data length
3536 * @is_read: read or write
3537 *
3538 * Returns:
3539 * Zero on success, negative error code if failed.
3540 */
3541 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3542 void *pdata, unsigned int bytes, bool is_read)
3543 {
3544 struct intel_gvt *gvt = vgpu->gvt;
3545 struct intel_gvt_mmio_info *mmio_info;
3546 struct gvt_mmio_block *mmio_block;
3547 gvt_mmio_func func;
3548 int ret;
3549
3550 if (WARN_ON(bytes > 8))
3551 return -EINVAL;
3552
3553 /*
3554 * Handle special MMIO blocks.
3555 */
3556 mmio_block = find_mmio_block(gvt, offset);
3557 if (mmio_block) {
3558 func = is_read ? mmio_block->read : mmio_block->write;
3559 if (func)
3560 return func(vgpu, offset, pdata, bytes);
3561 goto default_rw;
3562 }
3563
3564 /*
3565 * Normal tracked MMIOs.
3566 */
3567 mmio_info = find_mmio_info(gvt, offset);
3568 if (!mmio_info) {
3569 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
3570 goto default_rw;
3571 }
3572
3573 if (is_read)
3574 return mmio_info->read(vgpu, offset, pdata, bytes);
3575 else {
3576 u64 ro_mask = mmio_info->ro_mask;
3577 u32 old_vreg = 0;
3578 u64 data = 0;
3579
3580 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3581 old_vreg = vgpu_vreg(vgpu, offset);
3582 }
3583
3584 if (likely(!ro_mask))
3585 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3586 else if (!~ro_mask) {
3587 gvt_vgpu_err("try to write RO reg %x\n", offset);
3588 return 0;
3589 } else {
3590 /* keep the RO bits in the virtual register */
3591 memcpy(&data, pdata, bytes);
3592 data &= ~ro_mask;
3593 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3594 ret = mmio_info->write(vgpu, offset, &data, bytes);
3595 }
3596
3597 /* higher 16bits of mode ctl regs are mask bits for change */
3598 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3599 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3600
3601 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3602 | (vgpu_vreg(vgpu, offset) & mask);
3603 }
3604 }
3605
3606 return ret;
3607
3608 default_rw:
3609 return is_read ?
3610 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3611 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3612 }
Linux with added FPC-III support