2 * Copyright(c) 2011-2015 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include "i915_vgpu.h"
27 * DOC: Intel GVT-g guest support
29 * Intel GVT-g is a graphics virtualization technology which shares the
30 * GPU among multiple virtual machines on a time-sharing basis. Each
31 * virtual machine is presented a virtual GPU (vGPU), which has equivalent
32 * features as the underlying physical GPU (pGPU), so i915 driver can run
33 * seamlessly in a virtual machine. This file provides vGPU specific
34 * optimizations when running in a virtual machine, to reduce the complexity
35 * of vGPU emulation and to improve the overall performance.
37 * A primary function introduced here is so-called "address space ballooning"
38 * technique. Intel GVT-g partitions global graphics memory among multiple VMs,
39 * so each VM can directly access a portion of the memory without hypervisor's
40 * intervention, e.g. filling textures or queuing commands. However with the
41 * partitioning an unmodified i915 driver would assume a smaller graphics
42 * memory starting from address ZERO, then requires vGPU emulation module to
43 * translate the graphics address between 'guest view' and 'host view', for
44 * all registers and command opcodes which contain a graphics memory address.
45 * To reduce the complexity, Intel GVT-g introduces "address space ballooning",
46 * by telling the exact partitioning knowledge to each guest i915 driver, which
47 * then reserves and prevents non-allocated portions from allocation. Thus vGPU
48 * emulation module only needs to scan and validate graphics addresses without
49 * complexity of address translation.
54 * i915_detect_vgpu - detect virtual GPU
55 * @dev_priv: i915 device private
57 * This function is called at the initialization stage, to detect whether
60 void i915_detect_vgpu(struct drm_i915_private
*dev_priv
)
62 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
65 void __iomem
*shared_area
;
67 BUILD_BUG_ON(sizeof(struct vgt_if
) != VGT_PVINFO_SIZE
);
70 * This is called before we setup the main MMIO BAR mappings used via
71 * the uncore structure, so we need to access the BAR directly. Since
72 * we do not support VGT on older gens, return early so we don't have
73 * to consider differently numbered or sized MMIO bars
75 if (INTEL_GEN(dev_priv
) < 6)
78 shared_area
= pci_iomap_range(pdev
, 0, VGT_PVINFO_PAGE
, VGT_PVINFO_SIZE
);
80 DRM_ERROR("failed to map MMIO bar to check for VGT\n");
84 magic
= readq(shared_area
+ vgtif_offset(magic
));
85 if (magic
!= VGT_MAGIC
)
88 version_major
= readw(shared_area
+ vgtif_offset(version_major
));
89 if (version_major
< VGT_VERSION_MAJOR
) {
90 DRM_INFO("VGT interface version mismatch!\n");
94 dev_priv
->vgpu
.caps
= readl(shared_area
+ vgtif_offset(vgt_caps
));
96 dev_priv
->vgpu
.active
= true;
97 mutex_init(&dev_priv
->vgpu
.lock
);
98 DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
101 pci_iounmap(pdev
, shared_area
);
104 bool intel_vgpu_has_full_ppgtt(struct drm_i915_private
*dev_priv
)
106 return dev_priv
->vgpu
.caps
& VGT_CAPS_FULL_PPGTT
;
109 struct _balloon_info_
{
111 * There are up to 2 regions per mappable/unmappable graphic
112 * memory that might be ballooned. Here, index 0/1 is for mappable
113 * graphic memory, 2/3 for unmappable graphic memory.
115 struct drm_mm_node space
[4];
118 static struct _balloon_info_ bl_info
;
120 static void vgt_deballoon_space(struct i915_ggtt
*ggtt
,
121 struct drm_mm_node
*node
)
123 if (!drm_mm_node_allocated(node
))
126 DRM_DEBUG_DRIVER("deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n",
128 node
->start
+ node
->size
,
131 ggtt
->vm
.reserved
-= node
->size
;
132 drm_mm_remove_node(node
);
136 * intel_vgt_deballoon - deballoon reserved graphics address trunks
137 * @ggtt: the global GGTT from which we reserved earlier
139 * This function is called to deallocate the ballooned-out graphic memory, when
140 * driver is unloaded or when ballooning fails.
142 void intel_vgt_deballoon(struct i915_ggtt
*ggtt
)
146 if (!intel_vgpu_active(ggtt
->vm
.i915
))
149 DRM_DEBUG("VGT deballoon.\n");
151 for (i
= 0; i
< 4; i
++)
152 vgt_deballoon_space(ggtt
, &bl_info
.space
[i
]);
155 static int vgt_balloon_space(struct i915_ggtt
*ggtt
,
156 struct drm_mm_node
*node
,
157 unsigned long start
, unsigned long end
)
159 unsigned long size
= end
- start
;
165 DRM_INFO("balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.\n",
166 start
, end
, size
/ 1024);
167 ret
= i915_gem_gtt_reserve(&ggtt
->vm
, node
,
168 size
, start
, I915_COLOR_UNEVICTABLE
,
171 ggtt
->vm
.reserved
+= size
;
177 * intel_vgt_balloon - balloon out reserved graphics address trunks
178 * @ggtt: the global GGTT from which to reserve
180 * This function is called at the initialization stage, to balloon out the
181 * graphic address space allocated to other vGPUs, by marking these spaces as
182 * reserved. The ballooning related knowledge(starting address and size of
183 * the mappable/unmappable graphic memory) is described in the vgt_if structure
184 * in a reserved mmio range.
186 * To give an example, the drawing below depicts one typical scenario after
187 * ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned
188 * out each for the mappable and the non-mappable part. From the vGPU1 point of
189 * view, the total size is the same as the physical one, with the start address
190 * of its graphic space being zero. Yet there are some portions ballooned out(
191 * the shadow part, which are marked as reserved by drm allocator). From the
192 * host point of view, the graphic address space is partitioned by multiple
193 * vGPUs in different VMs. ::
195 * vGPU1 view Host view
196 * 0 ------> +-----------+ +-----------+
197 * ^ |###########| | vGPU3 |
198 * | |###########| +-----------+
199 * | |###########| | vGPU2 |
200 * | +-----------+ +-----------+
201 * mappable GM | available | ==> | vGPU1 |
202 * | +-----------+ +-----------+
203 * | |###########| | |
204 * v |###########| | Host |
205 * +=======+===========+ +===========+
206 * ^ |###########| | vGPU3 |
207 * | |###########| +-----------+
208 * | |###########| | vGPU2 |
209 * | +-----------+ +-----------+
210 * unmappable GM | available | ==> | vGPU1 |
211 * | +-----------+ +-----------+
212 * | |###########| | |
213 * | |###########| | Host |
214 * v |###########| | |
215 * total GM size ------> +-----------+ +-----------+
218 * zero on success, non-zero if configuration invalid or ballooning failed
220 int intel_vgt_balloon(struct i915_ggtt
*ggtt
)
222 struct intel_uncore
*uncore
= &ggtt
->vm
.i915
->uncore
;
223 unsigned long ggtt_end
= ggtt
->vm
.total
;
225 unsigned long mappable_base
, mappable_size
, mappable_end
;
226 unsigned long unmappable_base
, unmappable_size
, unmappable_end
;
229 if (!intel_vgpu_active(ggtt
->vm
.i915
))
233 intel_uncore_read(uncore
, vgtif_reg(avail_rs
.mappable_gmadr
.base
));
235 intel_uncore_read(uncore
, vgtif_reg(avail_rs
.mappable_gmadr
.size
));
237 intel_uncore_read(uncore
, vgtif_reg(avail_rs
.nonmappable_gmadr
.base
));
239 intel_uncore_read(uncore
, vgtif_reg(avail_rs
.nonmappable_gmadr
.size
));
241 mappable_end
= mappable_base
+ mappable_size
;
242 unmappable_end
= unmappable_base
+ unmappable_size
;
244 DRM_INFO("VGT ballooning configuration:\n");
245 DRM_INFO("Mappable graphic memory: base 0x%lx size %ldKiB\n",
246 mappable_base
, mappable_size
/ 1024);
247 DRM_INFO("Unmappable graphic memory: base 0x%lx size %ldKiB\n",
248 unmappable_base
, unmappable_size
/ 1024);
250 if (mappable_end
> ggtt
->mappable_end
||
251 unmappable_base
< ggtt
->mappable_end
||
252 unmappable_end
> ggtt_end
) {
253 DRM_ERROR("Invalid ballooning configuration!\n");
257 /* Unmappable graphic memory ballooning */
258 if (unmappable_base
> ggtt
->mappable_end
) {
259 ret
= vgt_balloon_space(ggtt
, &bl_info
.space
[2],
260 ggtt
->mappable_end
, unmappable_base
);
266 if (unmappable_end
< ggtt_end
) {
267 ret
= vgt_balloon_space(ggtt
, &bl_info
.space
[3],
268 unmappable_end
, ggtt_end
);
270 goto err_upon_mappable
;
273 /* Mappable graphic memory ballooning */
275 ret
= vgt_balloon_space(ggtt
, &bl_info
.space
[0],
279 goto err_upon_unmappable
;
282 if (mappable_end
< ggtt
->mappable_end
) {
283 ret
= vgt_balloon_space(ggtt
, &bl_info
.space
[1],
284 mappable_end
, ggtt
->mappable_end
);
287 goto err_below_mappable
;
290 DRM_INFO("VGT balloon successfully\n");
294 vgt_deballoon_space(ggtt
, &bl_info
.space
[0]);
296 vgt_deballoon_space(ggtt
, &bl_info
.space
[3]);
298 vgt_deballoon_space(ggtt
, &bl_info
.space
[2]);
300 DRM_ERROR("VGT balloon fail\n");