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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_device_info.c
blob6670a0763be2e77cfeb965b6b3ebd0b62428bddc
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <drm/drm_print.h>
26
27 #include "intel_device_info.h"
28 #include "i915_drv.h"
29
30 #define PLATFORM_NAME(x) [INTEL_##x] = #x
31 static const char * const platform_names[] = {
32 PLATFORM_NAME(I830),
33 PLATFORM_NAME(I845G),
34 PLATFORM_NAME(I85X),
35 PLATFORM_NAME(I865G),
36 PLATFORM_NAME(I915G),
37 PLATFORM_NAME(I915GM),
38 PLATFORM_NAME(I945G),
39 PLATFORM_NAME(I945GM),
40 PLATFORM_NAME(G33),
41 PLATFORM_NAME(PINEVIEW),
42 PLATFORM_NAME(I965G),
43 PLATFORM_NAME(I965GM),
44 PLATFORM_NAME(G45),
45 PLATFORM_NAME(GM45),
46 PLATFORM_NAME(IRONLAKE),
47 PLATFORM_NAME(SANDYBRIDGE),
48 PLATFORM_NAME(IVYBRIDGE),
49 PLATFORM_NAME(VALLEYVIEW),
50 PLATFORM_NAME(HASWELL),
51 PLATFORM_NAME(BROADWELL),
52 PLATFORM_NAME(CHERRYVIEW),
53 PLATFORM_NAME(SKYLAKE),
54 PLATFORM_NAME(BROXTON),
55 PLATFORM_NAME(KABYLAKE),
56 PLATFORM_NAME(GEMINILAKE),
57 PLATFORM_NAME(COFFEELAKE),
58 PLATFORM_NAME(CANNONLAKE),
59 PLATFORM_NAME(ICELAKE),
60 PLATFORM_NAME(ELKHARTLAKE),
61 PLATFORM_NAME(TIGERLAKE),
62 };
63 #undef PLATFORM_NAME
64
65 const char *intel_platform_name(enum intel_platform platform)
66 {
67 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
68
69 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
70 platform_names[platform] == NULL))
71 return "<unknown>";
72
73 return platform_names[platform];
74 }
75
76 static const char *iommu_name(void)
77 {
78 const char *msg = "n/a";
79
80 #ifdef CONFIG_INTEL_IOMMU
81 msg = enableddisabled(intel_iommu_gfx_mapped);
82 #endif
83
84 return msg;
85 }
86
87 void intel_device_info_print_static(const struct intel_device_info *info,
88 struct drm_printer *p)
89 {
90 drm_printf(p, "engines: %x\n", info->engine_mask);
91 drm_printf(p, "gen: %d\n", info->gen);
92 drm_printf(p, "gt: %d\n", info->gt);
93 drm_printf(p, "iommu: %s\n", iommu_name());
94 drm_printf(p, "memory-regions: %x\n", info->memory_regions);
95 drm_printf(p, "page-sizes: %x\n", info->page_sizes);
96 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
97 drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
98 drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
99
100 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
101 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
102 #undef PRINT_FLAG
103
104 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
105 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
106 #undef PRINT_FLAG
107 }
108
109 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
110 {
111 int s;
112
113 drm_printf(p, "slice total: %u, mask=%04x\n",
114 hweight8(sseu->slice_mask), sseu->slice_mask);
115 drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
116 for (s = 0; s < sseu->max_slices; s++) {
117 drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
118 s, intel_sseu_subslices_per_slice(sseu, s),
119 intel_sseu_get_subslices(sseu, s));
120 }
121 drm_printf(p, "EU total: %u\n", sseu->eu_total);
122 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
123 drm_printf(p, "has slice power gating: %s\n",
124 yesno(sseu->has_slice_pg));
125 drm_printf(p, "has subslice power gating: %s\n",
126 yesno(sseu->has_subslice_pg));
127 drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
128 }
129
130 void intel_device_info_print_runtime(const struct intel_runtime_info *info,
131 struct drm_printer *p)
132 {
133 sseu_dump(&info->sseu, p);
134
135 drm_printf(p, "CS timestamp frequency: %u kHz\n",
136 info->cs_timestamp_frequency_khz);
137 }
138
139 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
140 int subslice)
141 {
142 int slice_stride = sseu->max_subslices * sseu->eu_stride;
143
144 return slice * slice_stride + subslice * sseu->eu_stride;
145 }
146
147 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
148 int subslice)
149 {
150 int i, offset = sseu_eu_idx(sseu, slice, subslice);
151 u16 eu_mask = 0;
152
153 for (i = 0; i < sseu->eu_stride; i++) {
154 eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
155 (i * BITS_PER_BYTE);
156 }
157
158 return eu_mask;
159 }
160
161 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
162 u16 eu_mask)
163 {
164 int i, offset = sseu_eu_idx(sseu, slice, subslice);
165
166 for (i = 0; i < sseu->eu_stride; i++) {
167 sseu->eu_mask[offset + i] =
168 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
169 }
170 }
171
172 void intel_device_info_print_topology(const struct sseu_dev_info *sseu,
173 struct drm_printer *p)
174 {
175 int s, ss;
176
177 if (sseu->max_slices == 0) {
178 drm_printf(p, "Unavailable\n");
179 return;
180 }
181
182 for (s = 0; s < sseu->max_slices; s++) {
183 drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
184 s, intel_sseu_subslices_per_slice(sseu, s),
185 intel_sseu_get_subslices(sseu, s));
186
187 for (ss = 0; ss < sseu->max_subslices; ss++) {
188 u16 enabled_eus = sseu_get_eus(sseu, s, ss);
189
190 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n",
191 ss, hweight16(enabled_eus), enabled_eus);
192 }
193 }
194 }
195
196 static u16 compute_eu_total(const struct sseu_dev_info *sseu)
197 {
198 u16 i, total = 0;
199
200 for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
201 total += hweight8(sseu->eu_mask[i]);
202
203 return total;
204 }
205
206 static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
207 u8 s_en, u32 ss_en, u16 eu_en)
208 {
209 int s, ss;
210
211 /* ss_en represents entire subslice mask across all slices */
212 GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
213 sizeof(ss_en) * BITS_PER_BYTE);
214
215 for (s = 0; s < sseu->max_slices; s++) {
216 if ((s_en & BIT(s)) == 0)
217 continue;
218
219 sseu->slice_mask |= BIT(s);
220
221 intel_sseu_set_subslices(sseu, s, ss_en);
222
223 for (ss = 0; ss < sseu->max_subslices; ss++)
224 if (intel_sseu_has_subslice(sseu, s, ss))
225 sseu_set_eus(sseu, s, ss, eu_en);
226 }
227 sseu->eu_per_subslice = hweight16(eu_en);
228 sseu->eu_total = compute_eu_total(sseu);
229 }
230
231 static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
232 {
233 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
234 u8 s_en;
235 u32 dss_en;
236 u16 eu_en = 0;
237 u8 eu_en_fuse;
238 int eu;
239
240 /*
241 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
242 * Instead of splitting these, provide userspace with an array
243 * of DSS to more closely represent the hardware resource.
244 */
245 intel_sseu_set_info(sseu, 1, 6, 16);
246
247 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
248
249 dss_en = I915_READ(GEN12_GT_DSS_ENABLE);
250
251 /* one bit per pair of EUs */
252 eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
253 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
254 if (eu_en_fuse & BIT(eu))
255 eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
256
257 gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en);
258
259 /* TGL only supports slice-level power gating */
260 sseu->has_slice_pg = 1;
261 }
262
263 static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
264 {
265 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
266 u8 s_en;
267 u32 ss_en;
268 u8 eu_en;
269
270 if (IS_ELKHARTLAKE(dev_priv))
271 intel_sseu_set_info(sseu, 1, 4, 8);
272 else
273 intel_sseu_set_info(sseu, 1, 8, 8);
274
275 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
276 ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
277 eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
278
279 gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en);
280
281 /* ICL has no power gating restrictions. */
282 sseu->has_slice_pg = 1;
283 sseu->has_subslice_pg = 1;
284 sseu->has_eu_pg = 1;
285 }
286
287 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
288 {
289 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
290 const u32 fuse2 = I915_READ(GEN8_FUSE2);
291 int s, ss;
292 const int eu_mask = 0xff;
293 u32 subslice_mask, eu_en;
294
295 intel_sseu_set_info(sseu, 6, 4, 8);
296
297 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
298 GEN10_F2_S_ENA_SHIFT;
299
300 /* Slice0 */
301 eu_en = ~I915_READ(GEN8_EU_DISABLE0);
302 for (ss = 0; ss < sseu->max_subslices; ss++)
303 sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
304 /* Slice1 */
305 sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
306 eu_en = ~I915_READ(GEN8_EU_DISABLE1);
307 sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
308 /* Slice2 */
309 sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
310 sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
311 /* Slice3 */
312 sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
313 eu_en = ~I915_READ(GEN8_EU_DISABLE2);
314 sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
315 /* Slice4 */
316 sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
317 sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
318 /* Slice5 */
319 sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
320 eu_en = ~I915_READ(GEN10_EU_DISABLE3);
321 sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
322
323 subslice_mask = (1 << 4) - 1;
324 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
325 GEN10_F2_SS_DIS_SHIFT);
326
327 for (s = 0; s < sseu->max_slices; s++) {
328 u32 subslice_mask_with_eus = subslice_mask;
329
330 for (ss = 0; ss < sseu->max_subslices; ss++) {
331 if (sseu_get_eus(sseu, s, ss) == 0)
332 subslice_mask_with_eus &= ~BIT(ss);
333 }
334
335 /*
336 * Slice0 can have up to 3 subslices, but there are only 2 in
337 * slice1/2.
338 */
339 intel_sseu_set_subslices(sseu, s, s == 0 ?
340 subslice_mask_with_eus :
341 subslice_mask_with_eus & 0x3);
342 }
343
344 sseu->eu_total = compute_eu_total(sseu);
345
346 /*
347 * CNL is expected to always have a uniform distribution
348 * of EU across subslices with the exception that any one
349 * EU in any one subslice may be fused off for die
350 * recovery.
351 */
352 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
353 DIV_ROUND_UP(sseu->eu_total,
354 intel_sseu_subslice_total(sseu)) :
355 0;
356
357 /* No restrictions on Power Gating */
358 sseu->has_slice_pg = 1;
359 sseu->has_subslice_pg = 1;
360 sseu->has_eu_pg = 1;
361 }
362
363 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
364 {
365 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
366 u32 fuse;
367 u8 subslice_mask = 0;
368
369 fuse = I915_READ(CHV_FUSE_GT);
370
371 sseu->slice_mask = BIT(0);
372 intel_sseu_set_info(sseu, 1, 2, 8);
373
374 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
375 u8 disabled_mask =
376 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
377 CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
378 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
379 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
380
381 subslice_mask |= BIT(0);
382 sseu_set_eus(sseu, 0, 0, ~disabled_mask);
383 }
384
385 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
386 u8 disabled_mask =
387 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
388 CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
389 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
390 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
391
392 subslice_mask |= BIT(1);
393 sseu_set_eus(sseu, 0, 1, ~disabled_mask);
394 }
395
396 intel_sseu_set_subslices(sseu, 0, subslice_mask);
397
398 sseu->eu_total = compute_eu_total(sseu);
399
400 /*
401 * CHV expected to always have a uniform distribution of EU
402 * across subslices.
403 */
404 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
405 sseu->eu_total /
406 intel_sseu_subslice_total(sseu) :
407 0;
408 /*
409 * CHV supports subslice power gating on devices with more than
410 * one subslice, and supports EU power gating on devices with
411 * more than one EU pair per subslice.
412 */
413 sseu->has_slice_pg = 0;
414 sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1;
415 sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
416 }
417
418 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
419 {
420 struct intel_device_info *info = mkwrite_device_info(dev_priv);
421 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
422 int s, ss;
423 u32 fuse2, eu_disable, subslice_mask;
424 const u8 eu_mask = 0xff;
425
426 fuse2 = I915_READ(GEN8_FUSE2);
427 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
428
429 /* BXT has a single slice and at most 3 subslices. */
430 intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
431 IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
432
433 /*
434 * The subslice disable field is global, i.e. it applies
435 * to each of the enabled slices.
436 */
437 subslice_mask = (1 << sseu->max_subslices) - 1;
438 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
439 GEN9_F2_SS_DIS_SHIFT);
440
441 /*
442 * Iterate through enabled slices and subslices to
443 * count the total enabled EU.
444 */
445 for (s = 0; s < sseu->max_slices; s++) {
446 if (!(sseu->slice_mask & BIT(s)))
447 /* skip disabled slice */
448 continue;
449
450 intel_sseu_set_subslices(sseu, s, subslice_mask);
451
452 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
453 for (ss = 0; ss < sseu->max_subslices; ss++) {
454 int eu_per_ss;
455 u8 eu_disabled_mask;
456
457 if (!intel_sseu_has_subslice(sseu, s, ss))
458 /* skip disabled subslice */
459 continue;
460
461 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
462
463 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
464
465 eu_per_ss = sseu->max_eus_per_subslice -
466 hweight8(eu_disabled_mask);
467
468 /*
469 * Record which subslice(s) has(have) 7 EUs. we
470 * can tune the hash used to spread work among
471 * subslices if they are unbalanced.
472 */
473 if (eu_per_ss == 7)
474 sseu->subslice_7eu[s] |= BIT(ss);
475 }
476 }
477
478 sseu->eu_total = compute_eu_total(sseu);
479
480 /*
481 * SKL is expected to always have a uniform distribution
482 * of EU across subslices with the exception that any one
483 * EU in any one subslice may be fused off for die
484 * recovery. BXT is expected to be perfectly uniform in EU
485 * distribution.
486 */
487 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
488 DIV_ROUND_UP(sseu->eu_total,
489 intel_sseu_subslice_total(sseu)) :
490 0;
491 /*
492 * SKL+ supports slice power gating on devices with more than
493 * one slice, and supports EU power gating on devices with
494 * more than one EU pair per subslice. BXT+ supports subslice
495 * power gating on devices with more than one subslice, and
496 * supports EU power gating on devices with more than one EU
497 * pair per subslice.
498 */
499 sseu->has_slice_pg =
500 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
501 sseu->has_subslice_pg =
502 IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1;
503 sseu->has_eu_pg = sseu->eu_per_subslice > 2;
504
505 if (IS_GEN9_LP(dev_priv)) {
506 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
507 info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
508
509 sseu->min_eu_in_pool = 0;
510 if (info->has_pooled_eu) {
511 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
512 sseu->min_eu_in_pool = 3;
513 else if (IS_SS_DISABLED(1))
514 sseu->min_eu_in_pool = 6;
515 else
516 sseu->min_eu_in_pool = 9;
517 }
518 #undef IS_SS_DISABLED
519 }
520 }
521
522 static void bdw_sseu_info_init(struct drm_i915_private *dev_priv)
523 {
524 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
525 int s, ss;
526 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
527
528 fuse2 = I915_READ(GEN8_FUSE2);
529 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
530 intel_sseu_set_info(sseu, 3, 3, 8);
531
532 /*
533 * The subslice disable field is global, i.e. it applies
534 * to each of the enabled slices.
535 */
536 subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
537 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
538 GEN8_F2_SS_DIS_SHIFT);
539
540 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
541 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
542 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
543 (32 - GEN8_EU_DIS0_S1_SHIFT));
544 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
545 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
546 (32 - GEN8_EU_DIS1_S2_SHIFT));
547
548 /*
549 * Iterate through enabled slices and subslices to
550 * count the total enabled EU.
551 */
552 for (s = 0; s < sseu->max_slices; s++) {
553 if (!(sseu->slice_mask & BIT(s)))
554 /* skip disabled slice */
555 continue;
556
557 intel_sseu_set_subslices(sseu, s, subslice_mask);
558
559 for (ss = 0; ss < sseu->max_subslices; ss++) {
560 u8 eu_disabled_mask;
561 u32 n_disabled;
562
563 if (!intel_sseu_has_subslice(sseu, s, ss))
564 /* skip disabled subslice */
565 continue;
566
567 eu_disabled_mask =
568 eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
569
570 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
571
572 n_disabled = hweight8(eu_disabled_mask);
573
574 /*
575 * Record which subslices have 7 EUs.
576 */
577 if (sseu->max_eus_per_subslice - n_disabled == 7)
578 sseu->subslice_7eu[s] |= 1 << ss;
579 }
580 }
581
582 sseu->eu_total = compute_eu_total(sseu);
583
584 /*
585 * BDW is expected to always have a uniform distribution of EU across
586 * subslices with the exception that any one EU in any one subslice may
587 * be fused off for die recovery.
588 */
589 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ?
590 DIV_ROUND_UP(sseu->eu_total,
591 intel_sseu_subslice_total(sseu)) :
592 0;
593
594 /*
595 * BDW supports slice power gating on devices with more than
596 * one slice.
597 */
598 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
599 sseu->has_subslice_pg = 0;
600 sseu->has_eu_pg = 0;
601 }
602
603 static void hsw_sseu_info_init(struct drm_i915_private *dev_priv)
604 {
605 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
606 u32 fuse1;
607 u8 subslice_mask = 0;
608 int s, ss;
609
610 /*
611 * There isn't a register to tell us how many slices/subslices. We
612 * work off the PCI-ids here.
613 */
614 switch (INTEL_INFO(dev_priv)->gt) {
615 default:
616 MISSING_CASE(INTEL_INFO(dev_priv)->gt);
617 /* fall through */
618 case 1:
619 sseu->slice_mask = BIT(0);
620 subslice_mask = BIT(0);
621 break;
622 case 2:
623 sseu->slice_mask = BIT(0);
624 subslice_mask = BIT(0) | BIT(1);
625 break;
626 case 3:
627 sseu->slice_mask = BIT(0) | BIT(1);
628 subslice_mask = BIT(0) | BIT(1);
629 break;
630 }
631
632 fuse1 = I915_READ(HSW_PAVP_FUSE1);
633 switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
634 default:
635 MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
636 HSW_F1_EU_DIS_SHIFT);
637 /* fall through */
638 case HSW_F1_EU_DIS_10EUS:
639 sseu->eu_per_subslice = 10;
640 break;
641 case HSW_F1_EU_DIS_8EUS:
642 sseu->eu_per_subslice = 8;
643 break;
644 case HSW_F1_EU_DIS_6EUS:
645 sseu->eu_per_subslice = 6;
646 break;
647 }
648
649 intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
650 hweight8(subslice_mask),
651 sseu->eu_per_subslice);
652
653 for (s = 0; s < sseu->max_slices; s++) {
654 intel_sseu_set_subslices(sseu, s, subslice_mask);
655
656 for (ss = 0; ss < sseu->max_subslices; ss++) {
657 sseu_set_eus(sseu, s, ss,
658 (1UL << sseu->eu_per_subslice) - 1);
659 }
660 }
661
662 sseu->eu_total = compute_eu_total(sseu);
663
664 /* No powergating for you. */
665 sseu->has_slice_pg = 0;
666 sseu->has_subslice_pg = 0;
667 sseu->has_eu_pg = 0;
668 }
669
670 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
671 {
672 u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
673 u32 base_freq, frac_freq;
674
675 base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
676 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
677 base_freq *= 1000;
678
679 frac_freq = ((ts_override &
680 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
681 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
682 frac_freq = 1000 / (frac_freq + 1);
683
684 return base_freq + frac_freq;
685 }
686
687 static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
688 u32 rpm_config_reg)
689 {
690 u32 f19_2_mhz = 19200;
691 u32 f24_mhz = 24000;
692 u32 crystal_clock = (rpm_config_reg &
693 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
694 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
695
696 switch (crystal_clock) {
697 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
698 return f19_2_mhz;
699 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
700 return f24_mhz;
701 default:
702 MISSING_CASE(crystal_clock);
703 return 0;
704 }
705 }
706
707 static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
708 u32 rpm_config_reg)
709 {
710 u32 f19_2_mhz = 19200;
711 u32 f24_mhz = 24000;
712 u32 f25_mhz = 25000;
713 u32 f38_4_mhz = 38400;
714 u32 crystal_clock = (rpm_config_reg &
715 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
716 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
717
718 switch (crystal_clock) {
719 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
720 return f24_mhz;
721 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
722 return f19_2_mhz;
723 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
724 return f38_4_mhz;
725 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
726 return f25_mhz;
727 default:
728 MISSING_CASE(crystal_clock);
729 return 0;
730 }
731 }
732
733 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
734 {
735 u32 f12_5_mhz = 12500;
736 u32 f19_2_mhz = 19200;
737 u32 f24_mhz = 24000;
738
739 if (INTEL_GEN(dev_priv) <= 4) {
740 /* PRMs say:
741 *
742 * "The value in this register increments once every 16
743 * hclks." (through the “Clocking Configuration”
744 * (“CLKCFG”) MCHBAR register)
745 */
746 return dev_priv->rawclk_freq / 16;
747 } else if (INTEL_GEN(dev_priv) <= 8) {
748 /* PRMs say:
749 *
750 * "The PCU TSC counts 10ns increments; this timestamp
751 * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
752 * rolling over every 1.5 hours).
753 */
754 return f12_5_mhz;
755 } else if (INTEL_GEN(dev_priv) <= 9) {
756 u32 ctc_reg = I915_READ(CTC_MODE);
757 u32 freq = 0;
758
759 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
760 freq = read_reference_ts_freq(dev_priv);
761 } else {
762 freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;
763
764 /* Now figure out how the command stream's timestamp
765 * register increments from this frequency (it might
766 * increment only every few clock cycle).
767 */
768 freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
769 CTC_SHIFT_PARAMETER_SHIFT);
770 }
771
772 return freq;
773 } else if (INTEL_GEN(dev_priv) <= 12) {
774 u32 ctc_reg = I915_READ(CTC_MODE);
775 u32 freq = 0;
776
777 /* First figure out the reference frequency. There are 2 ways
778 * we can compute the frequency, either through the
779 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
780 * tells us which one we should use.
781 */
782 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
783 freq = read_reference_ts_freq(dev_priv);
784 } else {
785 u32 rpm_config_reg = I915_READ(RPM_CONFIG0);
786
787 if (INTEL_GEN(dev_priv) <= 10)
788 freq = gen10_get_crystal_clock_freq(dev_priv,
789 rpm_config_reg);
790 else
791 freq = gen11_get_crystal_clock_freq(dev_priv,
792 rpm_config_reg);
793
794 /* Now figure out how the command stream's timestamp
795 * register increments from this frequency (it might
796 * increment only every few clock cycle).
797 */
798 freq >>= 3 - ((rpm_config_reg &
799 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
800 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
801 }
802
803 return freq;
804 }
805
806 MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
807 return 0;
808 }
809
810 #undef INTEL_VGA_DEVICE
811 #define INTEL_VGA_DEVICE(id, info) (id)
812
813 static const u16 subplatform_ult_ids[] = {
814 INTEL_HSW_ULT_GT1_IDS(0),
815 INTEL_HSW_ULT_GT2_IDS(0),
816 INTEL_HSW_ULT_GT3_IDS(0),
817 INTEL_BDW_ULT_GT1_IDS(0),
818 INTEL_BDW_ULT_GT2_IDS(0),
819 INTEL_BDW_ULT_GT3_IDS(0),
820 INTEL_BDW_ULT_RSVD_IDS(0),
821 INTEL_SKL_ULT_GT1_IDS(0),
822 INTEL_SKL_ULT_GT2_IDS(0),
823 INTEL_SKL_ULT_GT3_IDS(0),
824 INTEL_KBL_ULT_GT1_IDS(0),
825 INTEL_KBL_ULT_GT2_IDS(0),
826 INTEL_KBL_ULT_GT3_IDS(0),
827 INTEL_CFL_U_GT2_IDS(0),
828 INTEL_CFL_U_GT3_IDS(0),
829 INTEL_WHL_U_GT1_IDS(0),
830 INTEL_WHL_U_GT2_IDS(0),
831 INTEL_WHL_U_GT3_IDS(0),
832 INTEL_CML_U_GT1_IDS(0),
833 INTEL_CML_U_GT2_IDS(0),
834 };
835
836 static const u16 subplatform_ulx_ids[] = {
837 INTEL_HSW_ULX_GT1_IDS(0),
838 INTEL_HSW_ULX_GT2_IDS(0),
839 INTEL_BDW_ULX_GT1_IDS(0),
840 INTEL_BDW_ULX_GT2_IDS(0),
841 INTEL_BDW_ULX_GT3_IDS(0),
842 INTEL_BDW_ULX_RSVD_IDS(0),
843 INTEL_SKL_ULX_GT1_IDS(0),
844 INTEL_SKL_ULX_GT2_IDS(0),
845 INTEL_KBL_ULX_GT1_IDS(0),
846 INTEL_KBL_ULX_GT2_IDS(0),
847 INTEL_AML_KBL_GT2_IDS(0),
848 INTEL_AML_CFL_GT2_IDS(0),
849 };
850
851 static const u16 subplatform_portf_ids[] = {
852 INTEL_CNL_PORT_F_IDS(0),
853 INTEL_ICL_PORT_F_IDS(0),
854 };
855
856 static bool find_devid(u16 id, const u16 *p, unsigned int num)
857 {
858 for (; num; num--, p++) {
859 if (*p == id)
860 return true;
861 }
862
863 return false;
864 }
865
866 void intel_device_info_subplatform_init(struct drm_i915_private *i915)
867 {
868 const struct intel_device_info *info = INTEL_INFO(i915);
869 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
870 const unsigned int pi = __platform_mask_index(rinfo, info->platform);
871 const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
872 u16 devid = INTEL_DEVID(i915);
873 u32 mask = 0;
874
875 /* Make sure IS_<platform> checks are working. */
876 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
877
878 /* Find and mark subplatform bits based on the PCI device id. */
879 if (find_devid(devid, subplatform_ult_ids,
880 ARRAY_SIZE(subplatform_ult_ids))) {
881 mask = BIT(INTEL_SUBPLATFORM_ULT);
882 } else if (find_devid(devid, subplatform_ulx_ids,
883 ARRAY_SIZE(subplatform_ulx_ids))) {
884 mask = BIT(INTEL_SUBPLATFORM_ULX);
885 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
886 /* ULX machines are also considered ULT. */
887 mask |= BIT(INTEL_SUBPLATFORM_ULT);
888 }
889 } else if (find_devid(devid, subplatform_portf_ids,
890 ARRAY_SIZE(subplatform_portf_ids))) {
891 mask = BIT(INTEL_SUBPLATFORM_PORTF);
892 }
893
894 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
895
896 RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
897 }
898
899 /**
900 * intel_device_info_runtime_init - initialize runtime info
901 * @dev_priv: the i915 device
902 *
903 * Determine various intel_device_info fields at runtime.
904 *
905 * Use it when either:
906 * - it's judged too laborious to fill n static structures with the limit
907 * when a simple if statement does the job,
908 * - run-time checks (eg read fuse/strap registers) are needed.
909 *
910 * This function needs to be called:
911 * - after the MMIO has been setup as we are reading registers,
912 * - after the PCH has been detected,
913 * - before the first usage of the fields it can tweak.
914 */
915 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
916 {
917 struct intel_device_info *info = mkwrite_device_info(dev_priv);
918 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
919 enum pipe pipe;
920
921 if (INTEL_GEN(dev_priv) >= 10) {
922 for_each_pipe(dev_priv, pipe)
923 runtime->num_scalers[pipe] = 2;
924 } else if (IS_GEN(dev_priv, 9)) {
925 runtime->num_scalers[PIPE_A] = 2;
926 runtime->num_scalers[PIPE_B] = 2;
927 runtime->num_scalers[PIPE_C] = 1;
928 }
929
930 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
931
932 if (INTEL_GEN(dev_priv) >= 11)
933 for_each_pipe(dev_priv, pipe)
934 runtime->num_sprites[pipe] = 6;
935 else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
936 for_each_pipe(dev_priv, pipe)
937 runtime->num_sprites[pipe] = 3;
938 else if (IS_BROXTON(dev_priv)) {
939 /*
940 * Skylake and Broxton currently don't expose the topmost plane as its
941 * use is exclusive with the legacy cursor and we only want to expose
942 * one of those, not both. Until we can safely expose the topmost plane
943 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
944 * we don't expose the topmost plane at all to prevent ABI breakage
945 * down the line.
946 */
947
948 runtime->num_sprites[PIPE_A] = 2;
949 runtime->num_sprites[PIPE_B] = 2;
950 runtime->num_sprites[PIPE_C] = 1;
951 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
952 for_each_pipe(dev_priv, pipe)
953 runtime->num_sprites[pipe] = 2;
954 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
955 for_each_pipe(dev_priv, pipe)
956 runtime->num_sprites[pipe] = 1;
957 }
958
959 if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) &&
960 HAS_PCH_SPLIT(dev_priv)) {
961 u32 fuse_strap = I915_READ(FUSE_STRAP);
962 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
963
964 /*
965 * SFUSE_STRAP is supposed to have a bit signalling the display
966 * is fused off. Unfortunately it seems that, at least in
967 * certain cases, fused off display means that PCH display
968 * reads don't land anywhere. In that case, we read 0s.
969 *
970 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
971 * should be set when taking over after the firmware.
972 */
973 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
974 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
975 (HAS_PCH_CPT(dev_priv) &&
976 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
977 DRM_INFO("Display fused off, disabling\n");
978 info->pipe_mask = 0;
979 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
980 DRM_INFO("PipeC fused off\n");
981 info->pipe_mask &= ~BIT(PIPE_C);
982 }
983 } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
984 u32 dfsm = I915_READ(SKL_DFSM);
985 u8 enabled_mask = info->pipe_mask;
986
987 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
988 enabled_mask &= ~BIT(PIPE_A);
989 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
990 enabled_mask &= ~BIT(PIPE_B);
991 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
992 enabled_mask &= ~BIT(PIPE_C);
993 if (INTEL_GEN(dev_priv) >= 12 &&
994 (dfsm & TGL_DFSM_PIPE_D_DISABLE))
995 enabled_mask &= ~BIT(PIPE_D);
996
997 /*
998 * At least one pipe should be enabled and if there are
999 * disabled pipes, they should be the last ones, with no holes
1000 * in the mask.
1001 */
1002 if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
1003 DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
1004 enabled_mask);
1005 else
1006 info->pipe_mask = enabled_mask;
1007
1008 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
1009 info->display.has_hdcp = 0;
1010
1011 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
1012 info->display.has_fbc = 0;
1013
1014 if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
1015 info->display.has_csr = 0;
1016
1017 if (INTEL_GEN(dev_priv) >= 10 &&
1018 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
1019 info->display.has_dsc = 0;
1020 }
1021
1022 /* Initialize slice/subslice/EU info */
1023 if (IS_HASWELL(dev_priv))
1024 hsw_sseu_info_init(dev_priv);
1025 else if (IS_CHERRYVIEW(dev_priv))
1026 cherryview_sseu_info_init(dev_priv);
1027 else if (IS_BROADWELL(dev_priv))
1028 bdw_sseu_info_init(dev_priv);
1029 else if (IS_GEN(dev_priv, 9))
1030 gen9_sseu_info_init(dev_priv);
1031 else if (IS_GEN(dev_priv, 10))
1032 gen10_sseu_info_init(dev_priv);
1033 else if (IS_GEN(dev_priv, 11))
1034 gen11_sseu_info_init(dev_priv);
1035 else if (INTEL_GEN(dev_priv) >= 12)
1036 gen12_sseu_info_init(dev_priv);
1037
1038 if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
1039 DRM_INFO("Disabling ppGTT for VT-d support\n");
1040 info->ppgtt_type = INTEL_PPGTT_NONE;
1041 }
1042
1043 /* Initialize command stream timestamp frequency */
1044 runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
1045 }
1046
1047 void intel_driver_caps_print(const struct intel_driver_caps *caps,
1048 struct drm_printer *p)
1049 {
1050 drm_printf(p, "Has logical contexts? %s\n",
1051 yesno(caps->has_logical_contexts));
1052 drm_printf(p, "scheduler: %x\n", caps->scheduler);
1053 }
1054
1055 /*
1056 * Determine which engines are fused off in our particular hardware. Since the
1057 * fuse register is in the blitter powerwell, we need forcewake to be ready at
1058 * this point (but later we need to prune the forcewake domains for engines that
1059 * are indeed fused off).
1060 */
1061 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
1062 {
1063 struct intel_device_info *info = mkwrite_device_info(dev_priv);
1064 unsigned int logical_vdbox = 0;
1065 unsigned int i;
1066 u32 media_fuse;
1067 u16 vdbox_mask;
1068 u16 vebox_mask;
1069
1070 if (INTEL_GEN(dev_priv) < 11)
1071 return;
1072
1073 media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
1074
1075 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
1076 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
1077 GEN11_GT_VEBOX_DISABLE_SHIFT;
1078
1079 for (i = 0; i < I915_MAX_VCS; i++) {
1080 if (!HAS_ENGINE(dev_priv, _VCS(i))) {
1081 vdbox_mask &= ~BIT(i);
1082 continue;
1083 }
1084
1085 if (!(BIT(i) & vdbox_mask)) {
1086 info->engine_mask &= ~BIT(_VCS(i));
1087 DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
1088 continue;
1089 }
1090
1091 /*
1092 * In Gen11, only even numbered logical VDBOXes are
1093 * hooked up to an SFC (Scaler & Format Converter) unit.
1094 * In TGL each VDBOX has access to an SFC.
1095 */
1096 if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0)
1097 RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
1098 }
1099 DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n",
1100 vdbox_mask, VDBOX_MASK(dev_priv));
1101 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv));
1102
1103 for (i = 0; i < I915_MAX_VECS; i++) {
1104 if (!HAS_ENGINE(dev_priv, _VECS(i))) {
1105 vebox_mask &= ~BIT(i);
1106 continue;
1107 }
1108
1109 if (!(BIT(i) & vebox_mask)) {
1110 info->engine_mask &= ~BIT(_VECS(i));
1111 DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
1112 }
1113 }
1114 DRM_DEBUG_DRIVER("vebox enable: %04x, instances: %04lx\n",
1115 vebox_mask, VEBOX_MASK(dev_priv));
1116 GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv));
1117 }
Linux with added FPC-III support