drivers/gpu/drm/msm/msm_gpu.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  */
   6
   7 #ifndef __MSM_GPU_H__
   8 #define __MSM_GPU_H__
   9
  10 #include <linux/clk.h>
  11 #include <linux/interconnect.h>
  12 #include <linux/regulator/consumer.h>
  13
  14 #include "msm_drv.h"
  15 #include "msm_fence.h"
  16 #include "msm_ringbuffer.h"
  17
  18 struct msm_gem_submit;
  19 struct msm_gpu_perfcntr;
  20 struct msm_gpu_state;
  21
  22 struct msm_gpu_config {
  23         const char *ioname;
  24         uint64_t va_start;
  25         uint64_t va_end;
  26         unsigned int nr_rings;
  27 };
  28
  29 /* So far, with hardware that I've seen to date, we can have:
  30  *  + zero, one, or two z180 2d cores
  31  *  + a3xx or a2xx 3d core, which share a common CP (the firmware
  32  *    for the CP seems to implement some different PM4 packet types
  33  *    but the basics of cmdstream submission are the same)
  34  *
  35  * Which means that the eventual complete "class" hierarchy, once
  36  * support for all past and present hw is in place, becomes:
  37  *  + msm_gpu
  38  *    + adreno_gpu
  39  *      + a3xx_gpu
  40  *      + a2xx_gpu
  41  *    + z180_gpu
  42  */
  43 struct msm_gpu_funcs {
  44         int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
  45         int (*hw_init)(struct msm_gpu *gpu);
  46         int (*pm_suspend)(struct msm_gpu *gpu);
  47         int (*pm_resume)(struct msm_gpu *gpu);
  48         void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
  49                         struct msm_file_private *ctx);
  50         void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
  51         irqreturn_t (*irq)(struct msm_gpu *irq);
  52         struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
  53         void (*recover)(struct msm_gpu *gpu);
  54         void (*destroy)(struct msm_gpu *gpu);
  55 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
  56         /* show GPU status in debugfs: */
  57         void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
  58                         struct drm_printer *p);
  59         /* for generation specific debugfs: */
  60         int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
  61 #endif
  62         unsigned long (*gpu_busy)(struct msm_gpu *gpu);
  63         struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
  64         int (*gpu_state_put)(struct msm_gpu_state *state);
  65         unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
  66         void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq);
  67 };
  68
  69 struct msm_gpu {
  70         const char *name;
  71         struct drm_device *dev;
  72         struct platform_device *pdev;
  73         const struct msm_gpu_funcs *funcs;
  74
  75         /* performance counters (hw & sw): */
  76         spinlock_t perf_lock;
  77         bool perfcntr_active;
  78         struct {
  79                 bool active;
  80                 ktime_t time;
  81         } last_sample;
  82         uint32_t totaltime, activetime;    /* sw counters */
  83         uint32_t last_cntrs[5];            /* hw counters */
  84         const struct msm_gpu_perfcntr *perfcntrs;
  85         uint32_t num_perfcntrs;
  86
  87         struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
  88         int nr_rings;
  89
  90         /* list of GEM active objects: */
  91         struct list_head active_list;
  92
  93         /* does gpu need hw_init? */
  94         bool needs_hw_init;
  95
  96         /* number of GPU hangs (for all contexts) */
  97         int global_faults;
  98
  99         /* worker for handling active-list retiring: */
 100         struct work_struct retire_work;
 101
 102         void __iomem *mmio;
 103         int irq;
 104
 105         struct msm_gem_address_space *aspace;
 106
 107         /* Power Control: */
 108         struct regulator *gpu_reg, *gpu_cx;
 109         struct clk_bulk_data *grp_clks;
 110         int nr_clocks;
 111         struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
 112         uint32_t fast_rate;
 113
 114         /* The gfx-mem interconnect path that's used by all GPU types. */
 115         struct icc_path *icc_path;
 116
 117         /*
 118          * Second interconnect path for some A3xx and all A4xx GPUs to the
 119          * On Chip MEMory (OCMEM).
 120          */
 121         struct icc_path *ocmem_icc_path;
 122
 123         /* Hang and Inactivity Detection:
 124          */
 125 #define DRM_MSM_INACTIVE_PERIOD   66 /* in ms (roughly four frames) */
 126
 127 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
 128 #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
 129         struct timer_list hangcheck_timer;
 130         struct work_struct recover_work;
 131
 132         struct drm_gem_object *memptrs_bo;
 133
 134         struct {
 135                 struct devfreq *devfreq;
 136                 u64 busy_cycles;
 137                 ktime_t time;
 138         } devfreq;
 139
 140         struct msm_gpu_state *crashstate;
 141 };
 142
 143 /* It turns out that all targets use the same ringbuffer size */
 144 #define MSM_GPU_RINGBUFFER_SZ SZ_32K
 145 #define MSM_GPU_RINGBUFFER_BLKSIZE 32
 146
 147 #define MSM_GPU_RB_CNTL_DEFAULT \
 148                 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
 149                 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
 150
 151 static inline bool msm_gpu_active(struct msm_gpu *gpu)
 152 {
 153         int i;
 154
 155         for (i = 0; i < gpu->nr_rings; i++) {
 156                 struct msm_ringbuffer *ring = gpu->rb[i];
 157
 158                 if (ring->seqno > ring->memptrs->fence)
 159                         return true;
 160         }
 161
 162         return false;
 163 }
 164
 165 /* Perf-Counters:
 166  * The select_reg and select_val are just there for the benefit of the child
 167  * class that actually enables the perf counter..  but msm_gpu base class
 168  * will handle sampling/displaying the counters.
 169  */
 170
 171 struct msm_gpu_perfcntr {
 172         uint32_t select_reg;
 173         uint32_t sample_reg;
 174         uint32_t select_val;
 175         const char *name;
 176 };
 177
 178 struct msm_gpu_submitqueue {
 179         int id;
 180         u32 flags;
 181         u32 prio;
 182         int faults;
 183         struct list_head node;
 184         struct kref ref;
 185 };
 186
 187 struct msm_gpu_state_bo {
 188         u64 iova;
 189         size_t size;
 190         void *data;
 191         bool encoded;
 192 };
 193
 194 struct msm_gpu_state {
 195         struct kref ref;
 196         struct timespec64 time;
 197
 198         struct {
 199                 u64 iova;
 200                 u32 fence;
 201                 u32 seqno;
 202                 u32 rptr;
 203                 u32 wptr;
 204                 void *data;
 205                 int data_size;
 206                 bool encoded;
 207         } ring[MSM_GPU_MAX_RINGS];
 208
 209         int nr_registers;
 210         u32 *registers;
 211
 212         u32 rbbm_status;
 213
 214         char *comm;
 215         char *cmd;
 216
 217         int nr_bos;
 218         struct msm_gpu_state_bo *bos;
 219 };
 220
 221 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
 222 {
 223         msm_writel(data, gpu->mmio + (reg << 2));
 224 }
 225
 226 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
 227 {
 228         return msm_readl(gpu->mmio + (reg << 2));
 229 }
 230
 231 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
 232 {
 233         uint32_t val = gpu_read(gpu, reg);
 234
 235         val &= ~mask;
 236         gpu_write(gpu, reg, val | or);
 237 }
 238
 239 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
 240 {
 241         u64 val;
 242
 243         /*
 244          * Why not a readq here? Two reasons: 1) many of the LO registers are
 245          * not quad word aligned and 2) the GPU hardware designers have a bit
 246          * of a history of putting registers where they fit, especially in
 247          * spins. The longer a GPU family goes the higher the chance that
 248          * we'll get burned.  We could do a series of validity checks if we
 249          * wanted to, but really is a readq() that much better? Nah.
 250          */
 251
 252         /*
 253          * For some lo/hi registers (like perfcounters), the hi value is latched
 254          * when the lo is read, so make sure to read the lo first to trigger
 255          * that
 256          */
 257         val = (u64) msm_readl(gpu->mmio + (lo << 2));
 258         val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
 259
 260         return val;
 261 }
 262
 263 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
 264 {
 265         /* Why not a writeq here? Read the screed above */
 266         msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
 267         msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
 268 }
 269
 270 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
 271 int msm_gpu_pm_resume(struct msm_gpu *gpu);
 272 void msm_gpu_resume_devfreq(struct msm_gpu *gpu);
 273
 274 int msm_gpu_hw_init(struct msm_gpu *gpu);
 275
 276 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
 277 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
 278 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
 279                 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
 280
 281 void msm_gpu_retire(struct msm_gpu *gpu);
 282 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 283                 struct msm_file_private *ctx);
 284
 285 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 286                 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
 287                 const char *name, struct msm_gpu_config *config);
 288
 289 void msm_gpu_cleanup(struct msm_gpu *gpu);
 290
 291 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
 292 void __init adreno_register(void);
 293 void __exit adreno_unregister(void);
 294
 295 static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
 296 {
 297         if (queue)
 298                 kref_put(&queue->ref, msm_submitqueue_destroy);
 299 }
 300
 301 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
 302 {
 303         struct msm_gpu_state *state = NULL;
 304
 305         mutex_lock(&gpu->dev->struct_mutex);
 306
 307         if (gpu->crashstate) {
 308                 kref_get(&gpu->crashstate->ref);
 309                 state = gpu->crashstate;
 310         }
 311
 312         mutex_unlock(&gpu->dev->struct_mutex);
 313
 314         return state;
 315 }
 316
 317 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
 318 {
 319         mutex_lock(&gpu->dev->struct_mutex);
 320
 321         if (gpu->crashstate) {
 322                 if (gpu->funcs->gpu_state_put(gpu->crashstate))
 323                         gpu->crashstate = NULL;
 324         }
 325
 326         mutex_unlock(&gpu->dev->struct_mutex);
 327 }
 328
 329 #endif /* __MSM_GPU_H__ */