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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / omapdrm / dss / dsi.c
blobda16ea095f13a8747a91e2d4d58a99485c7ac15f
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 */
6
7 #define DSS_SUBSYS_NAME "DSI"
8
9 #include <linux/kernel.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/regmap.h>
12 #include <linux/io.h>
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/mutex.h>
19 #include <linux/module.h>
20 #include <linux/semaphore.h>
21 #include <linux/seq_file.h>
22 #include <linux/platform_device.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/wait.h>
25 #include <linux/workqueue.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/of.h>
31 #include <linux/of_graph.h>
32 #include <linux/of_platform.h>
33 #include <linux/component.h>
34 #include <linux/sys_soc.h>
35
36 #include <video/mipi_display.h>
37
38 #include "omapdss.h"
39 #include "dss.h"
40
41 #define DSI_CATCH_MISSING_TE
42
43 struct dsi_reg { u16 module; u16 idx; };
44
45 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
46
47 /* DSI Protocol Engine */
48
49 #define DSI_PROTO 0
50 #define DSI_PROTO_SZ 0x200
51
52 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
53 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
54 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
55 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
56 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
57 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
58 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
59 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
60 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
61 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
62 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
63 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
64 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
65 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
66 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
67 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
68 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
69 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
70 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
71 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
72 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
73 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
74 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
75 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
76 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
77 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
78 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
79 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
80 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
81 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
82 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
83 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
84 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
85 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
86
87 /* DSIPHY_SCP */
88
89 #define DSI_PHY 1
90 #define DSI_PHY_OFFSET 0x200
91 #define DSI_PHY_SZ 0x40
92
93 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
94 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
95 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
96 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
97 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
98
99 /* DSI_PLL_CTRL_SCP */
100
101 #define DSI_PLL 2
102 #define DSI_PLL_OFFSET 0x300
103 #define DSI_PLL_SZ 0x20
104
105 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
106 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
107 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
108 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
109 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
110
111 #define REG_GET(dsi, idx, start, end) \
112 FLD_GET(dsi_read_reg(dsi, idx), start, end)
113
114 #define REG_FLD_MOD(dsi, idx, val, start, end) \
115 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
116
117 /* Global interrupts */
118 #define DSI_IRQ_VC0 (1 << 0)
119 #define DSI_IRQ_VC1 (1 << 1)
120 #define DSI_IRQ_VC2 (1 << 2)
121 #define DSI_IRQ_VC3 (1 << 3)
122 #define DSI_IRQ_WAKEUP (1 << 4)
123 #define DSI_IRQ_RESYNC (1 << 5)
124 #define DSI_IRQ_PLL_LOCK (1 << 7)
125 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
126 #define DSI_IRQ_PLL_RECALL (1 << 9)
127 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
128 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
129 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
130 #define DSI_IRQ_TE_TRIGGER (1 << 16)
131 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
132 #define DSI_IRQ_SYNC_LOST (1 << 18)
133 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
134 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
135 #define DSI_IRQ_ERROR_MASK \
136 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
137 DSI_IRQ_TA_TIMEOUT)
138 #define DSI_IRQ_CHANNEL_MASK 0xf
139
140 /* Virtual channel interrupts */
141 #define DSI_VC_IRQ_CS (1 << 0)
142 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
143 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
144 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
145 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
146 #define DSI_VC_IRQ_BTA (1 << 5)
147 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
148 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
149 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
150 #define DSI_VC_IRQ_ERROR_MASK \
151 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
152 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
153 DSI_VC_IRQ_FIFO_TX_UDF)
154
155 /* ComplexIO interrupts */
156 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
157 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
158 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
159 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
160 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
161 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
162 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
163 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
164 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
165 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
166 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
167 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
168 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
169 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
170 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
171 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
172 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
173 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
174 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
175 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
185 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
187 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
188 #define DSI_CIO_IRQ_ERROR_MASK \
189 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
190 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
191 DSI_CIO_IRQ_ERRSYNCESC5 | \
192 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
193 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
194 DSI_CIO_IRQ_ERRESC5 | \
195 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
196 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
197 DSI_CIO_IRQ_ERRCONTROL5 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
201 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
202 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
203
204 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
205 struct dsi_data;
206
207 static int dsi_display_init_dispc(struct dsi_data *dsi);
208 static void dsi_display_uninit_dispc(struct dsi_data *dsi);
209
210 static int dsi_vc_send_null(struct dsi_data *dsi, int channel);
211
212 /* DSI PLL HSDIV indices */
213 #define HSDIV_DISPC 0
214 #define HSDIV_DSI 1
215
216 #define DSI_MAX_NR_ISRS 2
217 #define DSI_MAX_NR_LANES 5
218
219 enum dsi_model {
220 DSI_MODEL_OMAP3,
221 DSI_MODEL_OMAP4,
222 DSI_MODEL_OMAP5,
223 };
224
225 enum dsi_lane_function {
226 DSI_LANE_UNUSED = 0,
227 DSI_LANE_CLK,
228 DSI_LANE_DATA1,
229 DSI_LANE_DATA2,
230 DSI_LANE_DATA3,
231 DSI_LANE_DATA4,
232 };
233
234 struct dsi_lane_config {
235 enum dsi_lane_function function;
236 u8 polarity;
237 };
238
239 struct dsi_isr_data {
240 omap_dsi_isr_t isr;
241 void *arg;
242 u32 mask;
243 };
244
245 enum fifo_size {
246 DSI_FIFO_SIZE_0 = 0,
247 DSI_FIFO_SIZE_32 = 1,
248 DSI_FIFO_SIZE_64 = 2,
249 DSI_FIFO_SIZE_96 = 3,
250 DSI_FIFO_SIZE_128 = 4,
251 };
252
253 enum dsi_vc_source {
254 DSI_VC_SOURCE_L4 = 0,
255 DSI_VC_SOURCE_VP,
256 };
257
258 struct dsi_irq_stats {
259 unsigned long last_reset;
260 unsigned int irq_count;
261 unsigned int dsi_irqs[32];
262 unsigned int vc_irqs[4][32];
263 unsigned int cio_irqs[32];
264 };
265
266 struct dsi_isr_tables {
267 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
268 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
269 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
270 };
271
272 struct dsi_clk_calc_ctx {
273 struct dsi_data *dsi;
274 struct dss_pll *pll;
275
276 /* inputs */
277
278 const struct omap_dss_dsi_config *config;
279
280 unsigned long req_pck_min, req_pck_nom, req_pck_max;
281
282 /* outputs */
283
284 struct dss_pll_clock_info dsi_cinfo;
285 struct dispc_clock_info dispc_cinfo;
286
287 struct videomode vm;
288 struct omap_dss_dsi_videomode_timings dsi_vm;
289 };
290
291 struct dsi_lp_clock_info {
292 unsigned long lp_clk;
293 u16 lp_clk_div;
294 };
295
296 struct dsi_module_id_data {
297 u32 address;
298 int id;
299 };
300
301 enum dsi_quirks {
302 DSI_QUIRK_PLL_PWR_BUG = (1 << 0), /* DSI-PLL power command 0x3 is not working */
303 DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1),
304 DSI_QUIRK_VC_OCP_WIDTH = (1 << 2),
305 DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3),
306 DSI_QUIRK_GNQ = (1 << 4),
307 DSI_QUIRK_PHY_DCC = (1 << 5),
308 };
309
310 struct dsi_of_data {
311 enum dsi_model model;
312 const struct dss_pll_hw *pll_hw;
313 const struct dsi_module_id_data *modules;
314 unsigned int max_fck_freq;
315 unsigned int max_pll_lpdiv;
316 enum dsi_quirks quirks;
317 };
318
319 struct dsi_data {
320 struct device *dev;
321 void __iomem *proto_base;
322 void __iomem *phy_base;
323 void __iomem *pll_base;
324
325 const struct dsi_of_data *data;
326 int module_id;
327
328 int irq;
329
330 bool is_enabled;
331
332 struct clk *dss_clk;
333 struct regmap *syscon;
334 struct dss_device *dss;
335
336 struct dispc_clock_info user_dispc_cinfo;
337 struct dss_pll_clock_info user_dsi_cinfo;
338
339 struct dsi_lp_clock_info user_lp_cinfo;
340 struct dsi_lp_clock_info current_lp_cinfo;
341
342 struct dss_pll pll;
343
344 bool vdds_dsi_enabled;
345 struct regulator *vdds_dsi_reg;
346
347 struct {
348 enum dsi_vc_source source;
349 struct omap_dss_device *dssdev;
350 enum fifo_size tx_fifo_size;
351 enum fifo_size rx_fifo_size;
352 int vc_id;
353 } vc[4];
354
355 struct mutex lock;
356 struct semaphore bus_lock;
357
358 spinlock_t irq_lock;
359 struct dsi_isr_tables isr_tables;
360 /* space for a copy used by the interrupt handler */
361 struct dsi_isr_tables isr_tables_copy;
362
363 int update_channel;
364 #ifdef DSI_PERF_MEASURE
365 unsigned int update_bytes;
366 #endif
367
368 bool te_enabled;
369 bool ulps_enabled;
370
371 void (*framedone_callback)(int, void *);
372 void *framedone_data;
373
374 struct delayed_work framedone_timeout_work;
375
376 #ifdef DSI_CATCH_MISSING_TE
377 struct timer_list te_timer;
378 #endif
379
380 unsigned long cache_req_pck;
381 unsigned long cache_clk_freq;
382 struct dss_pll_clock_info cache_cinfo;
383
384 u32 errors;
385 spinlock_t errors_lock;
386 #ifdef DSI_PERF_MEASURE
387 ktime_t perf_setup_time;
388 ktime_t perf_start_time;
389 #endif
390 int debug_read;
391 int debug_write;
392 struct {
393 struct dss_debugfs_entry *irqs;
394 struct dss_debugfs_entry *regs;
395 struct dss_debugfs_entry *clks;
396 } debugfs;
397
398 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
399 spinlock_t irq_stats_lock;
400 struct dsi_irq_stats irq_stats;
401 #endif
402
403 unsigned int num_lanes_supported;
404 unsigned int line_buffer_size;
405
406 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
407 unsigned int num_lanes_used;
408
409 unsigned int scp_clk_refcount;
410
411 struct dss_lcd_mgr_config mgr_config;
412 struct videomode vm;
413 enum omap_dss_dsi_pixel_format pix_fmt;
414 enum omap_dss_dsi_mode mode;
415 struct omap_dss_dsi_videomode_timings vm_timings;
416
417 struct omap_dss_device output;
418 };
419
420 struct dsi_packet_sent_handler_data {
421 struct dsi_data *dsi;
422 struct completion *completion;
423 };
424
425 #ifdef DSI_PERF_MEASURE
426 static bool dsi_perf;
427 module_param(dsi_perf, bool, 0644);
428 #endif
429
430 static inline struct dsi_data *to_dsi_data(struct omap_dss_device *dssdev)
431 {
432 return dev_get_drvdata(dssdev->dev);
433 }
434
435 static inline void dsi_write_reg(struct dsi_data *dsi,
436 const struct dsi_reg idx, u32 val)
437 {
438 void __iomem *base;
439
440 switch(idx.module) {
441 case DSI_PROTO: base = dsi->proto_base; break;
442 case DSI_PHY: base = dsi->phy_base; break;
443 case DSI_PLL: base = dsi->pll_base; break;
444 default: return;
445 }
446
447 __raw_writel(val, base + idx.idx);
448 }
449
450 static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx)
451 {
452 void __iomem *base;
453
454 switch(idx.module) {
455 case DSI_PROTO: base = dsi->proto_base; break;
456 case DSI_PHY: base = dsi->phy_base; break;
457 case DSI_PLL: base = dsi->pll_base; break;
458 default: return 0;
459 }
460
461 return __raw_readl(base + idx.idx);
462 }
463
464 static void dsi_bus_lock(struct omap_dss_device *dssdev)
465 {
466 struct dsi_data *dsi = to_dsi_data(dssdev);
467
468 down(&dsi->bus_lock);
469 }
470
471 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
472 {
473 struct dsi_data *dsi = to_dsi_data(dssdev);
474
475 up(&dsi->bus_lock);
476 }
477
478 static bool dsi_bus_is_locked(struct dsi_data *dsi)
479 {
480 return dsi->bus_lock.count == 0;
481 }
482
483 static void dsi_completion_handler(void *data, u32 mask)
484 {
485 complete((struct completion *)data);
486 }
487
488 static inline bool wait_for_bit_change(struct dsi_data *dsi,
489 const struct dsi_reg idx,
490 int bitnum, int value)
491 {
492 unsigned long timeout;
493 ktime_t wait;
494 int t;
495
496 /* first busyloop to see if the bit changes right away */
497 t = 100;
498 while (t-- > 0) {
499 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
500 return true;
501 }
502
503 /* then loop for 500ms, sleeping for 1ms in between */
504 timeout = jiffies + msecs_to_jiffies(500);
505 while (time_before(jiffies, timeout)) {
506 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
507 return true;
508
509 wait = ns_to_ktime(1000 * 1000);
510 set_current_state(TASK_UNINTERRUPTIBLE);
511 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
512 }
513
514 return false;
515 }
516
517 static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
518 {
519 switch (fmt) {
520 case OMAP_DSS_DSI_FMT_RGB888:
521 case OMAP_DSS_DSI_FMT_RGB666:
522 return 24;
523 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
524 return 18;
525 case OMAP_DSS_DSI_FMT_RGB565:
526 return 16;
527 default:
528 BUG();
529 return 0;
530 }
531 }
532
533 #ifdef DSI_PERF_MEASURE
534 static void dsi_perf_mark_setup(struct dsi_data *dsi)
535 {
536 dsi->perf_setup_time = ktime_get();
537 }
538
539 static void dsi_perf_mark_start(struct dsi_data *dsi)
540 {
541 dsi->perf_start_time = ktime_get();
542 }
543
544 static void dsi_perf_show(struct dsi_data *dsi, const char *name)
545 {
546 ktime_t t, setup_time, trans_time;
547 u32 total_bytes;
548 u32 setup_us, trans_us, total_us;
549
550 if (!dsi_perf)
551 return;
552
553 t = ktime_get();
554
555 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
556 setup_us = (u32)ktime_to_us(setup_time);
557 if (setup_us == 0)
558 setup_us = 1;
559
560 trans_time = ktime_sub(t, dsi->perf_start_time);
561 trans_us = (u32)ktime_to_us(trans_time);
562 if (trans_us == 0)
563 trans_us = 1;
564
565 total_us = setup_us + trans_us;
566
567 total_bytes = dsi->update_bytes;
568
569 pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n",
570 name,
571 setup_us,
572 trans_us,
573 total_us,
574 1000 * 1000 / total_us,
575 total_bytes,
576 total_bytes * 1000 / total_us);
577 }
578 #else
579 static inline void dsi_perf_mark_setup(struct dsi_data *dsi)
580 {
581 }
582
583 static inline void dsi_perf_mark_start(struct dsi_data *dsi)
584 {
585 }
586
587 static inline void dsi_perf_show(struct dsi_data *dsi, const char *name)
588 {
589 }
590 #endif
591
592 static int verbose_irq;
593
594 static void print_irq_status(u32 status)
595 {
596 if (status == 0)
597 return;
598
599 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
600 return;
601
602 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
603
604 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
605 status,
606 verbose_irq ? PIS(VC0) : "",
607 verbose_irq ? PIS(VC1) : "",
608 verbose_irq ? PIS(VC2) : "",
609 verbose_irq ? PIS(VC3) : "",
610 PIS(WAKEUP),
611 PIS(RESYNC),
612 PIS(PLL_LOCK),
613 PIS(PLL_UNLOCK),
614 PIS(PLL_RECALL),
615 PIS(COMPLEXIO_ERR),
616 PIS(HS_TX_TIMEOUT),
617 PIS(LP_RX_TIMEOUT),
618 PIS(TE_TRIGGER),
619 PIS(ACK_TRIGGER),
620 PIS(SYNC_LOST),
621 PIS(LDO_POWER_GOOD),
622 PIS(TA_TIMEOUT));
623 #undef PIS
624 }
625
626 static void print_irq_status_vc(int channel, u32 status)
627 {
628 if (status == 0)
629 return;
630
631 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
632 return;
633
634 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
635
636 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
637 channel,
638 status,
639 PIS(CS),
640 PIS(ECC_CORR),
641 PIS(ECC_NO_CORR),
642 verbose_irq ? PIS(PACKET_SENT) : "",
643 PIS(BTA),
644 PIS(FIFO_TX_OVF),
645 PIS(FIFO_RX_OVF),
646 PIS(FIFO_TX_UDF),
647 PIS(PP_BUSY_CHANGE));
648 #undef PIS
649 }
650
651 static void print_irq_status_cio(u32 status)
652 {
653 if (status == 0)
654 return;
655
656 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
657
658 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
659 status,
660 PIS(ERRSYNCESC1),
661 PIS(ERRSYNCESC2),
662 PIS(ERRSYNCESC3),
663 PIS(ERRESC1),
664 PIS(ERRESC2),
665 PIS(ERRESC3),
666 PIS(ERRCONTROL1),
667 PIS(ERRCONTROL2),
668 PIS(ERRCONTROL3),
669 PIS(STATEULPS1),
670 PIS(STATEULPS2),
671 PIS(STATEULPS3),
672 PIS(ERRCONTENTIONLP0_1),
673 PIS(ERRCONTENTIONLP1_1),
674 PIS(ERRCONTENTIONLP0_2),
675 PIS(ERRCONTENTIONLP1_2),
676 PIS(ERRCONTENTIONLP0_3),
677 PIS(ERRCONTENTIONLP1_3),
678 PIS(ULPSACTIVENOT_ALL0),
679 PIS(ULPSACTIVENOT_ALL1));
680 #undef PIS
681 }
682
683 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
684 static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus,
685 u32 *vcstatus, u32 ciostatus)
686 {
687 int i;
688
689 spin_lock(&dsi->irq_stats_lock);
690
691 dsi->irq_stats.irq_count++;
692 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
693
694 for (i = 0; i < 4; ++i)
695 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
696
697 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
698
699 spin_unlock(&dsi->irq_stats_lock);
700 }
701 #else
702 #define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus)
703 #endif
704
705 static int debug_irq;
706
707 static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus,
708 u32 *vcstatus, u32 ciostatus)
709 {
710 int i;
711
712 if (irqstatus & DSI_IRQ_ERROR_MASK) {
713 DSSERR("DSI error, irqstatus %x\n", irqstatus);
714 print_irq_status(irqstatus);
715 spin_lock(&dsi->errors_lock);
716 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
717 spin_unlock(&dsi->errors_lock);
718 } else if (debug_irq) {
719 print_irq_status(irqstatus);
720 }
721
722 for (i = 0; i < 4; ++i) {
723 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
724 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
725 i, vcstatus[i]);
726 print_irq_status_vc(i, vcstatus[i]);
727 } else if (debug_irq) {
728 print_irq_status_vc(i, vcstatus[i]);
729 }
730 }
731
732 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
733 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
734 print_irq_status_cio(ciostatus);
735 } else if (debug_irq) {
736 print_irq_status_cio(ciostatus);
737 }
738 }
739
740 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
741 unsigned int isr_array_size, u32 irqstatus)
742 {
743 struct dsi_isr_data *isr_data;
744 int i;
745
746 for (i = 0; i < isr_array_size; i++) {
747 isr_data = &isr_array[i];
748 if (isr_data->isr && isr_data->mask & irqstatus)
749 isr_data->isr(isr_data->arg, irqstatus);
750 }
751 }
752
753 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
754 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
755 {
756 int i;
757
758 dsi_call_isrs(isr_tables->isr_table,
759 ARRAY_SIZE(isr_tables->isr_table),
760 irqstatus);
761
762 for (i = 0; i < 4; ++i) {
763 if (vcstatus[i] == 0)
764 continue;
765 dsi_call_isrs(isr_tables->isr_table_vc[i],
766 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
767 vcstatus[i]);
768 }
769
770 if (ciostatus != 0)
771 dsi_call_isrs(isr_tables->isr_table_cio,
772 ARRAY_SIZE(isr_tables->isr_table_cio),
773 ciostatus);
774 }
775
776 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
777 {
778 struct dsi_data *dsi = arg;
779 u32 irqstatus, vcstatus[4], ciostatus;
780 int i;
781
782 if (!dsi->is_enabled)
783 return IRQ_NONE;
784
785 spin_lock(&dsi->irq_lock);
786
787 irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS);
788
789 /* IRQ is not for us */
790 if (!irqstatus) {
791 spin_unlock(&dsi->irq_lock);
792 return IRQ_NONE;
793 }
794
795 dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
796 /* flush posted write */
797 dsi_read_reg(dsi, DSI_IRQSTATUS);
798
799 for (i = 0; i < 4; ++i) {
800 if ((irqstatus & (1 << i)) == 0) {
801 vcstatus[i] = 0;
802 continue;
803 }
804
805 vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
806
807 dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]);
808 /* flush posted write */
809 dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
810 }
811
812 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
813 ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
814
815 dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
816 /* flush posted write */
817 dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
818 } else {
819 ciostatus = 0;
820 }
821
822 #ifdef DSI_CATCH_MISSING_TE
823 if (irqstatus & DSI_IRQ_TE_TRIGGER)
824 del_timer(&dsi->te_timer);
825 #endif
826
827 /* make a copy and unlock, so that isrs can unregister
828 * themselves */
829 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
830 sizeof(dsi->isr_tables));
831
832 spin_unlock(&dsi->irq_lock);
833
834 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
835
836 dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus);
837
838 dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus);
839
840 return IRQ_HANDLED;
841 }
842
843 /* dsi->irq_lock has to be locked by the caller */
844 static void _omap_dsi_configure_irqs(struct dsi_data *dsi,
845 struct dsi_isr_data *isr_array,
846 unsigned int isr_array_size,
847 u32 default_mask,
848 const struct dsi_reg enable_reg,
849 const struct dsi_reg status_reg)
850 {
851 struct dsi_isr_data *isr_data;
852 u32 mask;
853 u32 old_mask;
854 int i;
855
856 mask = default_mask;
857
858 for (i = 0; i < isr_array_size; i++) {
859 isr_data = &isr_array[i];
860
861 if (isr_data->isr == NULL)
862 continue;
863
864 mask |= isr_data->mask;
865 }
866
867 old_mask = dsi_read_reg(dsi, enable_reg);
868 /* clear the irqstatus for newly enabled irqs */
869 dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask);
870 dsi_write_reg(dsi, enable_reg, mask);
871
872 /* flush posted writes */
873 dsi_read_reg(dsi, enable_reg);
874 dsi_read_reg(dsi, status_reg);
875 }
876
877 /* dsi->irq_lock has to be locked by the caller */
878 static void _omap_dsi_set_irqs(struct dsi_data *dsi)
879 {
880 u32 mask = DSI_IRQ_ERROR_MASK;
881 #ifdef DSI_CATCH_MISSING_TE
882 mask |= DSI_IRQ_TE_TRIGGER;
883 #endif
884 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table,
885 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
886 DSI_IRQENABLE, DSI_IRQSTATUS);
887 }
888
889 /* dsi->irq_lock has to be locked by the caller */
890 static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc)
891 {
892 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc],
893 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
894 DSI_VC_IRQ_ERROR_MASK,
895 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
896 }
897
898 /* dsi->irq_lock has to be locked by the caller */
899 static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi)
900 {
901 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio,
902 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
903 DSI_CIO_IRQ_ERROR_MASK,
904 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
905 }
906
907 static void _dsi_initialize_irq(struct dsi_data *dsi)
908 {
909 unsigned long flags;
910 int vc;
911
912 spin_lock_irqsave(&dsi->irq_lock, flags);
913
914 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
915
916 _omap_dsi_set_irqs(dsi);
917 for (vc = 0; vc < 4; ++vc)
918 _omap_dsi_set_irqs_vc(dsi, vc);
919 _omap_dsi_set_irqs_cio(dsi);
920
921 spin_unlock_irqrestore(&dsi->irq_lock, flags);
922 }
923
924 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
925 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
926 {
927 struct dsi_isr_data *isr_data;
928 int free_idx;
929 int i;
930
931 BUG_ON(isr == NULL);
932
933 /* check for duplicate entry and find a free slot */
934 free_idx = -1;
935 for (i = 0; i < isr_array_size; i++) {
936 isr_data = &isr_array[i];
937
938 if (isr_data->isr == isr && isr_data->arg == arg &&
939 isr_data->mask == mask) {
940 return -EINVAL;
941 }
942
943 if (isr_data->isr == NULL && free_idx == -1)
944 free_idx = i;
945 }
946
947 if (free_idx == -1)
948 return -EBUSY;
949
950 isr_data = &isr_array[free_idx];
951 isr_data->isr = isr;
952 isr_data->arg = arg;
953 isr_data->mask = mask;
954
955 return 0;
956 }
957
958 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
959 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
960 {
961 struct dsi_isr_data *isr_data;
962 int i;
963
964 for (i = 0; i < isr_array_size; i++) {
965 isr_data = &isr_array[i];
966 if (isr_data->isr != isr || isr_data->arg != arg ||
967 isr_data->mask != mask)
968 continue;
969
970 isr_data->isr = NULL;
971 isr_data->arg = NULL;
972 isr_data->mask = 0;
973
974 return 0;
975 }
976
977 return -EINVAL;
978 }
979
980 static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
981 void *arg, u32 mask)
982 {
983 unsigned long flags;
984 int r;
985
986 spin_lock_irqsave(&dsi->irq_lock, flags);
987
988 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
989 ARRAY_SIZE(dsi->isr_tables.isr_table));
990
991 if (r == 0)
992 _omap_dsi_set_irqs(dsi);
993
994 spin_unlock_irqrestore(&dsi->irq_lock, flags);
995
996 return r;
997 }
998
999 static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
1000 void *arg, u32 mask)
1001 {
1002 unsigned long flags;
1003 int r;
1004
1005 spin_lock_irqsave(&dsi->irq_lock, flags);
1006
1007 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1008 ARRAY_SIZE(dsi->isr_tables.isr_table));
1009
1010 if (r == 0)
1011 _omap_dsi_set_irqs(dsi);
1012
1013 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1014
1015 return r;
1016 }
1017
1018 static int dsi_register_isr_vc(struct dsi_data *dsi, int channel,
1019 omap_dsi_isr_t isr, void *arg, u32 mask)
1020 {
1021 unsigned long flags;
1022 int r;
1023
1024 spin_lock_irqsave(&dsi->irq_lock, flags);
1025
1026 r = _dsi_register_isr(isr, arg, mask,
1027 dsi->isr_tables.isr_table_vc[channel],
1028 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1029
1030 if (r == 0)
1031 _omap_dsi_set_irqs_vc(dsi, channel);
1032
1033 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1034
1035 return r;
1036 }
1037
1038 static int dsi_unregister_isr_vc(struct dsi_data *dsi, int channel,
1039 omap_dsi_isr_t isr, void *arg, u32 mask)
1040 {
1041 unsigned long flags;
1042 int r;
1043
1044 spin_lock_irqsave(&dsi->irq_lock, flags);
1045
1046 r = _dsi_unregister_isr(isr, arg, mask,
1047 dsi->isr_tables.isr_table_vc[channel],
1048 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1049
1050 if (r == 0)
1051 _omap_dsi_set_irqs_vc(dsi, channel);
1052
1053 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1054
1055 return r;
1056 }
1057
1058 static int dsi_register_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr,
1059 void *arg, u32 mask)
1060 {
1061 unsigned long flags;
1062 int r;
1063
1064 spin_lock_irqsave(&dsi->irq_lock, flags);
1065
1066 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1067 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1068
1069 if (r == 0)
1070 _omap_dsi_set_irqs_cio(dsi);
1071
1072 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1073
1074 return r;
1075 }
1076
1077 static int dsi_unregister_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr,
1078 void *arg, u32 mask)
1079 {
1080 unsigned long flags;
1081 int r;
1082
1083 spin_lock_irqsave(&dsi->irq_lock, flags);
1084
1085 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1086 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1087
1088 if (r == 0)
1089 _omap_dsi_set_irqs_cio(dsi);
1090
1091 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1092
1093 return r;
1094 }
1095
1096 static u32 dsi_get_errors(struct dsi_data *dsi)
1097 {
1098 unsigned long flags;
1099 u32 e;
1100
1101 spin_lock_irqsave(&dsi->errors_lock, flags);
1102 e = dsi->errors;
1103 dsi->errors = 0;
1104 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1105 return e;
1106 }
1107
1108 static int dsi_runtime_get(struct dsi_data *dsi)
1109 {
1110 int r;
1111
1112 DSSDBG("dsi_runtime_get\n");
1113
1114 r = pm_runtime_get_sync(dsi->dev);
1115 WARN_ON(r < 0);
1116 return r < 0 ? r : 0;
1117 }
1118
1119 static void dsi_runtime_put(struct dsi_data *dsi)
1120 {
1121 int r;
1122
1123 DSSDBG("dsi_runtime_put\n");
1124
1125 r = pm_runtime_put_sync(dsi->dev);
1126 WARN_ON(r < 0 && r != -ENOSYS);
1127 }
1128
1129 static void _dsi_print_reset_status(struct dsi_data *dsi)
1130 {
1131 u32 l;
1132 int b0, b1, b2;
1133
1134 /* A dummy read using the SCP interface to any DSIPHY register is
1135 * required after DSIPHY reset to complete the reset of the DSI complex
1136 * I/O. */
1137 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1138
1139 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) {
1140 b0 = 28;
1141 b1 = 27;
1142 b2 = 26;
1143 } else {
1144 b0 = 24;
1145 b1 = 25;
1146 b2 = 26;
1147 }
1148
1149 #define DSI_FLD_GET(fld, start, end)\
1150 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end)
1151
1152 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1153 DSI_FLD_GET(PLL_STATUS, 0, 0),
1154 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1155 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1156 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1157 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1158 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1159 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1160 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1161
1162 #undef DSI_FLD_GET
1163 }
1164
1165 static inline int dsi_if_enable(struct dsi_data *dsi, bool enable)
1166 {
1167 DSSDBG("dsi_if_enable(%d)\n", enable);
1168
1169 enable = enable ? 1 : 0;
1170 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */
1171
1172 if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) {
1173 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1174 return -EIO;
1175 }
1176
1177 return 0;
1178 }
1179
1180 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi)
1181 {
1182 return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1183 }
1184
1185 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi)
1186 {
1187 return dsi->pll.cinfo.clkout[HSDIV_DSI];
1188 }
1189
1190 static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi)
1191 {
1192 return dsi->pll.cinfo.clkdco / 16;
1193 }
1194
1195 static unsigned long dsi_fclk_rate(struct dsi_data *dsi)
1196 {
1197 unsigned long r;
1198 enum dss_clk_source source;
1199
1200 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id);
1201 if (source == DSS_CLK_SRC_FCK) {
1202 /* DSI FCLK source is DSS_CLK_FCK */
1203 r = clk_get_rate(dsi->dss_clk);
1204 } else {
1205 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1206 r = dsi_get_pll_hsdiv_dsi_rate(dsi);
1207 }
1208
1209 return r;
1210 }
1211
1212 static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1213 unsigned long lp_clk_min, unsigned long lp_clk_max,
1214 struct dsi_lp_clock_info *lp_cinfo)
1215 {
1216 unsigned int lp_clk_div;
1217 unsigned long lp_clk;
1218
1219 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1220 lp_clk = dsi_fclk / 2 / lp_clk_div;
1221
1222 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1223 return -EINVAL;
1224
1225 lp_cinfo->lp_clk_div = lp_clk_div;
1226 lp_cinfo->lp_clk = lp_clk;
1227
1228 return 0;
1229 }
1230
1231 static int dsi_set_lp_clk_divisor(struct dsi_data *dsi)
1232 {
1233 unsigned long dsi_fclk;
1234 unsigned int lp_clk_div;
1235 unsigned long lp_clk;
1236 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv;
1237
1238
1239 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
1240
1241 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1242 return -EINVAL;
1243
1244 dsi_fclk = dsi_fclk_rate(dsi);
1245
1246 lp_clk = dsi_fclk / 2 / lp_clk_div;
1247
1248 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1249 dsi->current_lp_cinfo.lp_clk = lp_clk;
1250 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1251
1252 /* LP_CLK_DIVISOR */
1253 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1254
1255 /* LP_RX_SYNCHRO_ENABLE */
1256 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1257
1258 return 0;
1259 }
1260
1261 static void dsi_enable_scp_clk(struct dsi_data *dsi)
1262 {
1263 if (dsi->scp_clk_refcount++ == 0)
1264 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1265 }
1266
1267 static void dsi_disable_scp_clk(struct dsi_data *dsi)
1268 {
1269 WARN_ON(dsi->scp_clk_refcount == 0);
1270 if (--dsi->scp_clk_refcount == 0)
1271 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1272 }
1273
1274 enum dsi_pll_power_state {
1275 DSI_PLL_POWER_OFF = 0x0,
1276 DSI_PLL_POWER_ON_HSCLK = 0x1,
1277 DSI_PLL_POWER_ON_ALL = 0x2,
1278 DSI_PLL_POWER_ON_DIV = 0x3,
1279 };
1280
1281 static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state)
1282 {
1283 int t = 0;
1284
1285 /* DSI-PLL power command 0x3 is not working */
1286 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) &&
1287 state == DSI_PLL_POWER_ON_DIV)
1288 state = DSI_PLL_POWER_ON_ALL;
1289
1290 /* PLL_PWR_CMD */
1291 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30);
1292
1293 /* PLL_PWR_STATUS */
1294 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) {
1295 if (++t > 1000) {
1296 DSSERR("Failed to set DSI PLL power mode to %d\n",
1297 state);
1298 return -ENODEV;
1299 }
1300 udelay(1);
1301 }
1302
1303 return 0;
1304 }
1305
1306
1307 static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi,
1308 struct dss_pll_clock_info *cinfo)
1309 {
1310 unsigned long max_dsi_fck;
1311
1312 max_dsi_fck = dsi->data->max_fck_freq;
1313
1314 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
1315 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
1316 }
1317
1318 static int dsi_pll_enable(struct dss_pll *pll)
1319 {
1320 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1321 int r = 0;
1322
1323 DSSDBG("PLL init\n");
1324
1325 r = dsi_runtime_get(dsi);
1326 if (r)
1327 return r;
1328
1329 /*
1330 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1331 */
1332 dsi_enable_scp_clk(dsi);
1333
1334 r = regulator_enable(dsi->vdds_dsi_reg);
1335 if (r)
1336 goto err0;
1337
1338 /* XXX PLL does not come out of reset without this... */
1339 dispc_pck_free_enable(dsi->dss->dispc, 1);
1340
1341 if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) {
1342 DSSERR("PLL not coming out of reset.\n");
1343 r = -ENODEV;
1344 dispc_pck_free_enable(dsi->dss->dispc, 0);
1345 goto err1;
1346 }
1347
1348 /* XXX ... but if left on, we get problems when planes do not
1349 * fill the whole display. No idea about this */
1350 dispc_pck_free_enable(dsi->dss->dispc, 0);
1351
1352 r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL);
1353
1354 if (r)
1355 goto err1;
1356
1357 DSSDBG("PLL init done\n");
1358
1359 return 0;
1360 err1:
1361 regulator_disable(dsi->vdds_dsi_reg);
1362 err0:
1363 dsi_disable_scp_clk(dsi);
1364 dsi_runtime_put(dsi);
1365 return r;
1366 }
1367
1368 static void dsi_pll_disable(struct dss_pll *pll)
1369 {
1370 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1371
1372 dsi_pll_power(dsi, DSI_PLL_POWER_OFF);
1373
1374 regulator_disable(dsi->vdds_dsi_reg);
1375
1376 dsi_disable_scp_clk(dsi);
1377 dsi_runtime_put(dsi);
1378
1379 DSSDBG("PLL disable done\n");
1380 }
1381
1382 static int dsi_dump_dsi_clocks(struct seq_file *s, void *p)
1383 {
1384 struct dsi_data *dsi = s->private;
1385 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1386 enum dss_clk_source dispc_clk_src, dsi_clk_src;
1387 int dsi_module = dsi->module_id;
1388 struct dss_pll *pll = &dsi->pll;
1389
1390 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss);
1391 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module);
1392
1393 if (dsi_runtime_get(dsi))
1394 return 0;
1395
1396 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1397
1398 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1399
1400 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
1401
1402 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n",
1403 cinfo->clkdco, cinfo->m);
1404
1405 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1406 dss_get_clk_source_name(dsi_module == 0 ?
1407 DSS_CLK_SRC_PLL1_1 :
1408 DSS_CLK_SRC_PLL2_1),
1409 cinfo->clkout[HSDIV_DISPC],
1410 cinfo->mX[HSDIV_DISPC],
1411 dispc_clk_src == DSS_CLK_SRC_FCK ?
1412 "off" : "on");
1413
1414 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1415 dss_get_clk_source_name(dsi_module == 0 ?
1416 DSS_CLK_SRC_PLL1_2 :
1417 DSS_CLK_SRC_PLL2_2),
1418 cinfo->clkout[HSDIV_DSI],
1419 cinfo->mX[HSDIV_DSI],
1420 dsi_clk_src == DSS_CLK_SRC_FCK ?
1421 "off" : "on");
1422
1423 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1424
1425 seq_printf(s, "dsi fclk source = %s\n",
1426 dss_get_clk_source_name(dsi_clk_src));
1427
1428 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi));
1429
1430 seq_printf(s, "DDR_CLK\t\t%lu\n",
1431 cinfo->clkdco / 4);
1432
1433 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi));
1434
1435 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1436
1437 dsi_runtime_put(dsi);
1438
1439 return 0;
1440 }
1441
1442 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1443 static int dsi_dump_dsi_irqs(struct seq_file *s, void *p)
1444 {
1445 struct dsi_data *dsi = s->private;
1446 unsigned long flags;
1447 struct dsi_irq_stats stats;
1448
1449 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1450
1451 stats = dsi->irq_stats;
1452 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1453 dsi->irq_stats.last_reset = jiffies;
1454
1455 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1456
1457 seq_printf(s, "period %u ms\n",
1458 jiffies_to_msecs(jiffies - stats.last_reset));
1459
1460 seq_printf(s, "irqs %d\n", stats.irq_count);
1461 #define PIS(x) \
1462 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1463
1464 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1465 PIS(VC0);
1466 PIS(VC1);
1467 PIS(VC2);
1468 PIS(VC3);
1469 PIS(WAKEUP);
1470 PIS(RESYNC);
1471 PIS(PLL_LOCK);
1472 PIS(PLL_UNLOCK);
1473 PIS(PLL_RECALL);
1474 PIS(COMPLEXIO_ERR);
1475 PIS(HS_TX_TIMEOUT);
1476 PIS(LP_RX_TIMEOUT);
1477 PIS(TE_TRIGGER);
1478 PIS(ACK_TRIGGER);
1479 PIS(SYNC_LOST);
1480 PIS(LDO_POWER_GOOD);
1481 PIS(TA_TIMEOUT);
1482 #undef PIS
1483
1484 #define PIS(x) \
1485 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1486 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1487 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1488 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1489 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1490
1491 seq_printf(s, "-- VC interrupts --\n");
1492 PIS(CS);
1493 PIS(ECC_CORR);
1494 PIS(PACKET_SENT);
1495 PIS(FIFO_TX_OVF);
1496 PIS(FIFO_RX_OVF);
1497 PIS(BTA);
1498 PIS(ECC_NO_CORR);
1499 PIS(FIFO_TX_UDF);
1500 PIS(PP_BUSY_CHANGE);
1501 #undef PIS
1502
1503 #define PIS(x) \
1504 seq_printf(s, "%-20s %10d\n", #x, \
1505 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1506
1507 seq_printf(s, "-- CIO interrupts --\n");
1508 PIS(ERRSYNCESC1);
1509 PIS(ERRSYNCESC2);
1510 PIS(ERRSYNCESC3);
1511 PIS(ERRESC1);
1512 PIS(ERRESC2);
1513 PIS(ERRESC3);
1514 PIS(ERRCONTROL1);
1515 PIS(ERRCONTROL2);
1516 PIS(ERRCONTROL3);
1517 PIS(STATEULPS1);
1518 PIS(STATEULPS2);
1519 PIS(STATEULPS3);
1520 PIS(ERRCONTENTIONLP0_1);
1521 PIS(ERRCONTENTIONLP1_1);
1522 PIS(ERRCONTENTIONLP0_2);
1523 PIS(ERRCONTENTIONLP1_2);
1524 PIS(ERRCONTENTIONLP0_3);
1525 PIS(ERRCONTENTIONLP1_3);
1526 PIS(ULPSACTIVENOT_ALL0);
1527 PIS(ULPSACTIVENOT_ALL1);
1528 #undef PIS
1529
1530 return 0;
1531 }
1532 #endif
1533
1534 static int dsi_dump_dsi_regs(struct seq_file *s, void *p)
1535 {
1536 struct dsi_data *dsi = s->private;
1537
1538 if (dsi_runtime_get(dsi))
1539 return 0;
1540 dsi_enable_scp_clk(dsi);
1541
1542 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r))
1543 DUMPREG(DSI_REVISION);
1544 DUMPREG(DSI_SYSCONFIG);
1545 DUMPREG(DSI_SYSSTATUS);
1546 DUMPREG(DSI_IRQSTATUS);
1547 DUMPREG(DSI_IRQENABLE);
1548 DUMPREG(DSI_CTRL);
1549 DUMPREG(DSI_COMPLEXIO_CFG1);
1550 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1551 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1552 DUMPREG(DSI_CLK_CTRL);
1553 DUMPREG(DSI_TIMING1);
1554 DUMPREG(DSI_TIMING2);
1555 DUMPREG(DSI_VM_TIMING1);
1556 DUMPREG(DSI_VM_TIMING2);
1557 DUMPREG(DSI_VM_TIMING3);
1558 DUMPREG(DSI_CLK_TIMING);
1559 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1560 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1561 DUMPREG(DSI_COMPLEXIO_CFG2);
1562 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1563 DUMPREG(DSI_VM_TIMING4);
1564 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1565 DUMPREG(DSI_VM_TIMING5);
1566 DUMPREG(DSI_VM_TIMING6);
1567 DUMPREG(DSI_VM_TIMING7);
1568 DUMPREG(DSI_STOPCLK_TIMING);
1569
1570 DUMPREG(DSI_VC_CTRL(0));
1571 DUMPREG(DSI_VC_TE(0));
1572 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1573 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1574 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1575 DUMPREG(DSI_VC_IRQSTATUS(0));
1576 DUMPREG(DSI_VC_IRQENABLE(0));
1577
1578 DUMPREG(DSI_VC_CTRL(1));
1579 DUMPREG(DSI_VC_TE(1));
1580 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1581 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1582 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1583 DUMPREG(DSI_VC_IRQSTATUS(1));
1584 DUMPREG(DSI_VC_IRQENABLE(1));
1585
1586 DUMPREG(DSI_VC_CTRL(2));
1587 DUMPREG(DSI_VC_TE(2));
1588 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1589 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1590 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1591 DUMPREG(DSI_VC_IRQSTATUS(2));
1592 DUMPREG(DSI_VC_IRQENABLE(2));
1593
1594 DUMPREG(DSI_VC_CTRL(3));
1595 DUMPREG(DSI_VC_TE(3));
1596 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1597 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1598 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1599 DUMPREG(DSI_VC_IRQSTATUS(3));
1600 DUMPREG(DSI_VC_IRQENABLE(3));
1601
1602 DUMPREG(DSI_DSIPHY_CFG0);
1603 DUMPREG(DSI_DSIPHY_CFG1);
1604 DUMPREG(DSI_DSIPHY_CFG2);
1605 DUMPREG(DSI_DSIPHY_CFG5);
1606
1607 DUMPREG(DSI_PLL_CONTROL);
1608 DUMPREG(DSI_PLL_STATUS);
1609 DUMPREG(DSI_PLL_GO);
1610 DUMPREG(DSI_PLL_CONFIGURATION1);
1611 DUMPREG(DSI_PLL_CONFIGURATION2);
1612 #undef DUMPREG
1613
1614 dsi_disable_scp_clk(dsi);
1615 dsi_runtime_put(dsi);
1616
1617 return 0;
1618 }
1619
1620 enum dsi_cio_power_state {
1621 DSI_COMPLEXIO_POWER_OFF = 0x0,
1622 DSI_COMPLEXIO_POWER_ON = 0x1,
1623 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1624 };
1625
1626 static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state)
1627 {
1628 int t = 0;
1629
1630 /* PWR_CMD */
1631 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27);
1632
1633 /* PWR_STATUS */
1634 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1),
1635 26, 25) != state) {
1636 if (++t > 1000) {
1637 DSSERR("failed to set complexio power state to "
1638 "%d\n", state);
1639 return -ENODEV;
1640 }
1641 udelay(1);
1642 }
1643
1644 return 0;
1645 }
1646
1647 static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi)
1648 {
1649 int val;
1650
1651 /* line buffer on OMAP3 is 1024 x 24bits */
1652 /* XXX: for some reason using full buffer size causes
1653 * considerable TX slowdown with update sizes that fill the
1654 * whole buffer */
1655 if (!(dsi->data->quirks & DSI_QUIRK_GNQ))
1656 return 1023 * 3;
1657
1658 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1659
1660 switch (val) {
1661 case 1:
1662 return 512 * 3; /* 512x24 bits */
1663 case 2:
1664 return 682 * 3; /* 682x24 bits */
1665 case 3:
1666 return 853 * 3; /* 853x24 bits */
1667 case 4:
1668 return 1024 * 3; /* 1024x24 bits */
1669 case 5:
1670 return 1194 * 3; /* 1194x24 bits */
1671 case 6:
1672 return 1365 * 3; /* 1365x24 bits */
1673 case 7:
1674 return 1920 * 3; /* 1920x24 bits */
1675 default:
1676 BUG();
1677 return 0;
1678 }
1679 }
1680
1681 static int dsi_set_lane_config(struct dsi_data *dsi)
1682 {
1683 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1684 static const enum dsi_lane_function functions[] = {
1685 DSI_LANE_CLK,
1686 DSI_LANE_DATA1,
1687 DSI_LANE_DATA2,
1688 DSI_LANE_DATA3,
1689 DSI_LANE_DATA4,
1690 };
1691 u32 r;
1692 int i;
1693
1694 r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1);
1695
1696 for (i = 0; i < dsi->num_lanes_used; ++i) {
1697 unsigned int offset = offsets[i];
1698 unsigned int polarity, lane_number;
1699 unsigned int t;
1700
1701 for (t = 0; t < dsi->num_lanes_supported; ++t)
1702 if (dsi->lanes[t].function == functions[i])
1703 break;
1704
1705 if (t == dsi->num_lanes_supported)
1706 return -EINVAL;
1707
1708 lane_number = t;
1709 polarity = dsi->lanes[t].polarity;
1710
1711 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1712 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1713 }
1714
1715 /* clear the unused lanes */
1716 for (; i < dsi->num_lanes_supported; ++i) {
1717 unsigned int offset = offsets[i];
1718
1719 r = FLD_MOD(r, 0, offset + 2, offset);
1720 r = FLD_MOD(r, 0, offset + 3, offset + 3);
1721 }
1722
1723 dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r);
1724
1725 return 0;
1726 }
1727
1728 static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns)
1729 {
1730 /* convert time in ns to ddr ticks, rounding up */
1731 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1732
1733 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1734 }
1735
1736 static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr)
1737 {
1738 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1739
1740 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1741 }
1742
1743 static void dsi_cio_timings(struct dsi_data *dsi)
1744 {
1745 u32 r;
1746 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1747 u32 tlpx_half, tclk_trail, tclk_zero;
1748 u32 tclk_prepare;
1749
1750 /* calculate timings */
1751
1752 /* 1 * DDR_CLK = 2 * UI */
1753
1754 /* min 40ns + 4*UI max 85ns + 6*UI */
1755 ths_prepare = ns2ddr(dsi, 70) + 2;
1756
1757 /* min 145ns + 10*UI */
1758 ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2;
1759
1760 /* min max(8*UI, 60ns+4*UI) */
1761 ths_trail = ns2ddr(dsi, 60) + 5;
1762
1763 /* min 100ns */
1764 ths_exit = ns2ddr(dsi, 145);
1765
1766 /* tlpx min 50n */
1767 tlpx_half = ns2ddr(dsi, 25);
1768
1769 /* min 60ns */
1770 tclk_trail = ns2ddr(dsi, 60) + 2;
1771
1772 /* min 38ns, max 95ns */
1773 tclk_prepare = ns2ddr(dsi, 65);
1774
1775 /* min tclk-prepare + tclk-zero = 300ns */
1776 tclk_zero = ns2ddr(dsi, 260);
1777
1778 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1779 ths_prepare, ddr2ns(dsi, ths_prepare),
1780 ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero));
1781 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1782 ths_trail, ddr2ns(dsi, ths_trail),
1783 ths_exit, ddr2ns(dsi, ths_exit));
1784
1785 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1786 "tclk_zero %u (%uns)\n",
1787 tlpx_half, ddr2ns(dsi, tlpx_half),
1788 tclk_trail, ddr2ns(dsi, tclk_trail),
1789 tclk_zero, ddr2ns(dsi, tclk_zero));
1790 DSSDBG("tclk_prepare %u (%uns)\n",
1791 tclk_prepare, ddr2ns(dsi, tclk_prepare));
1792
1793 /* program timings */
1794
1795 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
1796 r = FLD_MOD(r, ths_prepare, 31, 24);
1797 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1798 r = FLD_MOD(r, ths_trail, 15, 8);
1799 r = FLD_MOD(r, ths_exit, 7, 0);
1800 dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r);
1801
1802 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
1803 r = FLD_MOD(r, tlpx_half, 20, 16);
1804 r = FLD_MOD(r, tclk_trail, 15, 8);
1805 r = FLD_MOD(r, tclk_zero, 7, 0);
1806
1807 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) {
1808 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
1809 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
1810 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
1811 }
1812
1813 dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r);
1814
1815 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
1816 r = FLD_MOD(r, tclk_prepare, 7, 0);
1817 dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r);
1818 }
1819
1820 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
1821 static void dsi_cio_enable_lane_override(struct dsi_data *dsi,
1822 unsigned int mask_p,
1823 unsigned int mask_n)
1824 {
1825 int i;
1826 u32 l;
1827 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
1828
1829 l = 0;
1830
1831 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1832 unsigned int p = dsi->lanes[i].polarity;
1833
1834 if (mask_p & (1 << i))
1835 l |= 1 << (i * 2 + (p ? 0 : 1));
1836
1837 if (mask_n & (1 << i))
1838 l |= 1 << (i * 2 + (p ? 1 : 0));
1839 }
1840
1841 /*
1842 * Bits in REGLPTXSCPDAT4TO0DXDY:
1843 * 17: DY0 18: DX0
1844 * 19: DY1 20: DX1
1845 * 21: DY2 22: DX2
1846 * 23: DY3 24: DX3
1847 * 25: DY4 26: DX4
1848 */
1849
1850 /* Set the lane override configuration */
1851
1852 /* REGLPTXSCPDAT4TO0DXDY */
1853 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
1854
1855 /* Enable lane override */
1856
1857 /* ENLPTXSCPDAT */
1858 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 1, 27, 27);
1859 }
1860
1861 static void dsi_cio_disable_lane_override(struct dsi_data *dsi)
1862 {
1863 /* Disable lane override */
1864 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
1865 /* Reset the lane override configuration */
1866 /* REGLPTXSCPDAT4TO0DXDY */
1867 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 22, 17);
1868 }
1869
1870 static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi)
1871 {
1872 int t, i;
1873 bool in_use[DSI_MAX_NR_LANES];
1874 static const u8 offsets_old[] = { 28, 27, 26 };
1875 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
1876 const u8 *offsets;
1877
1878 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC)
1879 offsets = offsets_old;
1880 else
1881 offsets = offsets_new;
1882
1883 for (i = 0; i < dsi->num_lanes_supported; ++i)
1884 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
1885
1886 t = 100000;
1887 while (true) {
1888 u32 l;
1889 int ok;
1890
1891 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1892
1893 ok = 0;
1894 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1895 if (!in_use[i] || (l & (1 << offsets[i])))
1896 ok++;
1897 }
1898
1899 if (ok == dsi->num_lanes_supported)
1900 break;
1901
1902 if (--t == 0) {
1903 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1904 if (!in_use[i] || (l & (1 << offsets[i])))
1905 continue;
1906
1907 DSSERR("CIO TXCLKESC%d domain not coming " \
1908 "out of reset\n", i);
1909 }
1910 return -EIO;
1911 }
1912 }
1913
1914 return 0;
1915 }
1916
1917 /* return bitmask of enabled lanes, lane0 being the lsb */
1918 static unsigned int dsi_get_lane_mask(struct dsi_data *dsi)
1919 {
1920 unsigned int mask = 0;
1921 int i;
1922
1923 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1924 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
1925 mask |= 1 << i;
1926 }
1927
1928 return mask;
1929 }
1930
1931 /* OMAP4 CONTROL_DSIPHY */
1932 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
1933
1934 #define OMAP4_DSI2_LANEENABLE_SHIFT 29
1935 #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
1936 #define OMAP4_DSI1_LANEENABLE_SHIFT 24
1937 #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
1938 #define OMAP4_DSI1_PIPD_SHIFT 19
1939 #define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
1940 #define OMAP4_DSI2_PIPD_SHIFT 14
1941 #define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
1942
1943 static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes)
1944 {
1945 u32 enable_mask, enable_shift;
1946 u32 pipd_mask, pipd_shift;
1947
1948 if (dsi->module_id == 0) {
1949 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
1950 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
1951 pipd_mask = OMAP4_DSI1_PIPD_MASK;
1952 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
1953 } else if (dsi->module_id == 1) {
1954 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
1955 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
1956 pipd_mask = OMAP4_DSI2_PIPD_MASK;
1957 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
1958 } else {
1959 return -ENODEV;
1960 }
1961
1962 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET,
1963 enable_mask | pipd_mask,
1964 (lanes << enable_shift) | (lanes << pipd_shift));
1965 }
1966
1967 /* OMAP5 CONTROL_DSIPHY */
1968
1969 #define OMAP5_DSIPHY_SYSCON_OFFSET 0x74
1970
1971 #define OMAP5_DSI1_LANEENABLE_SHIFT 24
1972 #define OMAP5_DSI2_LANEENABLE_SHIFT 19
1973 #define OMAP5_DSI_LANEENABLE_MASK 0x1f
1974
1975 static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes)
1976 {
1977 u32 enable_shift;
1978
1979 if (dsi->module_id == 0)
1980 enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT;
1981 else if (dsi->module_id == 1)
1982 enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT;
1983 else
1984 return -ENODEV;
1985
1986 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET,
1987 OMAP5_DSI_LANEENABLE_MASK << enable_shift,
1988 lanes << enable_shift);
1989 }
1990
1991 static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask)
1992 {
1993 if (dsi->data->model == DSI_MODEL_OMAP4)
1994 return dsi_omap4_mux_pads(dsi, lane_mask);
1995 if (dsi->data->model == DSI_MODEL_OMAP5)
1996 return dsi_omap5_mux_pads(dsi, lane_mask);
1997 return 0;
1998 }
1999
2000 static void dsi_disable_pads(struct dsi_data *dsi)
2001 {
2002 if (dsi->data->model == DSI_MODEL_OMAP4)
2003 dsi_omap4_mux_pads(dsi, 0);
2004 else if (dsi->data->model == DSI_MODEL_OMAP5)
2005 dsi_omap5_mux_pads(dsi, 0);
2006 }
2007
2008 static int dsi_cio_init(struct dsi_data *dsi)
2009 {
2010 int r;
2011 u32 l;
2012
2013 DSSDBG("DSI CIO init starts");
2014
2015 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi));
2016 if (r)
2017 return r;
2018
2019 dsi_enable_scp_clk(dsi);
2020
2021 /* A dummy read using the SCP interface to any DSIPHY register is
2022 * required after DSIPHY reset to complete the reset of the DSI complex
2023 * I/O. */
2024 dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
2025
2026 if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) {
2027 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2028 r = -EIO;
2029 goto err_scp_clk_dom;
2030 }
2031
2032 r = dsi_set_lane_config(dsi);
2033 if (r)
2034 goto err_scp_clk_dom;
2035
2036 /* set TX STOP MODE timer to maximum for this operation */
2037 l = dsi_read_reg(dsi, DSI_TIMING1);
2038 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2039 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2040 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2041 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2042 dsi_write_reg(dsi, DSI_TIMING1, l);
2043
2044 if (dsi->ulps_enabled) {
2045 unsigned int mask_p;
2046 int i;
2047
2048 DSSDBG("manual ulps exit\n");
2049
2050 /* ULPS is exited by Mark-1 state for 1ms, followed by
2051 * stop state. DSS HW cannot do this via the normal
2052 * ULPS exit sequence, as after reset the DSS HW thinks
2053 * that we are not in ULPS mode, and refuses to send the
2054 * sequence. So we need to send the ULPS exit sequence
2055 * manually by setting positive lines high and negative lines
2056 * low for 1ms.
2057 */
2058
2059 mask_p = 0;
2060
2061 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2062 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2063 continue;
2064 mask_p |= 1 << i;
2065 }
2066
2067 dsi_cio_enable_lane_override(dsi, mask_p, 0);
2068 }
2069
2070 r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON);
2071 if (r)
2072 goto err_cio_pwr;
2073
2074 if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) {
2075 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2076 r = -ENODEV;
2077 goto err_cio_pwr_dom;
2078 }
2079
2080 dsi_if_enable(dsi, true);
2081 dsi_if_enable(dsi, false);
2082 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2083
2084 r = dsi_cio_wait_tx_clk_esc_reset(dsi);
2085 if (r)
2086 goto err_tx_clk_esc_rst;
2087
2088 if (dsi->ulps_enabled) {
2089 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2090 ktime_t wait = ns_to_ktime(1000 * 1000);
2091 set_current_state(TASK_UNINTERRUPTIBLE);
2092 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2093
2094 /* Disable the override. The lanes should be set to Mark-11
2095 * state by the HW */
2096 dsi_cio_disable_lane_override(dsi);
2097 }
2098
2099 /* FORCE_TX_STOP_MODE_IO */
2100 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15);
2101
2102 dsi_cio_timings(dsi);
2103
2104 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2105 /* DDR_CLK_ALWAYS_ON */
2106 REG_FLD_MOD(dsi, DSI_CLK_CTRL,
2107 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2108 }
2109
2110 dsi->ulps_enabled = false;
2111
2112 DSSDBG("CIO init done\n");
2113
2114 return 0;
2115
2116 err_tx_clk_esc_rst:
2117 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2118 err_cio_pwr_dom:
2119 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
2120 err_cio_pwr:
2121 if (dsi->ulps_enabled)
2122 dsi_cio_disable_lane_override(dsi);
2123 err_scp_clk_dom:
2124 dsi_disable_scp_clk(dsi);
2125 dsi_disable_pads(dsi);
2126 return r;
2127 }
2128
2129 static void dsi_cio_uninit(struct dsi_data *dsi)
2130 {
2131 /* DDR_CLK_ALWAYS_ON */
2132 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
2133
2134 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
2135 dsi_disable_scp_clk(dsi);
2136 dsi_disable_pads(dsi);
2137 }
2138
2139 static void dsi_config_tx_fifo(struct dsi_data *dsi,
2140 enum fifo_size size1, enum fifo_size size2,
2141 enum fifo_size size3, enum fifo_size size4)
2142 {
2143 u32 r = 0;
2144 int add = 0;
2145 int i;
2146
2147 dsi->vc[0].tx_fifo_size = size1;
2148 dsi->vc[1].tx_fifo_size = size2;
2149 dsi->vc[2].tx_fifo_size = size3;
2150 dsi->vc[3].tx_fifo_size = size4;
2151
2152 for (i = 0; i < 4; i++) {
2153 u8 v;
2154 int size = dsi->vc[i].tx_fifo_size;
2155
2156 if (add + size > 4) {
2157 DSSERR("Illegal FIFO configuration\n");
2158 BUG();
2159 return;
2160 }
2161
2162 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2163 r |= v << (8 * i);
2164 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2165 add += size;
2166 }
2167
2168 dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r);
2169 }
2170
2171 static void dsi_config_rx_fifo(struct dsi_data *dsi,
2172 enum fifo_size size1, enum fifo_size size2,
2173 enum fifo_size size3, enum fifo_size size4)
2174 {
2175 u32 r = 0;
2176 int add = 0;
2177 int i;
2178
2179 dsi->vc[0].rx_fifo_size = size1;
2180 dsi->vc[1].rx_fifo_size = size2;
2181 dsi->vc[2].rx_fifo_size = size3;
2182 dsi->vc[3].rx_fifo_size = size4;
2183
2184 for (i = 0; i < 4; i++) {
2185 u8 v;
2186 int size = dsi->vc[i].rx_fifo_size;
2187
2188 if (add + size > 4) {
2189 DSSERR("Illegal FIFO configuration\n");
2190 BUG();
2191 return;
2192 }
2193
2194 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2195 r |= v << (8 * i);
2196 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2197 add += size;
2198 }
2199
2200 dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r);
2201 }
2202
2203 static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi)
2204 {
2205 u32 r;
2206
2207 r = dsi_read_reg(dsi, DSI_TIMING1);
2208 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2209 dsi_write_reg(dsi, DSI_TIMING1, r);
2210
2211 if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) {
2212 DSSERR("TX_STOP bit not going down\n");
2213 return -EIO;
2214 }
2215
2216 return 0;
2217 }
2218
2219 static bool dsi_vc_is_enabled(struct dsi_data *dsi, int channel)
2220 {
2221 return REG_GET(dsi, DSI_VC_CTRL(channel), 0, 0);
2222 }
2223
2224 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2225 {
2226 struct dsi_packet_sent_handler_data *vp_data =
2227 (struct dsi_packet_sent_handler_data *) data;
2228 struct dsi_data *dsi = vp_data->dsi;
2229 const int channel = dsi->update_channel;
2230 u8 bit = dsi->te_enabled ? 30 : 31;
2231
2232 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit) == 0)
2233 complete(vp_data->completion);
2234 }
2235
2236 static int dsi_sync_vc_vp(struct dsi_data *dsi, int channel)
2237 {
2238 DECLARE_COMPLETION_ONSTACK(completion);
2239 struct dsi_packet_sent_handler_data vp_data = {
2240 .dsi = dsi,
2241 .completion = &completion
2242 };
2243 int r = 0;
2244 u8 bit;
2245
2246 bit = dsi->te_enabled ? 30 : 31;
2247
2248 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2249 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2250 if (r)
2251 goto err0;
2252
2253 /* Wait for completion only if TE_EN/TE_START is still set */
2254 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit)) {
2255 if (wait_for_completion_timeout(&completion,
2256 msecs_to_jiffies(10)) == 0) {
2257 DSSERR("Failed to complete previous frame transfer\n");
2258 r = -EIO;
2259 goto err1;
2260 }
2261 }
2262
2263 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2264 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2265
2266 return 0;
2267 err1:
2268 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2269 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2270 err0:
2271 return r;
2272 }
2273
2274 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2275 {
2276 struct dsi_packet_sent_handler_data *l4_data =
2277 (struct dsi_packet_sent_handler_data *) data;
2278 struct dsi_data *dsi = l4_data->dsi;
2279 const int channel = dsi->update_channel;
2280
2281 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5) == 0)
2282 complete(l4_data->completion);
2283 }
2284
2285 static int dsi_sync_vc_l4(struct dsi_data *dsi, int channel)
2286 {
2287 DECLARE_COMPLETION_ONSTACK(completion);
2288 struct dsi_packet_sent_handler_data l4_data = {
2289 .dsi = dsi,
2290 .completion = &completion
2291 };
2292 int r = 0;
2293
2294 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2295 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2296 if (r)
2297 goto err0;
2298
2299 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2300 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5)) {
2301 if (wait_for_completion_timeout(&completion,
2302 msecs_to_jiffies(10)) == 0) {
2303 DSSERR("Failed to complete previous l4 transfer\n");
2304 r = -EIO;
2305 goto err1;
2306 }
2307 }
2308
2309 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2310 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2311
2312 return 0;
2313 err1:
2314 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2315 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2316 err0:
2317 return r;
2318 }
2319
2320 static int dsi_sync_vc(struct dsi_data *dsi, int channel)
2321 {
2322 WARN_ON(!dsi_bus_is_locked(dsi));
2323
2324 WARN_ON(in_interrupt());
2325
2326 if (!dsi_vc_is_enabled(dsi, channel))
2327 return 0;
2328
2329 switch (dsi->vc[channel].source) {
2330 case DSI_VC_SOURCE_VP:
2331 return dsi_sync_vc_vp(dsi, channel);
2332 case DSI_VC_SOURCE_L4:
2333 return dsi_sync_vc_l4(dsi, channel);
2334 default:
2335 BUG();
2336 return -EINVAL;
2337 }
2338 }
2339
2340 static int dsi_vc_enable(struct dsi_data *dsi, int channel, bool enable)
2341 {
2342 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2343 channel, enable);
2344
2345 enable = enable ? 1 : 0;
2346
2347 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 0, 0);
2348
2349 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 0, enable)) {
2350 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2351 return -EIO;
2352 }
2353
2354 return 0;
2355 }
2356
2357 static void dsi_vc_initial_config(struct dsi_data *dsi, int channel)
2358 {
2359 u32 r;
2360
2361 DSSDBG("Initial config of virtual channel %d", channel);
2362
2363 r = dsi_read_reg(dsi, DSI_VC_CTRL(channel));
2364
2365 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2366 DSSERR("VC(%d) busy when trying to configure it!\n",
2367 channel);
2368
2369 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2370 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2371 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2372 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2373 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2374 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2375 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2376 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH)
2377 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2378
2379 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2380 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2381
2382 dsi_write_reg(dsi, DSI_VC_CTRL(channel), r);
2383
2384 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2385 }
2386
2387 static int dsi_vc_config_source(struct dsi_data *dsi, int channel,
2388 enum dsi_vc_source source)
2389 {
2390 if (dsi->vc[channel].source == source)
2391 return 0;
2392
2393 DSSDBG("Source config of virtual channel %d", channel);
2394
2395 dsi_sync_vc(dsi, channel);
2396
2397 dsi_vc_enable(dsi, channel, 0);
2398
2399 /* VC_BUSY */
2400 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 15, 0)) {
2401 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2402 return -EIO;
2403 }
2404
2405 /* SOURCE, 0 = L4, 1 = video port */
2406 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), source, 1, 1);
2407
2408 /* DCS_CMD_ENABLE */
2409 if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) {
2410 bool enable = source == DSI_VC_SOURCE_VP;
2411 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 30, 30);
2412 }
2413
2414 dsi_vc_enable(dsi, channel, 1);
2415
2416 dsi->vc[channel].source = source;
2417
2418 return 0;
2419 }
2420
2421 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2422 bool enable)
2423 {
2424 struct dsi_data *dsi = to_dsi_data(dssdev);
2425
2426 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2427
2428 WARN_ON(!dsi_bus_is_locked(dsi));
2429
2430 dsi_vc_enable(dsi, channel, 0);
2431 dsi_if_enable(dsi, 0);
2432
2433 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 9, 9);
2434
2435 dsi_vc_enable(dsi, channel, 1);
2436 dsi_if_enable(dsi, 1);
2437
2438 dsi_force_tx_stop_mode_io(dsi);
2439
2440 /* start the DDR clock by sending a NULL packet */
2441 if (dsi->vm_timings.ddr_clk_always_on && enable)
2442 dsi_vc_send_null(dsi, channel);
2443 }
2444
2445 static void dsi_vc_flush_long_data(struct dsi_data *dsi, int channel)
2446 {
2447 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2448 u32 val;
2449 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2450 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2451 (val >> 0) & 0xff,
2452 (val >> 8) & 0xff,
2453 (val >> 16) & 0xff,
2454 (val >> 24) & 0xff);
2455 }
2456 }
2457
2458 static void dsi_show_rx_ack_with_err(u16 err)
2459 {
2460 DSSERR("\tACK with ERROR (%#x):\n", err);
2461 if (err & (1 << 0))
2462 DSSERR("\t\tSoT Error\n");
2463 if (err & (1 << 1))
2464 DSSERR("\t\tSoT Sync Error\n");
2465 if (err & (1 << 2))
2466 DSSERR("\t\tEoT Sync Error\n");
2467 if (err & (1 << 3))
2468 DSSERR("\t\tEscape Mode Entry Command Error\n");
2469 if (err & (1 << 4))
2470 DSSERR("\t\tLP Transmit Sync Error\n");
2471 if (err & (1 << 5))
2472 DSSERR("\t\tHS Receive Timeout Error\n");
2473 if (err & (1 << 6))
2474 DSSERR("\t\tFalse Control Error\n");
2475 if (err & (1 << 7))
2476 DSSERR("\t\t(reserved7)\n");
2477 if (err & (1 << 8))
2478 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2479 if (err & (1 << 9))
2480 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2481 if (err & (1 << 10))
2482 DSSERR("\t\tChecksum Error\n");
2483 if (err & (1 << 11))
2484 DSSERR("\t\tData type not recognized\n");
2485 if (err & (1 << 12))
2486 DSSERR("\t\tInvalid VC ID\n");
2487 if (err & (1 << 13))
2488 DSSERR("\t\tInvalid Transmission Length\n");
2489 if (err & (1 << 14))
2490 DSSERR("\t\t(reserved14)\n");
2491 if (err & (1 << 15))
2492 DSSERR("\t\tDSI Protocol Violation\n");
2493 }
2494
2495 static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int channel)
2496 {
2497 /* RX_FIFO_NOT_EMPTY */
2498 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2499 u32 val;
2500 u8 dt;
2501 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2502 DSSERR("\trawval %#08x\n", val);
2503 dt = FLD_GET(val, 5, 0);
2504 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2505 u16 err = FLD_GET(val, 23, 8);
2506 dsi_show_rx_ack_with_err(err);
2507 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2508 DSSERR("\tDCS short response, 1 byte: %#x\n",
2509 FLD_GET(val, 23, 8));
2510 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2511 DSSERR("\tDCS short response, 2 byte: %#x\n",
2512 FLD_GET(val, 23, 8));
2513 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2514 DSSERR("\tDCS long response, len %d\n",
2515 FLD_GET(val, 23, 8));
2516 dsi_vc_flush_long_data(dsi, channel);
2517 } else {
2518 DSSERR("\tunknown datatype 0x%02x\n", dt);
2519 }
2520 }
2521 return 0;
2522 }
2523
2524 static int dsi_vc_send_bta(struct dsi_data *dsi, int channel)
2525 {
2526 if (dsi->debug_write || dsi->debug_read)
2527 DSSDBG("dsi_vc_send_bta %d\n", channel);
2528
2529 WARN_ON(!dsi_bus_is_locked(dsi));
2530
2531 /* RX_FIFO_NOT_EMPTY */
2532 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2533 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2534 dsi_vc_flush_receive_data(dsi, channel);
2535 }
2536
2537 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2538
2539 /* flush posted write */
2540 dsi_read_reg(dsi, DSI_VC_CTRL(channel));
2541
2542 return 0;
2543 }
2544
2545 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2546 {
2547 struct dsi_data *dsi = to_dsi_data(dssdev);
2548 DECLARE_COMPLETION_ONSTACK(completion);
2549 int r = 0;
2550 u32 err;
2551
2552 r = dsi_register_isr_vc(dsi, channel, dsi_completion_handler,
2553 &completion, DSI_VC_IRQ_BTA);
2554 if (r)
2555 goto err0;
2556
2557 r = dsi_register_isr(dsi, dsi_completion_handler, &completion,
2558 DSI_IRQ_ERROR_MASK);
2559 if (r)
2560 goto err1;
2561
2562 r = dsi_vc_send_bta(dsi, channel);
2563 if (r)
2564 goto err2;
2565
2566 if (wait_for_completion_timeout(&completion,
2567 msecs_to_jiffies(500)) == 0) {
2568 DSSERR("Failed to receive BTA\n");
2569 r = -EIO;
2570 goto err2;
2571 }
2572
2573 err = dsi_get_errors(dsi);
2574 if (err) {
2575 DSSERR("Error while sending BTA: %x\n", err);
2576 r = -EIO;
2577 goto err2;
2578 }
2579 err2:
2580 dsi_unregister_isr(dsi, dsi_completion_handler, &completion,
2581 DSI_IRQ_ERROR_MASK);
2582 err1:
2583 dsi_unregister_isr_vc(dsi, channel, dsi_completion_handler,
2584 &completion, DSI_VC_IRQ_BTA);
2585 err0:
2586 return r;
2587 }
2588
2589 static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int channel,
2590 u8 data_type, u16 len, u8 ecc)
2591 {
2592 u32 val;
2593 u8 data_id;
2594
2595 WARN_ON(!dsi_bus_is_locked(dsi));
2596
2597 data_id = data_type | dsi->vc[channel].vc_id << 6;
2598
2599 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2600 FLD_VAL(ecc, 31, 24);
2601
2602 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(channel), val);
2603 }
2604
2605 static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int channel,
2606 u8 b1, u8 b2, u8 b3, u8 b4)
2607 {
2608 u32 val;
2609
2610 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2611
2612 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2613 b1, b2, b3, b4, val); */
2614
2615 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2616 }
2617
2618 static int dsi_vc_send_long(struct dsi_data *dsi, int channel, u8 data_type,
2619 u8 *data, u16 len, u8 ecc)
2620 {
2621 /*u32 val; */
2622 int i;
2623 u8 *p;
2624 int r = 0;
2625 u8 b1, b2, b3, b4;
2626
2627 if (dsi->debug_write)
2628 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2629
2630 /* len + header */
2631 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2632 DSSERR("unable to send long packet: packet too long.\n");
2633 return -EINVAL;
2634 }
2635
2636 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4);
2637
2638 dsi_vc_write_long_header(dsi, channel, data_type, len, ecc);
2639
2640 p = data;
2641 for (i = 0; i < len >> 2; i++) {
2642 if (dsi->debug_write)
2643 DSSDBG("\tsending full packet %d\n", i);
2644
2645 b1 = *p++;
2646 b2 = *p++;
2647 b3 = *p++;
2648 b4 = *p++;
2649
2650 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, b4);
2651 }
2652
2653 i = len % 4;
2654 if (i) {
2655 b1 = 0; b2 = 0; b3 = 0;
2656
2657 if (dsi->debug_write)
2658 DSSDBG("\tsending remainder bytes %d\n", i);
2659
2660 switch (i) {
2661 case 3:
2662 b1 = *p++;
2663 b2 = *p++;
2664 b3 = *p++;
2665 break;
2666 case 2:
2667 b1 = *p++;
2668 b2 = *p++;
2669 break;
2670 case 1:
2671 b1 = *p++;
2672 break;
2673 }
2674
2675 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, 0);
2676 }
2677
2678 return r;
2679 }
2680
2681 static int dsi_vc_send_short(struct dsi_data *dsi, int channel, u8 data_type,
2682 u16 data, u8 ecc)
2683 {
2684 u32 r;
2685 u8 data_id;
2686
2687 WARN_ON(!dsi_bus_is_locked(dsi));
2688
2689 if (dsi->debug_write)
2690 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2691 channel,
2692 data_type, data & 0xff, (data >> 8) & 0xff);
2693
2694 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4);
2695
2696 if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(channel)), 16, 16)) {
2697 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2698 return -EINVAL;
2699 }
2700
2701 data_id = data_type | dsi->vc[channel].vc_id << 6;
2702
2703 r = (data_id << 0) | (data << 8) | (ecc << 24);
2704
2705 dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2706
2707 return 0;
2708 }
2709
2710 static int dsi_vc_send_null(struct dsi_data *dsi, int channel)
2711 {
2712 return dsi_vc_send_long(dsi, channel, MIPI_DSI_NULL_PACKET, NULL, 0, 0);
2713 }
2714
2715 static int dsi_vc_write_nosync_common(struct dsi_data *dsi, int channel,
2716 u8 *data, int len,
2717 enum dss_dsi_content_type type)
2718 {
2719 int r;
2720
2721 if (len == 0) {
2722 BUG_ON(type == DSS_DSI_CONTENT_DCS);
2723 r = dsi_vc_send_short(dsi, channel,
2724 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2725 } else if (len == 1) {
2726 r = dsi_vc_send_short(dsi, channel,
2727 type == DSS_DSI_CONTENT_GENERIC ?
2728 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2729 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2730 } else if (len == 2) {
2731 r = dsi_vc_send_short(dsi, channel,
2732 type == DSS_DSI_CONTENT_GENERIC ?
2733 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2734 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2735 data[0] | (data[1] << 8), 0);
2736 } else {
2737 r = dsi_vc_send_long(dsi, channel,
2738 type == DSS_DSI_CONTENT_GENERIC ?
2739 MIPI_DSI_GENERIC_LONG_WRITE :
2740 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2741 }
2742
2743 return r;
2744 }
2745
2746 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2747 u8 *data, int len)
2748 {
2749 struct dsi_data *dsi = to_dsi_data(dssdev);
2750
2751 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2752 DSS_DSI_CONTENT_DCS);
2753 }
2754
2755 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2756 u8 *data, int len)
2757 {
2758 struct dsi_data *dsi = to_dsi_data(dssdev);
2759
2760 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2761 DSS_DSI_CONTENT_GENERIC);
2762 }
2763
2764 static int dsi_vc_write_common(struct omap_dss_device *dssdev,
2765 int channel, u8 *data, int len,
2766 enum dss_dsi_content_type type)
2767 {
2768 struct dsi_data *dsi = to_dsi_data(dssdev);
2769 int r;
2770
2771 r = dsi_vc_write_nosync_common(dsi, channel, data, len, type);
2772 if (r)
2773 goto err;
2774
2775 r = dsi_vc_send_bta_sync(dssdev, channel);
2776 if (r)
2777 goto err;
2778
2779 /* RX_FIFO_NOT_EMPTY */
2780 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2781 DSSERR("rx fifo not empty after write, dumping data:\n");
2782 dsi_vc_flush_receive_data(dsi, channel);
2783 r = -EIO;
2784 goto err;
2785 }
2786
2787 return 0;
2788 err:
2789 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
2790 channel, data[0], len);
2791 return r;
2792 }
2793
2794 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2795 int len)
2796 {
2797 return dsi_vc_write_common(dssdev, channel, data, len,
2798 DSS_DSI_CONTENT_DCS);
2799 }
2800
2801 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2802 int len)
2803 {
2804 return dsi_vc_write_common(dssdev, channel, data, len,
2805 DSS_DSI_CONTENT_GENERIC);
2806 }
2807
2808 static int dsi_vc_dcs_send_read_request(struct dsi_data *dsi, int channel,
2809 u8 dcs_cmd)
2810 {
2811 int r;
2812
2813 if (dsi->debug_read)
2814 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2815 channel, dcs_cmd);
2816
2817 r = dsi_vc_send_short(dsi, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
2818 if (r) {
2819 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
2820 " failed\n", channel, dcs_cmd);
2821 return r;
2822 }
2823
2824 return 0;
2825 }
2826
2827 static int dsi_vc_generic_send_read_request(struct dsi_data *dsi, int channel,
2828 u8 *reqdata, int reqlen)
2829 {
2830 u16 data;
2831 u8 data_type;
2832 int r;
2833
2834 if (dsi->debug_read)
2835 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
2836 channel, reqlen);
2837
2838 if (reqlen == 0) {
2839 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
2840 data = 0;
2841 } else if (reqlen == 1) {
2842 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
2843 data = reqdata[0];
2844 } else if (reqlen == 2) {
2845 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
2846 data = reqdata[0] | (reqdata[1] << 8);
2847 } else {
2848 BUG();
2849 return -EINVAL;
2850 }
2851
2852 r = dsi_vc_send_short(dsi, channel, data_type, data, 0);
2853 if (r) {
2854 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
2855 " failed\n", channel, reqlen);
2856 return r;
2857 }
2858
2859 return 0;
2860 }
2861
2862 static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf,
2863 int buflen, enum dss_dsi_content_type type)
2864 {
2865 u32 val;
2866 u8 dt;
2867 int r;
2868
2869 /* RX_FIFO_NOT_EMPTY */
2870 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20) == 0) {
2871 DSSERR("RX fifo empty when trying to read.\n");
2872 r = -EIO;
2873 goto err;
2874 }
2875
2876 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2877 if (dsi->debug_read)
2878 DSSDBG("\theader: %08x\n", val);
2879 dt = FLD_GET(val, 5, 0);
2880 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2881 u16 err = FLD_GET(val, 23, 8);
2882 dsi_show_rx_ack_with_err(err);
2883 r = -EIO;
2884 goto err;
2885
2886 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2887 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
2888 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
2889 u8 data = FLD_GET(val, 15, 8);
2890 if (dsi->debug_read)
2891 DSSDBG("\t%s short response, 1 byte: %02x\n",
2892 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2893 "DCS", data);
2894
2895 if (buflen < 1) {
2896 r = -EIO;
2897 goto err;
2898 }
2899
2900 buf[0] = data;
2901
2902 return 1;
2903 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2904 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
2905 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
2906 u16 data = FLD_GET(val, 23, 8);
2907 if (dsi->debug_read)
2908 DSSDBG("\t%s short response, 2 byte: %04x\n",
2909 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2910 "DCS", data);
2911
2912 if (buflen < 2) {
2913 r = -EIO;
2914 goto err;
2915 }
2916
2917 buf[0] = data & 0xff;
2918 buf[1] = (data >> 8) & 0xff;
2919
2920 return 2;
2921 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2922 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
2923 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
2924 int w;
2925 int len = FLD_GET(val, 23, 8);
2926 if (dsi->debug_read)
2927 DSSDBG("\t%s long response, len %d\n",
2928 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2929 "DCS", len);
2930
2931 if (len > buflen) {
2932 r = -EIO;
2933 goto err;
2934 }
2935
2936 /* two byte checksum ends the packet, not included in len */
2937 for (w = 0; w < len + 2;) {
2938 int b;
2939 val = dsi_read_reg(dsi,
2940 DSI_VC_SHORT_PACKET_HEADER(channel));
2941 if (dsi->debug_read)
2942 DSSDBG("\t\t%02x %02x %02x %02x\n",
2943 (val >> 0) & 0xff,
2944 (val >> 8) & 0xff,
2945 (val >> 16) & 0xff,
2946 (val >> 24) & 0xff);
2947
2948 for (b = 0; b < 4; ++b) {
2949 if (w < len)
2950 buf[w] = (val >> (b * 8)) & 0xff;
2951 /* we discard the 2 byte checksum */
2952 ++w;
2953 }
2954 }
2955
2956 return len;
2957 } else {
2958 DSSERR("\tunknown datatype 0x%02x\n", dt);
2959 r = -EIO;
2960 goto err;
2961 }
2962
2963 err:
2964 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
2965 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
2966
2967 return r;
2968 }
2969
2970 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
2971 u8 *buf, int buflen)
2972 {
2973 struct dsi_data *dsi = to_dsi_data(dssdev);
2974 int r;
2975
2976 r = dsi_vc_dcs_send_read_request(dsi, channel, dcs_cmd);
2977 if (r)
2978 goto err;
2979
2980 r = dsi_vc_send_bta_sync(dssdev, channel);
2981 if (r)
2982 goto err;
2983
2984 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen,
2985 DSS_DSI_CONTENT_DCS);
2986 if (r < 0)
2987 goto err;
2988
2989 if (r != buflen) {
2990 r = -EIO;
2991 goto err;
2992 }
2993
2994 return 0;
2995 err:
2996 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
2997 return r;
2998 }
2999
3000 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3001 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3002 {
3003 struct dsi_data *dsi = to_dsi_data(dssdev);
3004 int r;
3005
3006 r = dsi_vc_generic_send_read_request(dsi, channel, reqdata, reqlen);
3007 if (r)
3008 return r;
3009
3010 r = dsi_vc_send_bta_sync(dssdev, channel);
3011 if (r)
3012 return r;
3013
3014 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen,
3015 DSS_DSI_CONTENT_GENERIC);
3016 if (r < 0)
3017 return r;
3018
3019 if (r != buflen) {
3020 r = -EIO;
3021 return r;
3022 }
3023
3024 return 0;
3025 }
3026
3027 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3028 u16 len)
3029 {
3030 struct dsi_data *dsi = to_dsi_data(dssdev);
3031
3032 return dsi_vc_send_short(dsi, channel,
3033 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3034 }
3035
3036 static int dsi_enter_ulps(struct dsi_data *dsi)
3037 {
3038 DECLARE_COMPLETION_ONSTACK(completion);
3039 int r, i;
3040 unsigned int mask;
3041
3042 DSSDBG("Entering ULPS");
3043
3044 WARN_ON(!dsi_bus_is_locked(dsi));
3045
3046 WARN_ON(dsi->ulps_enabled);
3047
3048 if (dsi->ulps_enabled)
3049 return 0;
3050
3051 /* DDR_CLK_ALWAYS_ON */
3052 if (REG_GET(dsi, DSI_CLK_CTRL, 13, 13)) {
3053 dsi_if_enable(dsi, 0);
3054 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
3055 dsi_if_enable(dsi, 1);
3056 }
3057
3058 dsi_sync_vc(dsi, 0);
3059 dsi_sync_vc(dsi, 1);
3060 dsi_sync_vc(dsi, 2);
3061 dsi_sync_vc(dsi, 3);
3062
3063 dsi_force_tx_stop_mode_io(dsi);
3064
3065 dsi_vc_enable(dsi, 0, false);
3066 dsi_vc_enable(dsi, 1, false);
3067 dsi_vc_enable(dsi, 2, false);
3068 dsi_vc_enable(dsi, 3, false);
3069
3070 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3071 DSSERR("HS busy when enabling ULPS\n");
3072 return -EIO;
3073 }
3074
3075 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3076 DSSERR("LP busy when enabling ULPS\n");
3077 return -EIO;
3078 }
3079
3080 r = dsi_register_isr_cio(dsi, dsi_completion_handler, &completion,
3081 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3082 if (r)
3083 return r;
3084
3085 mask = 0;
3086
3087 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3088 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3089 continue;
3090 mask |= 1 << i;
3091 }
3092 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3093 /* LANEx_ULPS_SIG2 */
3094 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3095
3096 /* flush posted write and wait for SCP interface to finish the write */
3097 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2);
3098
3099 if (wait_for_completion_timeout(&completion,
3100 msecs_to_jiffies(1000)) == 0) {
3101 DSSERR("ULPS enable timeout\n");
3102 r = -EIO;
3103 goto err;
3104 }
3105
3106 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion,
3107 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3108
3109 /* Reset LANEx_ULPS_SIG2 */
3110 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3111
3112 /* flush posted write and wait for SCP interface to finish the write */
3113 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2);
3114
3115 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ULPS);
3116
3117 dsi_if_enable(dsi, false);
3118
3119 dsi->ulps_enabled = true;
3120
3121 return 0;
3122
3123 err:
3124 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion,
3125 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3126 return r;
3127 }
3128
3129 static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks,
3130 bool x4, bool x16)
3131 {
3132 unsigned long fck;
3133 unsigned long total_ticks;
3134 u32 r;
3135
3136 BUG_ON(ticks > 0x1fff);
3137
3138 /* ticks in DSI_FCK */
3139 fck = dsi_fclk_rate(dsi);
3140
3141 r = dsi_read_reg(dsi, DSI_TIMING2);
3142 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3143 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3144 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3145 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3146 dsi_write_reg(dsi, DSI_TIMING2, r);
3147
3148 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3149
3150 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3151 total_ticks,
3152 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3153 (total_ticks * 1000) / (fck / 1000 / 1000));
3154 }
3155
3156 static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks,
3157 bool x8, bool x16)
3158 {
3159 unsigned long fck;
3160 unsigned long total_ticks;
3161 u32 r;
3162
3163 BUG_ON(ticks > 0x1fff);
3164
3165 /* ticks in DSI_FCK */
3166 fck = dsi_fclk_rate(dsi);
3167
3168 r = dsi_read_reg(dsi, DSI_TIMING1);
3169 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3170 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3171 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3172 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3173 dsi_write_reg(dsi, DSI_TIMING1, r);
3174
3175 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3176
3177 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3178 total_ticks,
3179 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3180 (total_ticks * 1000) / (fck / 1000 / 1000));
3181 }
3182
3183 static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks,
3184 bool x4, bool x16)
3185 {
3186 unsigned long fck;
3187 unsigned long total_ticks;
3188 u32 r;
3189
3190 BUG_ON(ticks > 0x1fff);
3191
3192 /* ticks in DSI_FCK */
3193 fck = dsi_fclk_rate(dsi);
3194
3195 r = dsi_read_reg(dsi, DSI_TIMING1);
3196 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3197 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3198 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3199 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3200 dsi_write_reg(dsi, DSI_TIMING1, r);
3201
3202 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3203
3204 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3205 total_ticks,
3206 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3207 (total_ticks * 1000) / (fck / 1000 / 1000));
3208 }
3209
3210 static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks,
3211 bool x4, bool x16)
3212 {
3213 unsigned long fck;
3214 unsigned long total_ticks;
3215 u32 r;
3216
3217 BUG_ON(ticks > 0x1fff);
3218
3219 /* ticks in TxByteClkHS */
3220 fck = dsi_get_txbyteclkhs(dsi);
3221
3222 r = dsi_read_reg(dsi, DSI_TIMING2);
3223 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3224 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3225 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3226 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3227 dsi_write_reg(dsi, DSI_TIMING2, r);
3228
3229 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3230
3231 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3232 total_ticks,
3233 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3234 (total_ticks * 1000) / (fck / 1000 / 1000));
3235 }
3236
3237 static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi)
3238 {
3239 int num_line_buffers;
3240
3241 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3242 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3243 const struct videomode *vm = &dsi->vm;
3244 /*
3245 * Don't use line buffers if width is greater than the video
3246 * port's line buffer size
3247 */
3248 if (dsi->line_buffer_size <= vm->hactive * bpp / 8)
3249 num_line_buffers = 0;
3250 else
3251 num_line_buffers = 2;
3252 } else {
3253 /* Use maximum number of line buffers in command mode */
3254 num_line_buffers = 2;
3255 }
3256
3257 /* LINE_BUFFER */
3258 REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12);
3259 }
3260
3261 static void dsi_config_vp_sync_events(struct dsi_data *dsi)
3262 {
3263 bool sync_end;
3264 u32 r;
3265
3266 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3267 sync_end = true;
3268 else
3269 sync_end = false;
3270
3271 r = dsi_read_reg(dsi, DSI_CTRL);
3272 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3273 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3274 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3275 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3276 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3277 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3278 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3279 dsi_write_reg(dsi, DSI_CTRL, r);
3280 }
3281
3282 static void dsi_config_blanking_modes(struct dsi_data *dsi)
3283 {
3284 int blanking_mode = dsi->vm_timings.blanking_mode;
3285 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3286 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3287 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3288 u32 r;
3289
3290 /*
3291 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3292 * 1 = Long blanking packets are sent in corresponding blanking periods
3293 */
3294 r = dsi_read_reg(dsi, DSI_CTRL);
3295 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3296 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3297 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3298 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3299 dsi_write_reg(dsi, DSI_CTRL, r);
3300 }
3301
3302 /*
3303 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3304 * results in maximum transition time for data and clock lanes to enter and
3305 * exit HS mode. Hence, this is the scenario where the least amount of command
3306 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3307 * clock cycles that can be used to interleave command mode data in HS so that
3308 * all scenarios are satisfied.
3309 */
3310 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3311 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3312 {
3313 int transition;
3314
3315 /*
3316 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3317 * time of data lanes only, if it isn't set, we need to consider HS
3318 * transition time of both data and clock lanes. HS transition time
3319 * of Scenario 3 is considered.
3320 */
3321 if (ddr_alwon) {
3322 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3323 } else {
3324 int trans1, trans2;
3325 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3326 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3327 enter_hs + 1;
3328 transition = max(trans1, trans2);
3329 }
3330
3331 return blank > transition ? blank - transition : 0;
3332 }
3333
3334 /*
3335 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3336 * results in maximum transition time for data lanes to enter and exit LP mode.
3337 * Hence, this is the scenario where the least amount of command mode data can
3338 * be interleaved. We program the minimum amount of bytes that can be
3339 * interleaved in LP so that all scenarios are satisfied.
3340 */
3341 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3342 int lp_clk_div, int tdsi_fclk)
3343 {
3344 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3345 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3346 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3347 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3348 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3349
3350 /* maximum LP transition time according to Scenario 1 */
3351 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3352
3353 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3354 tlp_avail = thsbyte_clk * (blank - trans_lp);
3355
3356 ttxclkesc = tdsi_fclk * lp_clk_div;
3357
3358 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3359 26) / 16;
3360
3361 return max(lp_inter, 0);
3362 }
3363
3364 static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi)
3365 {
3366 int blanking_mode;
3367 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3368 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3369 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3370 int tclk_trail, ths_exit, exiths_clk;
3371 bool ddr_alwon;
3372 const struct videomode *vm = &dsi->vm;
3373 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3374 int ndl = dsi->num_lanes_used - 1;
3375 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
3376 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3377 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3378 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3379 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3380 u32 r;
3381
3382 r = dsi_read_reg(dsi, DSI_CTRL);
3383 blanking_mode = FLD_GET(r, 20, 20);
3384 hfp_blanking_mode = FLD_GET(r, 21, 21);
3385 hbp_blanking_mode = FLD_GET(r, 22, 22);
3386 hsa_blanking_mode = FLD_GET(r, 23, 23);
3387
3388 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
3389 hbp = FLD_GET(r, 11, 0);
3390 hfp = FLD_GET(r, 23, 12);
3391 hsa = FLD_GET(r, 31, 24);
3392
3393 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
3394 ddr_clk_post = FLD_GET(r, 7, 0);
3395 ddr_clk_pre = FLD_GET(r, 15, 8);
3396
3397 r = dsi_read_reg(dsi, DSI_VM_TIMING7);
3398 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3399 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3400
3401 r = dsi_read_reg(dsi, DSI_CLK_CTRL);
3402 lp_clk_div = FLD_GET(r, 12, 0);
3403 ddr_alwon = FLD_GET(r, 13, 13);
3404
3405 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
3406 ths_exit = FLD_GET(r, 7, 0);
3407
3408 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
3409 tclk_trail = FLD_GET(r, 15, 8);
3410
3411 exiths_clk = ths_exit + tclk_trail;
3412
3413 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3414 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3415
3416 if (!hsa_blanking_mode) {
3417 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3418 enter_hs_mode_lat, exit_hs_mode_lat,
3419 exiths_clk, ddr_clk_pre, ddr_clk_post);
3420 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3421 enter_hs_mode_lat, exit_hs_mode_lat,
3422 lp_clk_div, dsi_fclk_hsdiv);
3423 }
3424
3425 if (!hfp_blanking_mode) {
3426 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3427 enter_hs_mode_lat, exit_hs_mode_lat,
3428 exiths_clk, ddr_clk_pre, ddr_clk_post);
3429 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3430 enter_hs_mode_lat, exit_hs_mode_lat,
3431 lp_clk_div, dsi_fclk_hsdiv);
3432 }
3433
3434 if (!hbp_blanking_mode) {
3435 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3436 enter_hs_mode_lat, exit_hs_mode_lat,
3437 exiths_clk, ddr_clk_pre, ddr_clk_post);
3438
3439 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3440 enter_hs_mode_lat, exit_hs_mode_lat,
3441 lp_clk_div, dsi_fclk_hsdiv);
3442 }
3443
3444 if (!blanking_mode) {
3445 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3446 enter_hs_mode_lat, exit_hs_mode_lat,
3447 exiths_clk, ddr_clk_pre, ddr_clk_post);
3448
3449 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3450 enter_hs_mode_lat, exit_hs_mode_lat,
3451 lp_clk_div, dsi_fclk_hsdiv);
3452 }
3453
3454 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3455 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3456 bl_interleave_hs);
3457
3458 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3459 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3460 bl_interleave_lp);
3461
3462 r = dsi_read_reg(dsi, DSI_VM_TIMING4);
3463 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3464 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3465 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3466 dsi_write_reg(dsi, DSI_VM_TIMING4, r);
3467
3468 r = dsi_read_reg(dsi, DSI_VM_TIMING5);
3469 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3470 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3471 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3472 dsi_write_reg(dsi, DSI_VM_TIMING5, r);
3473
3474 r = dsi_read_reg(dsi, DSI_VM_TIMING6);
3475 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3476 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3477 dsi_write_reg(dsi, DSI_VM_TIMING6, r);
3478 }
3479
3480 static int dsi_proto_config(struct dsi_data *dsi)
3481 {
3482 u32 r;
3483 int buswidth = 0;
3484
3485 dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32,
3486 DSI_FIFO_SIZE_32,
3487 DSI_FIFO_SIZE_32,
3488 DSI_FIFO_SIZE_32);
3489
3490 dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32,
3491 DSI_FIFO_SIZE_32,
3492 DSI_FIFO_SIZE_32,
3493 DSI_FIFO_SIZE_32);
3494
3495 /* XXX what values for the timeouts? */
3496 dsi_set_stop_state_counter(dsi, 0x1000, false, false);
3497 dsi_set_ta_timeout(dsi, 0x1fff, true, true);
3498 dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true);
3499 dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true);
3500
3501 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3502 case 16:
3503 buswidth = 0;
3504 break;
3505 case 18:
3506 buswidth = 1;
3507 break;
3508 case 24:
3509 buswidth = 2;
3510 break;
3511 default:
3512 BUG();
3513 return -EINVAL;
3514 }
3515
3516 r = dsi_read_reg(dsi, DSI_CTRL);
3517 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3518 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3519 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3520 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3521 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3522 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3523 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3524 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3525 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) {
3526 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3527 /* DCS_CMD_CODE, 1=start, 0=continue */
3528 r = FLD_MOD(r, 0, 25, 25);
3529 }
3530
3531 dsi_write_reg(dsi, DSI_CTRL, r);
3532
3533 dsi_config_vp_num_line_buffers(dsi);
3534
3535 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3536 dsi_config_vp_sync_events(dsi);
3537 dsi_config_blanking_modes(dsi);
3538 dsi_config_cmd_mode_interleaving(dsi);
3539 }
3540
3541 dsi_vc_initial_config(dsi, 0);
3542 dsi_vc_initial_config(dsi, 1);
3543 dsi_vc_initial_config(dsi, 2);
3544 dsi_vc_initial_config(dsi, 3);
3545
3546 return 0;
3547 }
3548
3549 static void dsi_proto_timings(struct dsi_data *dsi)
3550 {
3551 unsigned int tlpx, tclk_zero, tclk_prepare;
3552 unsigned int tclk_pre, tclk_post;
3553 unsigned int ths_prepare, ths_prepare_ths_zero, ths_zero;
3554 unsigned int ths_trail, ths_exit;
3555 unsigned int ddr_clk_pre, ddr_clk_post;
3556 unsigned int enter_hs_mode_lat, exit_hs_mode_lat;
3557 unsigned int ths_eot;
3558 int ndl = dsi->num_lanes_used - 1;
3559 u32 r;
3560
3561 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
3562 ths_prepare = FLD_GET(r, 31, 24);
3563 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3564 ths_zero = ths_prepare_ths_zero - ths_prepare;
3565 ths_trail = FLD_GET(r, 15, 8);
3566 ths_exit = FLD_GET(r, 7, 0);
3567
3568 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
3569 tlpx = FLD_GET(r, 20, 16) * 2;
3570 tclk_zero = FLD_GET(r, 7, 0);
3571
3572 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
3573 tclk_prepare = FLD_GET(r, 7, 0);
3574
3575 /* min 8*UI */
3576 tclk_pre = 20;
3577 /* min 60ns + 52*UI */
3578 tclk_post = ns2ddr(dsi, 60) + 26;
3579
3580 ths_eot = DIV_ROUND_UP(4, ndl);
3581
3582 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3583 4);
3584 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3585
3586 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3587 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3588
3589 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
3590 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3591 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3592 dsi_write_reg(dsi, DSI_CLK_TIMING, r);
3593
3594 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3595 ddr_clk_pre,
3596 ddr_clk_post);
3597
3598 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3599 DIV_ROUND_UP(ths_prepare, 4) +
3600 DIV_ROUND_UP(ths_zero + 3, 4);
3601
3602 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3603
3604 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3605 FLD_VAL(exit_hs_mode_lat, 15, 0);
3606 dsi_write_reg(dsi, DSI_VM_TIMING7, r);
3607
3608 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3609 enter_hs_mode_lat, exit_hs_mode_lat);
3610
3611 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3612 /* TODO: Implement a video mode check_timings function */
3613 int hsa = dsi->vm_timings.hsa;
3614 int hfp = dsi->vm_timings.hfp;
3615 int hbp = dsi->vm_timings.hbp;
3616 int vsa = dsi->vm_timings.vsa;
3617 int vfp = dsi->vm_timings.vfp;
3618 int vbp = dsi->vm_timings.vbp;
3619 int window_sync = dsi->vm_timings.window_sync;
3620 bool hsync_end;
3621 const struct videomode *vm = &dsi->vm;
3622 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3623 int tl, t_he, width_bytes;
3624
3625 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3626 t_he = hsync_end ?
3627 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3628
3629 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3630
3631 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3632 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3633 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3634
3635 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3636 hfp, hsync_end ? hsa : 0, tl);
3637 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3638 vsa, vm->vactive);
3639
3640 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
3641 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3642 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3643 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3644 dsi_write_reg(dsi, DSI_VM_TIMING1, r);
3645
3646 r = dsi_read_reg(dsi, DSI_VM_TIMING2);
3647 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3648 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3649 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3650 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3651 dsi_write_reg(dsi, DSI_VM_TIMING2, r);
3652
3653 r = dsi_read_reg(dsi, DSI_VM_TIMING3);
3654 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */
3655 r = FLD_MOD(r, tl, 31, 16); /* TL */
3656 dsi_write_reg(dsi, DSI_VM_TIMING3, r);
3657 }
3658 }
3659
3660 static int dsi_configure_pins(struct omap_dss_device *dssdev,
3661 const struct omap_dsi_pin_config *pin_cfg)
3662 {
3663 struct dsi_data *dsi = to_dsi_data(dssdev);
3664 int num_pins;
3665 const int *pins;
3666 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3667 int num_lanes;
3668 int i;
3669
3670 static const enum dsi_lane_function functions[] = {
3671 DSI_LANE_CLK,
3672 DSI_LANE_DATA1,
3673 DSI_LANE_DATA2,
3674 DSI_LANE_DATA3,
3675 DSI_LANE_DATA4,
3676 };
3677
3678 num_pins = pin_cfg->num_pins;
3679 pins = pin_cfg->pins;
3680
3681 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3682 || num_pins % 2 != 0)
3683 return -EINVAL;
3684
3685 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3686 lanes[i].function = DSI_LANE_UNUSED;
3687
3688 num_lanes = 0;
3689
3690 for (i = 0; i < num_pins; i += 2) {
3691 u8 lane, pol;
3692 int dx, dy;
3693
3694 dx = pins[i];
3695 dy = pins[i + 1];
3696
3697 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3698 return -EINVAL;
3699
3700 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3701 return -EINVAL;
3702
3703 if (dx & 1) {
3704 if (dy != dx - 1)
3705 return -EINVAL;
3706 pol = 1;
3707 } else {
3708 if (dy != dx + 1)
3709 return -EINVAL;
3710 pol = 0;
3711 }
3712
3713 lane = dx / 2;
3714
3715 lanes[lane].function = functions[i / 2];
3716 lanes[lane].polarity = pol;
3717 num_lanes++;
3718 }
3719
3720 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3721 dsi->num_lanes_used = num_lanes;
3722
3723 return 0;
3724 }
3725
3726 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3727 {
3728 struct dsi_data *dsi = to_dsi_data(dssdev);
3729 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3730 u8 data_type;
3731 u16 word_count;
3732 int r;
3733
3734 r = dsi_display_init_dispc(dsi);
3735 if (r)
3736 return r;
3737
3738 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3739 switch (dsi->pix_fmt) {
3740 case OMAP_DSS_DSI_FMT_RGB888:
3741 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3742 break;
3743 case OMAP_DSS_DSI_FMT_RGB666:
3744 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3745 break;
3746 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3747 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3748 break;
3749 case OMAP_DSS_DSI_FMT_RGB565:
3750 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3751 break;
3752 default:
3753 r = -EINVAL;
3754 goto err_pix_fmt;
3755 }
3756
3757 dsi_if_enable(dsi, false);
3758 dsi_vc_enable(dsi, channel, false);
3759
3760 /* MODE, 1 = video mode */
3761 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 4, 4);
3762
3763 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8);
3764
3765 dsi_vc_write_long_header(dsi, channel, data_type,
3766 word_count, 0);
3767
3768 dsi_vc_enable(dsi, channel, true);
3769 dsi_if_enable(dsi, true);
3770 }
3771
3772 r = dss_mgr_enable(&dsi->output);
3773 if (r)
3774 goto err_mgr_enable;
3775
3776 return 0;
3777
3778 err_mgr_enable:
3779 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3780 dsi_if_enable(dsi, false);
3781 dsi_vc_enable(dsi, channel, false);
3782 }
3783 err_pix_fmt:
3784 dsi_display_uninit_dispc(dsi);
3785 return r;
3786 }
3787
3788 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3789 {
3790 struct dsi_data *dsi = to_dsi_data(dssdev);
3791
3792 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3793 dsi_if_enable(dsi, false);
3794 dsi_vc_enable(dsi, channel, false);
3795
3796 /* MODE, 0 = command mode */
3797 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 0, 4, 4);
3798
3799 dsi_vc_enable(dsi, channel, true);
3800 dsi_if_enable(dsi, true);
3801 }
3802
3803 dss_mgr_disable(&dsi->output);
3804
3805 dsi_display_uninit_dispc(dsi);
3806 }
3807
3808 static void dsi_update_screen_dispc(struct dsi_data *dsi)
3809 {
3810 unsigned int bytespp;
3811 unsigned int bytespl;
3812 unsigned int bytespf;
3813 unsigned int total_len;
3814 unsigned int packet_payload;
3815 unsigned int packet_len;
3816 u32 l;
3817 int r;
3818 const unsigned channel = dsi->update_channel;
3819 const unsigned int line_buf_size = dsi->line_buffer_size;
3820 u16 w = dsi->vm.hactive;
3821 u16 h = dsi->vm.vactive;
3822
3823 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3824
3825 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_VP);
3826
3827 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
3828 bytespl = w * bytespp;
3829 bytespf = bytespl * h;
3830
3831 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3832 * number of lines in a packet. See errata about VP_CLK_RATIO */
3833
3834 if (bytespf < line_buf_size)
3835 packet_payload = bytespf;
3836 else
3837 packet_payload = (line_buf_size) / bytespl * bytespl;
3838
3839 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3840 total_len = (bytespf / packet_payload) * packet_len;
3841
3842 if (bytespf % packet_payload)
3843 total_len += (bytespf % packet_payload) + 1;
3844
3845 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3846 dsi_write_reg(dsi, DSI_VC_TE(channel), l);
3847
3848 dsi_vc_write_long_header(dsi, channel, MIPI_DSI_DCS_LONG_WRITE,
3849 packet_len, 0);
3850
3851 if (dsi->te_enabled)
3852 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3853 else
3854 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3855 dsi_write_reg(dsi, DSI_VC_TE(channel), l);
3856
3857 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3858 * because DSS interrupts are not capable of waking up the CPU and the
3859 * framedone interrupt could be delayed for quite a long time. I think
3860 * the same goes for any DSS interrupts, but for some reason I have not
3861 * seen the problem anywhere else than here.
3862 */
3863 dispc_disable_sidle(dsi->dss->dispc);
3864
3865 dsi_perf_mark_start(dsi);
3866
3867 r = schedule_delayed_work(&dsi->framedone_timeout_work,
3868 msecs_to_jiffies(250));
3869 BUG_ON(r == 0);
3870
3871 dss_mgr_start_update(&dsi->output);
3872
3873 if (dsi->te_enabled) {
3874 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3875 * for TE is longer than the timer allows */
3876 REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3877
3878 dsi_vc_send_bta(dsi, channel);
3879
3880 #ifdef DSI_CATCH_MISSING_TE
3881 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3882 #endif
3883 }
3884 }
3885
3886 #ifdef DSI_CATCH_MISSING_TE
3887 static void dsi_te_timeout(struct timer_list *unused)
3888 {
3889 DSSERR("TE not received for 250ms!\n");
3890 }
3891 #endif
3892
3893 static void dsi_handle_framedone(struct dsi_data *dsi, int error)
3894 {
3895 /* SIDLEMODE back to smart-idle */
3896 dispc_enable_sidle(dsi->dss->dispc);
3897
3898 if (dsi->te_enabled) {
3899 /* enable LP_RX_TO again after the TE */
3900 REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3901 }
3902
3903 dsi->framedone_callback(error, dsi->framedone_data);
3904
3905 if (!error)
3906 dsi_perf_show(dsi, "DISPC");
3907 }
3908
3909 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
3910 {
3911 struct dsi_data *dsi = container_of(work, struct dsi_data,
3912 framedone_timeout_work.work);
3913 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
3914 * 250ms which would conflict with this timeout work. What should be
3915 * done is first cancel the transfer on the HW, and then cancel the
3916 * possibly scheduled framedone work. However, cancelling the transfer
3917 * on the HW is buggy, and would probably require resetting the whole
3918 * DSI */
3919
3920 DSSERR("Framedone not received for 250ms!\n");
3921
3922 dsi_handle_framedone(dsi, -ETIMEDOUT);
3923 }
3924
3925 static void dsi_framedone_irq_callback(void *data)
3926 {
3927 struct dsi_data *dsi = data;
3928
3929 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
3930 * turns itself off. However, DSI still has the pixels in its buffers,
3931 * and is sending the data.
3932 */
3933
3934 cancel_delayed_work(&dsi->framedone_timeout_work);
3935
3936 dsi_handle_framedone(dsi, 0);
3937 }
3938
3939 static int dsi_update(struct omap_dss_device *dssdev, int channel,
3940 void (*callback)(int, void *), void *data)
3941 {
3942 struct dsi_data *dsi = to_dsi_data(dssdev);
3943 u16 dw, dh;
3944
3945 dsi_perf_mark_setup(dsi);
3946
3947 dsi->update_channel = channel;
3948
3949 dsi->framedone_callback = callback;
3950 dsi->framedone_data = data;
3951
3952 dw = dsi->vm.hactive;
3953 dh = dsi->vm.vactive;
3954
3955 #ifdef DSI_PERF_MEASURE
3956 dsi->update_bytes = dw * dh *
3957 dsi_get_pixel_size(dsi->pix_fmt) / 8;
3958 #endif
3959 dsi_update_screen_dispc(dsi);
3960
3961 return 0;
3962 }
3963
3964 /* Display funcs */
3965
3966 static int dsi_configure_dispc_clocks(struct dsi_data *dsi)
3967 {
3968 struct dispc_clock_info dispc_cinfo;
3969 int r;
3970 unsigned long fck;
3971
3972 fck = dsi_get_pll_hsdiv_dispc_rate(dsi);
3973
3974 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
3975 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
3976
3977 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo);
3978 if (r) {
3979 DSSERR("Failed to calc dispc clocks\n");
3980 return r;
3981 }
3982
3983 dsi->mgr_config.clock_info = dispc_cinfo;
3984
3985 return 0;
3986 }
3987
3988 static int dsi_display_init_dispc(struct dsi_data *dsi)
3989 {
3990 enum omap_channel channel = dsi->output.dispc_channel;
3991 int r;
3992
3993 dss_select_lcd_clk_source(dsi->dss, channel, dsi->module_id == 0 ?
3994 DSS_CLK_SRC_PLL1_1 :
3995 DSS_CLK_SRC_PLL2_1);
3996
3997 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
3998 r = dss_mgr_register_framedone_handler(&dsi->output,
3999 dsi_framedone_irq_callback, dsi);
4000 if (r) {
4001 DSSERR("can't register FRAMEDONE handler\n");
4002 goto err;
4003 }
4004
4005 dsi->mgr_config.stallmode = true;
4006 dsi->mgr_config.fifohandcheck = true;
4007 } else {
4008 dsi->mgr_config.stallmode = false;
4009 dsi->mgr_config.fifohandcheck = false;
4010 }
4011
4012 r = dsi_configure_dispc_clocks(dsi);
4013 if (r)
4014 goto err1;
4015
4016 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4017 dsi->mgr_config.video_port_width =
4018 dsi_get_pixel_size(dsi->pix_fmt);
4019 dsi->mgr_config.lcden_sig_polarity = 0;
4020
4021 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config);
4022
4023 return 0;
4024 err1:
4025 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4026 dss_mgr_unregister_framedone_handler(&dsi->output,
4027 dsi_framedone_irq_callback, dsi);
4028 err:
4029 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK);
4030 return r;
4031 }
4032
4033 static void dsi_display_uninit_dispc(struct dsi_data *dsi)
4034 {
4035 enum omap_channel channel = dsi->output.dispc_channel;
4036
4037 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4038 dss_mgr_unregister_framedone_handler(&dsi->output,
4039 dsi_framedone_irq_callback, dsi);
4040
4041 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK);
4042 }
4043
4044 static int dsi_configure_dsi_clocks(struct dsi_data *dsi)
4045 {
4046 struct dss_pll_clock_info cinfo;
4047 int r;
4048
4049 cinfo = dsi->user_dsi_cinfo;
4050
4051 r = dss_pll_set_config(&dsi->pll, &cinfo);
4052 if (r) {
4053 DSSERR("Failed to set dsi clocks\n");
4054 return r;
4055 }
4056
4057 return 0;
4058 }
4059
4060 static int dsi_display_init_dsi(struct dsi_data *dsi)
4061 {
4062 int r;
4063
4064 r = dss_pll_enable(&dsi->pll);
4065 if (r)
4066 return r;
4067
4068 r = dsi_configure_dsi_clocks(dsi);
4069 if (r)
4070 goto err0;
4071
4072 dss_select_dsi_clk_source(dsi->dss, dsi->module_id,
4073 dsi->module_id == 0 ?
4074 DSS_CLK_SRC_PLL1_2 : DSS_CLK_SRC_PLL2_2);
4075
4076 DSSDBG("PLL OK\n");
4077
4078 if (!dsi->vdds_dsi_enabled) {
4079 r = regulator_enable(dsi->vdds_dsi_reg);
4080 if (r)
4081 goto err1;
4082
4083 dsi->vdds_dsi_enabled = true;
4084 }
4085
4086 r = dsi_cio_init(dsi);
4087 if (r)
4088 goto err2;
4089
4090 _dsi_print_reset_status(dsi);
4091
4092 dsi_proto_timings(dsi);
4093 dsi_set_lp_clk_divisor(dsi);
4094
4095 if (1)
4096 _dsi_print_reset_status(dsi);
4097
4098 r = dsi_proto_config(dsi);
4099 if (r)
4100 goto err3;
4101
4102 /* enable interface */
4103 dsi_vc_enable(dsi, 0, 1);
4104 dsi_vc_enable(dsi, 1, 1);
4105 dsi_vc_enable(dsi, 2, 1);
4106 dsi_vc_enable(dsi, 3, 1);
4107 dsi_if_enable(dsi, 1);
4108 dsi_force_tx_stop_mode_io(dsi);
4109
4110 return 0;
4111 err3:
4112 dsi_cio_uninit(dsi);
4113 err2:
4114 regulator_disable(dsi->vdds_dsi_reg);
4115 dsi->vdds_dsi_enabled = false;
4116 err1:
4117 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
4118 err0:
4119 dss_pll_disable(&dsi->pll);
4120
4121 return r;
4122 }
4123
4124 static void dsi_display_uninit_dsi(struct dsi_data *dsi, bool disconnect_lanes,
4125 bool enter_ulps)
4126 {
4127 if (enter_ulps && !dsi->ulps_enabled)
4128 dsi_enter_ulps(dsi);
4129
4130 /* disable interface */
4131 dsi_if_enable(dsi, 0);
4132 dsi_vc_enable(dsi, 0, 0);
4133 dsi_vc_enable(dsi, 1, 0);
4134 dsi_vc_enable(dsi, 2, 0);
4135 dsi_vc_enable(dsi, 3, 0);
4136
4137 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
4138 dsi_cio_uninit(dsi);
4139 dss_pll_disable(&dsi->pll);
4140
4141 if (disconnect_lanes) {
4142 regulator_disable(dsi->vdds_dsi_reg);
4143 dsi->vdds_dsi_enabled = false;
4144 }
4145 }
4146
4147 static void dsi_display_enable(struct omap_dss_device *dssdev)
4148 {
4149 struct dsi_data *dsi = to_dsi_data(dssdev);
4150 int r;
4151
4152 DSSDBG("dsi_display_enable\n");
4153
4154 WARN_ON(!dsi_bus_is_locked(dsi));
4155
4156 mutex_lock(&dsi->lock);
4157
4158 r = dsi_runtime_get(dsi);
4159 if (r)
4160 goto err_get_dsi;
4161
4162 _dsi_initialize_irq(dsi);
4163
4164 r = dsi_display_init_dsi(dsi);
4165 if (r)
4166 goto err_init_dsi;
4167
4168 mutex_unlock(&dsi->lock);
4169
4170 return;
4171
4172 err_init_dsi:
4173 dsi_runtime_put(dsi);
4174 err_get_dsi:
4175 mutex_unlock(&dsi->lock);
4176 DSSDBG("dsi_display_enable FAILED\n");
4177 }
4178
4179 static void dsi_display_disable(struct omap_dss_device *dssdev,
4180 bool disconnect_lanes, bool enter_ulps)
4181 {
4182 struct dsi_data *dsi = to_dsi_data(dssdev);
4183
4184 DSSDBG("dsi_display_disable\n");
4185
4186 WARN_ON(!dsi_bus_is_locked(dsi));
4187
4188 mutex_lock(&dsi->lock);
4189
4190 dsi_sync_vc(dsi, 0);
4191 dsi_sync_vc(dsi, 1);
4192 dsi_sync_vc(dsi, 2);
4193 dsi_sync_vc(dsi, 3);
4194
4195 dsi_display_uninit_dsi(dsi, disconnect_lanes, enter_ulps);
4196
4197 dsi_runtime_put(dsi);
4198
4199 mutex_unlock(&dsi->lock);
4200 }
4201
4202 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4203 {
4204 struct dsi_data *dsi = to_dsi_data(dssdev);
4205
4206 dsi->te_enabled = enable;
4207 return 0;
4208 }
4209
4210 #ifdef PRINT_VERBOSE_VM_TIMINGS
4211 static void print_dsi_vm(const char *str,
4212 const struct omap_dss_dsi_videomode_timings *t)
4213 {
4214 unsigned long byteclk = t->hsclk / 4;
4215 int bl, wc, pps, tot;
4216
4217 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4218 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4219 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4220 tot = bl + pps;
4221
4222 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4223
4224 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4225 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4226 str,
4227 byteclk,
4228 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4229 bl, pps, tot,
4230 TO_DSI_T(t->hss),
4231 TO_DSI_T(t->hsa),
4232 TO_DSI_T(t->hse),
4233 TO_DSI_T(t->hbp),
4234 TO_DSI_T(pps),
4235 TO_DSI_T(t->hfp),
4236
4237 TO_DSI_T(bl),
4238 TO_DSI_T(pps),
4239
4240 TO_DSI_T(tot));
4241 #undef TO_DSI_T
4242 }
4243
4244 static void print_dispc_vm(const char *str, const struct videomode *vm)
4245 {
4246 unsigned long pck = vm->pixelclock;
4247 int hact, bl, tot;
4248
4249 hact = vm->hactive;
4250 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch;
4251 tot = hact + bl;
4252
4253 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4254
4255 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4256 "%u/%u/%u/%u = %u + %u = %u\n",
4257 str,
4258 pck,
4259 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch,
4260 bl, hact, tot,
4261 TO_DISPC_T(vm->hsync_len),
4262 TO_DISPC_T(vm->hback_porch),
4263 TO_DISPC_T(hact),
4264 TO_DISPC_T(vm->hfront_porch),
4265 TO_DISPC_T(bl),
4266 TO_DISPC_T(hact),
4267 TO_DISPC_T(tot));
4268 #undef TO_DISPC_T
4269 }
4270
4271 /* note: this is not quite accurate */
4272 static void print_dsi_dispc_vm(const char *str,
4273 const struct omap_dss_dsi_videomode_timings *t)
4274 {
4275 struct videomode vm = { 0 };
4276 unsigned long byteclk = t->hsclk / 4;
4277 unsigned long pck;
4278 u64 dsi_tput;
4279 int dsi_hact, dsi_htot;
4280
4281 dsi_tput = (u64)byteclk * t->ndl * 8;
4282 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4283 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4284 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4285
4286 vm.pixelclock = pck;
4287 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4288 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk);
4289 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk);
4290 vm.hactive = t->hact;
4291
4292 print_dispc_vm(str, &vm);
4293 }
4294 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4295
4296 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4297 unsigned long pck, void *data)
4298 {
4299 struct dsi_clk_calc_ctx *ctx = data;
4300 struct videomode *vm = &ctx->vm;
4301
4302 ctx->dispc_cinfo.lck_div = lckd;
4303 ctx->dispc_cinfo.pck_div = pckd;
4304 ctx->dispc_cinfo.lck = lck;
4305 ctx->dispc_cinfo.pck = pck;
4306
4307 *vm = *ctx->config->vm;
4308 vm->pixelclock = pck;
4309 vm->hactive = ctx->config->vm->hactive;
4310 vm->vactive = ctx->config->vm->vactive;
4311 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1;
4312 vm->vfront_porch = vm->vback_porch = 0;
4313
4314 return true;
4315 }
4316
4317 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4318 void *data)
4319 {
4320 struct dsi_clk_calc_ctx *ctx = data;
4321
4322 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4323 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4324
4325 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
4326 ctx->req_pck_min, ctx->req_pck_max,
4327 dsi_cm_calc_dispc_cb, ctx);
4328 }
4329
4330 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4331 unsigned long clkdco, void *data)
4332 {
4333 struct dsi_clk_calc_ctx *ctx = data;
4334 struct dsi_data *dsi = ctx->dsi;
4335
4336 ctx->dsi_cinfo.n = n;
4337 ctx->dsi_cinfo.m = m;
4338 ctx->dsi_cinfo.fint = fint;
4339 ctx->dsi_cinfo.clkdco = clkdco;
4340
4341 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4342 dsi->data->max_fck_freq,
4343 dsi_cm_calc_hsdiv_cb, ctx);
4344 }
4345
4346 static bool dsi_cm_calc(struct dsi_data *dsi,
4347 const struct omap_dss_dsi_config *cfg,
4348 struct dsi_clk_calc_ctx *ctx)
4349 {
4350 unsigned long clkin;
4351 int bitspp, ndl;
4352 unsigned long pll_min, pll_max;
4353 unsigned long pck, txbyteclk;
4354
4355 clkin = clk_get_rate(dsi->pll.clkin);
4356 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4357 ndl = dsi->num_lanes_used - 1;
4358
4359 /*
4360 * Here we should calculate minimum txbyteclk to be able to send the
4361 * frame in time, and also to handle TE. That's not very simple, though,
4362 * especially as we go to LP between each pixel packet due to HW
4363 * "feature". So let's just estimate very roughly and multiply by 1.5.
4364 */
4365 pck = cfg->vm->pixelclock;
4366 pck = pck * 3 / 2;
4367 txbyteclk = pck * bitspp / 8 / ndl;
4368
4369 memset(ctx, 0, sizeof(*ctx));
4370 ctx->dsi = dsi;
4371 ctx->pll = &dsi->pll;
4372 ctx->config = cfg;
4373 ctx->req_pck_min = pck;
4374 ctx->req_pck_nom = pck;
4375 ctx->req_pck_max = pck * 3 / 2;
4376
4377 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4378 pll_max = cfg->hs_clk_max * 4;
4379
4380 return dss_pll_calc_a(ctx->pll, clkin,
4381 pll_min, pll_max,
4382 dsi_cm_calc_pll_cb, ctx);
4383 }
4384
4385 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4386 {
4387 struct dsi_data *dsi = ctx->dsi;
4388 const struct omap_dss_dsi_config *cfg = ctx->config;
4389 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4390 int ndl = dsi->num_lanes_used - 1;
4391 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
4392 unsigned long byteclk = hsclk / 4;
4393
4394 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4395 int xres;
4396 int panel_htot, panel_hbl; /* pixels */
4397 int dispc_htot, dispc_hbl; /* pixels */
4398 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4399 int hfp, hsa, hbp;
4400 const struct videomode *req_vm;
4401 struct videomode *dispc_vm;
4402 struct omap_dss_dsi_videomode_timings *dsi_vm;
4403 u64 dsi_tput, dispc_tput;
4404
4405 dsi_tput = (u64)byteclk * ndl * 8;
4406
4407 req_vm = cfg->vm;
4408 req_pck_min = ctx->req_pck_min;
4409 req_pck_max = ctx->req_pck_max;
4410 req_pck_nom = ctx->req_pck_nom;
4411
4412 dispc_pck = ctx->dispc_cinfo.pck;
4413 dispc_tput = (u64)dispc_pck * bitspp;
4414
4415 xres = req_vm->hactive;
4416
4417 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch +
4418 req_vm->hsync_len;
4419 panel_htot = xres + panel_hbl;
4420
4421 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4422
4423 /*
4424 * When there are no line buffers, DISPC and DSI must have the
4425 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4426 */
4427 if (dsi->line_buffer_size < xres * bitspp / 8) {
4428 if (dispc_tput != dsi_tput)
4429 return false;
4430 } else {
4431 if (dispc_tput < dsi_tput)
4432 return false;
4433 }
4434
4435 /* DSI tput must be over the min requirement */
4436 if (dsi_tput < (u64)bitspp * req_pck_min)
4437 return false;
4438
4439 /* When non-burst mode, DSI tput must be below max requirement. */
4440 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4441 if (dsi_tput > (u64)bitspp * req_pck_max)
4442 return false;
4443 }
4444
4445 hss = DIV_ROUND_UP(4, ndl);
4446
4447 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4448 if (ndl == 3 && req_vm->hsync_len == 0)
4449 hse = 1;
4450 else
4451 hse = DIV_ROUND_UP(4, ndl);
4452 } else {
4453 hse = 0;
4454 }
4455
4456 /* DSI htot to match the panel's nominal pck */
4457 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4458
4459 /* fail if there would be no time for blanking */
4460 if (dsi_htot < hss + hse + dsi_hact)
4461 return false;
4462
4463 /* total DSI blanking needed to achieve panel's TL */
4464 dsi_hbl = dsi_htot - dsi_hact;
4465
4466 /* DISPC htot to match the DSI TL */
4467 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4468
4469 /* verify that the DSI and DISPC TLs are the same */
4470 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4471 return false;
4472
4473 dispc_hbl = dispc_htot - xres;
4474
4475 /* setup DSI videomode */
4476
4477 dsi_vm = &ctx->dsi_vm;
4478 memset(dsi_vm, 0, sizeof(*dsi_vm));
4479
4480 dsi_vm->hsclk = hsclk;
4481
4482 dsi_vm->ndl = ndl;
4483 dsi_vm->bitspp = bitspp;
4484
4485 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4486 hsa = 0;
4487 } else if (ndl == 3 && req_vm->hsync_len == 0) {
4488 hsa = 0;
4489 } else {
4490 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom);
4491 hsa = max(hsa - hse, 1);
4492 }
4493
4494 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom);
4495 hbp = max(hbp, 1);
4496
4497 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4498 if (hfp < 1) {
4499 int t;
4500 /* we need to take cycles from hbp */
4501
4502 t = 1 - hfp;
4503 hbp = max(hbp - t, 1);
4504 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4505
4506 if (hfp < 1 && hsa > 0) {
4507 /* we need to take cycles from hsa */
4508 t = 1 - hfp;
4509 hsa = max(hsa - t, 1);
4510 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4511 }
4512 }
4513
4514 if (hfp < 1)
4515 return false;
4516
4517 dsi_vm->hss = hss;
4518 dsi_vm->hsa = hsa;
4519 dsi_vm->hse = hse;
4520 dsi_vm->hbp = hbp;
4521 dsi_vm->hact = xres;
4522 dsi_vm->hfp = hfp;
4523
4524 dsi_vm->vsa = req_vm->vsync_len;
4525 dsi_vm->vbp = req_vm->vback_porch;
4526 dsi_vm->vact = req_vm->vactive;
4527 dsi_vm->vfp = req_vm->vfront_porch;
4528
4529 dsi_vm->trans_mode = cfg->trans_mode;
4530
4531 dsi_vm->blanking_mode = 0;
4532 dsi_vm->hsa_blanking_mode = 1;
4533 dsi_vm->hfp_blanking_mode = 1;
4534 dsi_vm->hbp_blanking_mode = 1;
4535
4536 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4537 dsi_vm->window_sync = 4;
4538
4539 /* setup DISPC videomode */
4540
4541 dispc_vm = &ctx->vm;
4542 *dispc_vm = *req_vm;
4543 dispc_vm->pixelclock = dispc_pck;
4544
4545 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4546 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck,
4547 req_pck_nom);
4548 hsa = max(hsa, 1);
4549 } else {
4550 hsa = 1;
4551 }
4552
4553 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom);
4554 hbp = max(hbp, 1);
4555
4556 hfp = dispc_hbl - hsa - hbp;
4557 if (hfp < 1) {
4558 int t;
4559 /* we need to take cycles from hbp */
4560
4561 t = 1 - hfp;
4562 hbp = max(hbp - t, 1);
4563 hfp = dispc_hbl - hsa - hbp;
4564
4565 if (hfp < 1) {
4566 /* we need to take cycles from hsa */
4567 t = 1 - hfp;
4568 hsa = max(hsa - t, 1);
4569 hfp = dispc_hbl - hsa - hbp;
4570 }
4571 }
4572
4573 if (hfp < 1)
4574 return false;
4575
4576 dispc_vm->hfront_porch = hfp;
4577 dispc_vm->hsync_len = hsa;
4578 dispc_vm->hback_porch = hbp;
4579
4580 return true;
4581 }
4582
4583
4584 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4585 unsigned long pck, void *data)
4586 {
4587 struct dsi_clk_calc_ctx *ctx = data;
4588
4589 ctx->dispc_cinfo.lck_div = lckd;
4590 ctx->dispc_cinfo.pck_div = pckd;
4591 ctx->dispc_cinfo.lck = lck;
4592 ctx->dispc_cinfo.pck = pck;
4593
4594 if (dsi_vm_calc_blanking(ctx) == false)
4595 return false;
4596
4597 #ifdef PRINT_VERBOSE_VM_TIMINGS
4598 print_dispc_vm("dispc", &ctx->vm);
4599 print_dsi_vm("dsi ", &ctx->dsi_vm);
4600 print_dispc_vm("req ", ctx->config->vm);
4601 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4602 #endif
4603
4604 return true;
4605 }
4606
4607 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4608 void *data)
4609 {
4610 struct dsi_clk_calc_ctx *ctx = data;
4611 unsigned long pck_max;
4612
4613 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4614 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4615
4616 /*
4617 * In burst mode we can let the dispc pck be arbitrarily high, but it
4618 * limits our scaling abilities. So for now, don't aim too high.
4619 */
4620
4621 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4622 pck_max = ctx->req_pck_max + 10000000;
4623 else
4624 pck_max = ctx->req_pck_max;
4625
4626 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
4627 ctx->req_pck_min, pck_max,
4628 dsi_vm_calc_dispc_cb, ctx);
4629 }
4630
4631 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4632 unsigned long clkdco, void *data)
4633 {
4634 struct dsi_clk_calc_ctx *ctx = data;
4635 struct dsi_data *dsi = ctx->dsi;
4636
4637 ctx->dsi_cinfo.n = n;
4638 ctx->dsi_cinfo.m = m;
4639 ctx->dsi_cinfo.fint = fint;
4640 ctx->dsi_cinfo.clkdco = clkdco;
4641
4642 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4643 dsi->data->max_fck_freq,
4644 dsi_vm_calc_hsdiv_cb, ctx);
4645 }
4646
4647 static bool dsi_vm_calc(struct dsi_data *dsi,
4648 const struct omap_dss_dsi_config *cfg,
4649 struct dsi_clk_calc_ctx *ctx)
4650 {
4651 const struct videomode *vm = cfg->vm;
4652 unsigned long clkin;
4653 unsigned long pll_min;
4654 unsigned long pll_max;
4655 int ndl = dsi->num_lanes_used - 1;
4656 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4657 unsigned long byteclk_min;
4658
4659 clkin = clk_get_rate(dsi->pll.clkin);
4660
4661 memset(ctx, 0, sizeof(*ctx));
4662 ctx->dsi = dsi;
4663 ctx->pll = &dsi->pll;
4664 ctx->config = cfg;
4665
4666 /* these limits should come from the panel driver */
4667 ctx->req_pck_min = vm->pixelclock - 1000;
4668 ctx->req_pck_nom = vm->pixelclock;
4669 ctx->req_pck_max = vm->pixelclock + 1000;
4670
4671 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4672 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4673
4674 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4675 pll_max = cfg->hs_clk_max * 4;
4676 } else {
4677 unsigned long byteclk_max;
4678 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4679 ndl * 8);
4680
4681 pll_max = byteclk_max * 4 * 4;
4682 }
4683
4684 return dss_pll_calc_a(ctx->pll, clkin,
4685 pll_min, pll_max,
4686 dsi_vm_calc_pll_cb, ctx);
4687 }
4688
4689 static int dsi_set_config(struct omap_dss_device *dssdev,
4690 const struct omap_dss_dsi_config *config)
4691 {
4692 struct dsi_data *dsi = to_dsi_data(dssdev);
4693 struct dsi_clk_calc_ctx ctx;
4694 bool ok;
4695 int r;
4696
4697 mutex_lock(&dsi->lock);
4698
4699 dsi->pix_fmt = config->pixel_format;
4700 dsi->mode = config->mode;
4701
4702 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
4703 ok = dsi_vm_calc(dsi, config, &ctx);
4704 else
4705 ok = dsi_cm_calc(dsi, config, &ctx);
4706
4707 if (!ok) {
4708 DSSERR("failed to find suitable DSI clock settings\n");
4709 r = -EINVAL;
4710 goto err;
4711 }
4712
4713 dsi_pll_calc_dsi_fck(dsi, &ctx.dsi_cinfo);
4714
4715 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
4716 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
4717 if (r) {
4718 DSSERR("failed to find suitable DSI LP clock settings\n");
4719 goto err;
4720 }
4721
4722 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4723 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4724
4725 dsi->vm = ctx.vm;
4726
4727 /*
4728 * override interlace, logic level and edge related parameters in
4729 * videomode with default values
4730 */
4731 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
4732 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
4733 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
4734 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
4735 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
4736 /*
4737 * HACK: These flags should be handled through the omap_dss_device bus
4738 * flags, but this will only be possible when the DSI encoder will be
4739 * converted to the omapdrm-managed encoder model.
4740 */
4741 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
4742 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
4743 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
4744 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH;
4745 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
4746 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
4747
4748 dss_mgr_set_timings(&dsi->output, &dsi->vm);
4749
4750 dsi->vm_timings = ctx.dsi_vm;
4751
4752 mutex_unlock(&dsi->lock);
4753
4754 return 0;
4755 err:
4756 mutex_unlock(&dsi->lock);
4757
4758 return r;
4759 }
4760
4761 /*
4762 * Return a hardcoded channel for the DSI output. This should work for
4763 * current use cases, but this can be later expanded to either resolve
4764 * the channel in some more dynamic manner, or get the channel as a user
4765 * parameter.
4766 */
4767 static enum omap_channel dsi_get_channel(struct dsi_data *dsi)
4768 {
4769 switch (dsi->data->model) {
4770 case DSI_MODEL_OMAP3:
4771 return OMAP_DSS_CHANNEL_LCD;
4772
4773 case DSI_MODEL_OMAP4:
4774 switch (dsi->module_id) {
4775 case 0:
4776 return OMAP_DSS_CHANNEL_LCD;
4777 case 1:
4778 return OMAP_DSS_CHANNEL_LCD2;
4779 default:
4780 DSSWARN("unsupported module id\n");
4781 return OMAP_DSS_CHANNEL_LCD;
4782 }
4783
4784 case DSI_MODEL_OMAP5:
4785 switch (dsi->module_id) {
4786 case 0:
4787 return OMAP_DSS_CHANNEL_LCD;
4788 case 1:
4789 return OMAP_DSS_CHANNEL_LCD3;
4790 default:
4791 DSSWARN("unsupported module id\n");
4792 return OMAP_DSS_CHANNEL_LCD;
4793 }
4794
4795 default:
4796 DSSWARN("unsupported DSS version\n");
4797 return OMAP_DSS_CHANNEL_LCD;
4798 }
4799 }
4800
4801 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4802 {
4803 struct dsi_data *dsi = to_dsi_data(dssdev);
4804 int i;
4805
4806 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4807 if (!dsi->vc[i].dssdev) {
4808 dsi->vc[i].dssdev = dssdev;
4809 *channel = i;
4810 return 0;
4811 }
4812 }
4813
4814 DSSERR("cannot get VC for display %s", dssdev->name);
4815 return -ENOSPC;
4816 }
4817
4818 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4819 {
4820 struct dsi_data *dsi = to_dsi_data(dssdev);
4821
4822 if (vc_id < 0 || vc_id > 3) {
4823 DSSERR("VC ID out of range\n");
4824 return -EINVAL;
4825 }
4826
4827 if (channel < 0 || channel > 3) {
4828 DSSERR("Virtual Channel out of range\n");
4829 return -EINVAL;
4830 }
4831
4832 if (dsi->vc[channel].dssdev != dssdev) {
4833 DSSERR("Virtual Channel not allocated to display %s\n",
4834 dssdev->name);
4835 return -EINVAL;
4836 }
4837
4838 dsi->vc[channel].vc_id = vc_id;
4839
4840 return 0;
4841 }
4842
4843 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4844 {
4845 struct dsi_data *dsi = to_dsi_data(dssdev);
4846
4847 if ((channel >= 0 && channel <= 3) &&
4848 dsi->vc[channel].dssdev == dssdev) {
4849 dsi->vc[channel].dssdev = NULL;
4850 dsi->vc[channel].vc_id = 0;
4851 }
4852 }
4853
4854
4855 static int dsi_get_clocks(struct dsi_data *dsi)
4856 {
4857 struct clk *clk;
4858
4859 clk = devm_clk_get(dsi->dev, "fck");
4860 if (IS_ERR(clk)) {
4861 DSSERR("can't get fck\n");
4862 return PTR_ERR(clk);
4863 }
4864
4865 dsi->dss_clk = clk;
4866
4867 return 0;
4868 }
4869
4870 static int dsi_connect(struct omap_dss_device *src,
4871 struct omap_dss_device *dst)
4872 {
4873 return omapdss_device_connect(dst->dss, dst, dst->next);
4874 }
4875
4876 static void dsi_disconnect(struct omap_dss_device *src,
4877 struct omap_dss_device *dst)
4878 {
4879 omapdss_device_disconnect(dst, dst->next);
4880 }
4881
4882 static const struct omap_dss_device_ops dsi_ops = {
4883 .connect = dsi_connect,
4884 .disconnect = dsi_disconnect,
4885 .enable = dsi_display_enable,
4886
4887 .dsi = {
4888 .bus_lock = dsi_bus_lock,
4889 .bus_unlock = dsi_bus_unlock,
4890
4891 .disable = dsi_display_disable,
4892
4893 .enable_hs = dsi_vc_enable_hs,
4894
4895 .configure_pins = dsi_configure_pins,
4896 .set_config = dsi_set_config,
4897
4898 .enable_video_output = dsi_enable_video_output,
4899 .disable_video_output = dsi_disable_video_output,
4900
4901 .update = dsi_update,
4902
4903 .enable_te = dsi_enable_te,
4904
4905 .request_vc = dsi_request_vc,
4906 .set_vc_id = dsi_set_vc_id,
4907 .release_vc = dsi_release_vc,
4908
4909 .dcs_write = dsi_vc_dcs_write,
4910 .dcs_write_nosync = dsi_vc_dcs_write_nosync,
4911 .dcs_read = dsi_vc_dcs_read,
4912
4913 .gen_write = dsi_vc_generic_write,
4914 .gen_write_nosync = dsi_vc_generic_write_nosync,
4915 .gen_read = dsi_vc_generic_read,
4916
4917 .bta_sync = dsi_vc_send_bta_sync,
4918
4919 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
4920 },
4921 };
4922
4923 /* -----------------------------------------------------------------------------
4924 * PLL
4925 */
4926
4927 static const struct dss_pll_ops dsi_pll_ops = {
4928 .enable = dsi_pll_enable,
4929 .disable = dsi_pll_disable,
4930 .set_config = dss_pll_write_config_type_a,
4931 };
4932
4933 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
4934 .type = DSS_PLL_TYPE_A,
4935
4936 .n_max = (1 << 7) - 1,
4937 .m_max = (1 << 11) - 1,
4938 .mX_max = (1 << 4) - 1,
4939 .fint_min = 750000,
4940 .fint_max = 2100000,
4941 .clkdco_low = 1000000000,
4942 .clkdco_max = 1800000000,
4943
4944 .n_msb = 7,
4945 .n_lsb = 1,
4946 .m_msb = 18,
4947 .m_lsb = 8,
4948
4949 .mX_msb[0] = 22,
4950 .mX_lsb[0] = 19,
4951 .mX_msb[1] = 26,
4952 .mX_lsb[1] = 23,
4953
4954 .has_stopmode = true,
4955 .has_freqsel = true,
4956 .has_selfreqdco = false,
4957 .has_refsel = false,
4958 };
4959
4960 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
4961 .type = DSS_PLL_TYPE_A,
4962
4963 .n_max = (1 << 8) - 1,
4964 .m_max = (1 << 12) - 1,
4965 .mX_max = (1 << 5) - 1,
4966 .fint_min = 500000,
4967 .fint_max = 2500000,
4968 .clkdco_low = 1000000000,
4969 .clkdco_max = 1800000000,
4970
4971 .n_msb = 8,
4972 .n_lsb = 1,
4973 .m_msb = 20,
4974 .m_lsb = 9,
4975
4976 .mX_msb[0] = 25,
4977 .mX_lsb[0] = 21,
4978 .mX_msb[1] = 30,
4979 .mX_lsb[1] = 26,
4980
4981 .has_stopmode = true,
4982 .has_freqsel = false,
4983 .has_selfreqdco = false,
4984 .has_refsel = false,
4985 };
4986
4987 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
4988 .type = DSS_PLL_TYPE_A,
4989
4990 .n_max = (1 << 8) - 1,
4991 .m_max = (1 << 12) - 1,
4992 .mX_max = (1 << 5) - 1,
4993 .fint_min = 150000,
4994 .fint_max = 52000000,
4995 .clkdco_low = 1000000000,
4996 .clkdco_max = 1800000000,
4997
4998 .n_msb = 8,
4999 .n_lsb = 1,
5000 .m_msb = 20,
5001 .m_lsb = 9,
5002
5003 .mX_msb[0] = 25,
5004 .mX_lsb[0] = 21,
5005 .mX_msb[1] = 30,
5006 .mX_lsb[1] = 26,
5007
5008 .has_stopmode = true,
5009 .has_freqsel = false,
5010 .has_selfreqdco = true,
5011 .has_refsel = true,
5012 };
5013
5014 static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi)
5015 {
5016 struct dss_pll *pll = &dsi->pll;
5017 struct clk *clk;
5018 int r;
5019
5020 clk = devm_clk_get(dsi->dev, "sys_clk");
5021 if (IS_ERR(clk)) {
5022 DSSERR("can't get sys_clk\n");
5023 return PTR_ERR(clk);
5024 }
5025
5026 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
5027 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
5028 pll->clkin = clk;
5029 pll->base = dsi->pll_base;
5030 pll->hw = dsi->data->pll_hw;
5031 pll->ops = &dsi_pll_ops;
5032
5033 r = dss_pll_register(dss, pll);
5034 if (r)
5035 return r;
5036
5037 return 0;
5038 }
5039
5040 /* -----------------------------------------------------------------------------
5041 * Component Bind & Unbind
5042 */
5043
5044 static int dsi_bind(struct device *dev, struct device *master, void *data)
5045 {
5046 struct dss_device *dss = dss_get_device(master);
5047 struct dsi_data *dsi = dev_get_drvdata(dev);
5048 char name[10];
5049 u32 rev;
5050 int r;
5051
5052 dsi->dss = dss;
5053
5054 dsi_init_pll_data(dss, dsi);
5055
5056 r = dsi_runtime_get(dsi);
5057 if (r)
5058 return r;
5059
5060 rev = dsi_read_reg(dsi, DSI_REVISION);
5061 dev_dbg(dev, "OMAP DSI rev %d.%d\n",
5062 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5063
5064 dsi->line_buffer_size = dsi_get_line_buf_size(dsi);
5065
5066 dsi_runtime_put(dsi);
5067
5068 snprintf(name, sizeof(name), "dsi%u_regs", dsi->module_id + 1);
5069 dsi->debugfs.regs = dss_debugfs_create_file(dss, name,
5070 dsi_dump_dsi_regs, dsi);
5071 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5072 snprintf(name, sizeof(name), "dsi%u_irqs", dsi->module_id + 1);
5073 dsi->debugfs.irqs = dss_debugfs_create_file(dss, name,
5074 dsi_dump_dsi_irqs, dsi);
5075 #endif
5076 snprintf(name, sizeof(name), "dsi%u_clks", dsi->module_id + 1);
5077 dsi->debugfs.clks = dss_debugfs_create_file(dss, name,
5078 dsi_dump_dsi_clocks, dsi);
5079
5080 return 0;
5081 }
5082
5083 static void dsi_unbind(struct device *dev, struct device *master, void *data)
5084 {
5085 struct dsi_data *dsi = dev_get_drvdata(dev);
5086
5087 dss_debugfs_remove_file(dsi->debugfs.clks);
5088 dss_debugfs_remove_file(dsi->debugfs.irqs);
5089 dss_debugfs_remove_file(dsi->debugfs.regs);
5090
5091 WARN_ON(dsi->scp_clk_refcount > 0);
5092
5093 dss_pll_unregister(&dsi->pll);
5094 }
5095
5096 static const struct component_ops dsi_component_ops = {
5097 .bind = dsi_bind,
5098 .unbind = dsi_unbind,
5099 };
5100
5101 /* -----------------------------------------------------------------------------
5102 * Probe & Remove, Suspend & Resume
5103 */
5104
5105 static int dsi_init_output(struct dsi_data *dsi)
5106 {
5107 struct omap_dss_device *out = &dsi->output;
5108 int r;
5109
5110 out->dev = dsi->dev;
5111 out->id = dsi->module_id == 0 ?
5112 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5113
5114 out->type = OMAP_DISPLAY_TYPE_DSI;
5115 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5116 out->dispc_channel = dsi_get_channel(dsi);
5117 out->ops = &dsi_ops;
5118 out->owner = THIS_MODULE;
5119 out->of_ports = BIT(0);
5120 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
5121 | DRM_BUS_FLAG_DE_HIGH
5122 | DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
5123
5124 r = omapdss_device_init_output(out);
5125 if (r < 0)
5126 return r;
5127
5128 omapdss_device_register(out);
5129
5130 return 0;
5131 }
5132
5133 static void dsi_uninit_output(struct dsi_data *dsi)
5134 {
5135 struct omap_dss_device *out = &dsi->output;
5136
5137 omapdss_device_unregister(out);
5138 omapdss_device_cleanup_output(out);
5139 }
5140
5141 static int dsi_probe_of(struct dsi_data *dsi)
5142 {
5143 struct device_node *node = dsi->dev->of_node;
5144 struct property *prop;
5145 u32 lane_arr[10];
5146 int len, num_pins;
5147 int r, i;
5148 struct device_node *ep;
5149 struct omap_dsi_pin_config pin_cfg;
5150
5151 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
5152 if (!ep)
5153 return 0;
5154
5155 prop = of_find_property(ep, "lanes", &len);
5156 if (prop == NULL) {
5157 dev_err(dsi->dev, "failed to find lane data\n");
5158 r = -EINVAL;
5159 goto err;
5160 }
5161
5162 num_pins = len / sizeof(u32);
5163
5164 if (num_pins < 4 || num_pins % 2 != 0 ||
5165 num_pins > dsi->num_lanes_supported * 2) {
5166 dev_err(dsi->dev, "bad number of lanes\n");
5167 r = -EINVAL;
5168 goto err;
5169 }
5170
5171 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5172 if (r) {
5173 dev_err(dsi->dev, "failed to read lane data\n");
5174 goto err;
5175 }
5176
5177 pin_cfg.num_pins = num_pins;
5178 for (i = 0; i < num_pins; ++i)
5179 pin_cfg.pins[i] = (int)lane_arr[i];
5180
5181 r = dsi_configure_pins(&dsi->output, &pin_cfg);
5182 if (r) {
5183 dev_err(dsi->dev, "failed to configure pins");
5184 goto err;
5185 }
5186
5187 of_node_put(ep);
5188
5189 return 0;
5190
5191 err:
5192 of_node_put(ep);
5193 return r;
5194 }
5195
5196 static const struct dsi_of_data dsi_of_data_omap34xx = {
5197 .model = DSI_MODEL_OMAP3,
5198 .pll_hw = &dss_omap3_dsi_pll_hw,
5199 .modules = (const struct dsi_module_id_data[]) {
5200 { .address = 0x4804fc00, .id = 0, },
5201 { },
5202 },
5203 .max_fck_freq = 173000000,
5204 .max_pll_lpdiv = (1 << 13) - 1,
5205 .quirks = DSI_QUIRK_REVERSE_TXCLKESC,
5206 };
5207
5208 static const struct dsi_of_data dsi_of_data_omap36xx = {
5209 .model = DSI_MODEL_OMAP3,
5210 .pll_hw = &dss_omap3_dsi_pll_hw,
5211 .modules = (const struct dsi_module_id_data[]) {
5212 { .address = 0x4804fc00, .id = 0, },
5213 { },
5214 },
5215 .max_fck_freq = 173000000,
5216 .max_pll_lpdiv = (1 << 13) - 1,
5217 .quirks = DSI_QUIRK_PLL_PWR_BUG,
5218 };
5219
5220 static const struct dsi_of_data dsi_of_data_omap4 = {
5221 .model = DSI_MODEL_OMAP4,
5222 .pll_hw = &dss_omap4_dsi_pll_hw,
5223 .modules = (const struct dsi_module_id_data[]) {
5224 { .address = 0x58004000, .id = 0, },
5225 { .address = 0x58005000, .id = 1, },
5226 { },
5227 },
5228 .max_fck_freq = 170000000,
5229 .max_pll_lpdiv = (1 << 13) - 1,
5230 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
5231 | DSI_QUIRK_GNQ,
5232 };
5233
5234 static const struct dsi_of_data dsi_of_data_omap5 = {
5235 .model = DSI_MODEL_OMAP5,
5236 .pll_hw = &dss_omap5_dsi_pll_hw,
5237 .modules = (const struct dsi_module_id_data[]) {
5238 { .address = 0x58004000, .id = 0, },
5239 { .address = 0x58009000, .id = 1, },
5240 { },
5241 },
5242 .max_fck_freq = 209250000,
5243 .max_pll_lpdiv = (1 << 13) - 1,
5244 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
5245 | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC,
5246 };
5247
5248 static const struct of_device_id dsi_of_match[] = {
5249 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, },
5250 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, },
5251 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, },
5252 {},
5253 };
5254
5255 static const struct soc_device_attribute dsi_soc_devices[] = {
5256 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx },
5257 { .machine = "AM35*", .data = &dsi_of_data_omap34xx },
5258 { /* sentinel */ }
5259 };
5260
5261 static int dsi_probe(struct platform_device *pdev)
5262 {
5263 const struct soc_device_attribute *soc;
5264 const struct dsi_module_id_data *d;
5265 struct device *dev = &pdev->dev;
5266 struct dsi_data *dsi;
5267 struct resource *dsi_mem;
5268 struct resource *res;
5269 unsigned int i;
5270 int r;
5271
5272 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
5273 if (!dsi)
5274 return -ENOMEM;
5275
5276 dsi->dev = dev;
5277 dev_set_drvdata(dev, dsi);
5278
5279 spin_lock_init(&dsi->irq_lock);
5280 spin_lock_init(&dsi->errors_lock);
5281 dsi->errors = 0;
5282
5283 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5284 spin_lock_init(&dsi->irq_stats_lock);
5285 dsi->irq_stats.last_reset = jiffies;
5286 #endif
5287
5288 mutex_init(&dsi->lock);
5289 sema_init(&dsi->bus_lock, 1);
5290
5291 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5292 dsi_framedone_timeout_work_callback);
5293
5294 #ifdef DSI_CATCH_MISSING_TE
5295 timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
5296 #endif
5297
5298 dsi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proto");
5299 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem);
5300 if (IS_ERR(dsi->proto_base))
5301 return PTR_ERR(dsi->proto_base);
5302
5303 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
5304 dsi->phy_base = devm_ioremap_resource(dev, res);
5305 if (IS_ERR(dsi->phy_base))
5306 return PTR_ERR(dsi->phy_base);
5307
5308 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
5309 dsi->pll_base = devm_ioremap_resource(dev, res);
5310 if (IS_ERR(dsi->pll_base))
5311 return PTR_ERR(dsi->pll_base);
5312
5313 dsi->irq = platform_get_irq(pdev, 0);
5314 if (dsi->irq < 0) {
5315 DSSERR("platform_get_irq failed\n");
5316 return -ENODEV;
5317 }
5318
5319 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler,
5320 IRQF_SHARED, dev_name(dev), dsi);
5321 if (r < 0) {
5322 DSSERR("request_irq failed\n");
5323 return r;
5324 }
5325
5326 dsi->vdds_dsi_reg = devm_regulator_get(dev, "vdd");
5327 if (IS_ERR(dsi->vdds_dsi_reg)) {
5328 if (PTR_ERR(dsi->vdds_dsi_reg) != -EPROBE_DEFER)
5329 DSSERR("can't get DSI VDD regulator\n");
5330 return PTR_ERR(dsi->vdds_dsi_reg);
5331 }
5332
5333 soc = soc_device_match(dsi_soc_devices);
5334 if (soc)
5335 dsi->data = soc->data;
5336 else
5337 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data;
5338
5339 d = dsi->data->modules;
5340 while (d->address != 0 && d->address != dsi_mem->start)
5341 d++;
5342
5343 if (d->address == 0) {
5344 DSSERR("unsupported DSI module\n");
5345 return -ENODEV;
5346 }
5347
5348 dsi->module_id = d->id;
5349
5350 if (dsi->data->model == DSI_MODEL_OMAP4 ||
5351 dsi->data->model == DSI_MODEL_OMAP5) {
5352 struct device_node *np;
5353
5354 /*
5355 * The OMAP4/5 display DT bindings don't reference the padconf
5356 * syscon. Our only option to retrieve it is to find it by name.
5357 */
5358 np = of_find_node_by_name(NULL,
5359 dsi->data->model == DSI_MODEL_OMAP4 ?
5360 "omap4_padconf_global" : "omap5_padconf_global");
5361 if (!np)
5362 return -ENODEV;
5363
5364 dsi->syscon = syscon_node_to_regmap(np);
5365 of_node_put(np);
5366 }
5367
5368 /* DSI VCs initialization */
5369 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5370 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5371 dsi->vc[i].dssdev = NULL;
5372 dsi->vc[i].vc_id = 0;
5373 }
5374
5375 r = dsi_get_clocks(dsi);
5376 if (r)
5377 return r;
5378
5379 pm_runtime_enable(dev);
5380
5381 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5382 * of data to 3 by default */
5383 if (dsi->data->quirks & DSI_QUIRK_GNQ) {
5384 dsi_runtime_get(dsi);
5385 /* NB_DATA_LANES */
5386 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9);
5387 dsi_runtime_put(dsi);
5388 } else {
5389 dsi->num_lanes_supported = 3;
5390 }
5391
5392 r = of_platform_populate(dev->of_node, NULL, NULL, dev);
5393 if (r) {
5394 DSSERR("Failed to populate DSI child devices: %d\n", r);
5395 goto err_pm_disable;
5396 }
5397
5398 r = dsi_init_output(dsi);
5399 if (r)
5400 goto err_of_depopulate;
5401
5402 r = dsi_probe_of(dsi);
5403 if (r) {
5404 DSSERR("Invalid DSI DT data\n");
5405 goto err_uninit_output;
5406 }
5407
5408 r = component_add(&pdev->dev, &dsi_component_ops);
5409 if (r)
5410 goto err_uninit_output;
5411
5412 return 0;
5413
5414 err_uninit_output:
5415 dsi_uninit_output(dsi);
5416 err_of_depopulate:
5417 of_platform_depopulate(dev);
5418 err_pm_disable:
5419 pm_runtime_disable(dev);
5420 return r;
5421 }
5422
5423 static int dsi_remove(struct platform_device *pdev)
5424 {
5425 struct dsi_data *dsi = platform_get_drvdata(pdev);
5426
5427 component_del(&pdev->dev, &dsi_component_ops);
5428
5429 dsi_uninit_output(dsi);
5430
5431 of_platform_depopulate(&pdev->dev);
5432
5433 pm_runtime_disable(&pdev->dev);
5434
5435 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5436 regulator_disable(dsi->vdds_dsi_reg);
5437 dsi->vdds_dsi_enabled = false;
5438 }
5439
5440 return 0;
5441 }
5442
5443 static int dsi_runtime_suspend(struct device *dev)
5444 {
5445 struct dsi_data *dsi = dev_get_drvdata(dev);
5446
5447 dsi->is_enabled = false;
5448 /* ensure the irq handler sees the is_enabled value */
5449 smp_wmb();
5450 /* wait for current handler to finish before turning the DSI off */
5451 synchronize_irq(dsi->irq);
5452
5453 return 0;
5454 }
5455
5456 static int dsi_runtime_resume(struct device *dev)
5457 {
5458 struct dsi_data *dsi = dev_get_drvdata(dev);
5459
5460 dsi->is_enabled = true;
5461 /* ensure the irq handler sees the is_enabled value */
5462 smp_wmb();
5463
5464 return 0;
5465 }
5466
5467 static const struct dev_pm_ops dsi_pm_ops = {
5468 .runtime_suspend = dsi_runtime_suspend,
5469 .runtime_resume = dsi_runtime_resume,
5470 };
5471
5472 struct platform_driver omap_dsihw_driver = {
5473 .probe = dsi_probe,
5474 .remove = dsi_remove,
5475 .driver = {
5476 .name = "omapdss_dsi",
5477 .pm = &dsi_pm_ops,
5478 .of_match_table = dsi_of_match,
5479 .suppress_bind_attrs = true,
5480 },
5481 };
Linux with added FPC-III support