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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / omapdrm / dss / hdmi5_core.c
blobff4d35c8771f09331457d33dd4d5a86ebda8c6b2
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * OMAP5 HDMI CORE IP driver library
4 *
5 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors:
7 * Yong Zhi
8 * Mythri pk
9 * Archit Taneja <archit@ti.com>
10 * Tomi Valkeinen <tomi.valkeinen@ti.com>
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/seq_file.h>
20 #include <drm/drm_edid.h>
21 #include <sound/asound.h>
22 #include <sound/asoundef.h>
23
24 #include "hdmi5_core.h"
25
26 static void hdmi_core_ddc_init(struct hdmi_core_data *core)
27 {
28 void __iomem *base = core->base;
29 const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
30 const unsigned int ss_scl_high = 4700; /* ns */
31 const unsigned int ss_scl_low = 5500; /* ns */
32 const unsigned int fs_scl_high = 600; /* ns */
33 const unsigned int fs_scl_low = 1300; /* ns */
34 const unsigned int sda_hold = 1000; /* ns */
35 const unsigned int sfr_div = 10;
36 unsigned long long sfr;
37 unsigned int v;
38
39 sfr = iclk / sfr_div; /* SFR_DIV */
40 sfr /= 1000; /* SFR clock in kHz */
41
42 /* Reset */
43 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
44 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
45 0, 0, 1) != 1)
46 DSSERR("HDMI I2CM reset failed\n");
47
48 /* Standard (0) or Fast (1) Mode */
49 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
50
51 /* Standard Mode SCL High counter */
52 v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
53 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
54 (v >> 8) & 0xff, 7, 0);
55 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
56 v & 0xff, 7, 0);
57
58 /* Standard Mode SCL Low counter */
59 v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
60 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
61 (v >> 8) & 0xff, 7, 0);
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
63 v & 0xff, 7, 0);
64
65 /* Fast Mode SCL High Counter */
66 v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
68 (v >> 8) & 0xff, 7, 0);
69 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
70 v & 0xff, 7, 0);
71
72 /* Fast Mode SCL Low Counter */
73 v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
74 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
75 (v >> 8) & 0xff, 7, 0);
76 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
77 v & 0xff, 7, 0);
78
79 /* SDA Hold Time */
80 v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
81 REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
82
83 REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
84 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
85
86 /* NACK_POL to high */
87 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
88
89 /* NACK_MASK to unmasked */
90 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
91
92 /* ARBITRATION_POL to high */
93 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
94
95 /* ARBITRATION_MASK to unmasked */
96 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
97
98 /* DONE_POL to high */
99 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
100
101 /* DONE_MASK to unmasked */
102 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
103 }
104
105 static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
106 {
107 void __iomem *base = core->base;
108
109 /* Mask I2C interrupts */
110 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
111 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
112 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
113 }
114
115 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
116 {
117 void __iomem *base = core->base;
118 u8 cur_addr;
119 char checksum = 0;
120 const int retries = 1000;
121 u8 seg_ptr = ext / 2;
122 u8 edidbase = ((ext % 2) * 0x80);
123
124 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
125
126 /*
127 * TODO: We use polling here, although we probably should use proper
128 * interrupts.
129 */
130 for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
131 int i;
132
133 /* clear ERROR and DONE */
134 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
135
136 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
137 edidbase + cur_addr, 7, 0);
138
139 if (seg_ptr)
140 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
141 else
142 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
143
144 for (i = 0; i < retries; ++i) {
145 u32 stat;
146
147 stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
148
149 /* I2CM_ERROR */
150 if (stat & 1) {
151 DSSERR("HDMI I2C Master Error\n");
152 return -EIO;
153 }
154
155 /* I2CM_DONE */
156 if (stat & (1 << 1))
157 break;
158
159 usleep_range(250, 1000);
160 }
161
162 if (i == retries) {
163 DSSERR("HDMI I2C timeout reading EDID\n");
164 return -EIO;
165 }
166
167 pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
168 checksum += pedid[cur_addr];
169 }
170
171 return 0;
172
173 }
174
175 int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
176 {
177 int r, n, i;
178 int max_ext_blocks = (len / 128) - 1;
179
180 if (len < 128)
181 return -EINVAL;
182
183 hdmi_core_ddc_init(core);
184
185 r = hdmi_core_ddc_edid(core, edid, 0);
186 if (r)
187 goto out;
188
189 n = edid[0x7e];
190
191 if (n > max_ext_blocks)
192 n = max_ext_blocks;
193
194 for (i = 1; i <= n; i++) {
195 r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
196 if (r)
197 goto out;
198 }
199
200 out:
201 hdmi_core_ddc_uninit(core);
202
203 return r ? r : len;
204 }
205
206 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
207 {
208
209 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
210 hdmi_read_reg(core->base, r))
211
212 DUMPCORE(HDMI_CORE_FC_INVIDCONF);
213 DUMPCORE(HDMI_CORE_FC_INHACTIV0);
214 DUMPCORE(HDMI_CORE_FC_INHACTIV1);
215 DUMPCORE(HDMI_CORE_FC_INHBLANK0);
216 DUMPCORE(HDMI_CORE_FC_INHBLANK1);
217 DUMPCORE(HDMI_CORE_FC_INVACTIV0);
218 DUMPCORE(HDMI_CORE_FC_INVACTIV1);
219 DUMPCORE(HDMI_CORE_FC_INVBLANK);
220 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
221 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
222 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
223 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
224 DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
225 DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
226 DUMPCORE(HDMI_CORE_FC_CTRLDUR);
227 DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
228 DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
229 DUMPCORE(HDMI_CORE_FC_CH0PREAM);
230 DUMPCORE(HDMI_CORE_FC_CH1PREAM);
231 DUMPCORE(HDMI_CORE_FC_CH2PREAM);
232 DUMPCORE(HDMI_CORE_FC_AVICONF0);
233 DUMPCORE(HDMI_CORE_FC_AVICONF1);
234 DUMPCORE(HDMI_CORE_FC_AVICONF2);
235 DUMPCORE(HDMI_CORE_FC_AVIVID);
236 DUMPCORE(HDMI_CORE_FC_PRCONF);
237
238 DUMPCORE(HDMI_CORE_MC_CLKDIS);
239 DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
240 DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
241 DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
242 DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
243
244 DUMPCORE(HDMI_CORE_I2CM_SLAVE);
245 DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
246 DUMPCORE(HDMI_CORE_I2CM_DATAO);
247 DUMPCORE(HDMI_CORE_I2CM_DATAI);
248 DUMPCORE(HDMI_CORE_I2CM_OPERATION);
249 DUMPCORE(HDMI_CORE_I2CM_INT);
250 DUMPCORE(HDMI_CORE_I2CM_CTLINT);
251 DUMPCORE(HDMI_CORE_I2CM_DIV);
252 DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
253 DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
254 DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
255 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
256 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
257 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
258 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
259 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
260 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
261 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
262 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
263 DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
264 }
265
266 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
267 const struct hdmi_config *cfg)
268 {
269 DSSDBG("hdmi_core_init\n");
270
271 video_cfg->v_fc_config.vm = cfg->vm;
272
273 /* video core */
274 video_cfg->data_enable_pol = 1; /* It is always 1*/
275 video_cfg->hblank = cfg->vm.hfront_porch +
276 cfg->vm.hback_porch + cfg->vm.hsync_len;
277 video_cfg->vblank_osc = 0;
278 video_cfg->vblank = cfg->vm.vsync_len + cfg->vm.vfront_porch +
279 cfg->vm.vback_porch;
280 video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
281
282 if (cfg->vm.flags & DISPLAY_FLAGS_INTERLACED) {
283 /* set vblank_osc if vblank is fractional */
284 if (video_cfg->vblank % 2 != 0)
285 video_cfg->vblank_osc = 1;
286
287 video_cfg->v_fc_config.vm.vactive /= 2;
288 video_cfg->vblank /= 2;
289 video_cfg->v_fc_config.vm.vfront_porch /= 2;
290 video_cfg->v_fc_config.vm.vsync_len /= 2;
291 video_cfg->v_fc_config.vm.vback_porch /= 2;
292 }
293
294 if (cfg->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
295 video_cfg->v_fc_config.vm.hactive *= 2;
296 video_cfg->hblank *= 2;
297 video_cfg->v_fc_config.vm.hfront_porch *= 2;
298 video_cfg->v_fc_config.vm.hsync_len *= 2;
299 video_cfg->v_fc_config.vm.hback_porch *= 2;
300 }
301 }
302
303 /* DSS_HDMI_CORE_VIDEO_CONFIG */
304 static void hdmi_core_video_config(struct hdmi_core_data *core,
305 const struct hdmi_core_vid_config *cfg)
306 {
307 void __iomem *base = core->base;
308 const struct videomode *vm = &cfg->v_fc_config.vm;
309 unsigned char r = 0;
310 bool vsync_pol, hsync_pol;
311
312 vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
313 hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
314
315 /* Set hsync, vsync and data-enable polarity */
316 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
317 r = FLD_MOD(r, vsync_pol, 6, 6);
318 r = FLD_MOD(r, hsync_pol, 5, 5);
319 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
320 r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
321 r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 0, 0);
322 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
323
324 /* set x resolution */
325 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, vm->hactive >> 8, 4, 0);
326 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, vm->hactive & 0xFF, 7, 0);
327
328 /* set y resolution */
329 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, vm->vactive >> 8, 4, 0);
330 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, vm->vactive & 0xFF, 7, 0);
331
332 /* set horizontal blanking pixels */
333 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
334 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
335
336 /* set vertial blanking pixels */
337 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
338
339 /* set horizontal sync offset */
340 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, vm->hfront_porch >> 8,
341 4, 0);
342 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, vm->hfront_porch & 0xFF,
343 7, 0);
344
345 /* set vertical sync offset */
346 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, vm->vfront_porch, 7, 0);
347
348 /* set horizontal sync pulse width */
349 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (vm->hsync_len >> 8),
350 1, 0);
351 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, vm->hsync_len & 0xFF,
352 7, 0);
353
354 /* set vertical sync pulse width */
355 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, vm->vsync_len, 5, 0);
356
357 /* select DVI mode */
358 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
359 cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
360
361 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
362 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4);
363 else
364 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4);
365 }
366
367 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
368 {
369 void __iomem *base = core->base;
370 int clr_depth = 0; /* 24 bit color depth */
371
372 /* COLOR_DEPTH */
373 REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
374 /* BYPASS_EN */
375 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
376 /* PP_EN */
377 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
378 /* YCC422_EN */
379 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
380 /* PP_STUFFING */
381 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
382 /* YCC422_STUFFING */
383 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
384 /* OUTPUT_SELECTOR */
385 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
386 }
387
388 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
389 {
390 int video_mapping = 1; /* for 24 bit color depth */
391
392 /* VIDEO_MAPPING */
393 REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
394 }
395
396 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
397 struct hdmi_avi_infoframe *frame)
398 {
399 void __iomem *base = core->base;
400 u8 data[HDMI_INFOFRAME_SIZE(AVI)];
401 u8 *ptr;
402 unsigned int y, a, b, s;
403 unsigned int c, m, r;
404 unsigned int itc, ec, q, sc;
405 unsigned int vic;
406 unsigned int yq, cn, pr;
407
408 hdmi_avi_infoframe_pack(frame, data, sizeof(data));
409
410 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
411 HDMI_INFOFRAME_SIZE(AVI), false);
412
413 ptr = data + HDMI_INFOFRAME_HEADER_SIZE;
414
415 y = (ptr[0] >> 5) & 0x3;
416 a = (ptr[0] >> 4) & 0x1;
417 b = (ptr[0] >> 2) & 0x3;
418 s = (ptr[0] >> 0) & 0x3;
419
420 c = (ptr[1] >> 6) & 0x3;
421 m = (ptr[1] >> 4) & 0x3;
422 r = (ptr[1] >> 0) & 0xf;
423
424 itc = (ptr[2] >> 7) & 0x1;
425 ec = (ptr[2] >> 4) & 0x7;
426 q = (ptr[2] >> 2) & 0x3;
427 sc = (ptr[2] >> 0) & 0x3;
428
429 vic = ptr[3];
430
431 yq = (ptr[4] >> 6) & 0x3;
432 cn = (ptr[4] >> 4) & 0x3;
433 pr = (ptr[4] >> 0) & 0xf;
434
435 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0,
436 (a << 6) | (s << 4) | (b << 2) | (y << 0));
437
438 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1,
439 (c << 6) | (m << 4) | (r << 0));
440
441 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2,
442 (itc << 7) | (ec << 4) | (q << 2) | (sc << 0));
443
444 hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);
445
446 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3,
447 (yq << 2) | (cn << 0));
448
449 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
450 }
451
452 static void hdmi_core_write_csc(struct hdmi_core_data *core,
453 const struct csc_table *csc_coeff)
454 {
455 void __iomem *base = core->base;
456
457 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff->a1 >> 8, 6, 0);
458 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff->a1, 7, 0);
459 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff->a2 >> 8, 6, 0);
460 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff->a2, 7, 0);
461 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff->a3 >> 8, 6, 0);
462 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff->a3, 7, 0);
463 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff->a4 >> 8, 6, 0);
464 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff->a4, 7, 0);
465 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff->b1 >> 8, 6, 0);
466 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff->b1, 7, 0);
467 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff->b2 >> 8, 6, 0);
468 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff->b2, 7, 0);
469 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff->b3 >> 8, 6, 0);
470 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff->b3, 7, 0);
471 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff->b4 >> 8, 6, 0);
472 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff->b4, 7, 0);
473 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff->c1 >> 8, 6, 0);
474 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff->c1, 7, 0);
475 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff->c2 >> 8, 6, 0);
476 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff->c2, 7, 0);
477 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff->c3 >> 8, 6, 0);
478 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff->c3, 7, 0);
479 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff->c4 >> 8, 6, 0);
480 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff->c4, 7, 0);
481
482 /* enable CSC */
483 REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
484 }
485
486 static void hdmi_core_configure_range(struct hdmi_core_data *core,
487 enum hdmi_quantization_range range)
488 {
489 static const struct csc_table csc_limited_range = {
490 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32
491 };
492 static const struct csc_table csc_full_range = {
493 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0
494 };
495 const struct csc_table *csc_coeff;
496
497 /* CSC_COLORDEPTH = 24 bits*/
498 REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, 0, 7, 4);
499
500 switch (range) {
501 case HDMI_QUANTIZATION_RANGE_FULL:
502 csc_coeff = &csc_full_range;
503 break;
504
505 case HDMI_QUANTIZATION_RANGE_DEFAULT:
506 case HDMI_QUANTIZATION_RANGE_LIMITED:
507 default:
508 csc_coeff = &csc_limited_range;
509 break;
510 }
511
512 hdmi_core_write_csc(core, csc_coeff);
513 }
514
515 static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
516 {
517 void __iomem *base = core->base;
518
519 DSSDBG("hdmi_core_enable_video_path\n");
520
521 REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
522 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
523 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
524 REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
525 REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
526 REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
527 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
528 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
529 }
530
531 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
532 {
533 void __iomem *base = core->base;
534
535 /* Master IRQ mask */
536 REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
537
538 /* Mask all the interrupts in HDMI core */
539
540 REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
541 REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
542 REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
543 REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
544
545 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
546 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
547
548 REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
549
550 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
551 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
552 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
553
554 REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
555
556 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
557
558 /* Clear all the current interrupt bits */
559
560 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
561 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
562 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
563 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
564
565 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
566
567 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
568
569 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
570
571 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
572 }
573
574 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
575 {
576 /* Unmute interrupts */
577 REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
578 }
579
580 int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
581 {
582 void __iomem *base = core->base;
583
584 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
585 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
586 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
587 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
588 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
589 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
590 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
591 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
592 REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
593
594 return 0;
595 }
596
597 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
598 struct hdmi_config *cfg)
599 {
600 struct videomode vm;
601 struct hdmi_video_format video_format;
602 struct hdmi_core_vid_config v_core_cfg;
603 enum hdmi_quantization_range range;
604
605 hdmi_core_mask_interrupts(core);
606
607 if (cfg->hdmi_dvi_mode == HDMI_HDMI) {
608 char vic = cfg->infoframe.video_code;
609
610 /* All CEA modes other than VIC 1 use limited quantization range. */
611 range = vic > 1 ? HDMI_QUANTIZATION_RANGE_LIMITED :
612 HDMI_QUANTIZATION_RANGE_FULL;
613 } else {
614 range = HDMI_QUANTIZATION_RANGE_FULL;
615 }
616
617 hdmi_core_init(&v_core_cfg, cfg);
618
619 hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
620
621 hdmi_wp_video_config_timing(wp, &vm);
622
623 /* video config */
624 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
625
626 hdmi_wp_video_config_format(wp, &video_format);
627
628 hdmi_wp_video_config_interface(wp, &vm);
629
630 hdmi_core_configure_range(core, range);
631 cfg->infoframe.quantization_range = range;
632
633 /*
634 * configure core video part, set software reset in the core
635 */
636 v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
637
638 hdmi_core_video_config(core, &v_core_cfg);
639
640 hdmi_core_config_video_packetizer(core);
641 hdmi_core_config_video_sampler(core);
642
643 if (cfg->hdmi_dvi_mode == HDMI_HDMI)
644 hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
645
646 hdmi_core_enable_video_path(core);
647
648 hdmi_core_enable_interrupts(core);
649 }
650
651 static void hdmi5_core_audio_config(struct hdmi_core_data *core,
652 struct hdmi_core_audio_config *cfg)
653 {
654 void __iomem *base = core->base;
655 u8 val;
656
657 /* Mute audio before configuring */
658 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
659
660 /* Set the N parameter */
661 REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
662 REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
663 REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
664
665 /*
666 * CTS manual mode. Automatic mode is not supported when using audio
667 * parallel interface.
668 */
669 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
670 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
671 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
672 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
673
674 /* Layout of Audio Sample Packets: 2-channel or multichannels */
675 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
676 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
677 else
678 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
679
680 /* Configure IEC-609580 Validity bits */
681 /* Channel 0 is valid */
682 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
683 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
684
685 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
686 val = 1;
687 else
688 val = 0;
689
690 /* Channels 1, 2 setting */
691 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
692 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
693 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
694 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
695 /* Channel 3 setting */
696 if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
697 val = 1;
698 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
699 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
700
701 /* Configure IEC-60958 User bits */
702 /* TODO: should be set by user. */
703 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
704
705 /* Configure IEC-60958 Channel Status word */
706 /* CGMSA */
707 val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
708 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
709
710 /* Copyright */
711 val = (cfg->iec60958_cfg->status[0] &
712 IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
713 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
714
715 /* Category */
716 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
717 cfg->iec60958_cfg->status[1]);
718
719 /* PCM audio mode */
720 val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
721 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
722
723 /* Source number */
724 val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
725 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0);
726
727 /* Channel number right 0 */
728 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
729 /* Channel number right 1*/
730 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
731 /* Channel number right 2 */
732 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
733 /* Channel number right 3*/
734 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
735 /* Channel number left 0 */
736 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
737 /* Channel number left 1*/
738 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
739 /* Channel number left 2 */
740 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
741 /* Channel number left 3*/
742 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
743
744 /* Clock accuracy and sample rate */
745 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
746 cfg->iec60958_cfg->status[3]);
747
748 /* Original sample rate and word length */
749 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
750 cfg->iec60958_cfg->status[4]);
751
752 /* Enable FIFO empty and full interrupts */
753 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
754
755 /* Configure GPA */
756 /* select HBR/SPDIF interfaces */
757 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
758 /* select HBR/SPDIF interfaces */
759 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
760 /* enable two channels in GPA */
761 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
762 } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
763 /* select HBR/SPDIF interfaces */
764 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
765 /* enable six channels in GPA */
766 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
767 } else {
768 /* select HBR/SPDIF interfaces */
769 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
770 /* enable eight channels in GPA */
771 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
772 }
773
774 /* disable HBR */
775 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
776 /* enable PCUV */
777 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
778 /* enable GPA FIFO full and empty mask */
779 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
780 /* set polarity of GPA FIFO empty interrupts */
781 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
782
783 /* unmute audio */
784 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
785 }
786
787 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
788 struct snd_cea_861_aud_if *info_aud)
789 {
790 void __iomem *base = core->base;
791
792 /* channel count and coding type fields in AUDICONF0 are swapped */
793 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
794 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
795 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
796
797 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
798 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
799 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3,
800 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 |
801 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV));
802 }
803
804 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
805 struct omap_dss_audio *audio, u32 pclk)
806 {
807 struct hdmi_audio_format audio_format;
808 struct hdmi_audio_dma audio_dma;
809 struct hdmi_core_audio_config core_cfg;
810 int n, cts, channel_count;
811 unsigned int fs_nr;
812 bool word_length_16b = false;
813
814 if (!audio || !audio->iec || !audio->cea || !core)
815 return -EINVAL;
816
817 core_cfg.iec60958_cfg = audio->iec;
818
819 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
820 (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
821 word_length_16b = true;
822
823 /* only 16-bit word length supported atm */
824 if (!word_length_16b)
825 return -EINVAL;
826
827 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
828 case IEC958_AES3_CON_FS_32000:
829 fs_nr = 32000;
830 break;
831 case IEC958_AES3_CON_FS_44100:
832 fs_nr = 44100;
833 break;
834 case IEC958_AES3_CON_FS_48000:
835 fs_nr = 48000;
836 break;
837 case IEC958_AES3_CON_FS_88200:
838 fs_nr = 88200;
839 break;
840 case IEC958_AES3_CON_FS_96000:
841 fs_nr = 96000;
842 break;
843 case IEC958_AES3_CON_FS_176400:
844 fs_nr = 176400;
845 break;
846 case IEC958_AES3_CON_FS_192000:
847 fs_nr = 192000;
848 break;
849 default:
850 return -EINVAL;
851 }
852
853 hdmi_compute_acr(pclk, fs_nr, &n, &cts);
854 core_cfg.n = n;
855 core_cfg.cts = cts;
856
857 /* Audio channels settings */
858 channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
859 + 1;
860
861 if (channel_count == 2)
862 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
863 else if (channel_count == 6)
864 core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
865 else
866 core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
867
868 /* DMA settings */
869 if (word_length_16b)
870 audio_dma.transfer_size = 0x10;
871 else
872 audio_dma.transfer_size = 0x20;
873 audio_dma.block_size = 0xC0;
874 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
875 audio_dma.fifo_threshold = 0x20; /* in number of samples */
876
877 /* audio FIFO format settings for 16-bit samples*/
878 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
879 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
880 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
881 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
882
883 /* only LPCM atm */
884 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
885
886 /* only allowed option */
887 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
888
889 /* disable start/stop signals of IEC 60958 blocks */
890 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
891
892 /* configure DMA and audio FIFO format*/
893 hdmi_wp_audio_config_dma(wp, &audio_dma);
894 hdmi_wp_audio_config_format(wp, &audio_format);
895
896 /* configure the core */
897 hdmi5_core_audio_config(core, &core_cfg);
898
899 /* configure CEA 861 audio infoframe */
900 hdmi5_core_audio_infoframe_cfg(core, audio->cea);
901
902 return 0;
903 }
904
905 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
906 {
907 struct resource *res;
908
909 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
910 core->base = devm_ioremap_resource(&pdev->dev, res);
911 if (IS_ERR(core->base))
912 return PTR_ERR(core->base);
913
914 return 0;
915 }
Linux with added FPC-III support