drivers/gpu/drm/rcar-du/rcar_lvds.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * rcar_lvds.c  --  R-Car LVDS Encoder
   4  *
   5  * Copyright (C) 2013-2018 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_graph.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/sys_soc.h>
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_bridge.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drm_probe_helper.h>
  27
  28 #include "rcar_lvds.h"
  29 #include "rcar_lvds_regs.h"
  30
  31 struct rcar_lvds;
  32
  33 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
  34 enum rcar_lvds_mode {
  35         RCAR_LVDS_MODE_JEIDA = 0,
  36         RCAR_LVDS_MODE_MIRROR = 1,
  37         RCAR_LVDS_MODE_VESA = 4,
  38 };
  39
  40 enum rcar_lvds_link_type {
  41         RCAR_LVDS_SINGLE_LINK = 0,
  42         RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS = 1,
  43         RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS = 2,
  44 };
  45
  46 #define RCAR_LVDS_QUIRK_LANES           BIT(0)  /* LVDS lanes 1 and 3 inverted */
  47 #define RCAR_LVDS_QUIRK_GEN3_LVEN       BIT(1)  /* LVEN bit needs to be set on R8A77970/R8A7799x */
  48 #define RCAR_LVDS_QUIRK_PWD             BIT(2)  /* PWD bit available (all of Gen3 but E3) */
  49 #define RCAR_LVDS_QUIRK_EXT_PLL         BIT(3)  /* Has extended PLL */
  50 #define RCAR_LVDS_QUIRK_DUAL_LINK       BIT(4)  /* Supports dual-link operation */
  51
  52 struct rcar_lvds_device_info {
  53         unsigned int gen;
  54         unsigned int quirks;
  55         void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
  56 };
  57
  58 struct rcar_lvds {
  59         struct device *dev;
  60         const struct rcar_lvds_device_info *info;
  61
  62         struct drm_bridge bridge;
  63
  64         struct drm_bridge *next_bridge;
  65         struct drm_connector connector;
  66         struct drm_panel *panel;
  67
  68         void __iomem *mmio;
  69         struct {
  70                 struct clk *mod;                /* CPG module clock */
  71                 struct clk *extal;              /* External clock */
  72                 struct clk *dotclkin[2];        /* External DU clocks */
  73         } clocks;
  74
  75         struct drm_bridge *companion;
  76         enum rcar_lvds_link_type link_type;
  77 };
  78
  79 #define bridge_to_rcar_lvds(b) \
  80         container_of(b, struct rcar_lvds, bridge)
  81
  82 #define connector_to_rcar_lvds(c) \
  83         container_of(c, struct rcar_lvds, connector)
  84
  85 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
  86 {
  87         iowrite32(data, lvds->mmio + reg);
  88 }
  89
  90 /* -----------------------------------------------------------------------------
  91  * Connector & Panel
  92  */
  93
  94 static int rcar_lvds_connector_get_modes(struct drm_connector *connector)
  95 {
  96         struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
  97
  98         return drm_panel_get_modes(lvds->panel, connector);
  99 }
 100
 101 static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
 102                                             struct drm_atomic_state *state)
 103 {
 104         struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
 105         const struct drm_display_mode *panel_mode;
 106         struct drm_connector_state *conn_state;
 107         struct drm_crtc_state *crtc_state;
 108
 109         conn_state = drm_atomic_get_new_connector_state(state, connector);
 110         if (!conn_state->crtc)
 111                 return 0;
 112
 113         if (list_empty(&connector->modes)) {
 114                 dev_dbg(lvds->dev, "connector: empty modes list\n");
 115                 return -EINVAL;
 116         }
 117
 118         panel_mode = list_first_entry(&connector->modes,
 119                                       struct drm_display_mode, head);
 120
 121         /* We're not allowed to modify the resolution. */
 122         crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
 123         if (IS_ERR(crtc_state))
 124                 return PTR_ERR(crtc_state);
 125
 126         if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||
 127             crtc_state->mode.vdisplay != panel_mode->vdisplay)
 128                 return -EINVAL;
 129
 130         /* The flat panel mode is fixed, just copy it to the adjusted mode. */
 131         drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);
 132
 133         return 0;
 134 }
 135
 136 static const struct drm_connector_helper_funcs rcar_lvds_conn_helper_funcs = {
 137         .get_modes = rcar_lvds_connector_get_modes,
 138         .atomic_check = rcar_lvds_connector_atomic_check,
 139 };
 140
 141 static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
 142         .reset = drm_atomic_helper_connector_reset,
 143         .fill_modes = drm_helper_probe_single_connector_modes,
 144         .destroy = drm_connector_cleanup,
 145         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 146         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 147 };
 148
 149 /* -----------------------------------------------------------------------------
 150  * PLL Setup
 151  */
 152
 153 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
 154 {
 155         u32 val;
 156
 157         if (freq < 39000000)
 158                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
 159         else if (freq < 61000000)
 160                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
 161         else if (freq < 121000000)
 162                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
 163         else
 164                 val = LVDPLLCR_PLLDLYCNT_150M;
 165
 166         rcar_lvds_write(lvds, LVDPLLCR, val);
 167 }
 168
 169 static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
 170 {
 171         u32 val;
 172
 173         if (freq < 42000000)
 174                 val = LVDPLLCR_PLLDIVCNT_42M;
 175         else if (freq < 85000000)
 176                 val = LVDPLLCR_PLLDIVCNT_85M;
 177         else if (freq < 128000000)
 178                 val = LVDPLLCR_PLLDIVCNT_128M;
 179         else
 180                 val = LVDPLLCR_PLLDIVCNT_148M;
 181
 182         rcar_lvds_write(lvds, LVDPLLCR, val);
 183 }
 184
 185 struct pll_info {
 186         unsigned long diff;
 187         unsigned int pll_m;
 188         unsigned int pll_n;
 189         unsigned int pll_e;
 190         unsigned int div;
 191         u32 clksel;
 192 };
 193
 194 static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
 195                                      unsigned long target, struct pll_info *pll,
 196                                      u32 clksel, bool dot_clock_only)
 197 {
 198         unsigned int div7 = dot_clock_only ? 1 : 7;
 199         unsigned long output;
 200         unsigned long fin;
 201         unsigned int m_min;
 202         unsigned int m_max;
 203         unsigned int m;
 204         int error;
 205
 206         if (!clk)
 207                 return;
 208
 209         /*
 210          * The LVDS PLL is made of a pre-divider and a multiplier (strangely
 211          * enough called M and N respectively), followed by a post-divider E.
 212          *
 213          *         ,-----.         ,-----.     ,-----.         ,-----.
 214          * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
 215          *         `-----'     ,-> |     |     `-----'   |     `-----'
 216          *                     |   `-----'               |
 217          *                     |         ,-----.         |
 218          *                     `-------- | 1/N | <-------'
 219          *                               `-----'
 220          *
 221          * The clock output by the PLL is then further divided by a programmable
 222          * divider DIV to achieve the desired target frequency. Finally, an
 223          * optional fixed /7 divider is used to convert the bit clock to a pixel
 224          * clock (as LVDS transmits 7 bits per lane per clock sample).
 225          *
 226          *          ,-------.     ,-----.     |\
 227          * Fout --> | 1/DIV | --> | 1/7 | --> | |
 228          *          `-------'  |  `-----'     | | --> dot clock
 229          *                     `------------> | |
 230          *                                    |/
 231          *
 232          * The /7 divider is optional, it is enabled when the LVDS PLL is used
 233          * to drive the LVDS encoder, and disabled when  used to generate a dot
 234          * clock for the DU RGB output, without using the LVDS encoder.
 235          *
 236          * The PLL allowed input frequency range is 12 MHz to 192 MHz.
 237          */
 238
 239         fin = clk_get_rate(clk);
 240         if (fin < 12000000 || fin > 192000000)
 241                 return;
 242
 243         /*
 244          * The comparison frequency range is 12 MHz to 24 MHz, which limits the
 245          * allowed values for the pre-divider M (normal range 1-8).
 246          *
 247          * Fpfd = Fin / M
 248          */
 249         m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
 250         m_max = min_t(unsigned int, 8, fin / 12000000);
 251
 252         for (m = m_min; m <= m_max; ++m) {
 253                 unsigned long fpfd;
 254                 unsigned int n_min;
 255                 unsigned int n_max;
 256                 unsigned int n;
 257
 258                 /*
 259                  * The VCO operating range is 900 Mhz to 1800 MHz, which limits
 260                  * the allowed values for the multiplier N (normal range
 261                  * 60-120).
 262                  *
 263                  * Fvco = Fin * N / M
 264                  */
 265                 fpfd = fin / m;
 266                 n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
 267                 n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
 268
 269                 for (n = n_min; n < n_max; ++n) {
 270                         unsigned long fvco;
 271                         unsigned int e_min;
 272                         unsigned int e;
 273
 274                         /*
 275                          * The output frequency is limited to 1039.5 MHz,
 276                          * limiting again the allowed values for the
 277                          * post-divider E (normal value 1, 2 or 4).
 278                          *
 279                          * Fout = Fvco / E
 280                          */
 281                         fvco = fpfd * n;
 282                         e_min = fvco > 1039500000 ? 1 : 0;
 283
 284                         for (e = e_min; e < 3; ++e) {
 285                                 unsigned long fout;
 286                                 unsigned long diff;
 287                                 unsigned int div;
 288
 289                                 /*
 290                                  * Finally we have a programable divider after
 291                                  * the PLL, followed by a an optional fixed /7
 292                                  * divider.
 293                                  */
 294                                 fout = fvco / (1 << e) / div7;
 295                                 div = max(1UL, DIV_ROUND_CLOSEST(fout, target));
 296                                 diff = abs(fout / div - target);
 297
 298                                 if (diff < pll->diff) {
 299                                         pll->diff = diff;
 300                                         pll->pll_m = m;
 301                                         pll->pll_n = n;
 302                                         pll->pll_e = e;
 303                                         pll->div = div;
 304                                         pll->clksel = clksel;
 305
 306                                         if (diff == 0)
 307                                                 goto done;
 308                                 }
 309                         }
 310                 }
 311         }
 312
 313 done:
 314         output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
 315                / div7 / pll->div;
 316         error = (long)(output - target) * 10000 / (long)target;
 317
 318         dev_dbg(lvds->dev,
 319                 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
 320                 clk, fin, output, target, error / 100,
 321                 error < 0 ? -error % 100 : error % 100,
 322                 pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
 323 }
 324
 325 static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
 326                                         unsigned int freq, bool dot_clock_only)
 327 {
 328         struct pll_info pll = { .diff = (unsigned long)-1 };
 329         u32 lvdpllcr;
 330
 331         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
 332                                  LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only);
 333         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
 334                                  LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only);
 335         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
 336                                  LVDPLLCR_CKSEL_EXTAL, dot_clock_only);
 337
 338         lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
 339                  | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
 340
 341         if (pll.pll_e > 0)
 342                 lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
 343                          |  LVDPLLCR_PLLE(pll.pll_e - 1);
 344
 345         if (dot_clock_only)
 346                 lvdpllcr |= LVDPLLCR_OCKSEL;
 347
 348         rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
 349
 350         if (pll.div > 1)
 351                 /*
 352                  * The DIVRESET bit is a misnomer, setting it to 1 deasserts the
 353                  * divisor reset.
 354                  */
 355                 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
 356                                 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
 357         else
 358                 rcar_lvds_write(lvds, LVDDIV, 0);
 359 }
 360
 361 static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
 362 {
 363         __rcar_lvds_pll_setup_d3_e3(lvds, freq, false);
 364 }
 365
 366 /* -----------------------------------------------------------------------------
 367  * Clock - D3/E3 only
 368  */
 369
 370 int rcar_lvds_clk_enable(struct drm_bridge *bridge, unsigned long freq)
 371 {
 372         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 373         int ret;
 374
 375         if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
 376                 return -ENODEV;
 377
 378         dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
 379
 380         ret = clk_prepare_enable(lvds->clocks.mod);
 381         if (ret < 0)
 382                 return ret;
 383
 384         __rcar_lvds_pll_setup_d3_e3(lvds, freq, true);
 385
 386         return 0;
 387 }
 388 EXPORT_SYMBOL_GPL(rcar_lvds_clk_enable);
 389
 390 void rcar_lvds_clk_disable(struct drm_bridge *bridge)
 391 {
 392         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 393
 394         if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
 395                 return;
 396
 397         dev_dbg(lvds->dev, "disabling LVDS PLL\n");
 398
 399         rcar_lvds_write(lvds, LVDPLLCR, 0);
 400
 401         clk_disable_unprepare(lvds->clocks.mod);
 402 }
 403 EXPORT_SYMBOL_GPL(rcar_lvds_clk_disable);
 404
 405 /* -----------------------------------------------------------------------------
 406  * Bridge
 407  */
 408
 409 static enum rcar_lvds_mode rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds,
 410                                         const struct drm_connector *connector)
 411 {
 412         const struct drm_display_info *info;
 413         enum rcar_lvds_mode mode;
 414
 415         /*
 416          * There is no API yet to retrieve LVDS mode from a bridge, only panels
 417          * are supported.
 418          */
 419         if (!lvds->panel)
 420                 return RCAR_LVDS_MODE_JEIDA;
 421
 422         info = &connector->display_info;
 423         if (!info->num_bus_formats || !info->bus_formats) {
 424                 dev_warn(lvds->dev,
 425                          "no LVDS bus format reported, using JEIDA\n");
 426                 return RCAR_LVDS_MODE_JEIDA;
 427         }
 428
 429         switch (info->bus_formats[0]) {
 430         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 431         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
 432                 mode = RCAR_LVDS_MODE_JEIDA;
 433                 break;
 434         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
 435                 mode = RCAR_LVDS_MODE_VESA;
 436                 break;
 437         default:
 438                 dev_warn(lvds->dev,
 439                          "unsupported LVDS bus format 0x%04x, using JEIDA\n",
 440                          info->bus_formats[0]);
 441                 return RCAR_LVDS_MODE_JEIDA;
 442         }
 443
 444         if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
 445                 mode |= RCAR_LVDS_MODE_MIRROR;
 446
 447         return mode;
 448 }
 449
 450 static void __rcar_lvds_atomic_enable(struct drm_bridge *bridge,
 451                                       struct drm_atomic_state *state,
 452                                       struct drm_crtc *crtc,
 453                                       struct drm_connector *connector)
 454 {
 455         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 456         u32 lvdhcr;
 457         u32 lvdcr0;
 458         int ret;
 459
 460         ret = clk_prepare_enable(lvds->clocks.mod);
 461         if (ret < 0)
 462                 return;
 463
 464         /* Enable the companion LVDS encoder in dual-link mode. */
 465         if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
 466                 __rcar_lvds_atomic_enable(lvds->companion, state, crtc,
 467                                           connector);
 468
 469         /*
 470          * Hardcode the channels and control signals routing for now.
 471          *
 472          * HSYNC -> CTRL0
 473          * VSYNC -> CTRL1
 474          * DISP  -> CTRL2
 475          * 0     -> CTRL3
 476          */
 477         rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
 478                         LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
 479                         LVDCTRCR_CTR0SEL_HSYNC);
 480
 481         if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
 482                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
 483                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
 484         else
 485                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
 486                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
 487
 488         rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
 489
 490         if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
 491                 u32 lvdstripe = 0;
 492
 493                 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK) {
 494                         /*
 495                          * By default we generate even pixels from the primary
 496                          * encoder and odd pixels from the companion encoder.
 497                          * Swap pixels around if the sink requires odd pixels
 498                          * from the primary encoder and even pixels from the
 499                          * companion encoder.
 500                          */
 501                         bool swap_pixels = lvds->link_type ==
 502                                 RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
 503
 504                         /*
 505                          * Configure vertical stripe since we are dealing with
 506                          * an LVDS dual-link connection.
 507                          *
 508                          * ST_SWAP is reserved for the companion encoder, only
 509                          * set it in the primary encoder.
 510                          */
 511                         lvdstripe = LVDSTRIPE_ST_ON
 512                                   | (lvds->companion && swap_pixels ?
 513                                      LVDSTRIPE_ST_SWAP : 0);
 514                 }
 515                 rcar_lvds_write(lvds, LVDSTRIPE, lvdstripe);
 516         }
 517
 518         /*
 519          * PLL clock configuration on all instances but the companion in
 520          * dual-link mode.
 521          */
 522         if (lvds->link_type == RCAR_LVDS_SINGLE_LINK || lvds->companion) {
 523                 const struct drm_crtc_state *crtc_state =
 524                         drm_atomic_get_new_crtc_state(state, crtc);
 525                 const struct drm_display_mode *mode =
 526                         &crtc_state->adjusted_mode;
 527
 528                 lvds->info->pll_setup(lvds, mode->clock * 1000);
 529         }
 530
 531         /* Set the LVDS mode and select the input. */
 532         lvdcr0 = rcar_lvds_get_lvds_mode(lvds, connector) << LVDCR0_LVMD_SHIFT;
 533
 534         if (lvds->bridge.encoder) {
 535                 if (drm_crtc_index(crtc) == 2)
 536                         lvdcr0 |= LVDCR0_DUSEL;
 537         }
 538
 539         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 540
 541         /* Turn all the channels on. */
 542         rcar_lvds_write(lvds, LVDCR1,
 543                         LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
 544                         LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
 545
 546         if (lvds->info->gen < 3) {
 547                 /* Enable LVDS operation and turn the bias circuitry on. */
 548                 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
 549                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 550         }
 551
 552         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
 553                 /*
 554                  * Turn the PLL on (simple PLL only, extended PLL is fully
 555                  * controlled through LVDPLLCR).
 556                  */
 557                 lvdcr0 |= LVDCR0_PLLON;
 558                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 559         }
 560
 561         if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
 562                 /* Set LVDS normal mode. */
 563                 lvdcr0 |= LVDCR0_PWD;
 564                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 565         }
 566
 567         if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
 568                 /*
 569                  * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
 570                  * set at the same time, so don't write the register yet.
 571                  */
 572                 lvdcr0 |= LVDCR0_LVEN;
 573                 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
 574                         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 575         }
 576
 577         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
 578                 /* Wait for the PLL startup delay (simple PLL only). */
 579                 usleep_range(100, 150);
 580         }
 581
 582         /* Turn the output on. */
 583         lvdcr0 |= LVDCR0_LVRES;
 584         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 585
 586         if (lvds->panel) {
 587                 drm_panel_prepare(lvds->panel);
 588                 drm_panel_enable(lvds->panel);
 589         }
 590 }
 591
 592 static void rcar_lvds_atomic_enable(struct drm_bridge *bridge,
 593                                     struct drm_atomic_state *state)
 594 {
 595         struct drm_connector *connector;
 596         struct drm_crtc *crtc;
 597
 598         connector = drm_atomic_get_new_connector_for_encoder(state,
 599                                                              bridge->encoder);
 600         crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
 601
 602         __rcar_lvds_atomic_enable(bridge, state, crtc, connector);
 603 }
 604
 605 static void rcar_lvds_atomic_disable(struct drm_bridge *bridge,
 606                                      struct drm_atomic_state *state)
 607 {
 608         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 609
 610         if (lvds->panel) {
 611                 drm_panel_disable(lvds->panel);
 612                 drm_panel_unprepare(lvds->panel);
 613         }
 614
 615         rcar_lvds_write(lvds, LVDCR0, 0);
 616         rcar_lvds_write(lvds, LVDCR1, 0);
 617         rcar_lvds_write(lvds, LVDPLLCR, 0);
 618
 619         /* Disable the companion LVDS encoder in dual-link mode. */
 620         if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
 621                 lvds->companion->funcs->atomic_disable(lvds->companion, state);
 622
 623         clk_disable_unprepare(lvds->clocks.mod);
 624 }
 625
 626 static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
 627                                  const struct drm_display_mode *mode,
 628                                  struct drm_display_mode *adjusted_mode)
 629 {
 630         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 631         int min_freq;
 632
 633         /*
 634          * The internal LVDS encoder has a restricted clock frequency operating
 635          * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
 636          * 148.5MHz on all other platforms. Clamp the clock accordingly.
 637          */
 638         min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
 639         adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
 640
 641         return true;
 642 }
 643
 644 static int rcar_lvds_attach(struct drm_bridge *bridge)
 645 {
 646         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 647         struct drm_connector *connector = &lvds->connector;
 648         struct drm_encoder *encoder = bridge->encoder;
 649         int ret;
 650
 651         /* If we have a next bridge just attach it. */
 652         if (lvds->next_bridge)
 653                 return drm_bridge_attach(bridge->encoder, lvds->next_bridge,
 654                                          bridge);
 655
 656         /* Otherwise if we have a panel, create a connector. */
 657         if (!lvds->panel)
 658                 return 0;
 659
 660         ret = drm_connector_init(bridge->dev, connector, &rcar_lvds_conn_funcs,
 661                                  DRM_MODE_CONNECTOR_LVDS);
 662         if (ret < 0)
 663                 return ret;
 664
 665         drm_connector_helper_add(connector, &rcar_lvds_conn_helper_funcs);
 666
 667         ret = drm_connector_attach_encoder(connector, encoder);
 668         if (ret < 0)
 669                 return ret;
 670
 671         return drm_panel_attach(lvds->panel, connector);
 672 }
 673
 674 static void rcar_lvds_detach(struct drm_bridge *bridge)
 675 {
 676         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 677
 678         if (lvds->panel)
 679                 drm_panel_detach(lvds->panel);
 680 }
 681
 682 static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
 683         .attach = rcar_lvds_attach,
 684         .detach = rcar_lvds_detach,
 685         .atomic_enable = rcar_lvds_atomic_enable,
 686         .atomic_disable = rcar_lvds_atomic_disable,
 687         .mode_fixup = rcar_lvds_mode_fixup,
 688 };
 689
 690 bool rcar_lvds_dual_link(struct drm_bridge *bridge)
 691 {
 692         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 693
 694         return lvds->link_type != RCAR_LVDS_SINGLE_LINK;
 695 }
 696 EXPORT_SYMBOL_GPL(rcar_lvds_dual_link);
 697
 698 /* -----------------------------------------------------------------------------
 699  * Probe & Remove
 700  */
 701
 702 static int rcar_lvds_parse_dt_companion(struct rcar_lvds *lvds)
 703 {
 704         const struct of_device_id *match;
 705         struct device_node *companion;
 706         struct device_node *port0, *port1;
 707         struct rcar_lvds *companion_lvds;
 708         struct device *dev = lvds->dev;
 709         int dual_link;
 710         int ret = 0;
 711
 712         /* Locate the companion LVDS encoder for dual-link operation, if any. */
 713         companion = of_parse_phandle(dev->of_node, "renesas,companion", 0);
 714         if (!companion)
 715                 return 0;
 716
 717         /*
 718          * Sanity check: the companion encoder must have the same compatible
 719          * string.
 720          */
 721         match = of_match_device(dev->driver->of_match_table, dev);
 722         if (!of_device_is_compatible(companion, match->compatible)) {
 723                 dev_err(dev, "Companion LVDS encoder is invalid\n");
 724                 ret = -ENXIO;
 725                 goto done;
 726         }
 727
 728         /*
 729          * We need to work out if the sink is expecting us to function in
 730          * dual-link mode. We do this by looking at the DT port nodes we are
 731          * connected to, if they are marked as expecting even pixels and
 732          * odd pixels than we need to enable vertical stripe output.
 733          */
 734         port0 = of_graph_get_port_by_id(dev->of_node, 1);
 735         port1 = of_graph_get_port_by_id(companion, 1);
 736         dual_link = drm_of_lvds_get_dual_link_pixel_order(port0, port1);
 737         of_node_put(port0);
 738         of_node_put(port1);
 739
 740         switch (dual_link) {
 741         case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
 742                 lvds->link_type = RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
 743                 break;
 744         case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
 745                 lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
 746                 break;
 747         default:
 748                 /*
 749                  * Early dual-link bridge specific implementations populate the
 750                  * timings field of drm_bridge. If the flag is set, we assume
 751                  * that we are expected to generate even pixels from the primary
 752                  * encoder, and odd pixels from the companion encoder.
 753                  */
 754                 if (lvds->next_bridge && lvds->next_bridge->timings &&
 755                     lvds->next_bridge->timings->dual_link)
 756                         lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
 757                 else
 758                         lvds->link_type = RCAR_LVDS_SINGLE_LINK;
 759         }
 760
 761         if (lvds->link_type == RCAR_LVDS_SINGLE_LINK) {
 762                 dev_dbg(dev, "Single-link configuration detected\n");
 763                 goto done;
 764         }
 765
 766         lvds->companion = of_drm_find_bridge(companion);
 767         if (!lvds->companion) {
 768                 ret = -EPROBE_DEFER;
 769                 goto done;
 770         }
 771
 772         dev_dbg(dev,
 773                 "Dual-link configuration detected (companion encoder %pOF)\n",
 774                 companion);
 775
 776         if (lvds->link_type == RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS)
 777                 dev_dbg(dev, "Data swapping required\n");
 778
 779         /*
 780          * FIXME: We should not be messing with the companion encoder private
 781          * data from the primary encoder, we should rather let the companion
 782          * encoder work things out on its own. However, the companion encoder
 783          * doesn't hold a reference to the primary encoder, and
 784          * drm_of_lvds_get_dual_link_pixel_order needs to be given references
 785          * to the output ports of both encoders, therefore leave it like this
 786          * for the time being.
 787          */
 788         companion_lvds = bridge_to_rcar_lvds(lvds->companion);
 789         companion_lvds->link_type = lvds->link_type;
 790
 791 done:
 792         of_node_put(companion);
 793
 794         return ret;
 795 }
 796
 797 static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
 798 {
 799         int ret;
 800
 801         ret = drm_of_find_panel_or_bridge(lvds->dev->of_node, 1, 0,
 802                                           &lvds->panel, &lvds->next_bridge);
 803         if (ret)
 804                 goto done;
 805
 806         if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK)
 807                 ret = rcar_lvds_parse_dt_companion(lvds);
 808
 809 done:
 810         /*
 811          * On D3/E3 the LVDS encoder provides a clock to the DU, which can be
 812          * used for the DPAD output even when the LVDS output is not connected.
 813          * Don't fail probe in that case as the DU will need the bridge to
 814          * control the clock.
 815          */
 816         if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
 817                 return ret == -ENODEV ? 0 : ret;
 818
 819         return ret;
 820 }
 821
 822 static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
 823                                        bool optional)
 824 {
 825         struct clk *clk;
 826
 827         clk = devm_clk_get(lvds->dev, name);
 828         if (!IS_ERR(clk))
 829                 return clk;
 830
 831         if (PTR_ERR(clk) == -ENOENT && optional)
 832                 return NULL;
 833
 834         if (PTR_ERR(clk) != -EPROBE_DEFER)
 835                 dev_err(lvds->dev, "failed to get %s clock\n",
 836                         name ? name : "module");
 837
 838         return clk;
 839 }
 840
 841 static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
 842 {
 843         lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
 844         if (IS_ERR(lvds->clocks.mod))
 845                 return PTR_ERR(lvds->clocks.mod);
 846
 847         /*
 848          * LVDS encoders without an extended PLL have no external clock inputs.
 849          */
 850         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
 851                 return 0;
 852
 853         lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
 854         if (IS_ERR(lvds->clocks.extal))
 855                 return PTR_ERR(lvds->clocks.extal);
 856
 857         lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
 858         if (IS_ERR(lvds->clocks.dotclkin[0]))
 859                 return PTR_ERR(lvds->clocks.dotclkin[0]);
 860
 861         lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
 862         if (IS_ERR(lvds->clocks.dotclkin[1]))
 863                 return PTR_ERR(lvds->clocks.dotclkin[1]);
 864
 865         /* At least one input to the PLL must be available. */
 866         if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
 867             !lvds->clocks.dotclkin[1]) {
 868                 dev_err(lvds->dev,
 869                         "no input clock (extal, dclkin.0 or dclkin.1)\n");
 870                 return -EINVAL;
 871         }
 872
 873         return 0;
 874 }
 875
 876 static const struct rcar_lvds_device_info rcar_lvds_r8a7790es1_info = {
 877         .gen = 2,
 878         .quirks = RCAR_LVDS_QUIRK_LANES,
 879         .pll_setup = rcar_lvds_pll_setup_gen2,
 880 };
 881
 882 static const struct soc_device_attribute lvds_quirk_matches[] = {
 883         {
 884                 .soc_id = "r8a7790", .revision = "ES1.*",
 885                 .data = &rcar_lvds_r8a7790es1_info,
 886         },
 887         { /* sentinel */ }
 888 };
 889
 890 static int rcar_lvds_probe(struct platform_device *pdev)
 891 {
 892         const struct soc_device_attribute *attr;
 893         struct rcar_lvds *lvds;
 894         struct resource *mem;
 895         int ret;
 896
 897         lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
 898         if (lvds == NULL)
 899                 return -ENOMEM;
 900
 901         platform_set_drvdata(pdev, lvds);
 902
 903         lvds->dev = &pdev->dev;
 904         lvds->info = of_device_get_match_data(&pdev->dev);
 905
 906         attr = soc_device_match(lvds_quirk_matches);
 907         if (attr)
 908                 lvds->info = attr->data;
 909
 910         ret = rcar_lvds_parse_dt(lvds);
 911         if (ret < 0)
 912                 return ret;
 913
 914         lvds->bridge.driver_private = lvds;
 915         lvds->bridge.funcs = &rcar_lvds_bridge_ops;
 916         lvds->bridge.of_node = pdev->dev.of_node;
 917
 918         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 919         lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
 920         if (IS_ERR(lvds->mmio))
 921                 return PTR_ERR(lvds->mmio);
 922
 923         ret = rcar_lvds_get_clocks(lvds);
 924         if (ret < 0)
 925                 return ret;
 926
 927         drm_bridge_add(&lvds->bridge);
 928
 929         return 0;
 930 }
 931
 932 static int rcar_lvds_remove(struct platform_device *pdev)
 933 {
 934         struct rcar_lvds *lvds = platform_get_drvdata(pdev);
 935
 936         drm_bridge_remove(&lvds->bridge);
 937
 938         return 0;
 939 }
 940
 941 static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
 942         .gen = 2,
 943         .pll_setup = rcar_lvds_pll_setup_gen2,
 944 };
 945
 946 static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
 947         .gen = 3,
 948         .quirks = RCAR_LVDS_QUIRK_PWD,
 949         .pll_setup = rcar_lvds_pll_setup_gen3,
 950 };
 951
 952 static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
 953         .gen = 3,
 954         .quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
 955         .pll_setup = rcar_lvds_pll_setup_gen2,
 956 };
 957
 958 static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
 959         .gen = 3,
 960         .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
 961                 | RCAR_LVDS_QUIRK_DUAL_LINK,
 962         .pll_setup = rcar_lvds_pll_setup_d3_e3,
 963 };
 964
 965 static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
 966         .gen = 3,
 967         .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
 968                 | RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
 969         .pll_setup = rcar_lvds_pll_setup_d3_e3,
 970 };
 971
 972 static const struct of_device_id rcar_lvds_of_table[] = {
 973         { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
 974         { .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
 975         { .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info },
 976         { .compatible = "renesas,r8a774b1-lvds", .data = &rcar_lvds_gen3_info },
 977         { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
 978         { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_gen2_info },
 979         { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
 980         { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
 981         { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
 982         { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
 983         { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
 984         { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
 985         { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
 986         { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
 987         { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
 988         { }
 989 };
 990
 991 MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
 992
 993 static struct platform_driver rcar_lvds_platform_driver = {
 994         .probe          = rcar_lvds_probe,
 995         .remove         = rcar_lvds_remove,
 996         .driver         = {
 997                 .name   = "rcar-lvds",
 998                 .of_match_table = rcar_lvds_of_table,
 999         },
1000 };
1001
1002 module_platform_driver(rcar_lvds_platform_driver);
1003
1004 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1005 MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
1006 MODULE_LICENSE("GPL");